Chapter 3 Sizing the Design

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Functional Specification - A Closer Look Review the Available Arrays Architectural Specification or Hardware Specification Array Sizing Cell Capabilities Array Architecture Netlist Example: AMCC Interface Options Example - AMCC Arrays - Power Supply Options Interface Cell Functionality Examples Internal Cell Functionality Multi-Cell Macros Hard and soft macros Refining Interface Requirements Adding Extra Power and Ground Macros Dual-Function I/O Macros Example - Simultaneously Switching Outputs Thermal Diodes The AMCC Speed Monitor Final Interface Cell Utilization Drivers Exercises

Sizing the Design - Selecting the Array
Functional Specification - A Closer Look
The functional or target specification is the first level of description of the project that may encompass one or more arrays when the design is partitioned. There may be a specification tree with the total project at the top node and individual circuit blocks or modules detailed underneath. Topics included in a functional specification are listed in Table 3-1. At this early stage, a functional description of what is to be accomplished is created along with some of the top-level circuit requirements.

Array Interfacing
For the partitioned project (multiple arrays), the individual array specifications would include a description of array interfacing. Interconnection between arrays is faster when done with ECL. When choosing single or dual (differential) rail ECL use the following guidelines:
• • •

If the arrays will be placed on the same board and will be adjacent to each other, single rail (non-differential) ECL may be acceptable. If the arrays will communicate across a backplane or be remote on the board, differential ECL may be required. Differential ECL is required if the operating speeds exceed the maximum frequency specifications for single rail ECL.

The potential need for differential ECL should be indicated at the functional specifica tion level.

Partitioned circuits should attempt to balance the distribution of I/O and internal cell usage between the different arrays while maintaining critical paths within one array if possible. This is still the rule to follow - no matter how big the arrays get. It is also a good guideline for how to break up a 6-8 million gate array into top-level blocks - keep the critical paths inside the block if possible. Interblock connections today are what interarray connections were yesterday.

Table 3-1 Components of the Functional specification Functional Specification Block diagram to the module level- including any partitioning into more than one array Description of the boundaries between the modules and the rest of the system Initial sizing of the I/O interface by type - ECL, TTL, etc. Functional Description of the Modules Description of the interface between the circuit modules - busses, control, critical interconnects The overall performance requirements - - - the maximum frequency of operation - - - target clock speed (per clock) - - - path propagation delay requirements set by modules external to this design I/O toggle rates Synchronous/asynchronous signals Allowed or available power supplies Power restrictions Physical size restrictions Environmental requirements -Commercial, Military, Industrial, Other Packaging requirements Derating for junction temperature Prioritized design objectives

Hard Specifications
Design criteria that are considered as hard (inflexible) specifications should be clearly documented as such. Specifications that might be alterable should also be clearly identified. If a tradeoff or judgment call needs to be made during the remainder of the design project, such information can save time and possibly the project.

Design Objectives
Overall design objectives should be clearly identified and documented. These include optimization for speed, power or die size, which translates to minimized internal cell utilization and minimized I/O utilization. Since these objectives are in conflict, they should be prioritized. As a last step, there should be a careful design review of the circuit and sys tem functional specifications and the partitioning

Review the Available Arrays
With a clear understanding of the design description and overall objectives, review the arrays currently available that could be used. For a listing of currently-available array series, check with the latest ASIC vendor surveys run by several of the engineering magazines. These buyer's guides provide a cursory look at what is available and allow a first-pass sort of available arrays into feasible and non-feasible, a staring point from which the designer can proceed. They have limited space to review technology, die size, cell counts, metal layers, number of macros, interface levels, second sources and the EWS workstations the array vendor supports. They may not have the latest updates on an array series. They can provide addresses and phone numbers for array vendors. Once one or more vendors have been selected, the designer should obtain data sheets and design guides from the prospective vendors for the most promising array series and begin a more in-depth review.

Example - The AMCC Arrays - as of 1991
The industry shows an evolutionary trend as designers drive them to develop larger, faster and cooler arrays. There have been five bipolar array families from AMCC since 1984, (see Table 3-2) increasing in cell size and speed while reducing die size and power. The most recent is the AMCC Q20000 series, officially released in September 1989. Table 3-2 AMCC Bipolar Array Series AMCC Array Series Year Q20000 Q5000 Q3500 Q1500 Q700 1989 1987 1986 1985 1981

The Q20000 Series speed estimates list its internal toggle rate, at least twice as fast as that of the previous Q5000 Series, at 1.25GHz, with an enhanced drive and much lower power. Individual macros have been found to run at 1.4GHz and higher. There are two AMCC BiCMOS array families, the Q14000 Series and the Q24000 Series, a partial shrink of the Q14000, as shown in Table 3-3. Table 3-3 AMCC BiCMOS Array Series AMCC Array Series Year Q24000 Series Q14000 Series 1990 1988

The current BiCMOS families were preceded by three CMOS array series, each faster than its predecessor. The BiCMOS arrays combine the drive and interface ability of bipolar with the cooler operation of CMOS. The newer BiCMOS Series must be larger, faster and cooler.

Comparing the arrays
The items that define the differences between array series include those shown in Table 3-4. Table 3-4 Features for Array Series Comparison Array Series Comparison Topics The process technology Metal layers routed (2, 3) Series gating techniques Sea-of-cells versus routing track architectures also called channelless vs. channelled Overall Maximum Speed of Operation specified as I/O and internal toggle rates Frequency Ft (frequency at which beta for transistor becomes unity) Noise immunity Edge rates - programmable or not Symmetry in rise and fall times Power-supply options allowed Power-supply variation stability

. etc. product profiles and macro library design guides or design manuals supply the specific information for an array series. speed-power programmability Variety in the macro library available Wire-ORs (dot-wire) allowed or not Design constraints Power dissipation per gate Packaging Available Autoplace. This is on a smaller module scale than the . Autoroute Engineering Workstation support Simulators supported Second source Military compatible Commercial compatible Military qualified testing Other topics as dictated by the arrays.. MIXED. The design manual.) ECL terminations On-chip translators Maximum number of internal cells or gates available Features for Array Series Comparison Macro Options .. Fast (V).e. Architectural Specification or Hardware Specification Once a clear definition exists of the circuit or circuits that will be placed on one array. and details about interfacing. their technology and the design issues The arrays within a series refine these differences with specific information on size. High-speed (H). ECL. supplied with the array library media. is the controlling document. Drivers (D). i.or lack of options. number of cells by type.Maximum number of I/O cells available I/O modes allowed (TTL.Standard (S). Power (P). then the planned design can be developed. Data sheets. as shown in Table 3-5. super-drivers (D) . Lowpower (L).

such a parametric gate tree or parity logic is to be used. adders. at the level of counters.g. The hardware design specification details what the designer intends to do to meet the target functional specification.block-level functional specification. The specification may include proposed vendors and arrays. the sizing estimates must take this additional logic into account. and its derivatives. registers. hardware description language. latches. With the descriptions developed for the modules. equivalent gate estimates can be made for the circuit. This level of specification can be equated to a PDL (program definition language) description of software and is the basis for the evolution of HDL. it must be included in the sizing estimates.. If additional testing logic. sequencers. The performance requirements defined in the functional specification can be used to select the technology. The array vendor Applications Engineer can help with the sizing estimate. etc. If a particular testing methodology is being enforced. . e. CML outputs Placement rules that affect design Variable bonding The review of available arrays is conducted in parallel with the creation of the hardware specification. Table 3-5 Array-Specific Specifications Hardware or Architectural Specification Number of internal cells Number of I/O cells Number of outputs Number of bidirectional macros Number of fixed power and grounds Rules for adding power and ground Packaging Options Maximum internal current limits On-chip memory Macro-type design use restrictions such as number of Darlington. or estimated cell usages can be computed for the circuit on a specific array.

all four types partitioned into inputs and outputs and bidirectionals --.estimated internal pin counts Refined details on the array interface --. the specification should be revised to show that series and all computations performed for that series.estimated pad utilization --.Table 3-6 Components of The Hardware Specification Hardware Specification Components The selected technology or technologies Potential array series (1-3 at the most) Block level diagram to the sub-module level The functional description of the different circuit sub -modules such as adders. counters.number of TTL I/O --. Sub-module sizing --.external set-up and hold window unless this circuit will establish the window specification for the driving circuit Critical path throughput performance Estimated power .DC and AC as required Package to be used Heatsinks required and/or air cooling required Estimated junction temperature There should be a design review of the architectural or hardware specification before final selection of an array series.number of ECL 10K I/O --.estimated I/O cell utilization --.maximum toggle frequencies for each I/O --. registers. .number of outputs switching simultaneously (by type) (SSOs) --.equivalent gates or estimated internal cell utilization --. On final selection.number of ECL 100K I/O --.number of CMOS I/O --. etc.

the Q20000 Series D flip/flop uses 2 internal cells. (This tool is vendor-dependent. The designer would need the algorithms before a rational comparison based on equivalent gates can be made between and two array series. The cells will vary between array series. vendors use many different methods for computing equivalent gates. 2 or 3 gates. regardless of the vendor. The critical path may be captured in more than one version and comparisons made based on an annotated simulation.5 transistors is equivalent to a gate (Digital Equipment's definition). equivalent gates = ( number of internal cells / 2 ) * 11 . Circuits were "sized" based on the number of equivalent gates it would take to create them. even from the same vendor.Method 1 One approach to array sizing is to count the number of transistors in the internal core cells. Example . Sizing the D flip/flop as 11 gates. assume that 2. Array Sizing Cell Structure Each cell in an array consists of a number of uncommitted transistors. Power and sizing details can be run against a macro list rather than a full interconnect netlist.Note that a workstation can provide some assistance. The product of the number of cells times the number of gates per cell provides the equivalent gates per array.5 ) Example . Bipolar array cell complexities render equivalent gates a rough measure at best. MSI and LSI based on their equivalent gate counts.Method 2 Another method is to use the D flip/flop. Bipolar arrays carry equivalent gate counts on their data sheets as a sizing measure but it serves only to show relative sizing between arrays in the same series. BiCMOS cells are more complex than CMOS and equivalent gate estimates are not recommended for them either. resistors and other discrete components and is designed around the performance criteria for the intended macro library. Integrated circuits were classed as SSI. and compute the number of equivalent gates per cell. CMOS arrays carried on with the equivalent gate count and it was reasonable because the internal cell in a CMOS array can be sized as 1. Equivalent gates The number of equivalent gates has been a design measure dating from the days of discrete designs first converting into SSI-level ICs. To complicate the problem. equivalent gates = ( number of transistors in core / 2.) Check if such a pre-capture tool is available to help size the circuit.

For the Q20000 Series. equivalent gates = (number of internal cells / 3) * 16 or: equivalent gates = [(number of internal cells / number of cells required for measuring function) * number of gates in function] AMCC ASIC Product Selection Guide with Equivalent Gates Listed (1996) AMCC ASIC PRODUCT SELECTION GUIDE (1990''s) Equivalent Number Structured Gates (Full Adder of I/O Array Blocks Method) 671 1469 4032 6782 11242 18777 928 3120 13475 28 66 100 128 162 198 34 51 195 None None None None None None 1 GHz PLL 1 GHz PLL RAM Part Number Technology Q20004 1 Micron Bipolar Q20010 1 Micron Bipolar Q20025 1 Micron Bipolar Q20045 1 Micron Bipolar Q20080 1 Micron Bipolar Q20120 1 Micron Bipolar Q20P010 1 Micron Bipolar Q20P025 1 Micron Bipolar Q20M100 1 Micron Bipolar I/O cell contributions None of these methods for estimating equivalent gates take the logic capability of the interface cells into account.Example . a 1-bit full adder takes 3 internal cells.Method 4 The last method discussed here is to size a full adder at 16 gates. equivalent gates = (number of internal cells / 3) * 11 Example . Some vendors do count them in their published equivalent gate counts and others do not. . The Q20000 Series 3:1 MUX-D flip/flop uses 3 internal cells.Method 3 The usual AMCC method is to size a 3:1 MUX-D flip/flop macro as 11 gates.

BiCMOS or CMOS). latch and flip/flop implementations.and L-option D flip/flops use two cells while H-option D flip /flops require three. Older AMCC arrays had buffer cells internally and specialized input or output-only . either utilization limits or cell count limits should also be readily available. For the AMCC BiCMOS arrays.AMCC Cell types The basic AMCC logic array is composed of two classes of cells: the internal cells. Cell types and resources The vendor data sheet and design guide or design manual should clearly identify cell types and the number of each on each array in the series. and the perimeter cells composed of input. two simple (no RESET. The cells for different array series. either in a table summarizing the array cell capability or through the macro library documentation. Example . a 3:1 MUX and D flip/flop. The Q20000 Series internal cell is roughly comparable to a half-cell for the Q5000 Series if size of function alone is considered as the basis for comparison.AMCC cell capabilities An internal cell for the Q5000 Series can support a complex D flip/flop. a triple latch. same technology (bipolar. For the bipolar arrays. The logic cell for the Q20000 Series is defined as the smallest partition possible and each internal cell supports one Turbo macro output. output or bidirectional (I/O) cell. No power is used by a cell in its base configuration.Example . from the same vendor may also differ widely in the approach used in their design and in their functional complexity. S. Cell capabilities Cells for each array have different capabilities.AMCC cell design AMCC cell design is optimized for MUX. These added power and ground macros usually reside on an I/O cell and pad and can affect the number of cells left for circuit signals. The Q20000 Series internal cell alone cannot support a D flip/flop. Example . or triple 2:1 MUXs with common select. which is composed of logic (L) and memory (M) cells for bipolar arrays or basic (B) cells for BiCMOS arrays. Included in these descriptions should be a measure of cell functionality. single output) D flip/flops. a cell is roughly 3 gates. Any restrictions in the use of the cells. Turbo is a Q20000 feature that provides high drive (18 loads) with less power and less skew. As a part of the cell resources identification. a logic cell is a more complex structure and varies with the series. Each cell is designed to support high-speed requirements so that there are no placement restrictions on the high-speed option macros due to cell limitations. the vendor should be supply a clear description of the fixed power and ground pads and procedures to added additional power and ground pads.

Output. for the Q5000 Series in Table 3-9 and for the Q20000 Series in Table 3-10. An array may or may not have specialized I/O cells. Buffer. The QM1600S (now the QM1600T) was the first of the AMCC arrays to incorporate memory on a logic array. AMCC cell types are shown in Table 3-7.Cell Resources Array Name Q24280 Q24140 Q24091 Q24060 Q24021 Q24008 Internal B Cells 6880 3360 2268 1440 540 190 I/O Cells 300 226 160 132 80 66 Pads 256 226 160 132 80 44 Usage restrictions: Refer to the Q24000 Design Manual for details. Table 3-9 AMCC Q5000 Series Arrays .interface cells.Cell Resources Array Name Q5000T Q3500T Q1300T QM1600T Internal L Cells 352 242 84 114 I/O Cells 160 120 76 106 Output Limit 120 Memory Cells 2 (1240 bits) . Cell resources for the Q24000 Series are shown in Table 3-8. Basic. SpecialI/O PERIPHERAL: Input. Refer to the cell resources table for an approximate idea of the array cell capacity for three series and note the differences. Note that no two series are alike! Table 3-8 AMCC Q24000 Series Arrays . Memory I/O. Table 3-7 Cell Types INTERNAL: Logic.

Loop .Cell Resources I/O I/O Signals Signals Internal Cells Cells .Table 3-10 AMCC Q20000 Series Arrays . ** Only for the largest arrays. Arrays that contain memory place the RAM blocks in the core . (2) 51 for external loop (3) 34 for external loop Array architecture The base arrays for the various series are similar in their design concept in that the core of most arrays is composed of an array or matrix of logic or basic cells organized in a row-column configuration. 100_LDCC for the Q20P010 and 132_LDCC for the Q20P025 Add last four columns to find total I/O cells and pads. ECL TTL PLL Power/Ground Outputs Outputs Power/Ground (1) Limit Limit 172 130 100 45 (2) 80 23 (3) 50 100 80 64 45 (2) 48 23 (3) 24 8 8 78 52 52 26 36 20 32 Array Name Q20120 Q20080 Q20045 Q20P025 Q20025 Q20P010 Q20010 (1) Add last two columns to find total number of fixed power and grounds.PLL Cells (For (Fixed) FIlter Related Signals) (1) (2) 3414 2044 1227 595 733 177 267 198 162 128 76 100 54 66 4 4 4 4 4 4 4 13 13 8 8 - Array Name Q20120 Q20080 Q20045 Q20P025 Q20025 Q20P010 Q20010 * Two pads are used by the AC Speed Monitor and two by the thermal diode.

have PLL locations that straddle both core and interface areas. The base array for a single +5V supply will be different from that for a mixed-mode +5V/-5. There are different base arrays for different power supply configurations. with the rest of the core designated for internal logic cells. Figure 3-1 Q20080 Die Plot Figure 3-2 Q24140 Die Plot .2V dual supply. A generic die plot for the Q20080 array is shown in Figure 3-1 and one for the BiCMOS Q24091 is shown in Figure 3-2. the PLL arrays. Interface (I/O) cells are placed around the perimeter of the array interspersed with power and ground.area. with the interconnect pattern in Figure 3-3. Phase-Lock loop arrays.

The internal interconnect for a simple macro is generally confined to one layer of metal. Macros can occupy a cell. the specific layers being array and series dependent. For an array with three layers of metal. Cell Interconnect The process of interconnecting macros is called routing. Horizontal and vertical tracks are assigned to specific metal layers. The particular layer will depend on the array series. . In practice. a partial cell (usually 0. The Q24000 sea-of-gates and Q20000 sea-of-cells (Channelless) architectures use three layers of metal. routing is performed following specific routing tracks.5 cell). The interconnect is on the first and second layers of metal in a two layer metalization array. the second and third layers will be used for intermacro routing and the first layer for intra-macro routing. Macros are interconnected on one level and interconnect between macros occurs on the other two.Figure 3-3 BiCMOS Macro Interconnect Pattern Macro configurations Macros are individually configured by interconnecting the components within a cell with one layer of metal to form the selected macro function. Channelless architecture Channelless architectures have been developed to avoid some of the limitations imposed by restricted number of routing tracks. or require several cells. the hard definition of which layer of metalization is restricted to which operation can be blurred. For channeled architectures.

Parametric information that is included in the netlist is array and array-vendor dependent. A library such as the Q20000 is shipped to customers with a Macro Parameter File.AMCC generic interface format. This netlist is used as input to the AMCC MacroMatrix software as listed in Table 3-11. the internal macro connects (intraconnect) are on second and third metal with macro and I/O interconnects on the first layer. The standardized netlist is named circuit. There is no standard workstation or simulator netlist format although efforts are directed toward that goal (see EDIF) and some success has been recently attained. Each workstation produces a netlist in its own format. AMCC refers to this as AGIF .For the Q20000 Series arrays.sdi MacroMatrix AMCCERC rules check MacroMatrix AMCCPACKAGE (Package Check and Data) MacroMatrix AMCCANN annotation MacroMatrix AMCCSIMFMT simulation file formatter MacroMatrix AMCCVRC vector check MacroMatrix AMCCSUBMIT submission check AMCCAD place and route system . Example: The AMCC netlist To accommodate transfer of designs from any workstation or from any of the sup ported netlisters (Laser 6 and Verilog) to the mainframe-based place and route sys tem. A different conversion program is required for each workstation or simulator that AMCC supports. This pattern is described in a netlist. These parameters are included in the netlist for each occurrence of each macro used in the design.sdi . Routing on all three layers is possible and four layers of metal is a future possibility. Sizing the Design . where the workstation netlist is translated into a standard interface format. netlist conversion is performed. Table 3-11 AMCC MacroMatrix and Design Support Software .using circuit.Selecting the Array Netlist The combination of the macro layout patterns (component interconnect) and the macro interconnect forms the metalization pattern required to implement the circuit on a given array. which supplies the parameters for each macro in the library. carrying along whatever in formation the workstation vendor has decided was necessary.

The power supply and the interface combination define the I/O mode of the array. ECL 10K. Each I. Example: AMCC interface options For all AMCC arrays. Interface types Once it is seen that the interface mix can be supported on an array series. O. or I/O cell can be configured to be either TTL.Test vector transfer software Verilog simulator Interface options . or I/O cells for external interfacing to both ECL and TTL. Table 3-12 AMCC Interface Combinations IF INPUT IS OF TYPE: OUTPUT CAN BE ANY OF: TTL ECL 10K ECL 100K TTL ECL 10K X X X X X X X X X X X X X X X X X ECL 100K X X X X X Table 3-13 TTL OUTPUT OPTIONS standard TTL open-collector three-state or 3-state also called tri-state standard TTL output bidirectional open-collector output bidirectional . Not all arrays support all possible I/O modes with all possible power-supply combinations. I/O cells can usually be used for input macros. O. ECL 100K or as a power or ground pad. TTL and ECL translators are included in the I. ECL 10KH. Table 3-12 shows the possible I/O combinations allowed on AMCC arrays while Table 3-13 details the TTL output options and Table 3-14 the ECL output options.I/O modes Interface combinations required for the design should be compared to those offered by the arrays under evaluation. output macros or bidirectional macros. the type of TTL and ECL outputs that will be required is used to help size the I/O requirements of the array.

25 ohm termination Darlington ECL Hi-Z 10K Darlington ECL Hi-Z 100K Darlington On-chip 50 ohm series termination ECL 10K Darlington On-chip 50 ohm series termination ECL 100K Darlington On-chip 100 ohm series termination ECL 10K Darlington On-chip 100 ohm series termination ECL 100K From CML forward in the above list are types identified as possible for the Q20000 Series. 25 ohm termination Darlington ECL 100K.The 3-state outputs and TTL bidirectional macros have an enable pin that is either restricted to being driven by a specific macro type (a 3-state enable driver) or unrestricted and driveable by any internal-level signal. 50 ohm termination bidirectional ECL 100K. 50 ohm termination ECL 10K. 50 ohm termination ECL 100K. 50 ohm termination Darlington ECL 100K. 25 ohm termination ECL 10K. 100K. . 50 ohm termination bidirectional CML outputs (> 600MHz). Table 3-14 ECL Output Options Output Options ECL 10K. Standard ECL 10K. CML and Darlington outputs were in the first re lease of the macro library for the series. ECL''s version of an open-collector On-chip 50 ohm series termination ECL 10K On-chip 50 ohm series termination ECL 100K On-chip 100 ohm series termination ECL 10K On-chip 100 ohm series termination ECL 100K Darlington ECL 10K. 50 ohm termination Darlington ECL 10K. The restriction depends on the array and on the mode (100% TTL or Mixed ECL/TTL) of the circuit. 25 ohm termination ECL 100K.

Example .2V with ECL 10K. the power supply or power supplies to be used should be compared to the supplies allowed for the array.2V +5V/-4. Effects on Parametrics When non-standard voltages are used. Both ECL types may be used for output on the same array. the number of fixed power and ground pads and their locations should be reviewed for their applicability to the design in question.2V -4.5V 100% ECL 100K x ECL10K/TTL ECL100K/TTL x x . The Q5000 and Q20000 Series arrays are bipolar arrays. such as -4. There is often a need to have an array interface with several types of I/O while keeping power supply requirements in line with what is already provided on the target PCB (printed circuit board). They use an internal ECL core (0. either ECL 10K/TTL or ECL 100K/TTL or all three.5V with ECL 10K and -5.Power Supply Options The power-supply and interface type matrix for the AMCC arrays shows a very flex ible approach to solving interface problems. The data sheet for the array series will call out the parametrics for standard supplies.5V +5V/-5. The supplies. ECL 10K or to ECL 100K.5V) as shown in Table 3-15. the DC parametrics for the array will be affected. Table 3-15 AMCC Power Supply Options SINGLE POWER SUPPLY DUAL POWER SUPPLY I/O MODE 100% TTL 100% ECL 10K +5V x x x x x x x x x x x x x x -5.Power supply options In addition to the types of interface required. Only one type of ECL may be used for input on a single array. AMCC arrays allow for the mixed mode operation of ECL/TTL on the same array.5V ECL) and can externally interface to either Schottky TTL.2V or +5V/-4. The vendor must be consulted for computational procedures to be used when non-standard power supplies are used. Many of the AMCC arrays can be used with a single power supply (+5V) or dual supplies (+5V/ -5.AMCC Arrays . This can lead to operation of a technology with non-standard voltages.

. and elementary logic possible in an interface cell varies by array series. Table 3-15. including population and cell type limit checks. bidirectional macro counts. also applies to the Q24000 Series BiCMOS arrays. The idea of operating ECL 10K at ECL 100K power supplies and visa versa was also the result of customer requests. This is in addition to level translation and buffering functions. it is a function of the I/O cell complexity and the components available within the cell.) The chip macro communicates parameters to the AMCC MacroMatrix software modules that are performing design validation. They have a CMOS core and bipolar I/O and they can interface to CMOS. with the exception of "DECL". The amount of buffering. the input macros also provide simple AND/NAND or OR/NOR logic or high fan-out driver operations. and other checks. simultaneously switching outputs. Figure 3-4 A Chip Macro (1994) Interface cell functionality Interface cells are designed to support TTL-translators. The array-specific checks use chip macro parameters to set limits for TTL outputs. The amount of logic contained within an interface macro is series-dependent. Example. The concept of mixed ECL-TTL interface on a single array was originated as a result of customer demand. (See Figure 34. The AMCCERC software can spot mismatched interface macros and exceeded macro type limits and issue appropriate error messages. It can also adjust the DC power module to use the correct power supply in the power computation. The output macros for TTL contain OR or NOR operations and those for ECL may contain these operations plus others as complex as a latch or a 2:1 MUX. For many of the arrays.100% ECL run with dual power supplies is called "DECL".communicating to the software AMCC uses dummy macros called chip macros that allow a user to specify precisely what array is to be used in what interface mode with what power supplies. Darlington outputs. ECL output terminations to 25 or 50 ohms. ECL-translators and most of the required buffers for external interfacing to both ECL and TTL. single-cell bidirectional macros. the capability of the cell to support high fan-out drivers.

flip/flops. output or bidirectional) cells that require a buffer for each input and each output macro. and bidirectional macros the first time all buffers were removed from the internal cell area. The buffer macros were placed on internal cells (L or B). the only macro to behave in this manner. and were placed on a B cell. output. latches. It can drive eight loads. The following gives an idea of the choices that have existed on the arrays from one vendor. The QH1500A array used I and I/O cells. A bidirectional macro was composed of one interface and two buffer cells. output and bidirectional macros. with buffering included in the input.Variability in I/O design The various array series and even arrays within a series differ in their approach to interface. The I/O cell could support single -cell bidirectional macros. Bidirectionals were constructed from two macros on two adjacent cells using the same methods now used on the Q14000 Series arrays. The Q14000 Series uses I/O cells. EXOR networks. reduc ing the L-cells available for internal logic functions. • • • • • • • . The Q1500. TTL outputs (output macros and bidirectional macros) are limited to a number that varies per array. Load capacitance presented to the source driving the unbuffered ECL input increases by 1 pF per fan-out. The Q3500 and Q5000 Series use I/O cells only. The BExx macros were for ECL output buffering. The BIxx macros are placed on internal macros (L or B). with buffering included in the input. TTL input buffers are part of the input macro that was placed on an I cell. The unbuffered ECL input macro does not suffer any degradation in speed due to loading delay. The BIxx series macros are made up of representative logical functions from the rest of the macro library (gates. • The Q700 Series used unbuffered I (input-only) and I/O (input. Additional bidirectional macros must be built from one input and one output macro. with buffering but no logic functions. The bidirectional macros use twocells and provide an added ground pad by using the left-over pad. The Q20000 Series uses I/O cells. MUXs and decoders) which also includes the ECL input buffering function on selected input pins. for example. The selected pins are pin-restricted to be driven by any unbuffered ECL input macro. Single cell bidirectional macros can only be used on the Q9100B or Q2100B and then only in specific "special-I/O" cell locations. with buffering and logic as is used in the Q5000 Series. ECL outputs are also limited. The Q1500A array used I (input-only) and O (output-only) cells. with buffering either in the input or output macro or in a separate macro. There was a D-cell on one array in the series to provide a pin-restrictive three-state enable driver that could drive more than eight loads. Q3500 and Q5000 Series also provide unbuffered ECL input and the buffered logic macros to support it. Similar variability and evolution can be traced for other vendors.

the internal macro routing eliminates the need for two sets of test vectors or an extra bonded-out pad. If an array series has no bidirectional macros. but this requires two test vector sets. but this requires two package pins. and placed on two adjacent I/O cells. These four pads and cells are not available for use with any other function. one-pin. triple latch-common clock. If more bidirectional macros are needed. Each bidirectional macro also contains either an IEVCC pad (ECL VCC) or an ITGND (TTL GROUND) pad. decoders. In this case. both time and money are required. one input and one output. multiplexors. As stated before (see "Cell structure"). They are usually tied together outside of the package to keep testing simplified. The two macros can be tied together into one package pin. latches. they may need to be constructed. Examples The Q20000 Series arrays support a bidirectional macro that sits on two I/O cells. and debugging time may need to be increased. These cells can support a 3:1 MUX-D flip/flop combination. EXOR and EXNOR net works. These signals are used by the on-chip thermal diode (one anode and one cathode) and the on-chip AC speed monitor (one is power and the other is an output signal). triple 2:1 MUX-common select and dual D F/Fs. Watch out for incompatibility with the workstations . they are constructed from two macros. one-cell or two-cell macros. one for wafer sort and one for packaged part testing. The Q20000 Series provides a single-cell 25 ohm termination macro but limits its use to arrays using two power supplies.• Most 25 ohm termination macros require two I/O cells. (Refer to "Added power and grounds" for a discussion of pad plane interconnections for added power and ground pads. The Q20000 Series uses four fixed I/O signals per array. high-fan-out drivers. Anytime that hand-edits or customization of the interconnect or base is involved. Darlington macros are limited to arrays with two power supplies.) Internal Cell Functionality The logic (bipolar) and basic (BiCMOS) cells are organized to provide logic functions such as basic logic gates and buffers. gate networks.a work-around may be required for proper simulation of bidirectional macros. unlike the single-cell approach of the Q5000 Series. and flip/flops. the number of cells required for any of these functions will vary by array series. A third approach not liked by the array vendors is to stitch two macros together in the interconnect so that only one pad and one pin are used. • Bidirectional macros Bidirectional macros can be two-pin. .

The MSI macros in the Q5000 Series were originally designed to allow placement in several different configurations to facilitate the auto-place algorithm (best-fit approach). The larger multi-cell macros. Both the BiCMOS Q14000 and Q20000 Series MSI macros use hard-macros. A cell may be designated as the smallest divisible or addressable unit (SAU). so that the interconnect delay could be kept minimal. and the problems in net weighting and prioritizing the internal nets to the router. the simulation model. 4-bit carry-look ahead adders and their companion carry-look-ahead generator. can be increased by 2040% while reducing design partitioning and macro conversion efforts. named MSI macros by AMCC.The number of cells required to implement a function depends on the component mix present in the cell and that required by the function. Hard and soft macros There are two types of MSI or multi-cell macros. where the cells composing the macro have a preferred. Design density. interconnect components spread across several cells more efficiently than the schematic interconnection of the equivalent function formed from basic macros. The other type is soft. Multi-Cell Macros Groups of internal and/or interface cells can also be combined into large multi-cell macros for higher functionality. where an MSI macro is laid-out as a single multi-cell unit and handled by the placement soft ware . The simple and MSI macros available with a specific array series are documented.5 cells. which invalidates the timing specifications and therefore. 4-bit registers. along with any use or placement restrictions. The problems in improper placement. 6-bit comparators and 8-bit latches. which also allows sizes such as 4. The large MSI macros include MSI and LSI functions. specified-to layout pattern but which requires the interconnect to be routed as if it were any other interconnect net. while closely maintaining the specified performance for the macro. A preferred placement is documented. Always refer to the latest version of these manuals when performing an evaluation. This is a soft-macro. 4-bit up and down counters. Example MSI macros are 6-bit comparators. in the appropriate Design Guide or Design Manual. make the soft MSI macro approach unattractive. An array cell size may be divisible so that half-cell macros are possible. The result is a denser functionality with the resultant speed improvement. measured by the cell utilization per functionality. One type is hard. where the cell interconnect is treated as one large macro and no variations in layout are permitted. in which case a one cell macro is the smallest macro allowed. Arrays are designed for a specific set of applications or targets and base array design is optimized for those applications. Different array series offer different MSI macros.

as an inflexible black box. high-speed signal isolation and ECL . Future AMCC arrays will use the hard macro approach. Hard-macros facilitate automated placement.TTL isolation. Figure 3-5 shows an MSI-based 16 -bit adder. which can be reduced by the addition of TTL VCC . package restrictions. the interface requirements must be refined. These include: • • • • simultaneously switching outputs. Simultaneous switching TTL or ECL outputs is a potential source of system noise.TTL Ground pairs and/or ECL VCC. Figure 3-5 16-Bit MSI Adder (1994) Refining Interface Requirements When the interface types and their power supply requirements are documented and one or more arrays chosen as candidates for the final selection. There are several conditions under which additional power or ground pads will need to be added to an array beyond the fixed power and ground pads provided. .

In spite of the drawbacks. (See Figure 3-6. The vendor provided a list of how many would need to be used depending on the signals used by the design. O and I/O cells should also be independent to insure steady operation. then one must be added. When a fixed ground is not available. it is time consuming and expensive.) For standard refer-ence ECL. Isolation of CMOS inputs from the faster switching TTL and ECL signals may also be required. they can reduce silicon requirements while maintaining functionality. This type of flexibility is detrimental to standard packaging. IEVCC represents a ground pad. To offset this waste. The criteria for requiring that these fixed positions be used or that additional power and grounds be added is based on the number and types of interface macros used. Others require that a ground exist between simultaneously switching TTL outputs and ECL inputs. recent BiCMOS designs have returned to this approach. (See Figure 3-7. AMCC arrays use the ITPWR (+5V). O or I/O cells. IEVCC represents a power pad. providing the minimal number of power and grounds and allowing other fixed-position power and grounds to go unbonded (unconnected). The threshold and reference voltage generators for the logic array internal cells and I. many macro libraries include dual-function macros that use the I/O cell for one function and the pad for added ground. Figure 3-6 Added power and Ground macros (AMCC) Dual-Function I/O Macros Each added power and ground macro uses a pad and disables the cell that is associated with that pad. For +5V REF ECL. Variable Requirements for Power and Ground Bipolar arrays require that all fixed power and ground be used or bonded out to the package.Some arrays require that drivers be placed next to ground. CMOS arrays have some or all of their fixed power and ground pads under user placement control. The macros avail able are array series-specific and vary widely. Additional power and grounds are based on simultaneously switching out puts or isolation requirements. The design rules for any array series are called out in the Design Manual for the array. noise feedback due to output switching is minimized. Silicon efficiency can be achieved with the dual function macros. ITGND (0V) and IEVCC (ECL VCC) macros to add power or ground. reducing the number of these cells and pads available for I/O operations.) . Adding Extra Power and Ground pads Adding a power pad or a ground pad to an array can be accomplished by placing a power or ground macro on the desired pad (array-specific procedure. or between any TTL output and an ECL input. When the power busses supporting the internal core are isolated from the busses supporting the peripheral I. If any of these functions applies to the design.

with the exception of the Q20000 Bipolar Series and the BiCMOS Q24008 array. This requires one cell. depending on the package. Allow 8 ECL SSO outputs per quadrant. All TTL output counts are converted to "equivalent" 8 mA outputs. two pads and. then add one ECLVCC macro for each group of 1-8 after the first eight. depending on the package. then add one TTLPWR and one TTLGND macro for each group of 1-8 after the first eight. one pad and. This requires two cells.Example macros include: • • input function with 3-state enable driver 3-state enable driver with added ground bidirectional input with added ground Figure 3-7 Example Dual-Function I/O Macro Example . Add another pair for the next group of 1-8 and another for the next group of 1-8 and so on. place the ECLVCC macro so that it is interspersed with the simultaneously switching outputs and can be bonded to the power or ground package plane as required. use the following rules for adding power and ground due to simultaneously switching outputs (SSO). Note that ECLVCC is a power pad in a +5V do nothing add 1 pair add 2 pairs . TTLGND PAIRS: 0-8 9-16 7-24 Etc. For packages with internal power and ground planes.) For packages with internal power and ground planes. Allow 8 TTL SSO outputs per quadrant. one package pin. called an output group. Add another pair for the next group of 1-8 and another pair for the next group and so on. (See Table 3-16. Table 3-16 Sample Rules for Adding TTL Power and Ground PER TTL SSO ADD TTLPWR.Simultaneously Switching Outputs All AMCC arrays. two package pins. place the TTLPWR and TTLGND macros so that they are interspersed with the simultaneously switching outputs and can be bonded to the power or ground package plane.

. Example . do nothing do nothing add 1 add 1 add 2 add 2 Etc. Thermal diode macros also exist for the Q20000 Series for those cases where a second thermal diode measurement is felt to be necessary. (See Figure 3-8. do nothing add 1 add 2 add 3 add 4 add 5 The Q20000 Series requires one ECLVCC per additional 1-4 ECL SSO after the first group of four. Where there might be doubt.) One earlier version of the implementation also used one internal cell. additional thermal diode pairs can be added.AMCC thermal diodes (1994) Thermal diode macros exist for the Q14000 and Q5000 Series libraries and the de signer is required to add one thermal diode macro pair per circuit. The macros are treated as any other macro and are placed on interface cells. Using more than one was found to be unnecessary as the thermal gradient across the chips was found to be insignificant. No differences were found to exist between these two versions. These pads must be brought out to package pins. These pads are not accessible to any other macro function. All output counts are converted to "equivalent" 50 ohm outputs. Thermal Diodes As the arrays have become larger and dissipate more power. Each pair uses two I/O cells. The extremely high speeds of these arrays require design procedures to ensure minimal noise.) Table 3-17 Sample Rules for Adding ECL Power OR Ground PER ECL SSO ADD ECLVCC Q20000 Rules 0-4 4-8 9-12 13-16 17-21 21-24 Etc. have thermal diodes built into the base array. Newer arrays. such as the Q20000 Series. (See Table 3-17. macros have been developed that allow the designer to add one or more thermal diodes to the design. Some means of evaluating array junction temperature must be developed for each array series.reference ECL circuit (5V REF ECL) and a ground pad in a standard reference ECL circuit. thermal characterization becomes an increasingly important issue. The Q20000 Series arrays have a thermal diode structure embedded in the base and brought out to dedicated or fixed pads. For some of these series.

they may only need identification and routing connections rather than actual cell placement. if dual power supplies are not available would result in two-cell 25-ohm terminations. For very high speeds. For example. The singlecell 25 ohm ECL termination. a single-cell bidirectional macro limit would result in two-cell bidirectional macros being used for additional bidirectional signals. Testing may require that parts of the circuit are degated while other parts are being tested. doubling the cell and pad counts of those signals. These pads must be brought out to package pins. including the simultaneous enable-disable of three-state or bidirectional macros. VBB Reference voltages There are some instances where VBB reference voltages are desired.routable generators The designer is not usually concerned with the threshold generators. They will connect to external package pins. Speed and testing interface cell utilization Maximum speed of operation and testing requirements will have an affect on the final interface cell count. . where I/O utilization is high and the designer is using single-rail ECL where differential ECL is required. Test-enables may be required to partition the circuit for testing. differential ECL may be required by the array vendor. the Q20000 Series arrays each has a built-in AC speed monitor with two fixed pads assigned to it. In cases where they are required. Population or cell type limits and utilization Where population restrictions exist.Figure 3-8 Thermal Diode Pair The AMCC AC Speed Monitor AC testing is a problem for both the designer and the vendor and to reduce the problems associated with it. Threshold generators . These reference voltages are supplied with a macro and are placed on an interface cell. This will occur when a simultaneously switching group is very large. and test enables will use cells and pads. circumvention of the limits may include the addition of interface macros.

If this is not possible. Interface Cell Utilization (general) To find interface cell utilization. Added grounds use pads and disable the accompanying cell. . Final Interface Cell Utilization The final interface cell count for the circuit in its estimated stage should look at all the factors that could increase interface cell requirements. This is to provide a smaller option if I/O minimization can reduce the requirements and to provide a larger option should the interface requirements grow out of the original selection. If not. add the items in the list in Table 3-18.Placement restrictions High-frequency signals in particular will often require placement in specific cell locations and require that these macros be isolated with added grounds. the effects on cell utilization must be anticipated in the initial estimate. Table 3-18 Interface Cell Utilization Interface Cell Utilization cells for input signals cells for output signals cells for bidirectional signals cells for thermal diodes (I/O) cells for AC speed monitor (I/O) cells for reference generators cells blocked by added power pads cells blocked by added ground pads cells dedicated to fixed I/O signals Divide this sum by the number of interface cells available on the array of choice. with no more than 100% interface utilization for the final design. In the ideal situation. Where placement restrictions require the addition of macros or a change in the macros selected. then the interface utilization should be no more than 90% during development. an array chosen for a design should be somewhere in the middle of an array series. The interface cell utilization for a non-captured circuit should be less than 100% if possible to allow for adjustments and expansion. than the rest of the design must be completed using I/O cell utilization minimization as a priority design objective.

distortion-sensitive and high-speed paths should be designed with a derated fan-out load limit. .Interface cell utilization = (number of interface cells used by the circuit) / (number of interface cells available on the array) Example .e. either pads or cells may be rendered inaccessible. If an interface macro is driving too many loads. then PAD utilization may also be required. Macros will be specified with both fan-in and fan-out load limits. PAD utilization = (number of PADS used by the circuit) / (number of PADS available on the array) Fan-out load limits Internal cell usage will depend on the macros required to implement the desired functions. Assume that the breakpoint frequency is currently set at 400MHz. others are not. derate the fan-out load limit by 20% up to the breakpoint and 40% at or above the breakpoint frequency. all internal macros have the Turbo speed enhancement allowing a fan-out load limit of 18 loads. The TTL input and bidirectional input macros are the only interface macros that do not have this Turbo enhancement and their fan-out load limit is 9 loads. If internal macros are driving too many loads. These buffer trees use cells and current. hook-up and pin restrictions for those macros are evaluated. Example . Each AMCC array series is different in the value of the breakpoint frequency but each has the same basic rule. with macros operating well below their specified limits. Check with the array vendor for their definition. Certain macros placed on these structures are very efficient. The Q24008 and Q24280 arrays have 2-cell-1-pad structures. Refinements to that estimate come when the fan-out load limits. The fan-in numbers represent the load that the macro presents to the macro driving it.fan-out derating For the Q20000 Series. internal macro buffers will be needed to divide that load or additional interface macros will be needed. the same approach is used.. The algorithm requires a check on both cells and pads. For sensitive and clock paths. These arrays have a complex algorithm available to allow sizing. The fan-out limit is the number of loads that the macro can safely drive before signal degradation becomes a predominant factor. i. A load unit can be considered to be equivalent to one pico-farad. The array may be specified with a guideline as to the frequency . single-cell or multi-cell.BiCMOS Cell/PAD Utilization When an array does not have a one-to-one ration of I/O cells and pads. Derated fan-out load limits Clock paths. Depending on the macros used.derating schedule.

. Hook-up or interconnect restrictions Hook-up is used here to define the rules on grounding an input pin to a macro. there will be cases where specific macro pins are restricted. These drivers will use more current and more cells then the non-driver but fewer of them are required to drive the same load. For some arrays.0 . The ground symbol on the schematic is for human comprehension and to allow checking software to understand that the designer meant to leave the pin unattached. resulting in lower inter-macro delays for the same load than a non-driver macro could provide. As an example. Another feature of drivers should be considered. Whether or not the pins are allowed to float. When hook-up restrictions exist. For the Q20000 Series these pins are base input to transistors and when unused are tied to the emitter to ensure a logical low. a macro input pin connected to global ground on a schematic will mean that the pin "floats". the super-drivers and drivers will be seen to have a lower k-factor (drive factor) than the nondriver macros. these pins cannot be attached to global ground but must be driven low by another macro. Pin restrictions . The number added will depend on the number of loads that must be driven low or high.interconnect restrictions Some macros are pin-restricted in that they may not be freely connected to any other macro but much be driven by or drive a specific class of macro. or is unattached to anything when silicon is built.4) * 18 = 10 (truncated) Drivers Special driver macros may be provided in a library. these pins are physically attached to a confirmed logical low by connecting to a rail (CMOS) or by strapping the base to the emitter (bipolar) through conditional geometry. When timing analysis is performed. the derated fan-out load limit would be: (1. the pins were allowed to float. no exceptions. They are designed to provide a clean edge even when loaded to their rated limit.e. The result may be the same cell utilization and the same power. These "super-drivers" are not derated. For the Q5000 Series. Drivers may be interface macros or internal macros. i. CMOS and BiCMOS technologies require that all unused macro input pins (non-primary array inputs) be clipped to VDD or VSS. For others. some macro must be added to the schematic to drive these pins low (or high).0.For an ECL input toggling at 500MHZ. Bipolar technologies allow the unused input pins to be tied to global ground. TTL three-state outputs and TTL bidirectional macros in some macro libraries must have their . This is a hook-up restriction.

Exercises 1. the impact on cell utilization must be considered. three-state enable drivers may only be placed on interface I/O cells. or for cell utilization reduction for either interface or internal cells. For the selected series. they may not be used to drive other macros. pin restrictions.. etc. Any limits on outputs o TTL o ECL c. In the Q5000 library. Internal cell utilization = (number of internal cells used by the circuit) / (number of internal cells available on the array) Further changes Other factors that can change the estimated cell utilization include adjustments made for power reduction. List: • • • • • the processing technology available power supply configurations types of TTL input and outputs allowed types of ECL input and output allowed how bidirectional macros are handled 2. Any limits on inputs b. Any rules for simultaneously switching outputs Are the rules easy to find? 3. Internal cell utilization When the paths have all been checked for fan-out. how many fixed power and ground pads are on each array in the series? How are additional power and ground pads added? . Any limits on bidirectionals d. even when they are driven by internal signals. The three-state enable drivers can only be connected to drive these specific pins. Select a semi-custom array series (any). for speed enhancement. this is the sum of all the internal cells used divided by the number of internal cells available. leaving the pad unused in this case. what cell usage restrictions exist? • • • • • a. For the selected series. As stated in Chapter 2. hook-up restrictions. No other macro may drive that enable pin. placement rules.enable pins driven by a macro known as a three-state enable driver. When pin-restrictions cause the use of specific macros and these macros have restricted placements. the internal cell utilization can be estimated.

17 D flip/flops. carry-in). reset. Register: 32 D flip/flops. Given a 32-bit register. what types of cells are available on each array and how many of each type? 5. buffers and gates as required. Fast adder: four 4-bit fast adders with carry-propagate outputs. 16 DATAA and 16 DATAB inputs.4. 35 ECL inputs. size the design for the macro library for the selected array series.2V. buffers and gates as required. 35 ECL inputs (32 data. dual-power supplies of +5V and -5. 7. 8 D flip/flops)? 6. ECL is ECL 10K or ECL 10KH. dual ECLTTL outputs (32 TTL 3-state and 32 ECL. 35 ECL inputs. Assume a COMMERCIAL environment. How many internal cells would be required by the selected array series macros to implement an 8-bit barrel shift register (8 2:1 MUXs with 8 4:1 MUXs. ECL is ECL 10K or ECL 10KH. necessary controls (clock. 3-state enable). 17 outputs. For the selected series. Assume a MILITARY environment. added power and ground as required . Given a 16-bit fast adder design using carry-look ahead. same signals). 64 ECL outputs. reset. clock. added power/ground as required. 17 outputs (sum plus carry out). single -5.2V power supply. one 4-bit carry-look ahead unit. a registered output. size the design for the selected array series.

Q20000 Selecting a Flip/Flop .First Pass Selecting the ECL Output Clock Input 16:1 MUX Parity Tree Review Status so far Exercise Simultaneously Switching Outputs Fanout Loads ƒ Select Lines for 16:1 MUX ƒ Reset Loading ƒ Clock ƒ Static Driver Review of Size .Second Pass Package Size Problems Alternative Solution Power Further Thought The Schematics TARGET ARRAY: AMCC's Q20080 {Based on 1994 data} The following exercise is not intended as a practical circuit for actual construction on an array. See Figure A-1. It will be solved here using a Q20080 array as the intended target solution but could be solved with any macro library provided one of the supported arrays in that series can accommodate approx. however. . 160 I/O signals and toggle at 500MHz.Chapter 3 Appendix: Case Study in Sizing a Design o o o o o o o o o o o o o o o o o o Target Array: AMCC Q20080 (1994 Data) Solution . this exercise will examine nearly every design rule and restriction for the example array series.

The target maximum speed of operation is 500MHz. All 32 multiplexors are to have a common select. Each data input to the first flip/flop stage is to be driven by a 2:1 MUX.) .Figure A-1 Sample Classroom Exercise THE DESIGN Using the following list of requirements. (Design Objective. All flip/flops are required to be reset by way of a master reset signal. if possible. design a circuit using AMCC macros for the Q20000 Series and size the design to fit the Q20080 array in that series: A pipelined structure two flip/flops deep is to be 32 bits wide. The common clock is to be a differential signal. the inputs of which are driven by ECL 10KH inputs.

All input signals. The flip/flop output stage is connected to non-Darlington ECL 10KH outputs. which sets the I/O mode at 100% ECL with ECL 10K/KH inputs. A six-bit pass-through bus (input to output without logic) is included which uses ECL inputs and outputs.2V supply is allowed. Between them. This problem or a similar one will be referred to in other chapters. using the MIL5 library and annotation data. Note: Keep your data. The power supply parameter is set at STD5 for standard reference 5.2V single-supply circuit. Figure A-2 AMCC Icon for the Chip Macro . This structure is to be used for parametric testing.All dataA inputs (32 of them) are to be fed in groups of four into two 16:1 multiplexors. The chip macro is shown in Figure A-2. Pick an array from the series that would fit the design.Q20000 Check for I/O mode and power supply.2V supply. SOLUTION . There are four common select lines for the two 16:1 multiplexors and two outputs. Both true and complementary outputs are to be brought out to external pins. controlled by enables (one per signal). The product grade parameter is set at MIL for military. standard reference ECL -5. Perform all required population checking for that series. Exercise Review the selected design manual. data and controls. are to be fed into a parity tree. a gate tree that will produce a single output. these parameters define this circuit as a MIL5 circuit. The AMCC chip macro is Q20080ECL10K. select macros and compute cell utilization. This is a military. This is a 100% ECL circuit and uses no Darlingtons so that a single -5.

For the chosen Q20000 macro library. The second stage flip/flop needs a reset and at this stage in the design process needs both Q and QN outputs. The use of a 2:1 MUX flip/flop combination will further reduce the choices for the first stage of the circuit. FF10S was chosen as the appropriate macro. FF46S is a D flip/flop with a 2:1 MUX on the data input and an asynchronous reset. See Figure A-3.first pass The need for a master reset will reduce the set of available flip/flop macros that could be used to those with a synchronous or asynchronous reset (or set). Figure A-3 MUX and two F/Fs in Two Macros .Selecting a flip/flop . It is more silicon-efficient to use a combination MUXF/F macro than to implement the design with individual multiplexor and flip/flop macros.

output enables and data) except the clock will use the IE93S. The clock will have two loads. This option would use three loads on the Y path. the IE94 version with only the Y output could have been chosen. 32 dataA and 32 dataB. There are 64 data inputs. selects.Selecting the ECL input All inputs (reset. . Each macro uses one I/O cell and one pad. use IE31H.) Table A-1 Required IE93S Inputs 32 data A 32 data B 1 reset control 5 data MUX control select 2 output enables (MUX outputs) 6 pass-through inputs 78 IE93S inputs Clock input The clock input will use IE34H. plus one select for the input 2:1 MUX. It uses two I/O cells and two pads. In another instance. (See Table A-1. a simple buffered input that produces both Y and YN outputs shown in Figure A-4. two to the main circuit (register input and 16:1 MUX input) and one to the parametric tree. To reduce power. the reduction of one load could be the difference between meeting or failing specification. The YN output will be used to input to the gate tree to keep loading off the Y path. and four for the 16:1 MUX controls (and four 16:1 MUXs) for a total of 82 IE93S macros. a differential high-speed input with a Y and YN output. the saving of one load is not significant in that the loads are not in the critical path. Figure A-4 Output Macro with Complementary Outputs For this circuit. For CML-compatible input. The clock is in the critical path.

two MUX outputs and an output for the parametric gate tree for a total of 73 outputs. a macro that supplies steady HIGH and LOW signals when unused macro pins cannot be "clipped" low or allowed to float. Each OE42S uses one I/O cell and one pad. rated for 350MHz. (This macro was the only 50 ohm non-Darlington termination in the initial release of the library. the IE32D would be the choice for a speed upgrade. The other option is to have a custom 50 ohm macro created. not worth the effort for the case study but something that should be reviewed in a real circuit where power and cell space are at a premium. If the IE34H proves to be too slow or the inter-macro delays too long. The OE42S enable is tied low by way of the GT87D static driver. a NOR-input 50 ohm termination. a cut-off (ECL output with an enable) macro used with the enable tied low (always on) except for the two controlled outputs. . The fan-out load limit for the GT87D is 50 loads so two will be required to supply the OE42S enable pins in this first version of the design. Note that the OE11S is easier to use and uses less power . Figure A-5 Differential Input Macro ECL outputs . There will be 64 data output for the pipeline.Other options that could be considered include the use of the driver version of the differential input. The basic module is shown in Figure A-6. The driver handles 32 loads and has k-factors with less skew than those of the H-option IE34H.reasons to consider challenging the initial solution. six outputs for the pass-through signals.first pass All outputs in the initial version of the circuit were the OE42S.) The (111) version of the library added OE11S. IE32D. The driver is shown in Figure A-5.

The basic design is shown in Figure A-7.Figure A-6 Macro Design Restrictions 16:1 MUX The 16:1 MUX is constructed from five MX21S macros. there will be 10 MX21S macros required. . Four of these will feed into the fifth to form the 16:1 MUX structure. This is the largest multiplexor in the first release. each a 4:1 MUX with two selects. Since there are two 16:1 MUXs. An 8:1 or 16:1 MUX MSI macro would simplify the design.

Figure A-7 Schematic Page for the 16:1 MUX Copyright @ 2001. The speed of the gate tree is not important since testing is functional at 100ns intervals. 2002 Donnamaie E. White Enterprises For problems or questions on these pages. contact dew@Donnamaie.com Parity tree A parity tree of all inputs (required for parametric VIL. White. VIH testing) can be formed from NOR gates using the GT60L or GT60S. . (The 78 data signals plus the clock are required. an 8-input NOR macro.) The parity tree is shown in Figure A-8. The first estimate for the tree is to use eleven GT60S macros in a three-level structure to accommodate the 79 input signals. The L-option is slower and uses less power.

Table A-2 First Sizing Estimates # MACROS Macro # I/O Cells Required 78 73 1 IE93S OE42S IE31H 78 73 2 TOTAL I/O CELLS: 153 .Figure A-8 Parity Tree REVIEW STATUS SO FAR The first sizing estimate provides the cell counts shown in Table A-2.

allowing a reduction in added ground. speed and power in making changes. By tagging the switching groups and the added power and ground macros that belong to the groups with a SWGROUP parameter or property. A total of 16 IEVCC macros is required for these outputs and each blocks off one I/O cell and uses one pad. create the same table for the chosen library. the AMCC MacroMatrix can check for sufficient added power and grounds. This is exactly the number of I/O cells available for circuit use on the . • • If the outputs switch within one macro delay (or within 2 ns.# MACROS Macro 10 11 32 32 MX21S GT60L FF10S FF46S # L Cells Required 20 33 96 96 TOTAL L CELLS: 245 The number of macros is not the same as the number of cells. For this design. the number of I/O cells used is 162. SIMULTANEOUSLY SWITCHING OUTPUTS Since 64 outputs are switching simultaneously in the worst case (master reset is one example). This is the minimum number of added power and grounds recommended for worst-case conditions. Allowing 8 IEVCC for the pipeline outputs (switching group AAA) and one for the rest of the circuit (switching group BBB). whichever is larger) of the other switching group additional IEVCC is required. (Changes should be made!) If you are designing with a different array series. even for the I/O macros. then the added IEVCC for this group will not be required. If they switch well separated in time from the other group. Consider size. Check for new MSI macros or new I/O macros that might be used in place of those selected (such as OE11S). Adding two more outputs for the 16:1 MUX Y outputs. assume that the groups are not simultaneously switching more than 32 signals. Exercise Check the cell counts against the current design manual for the Q20000 Series. six for the pass-through and one for the gate tree. requires two more IEVCC macros. nine IEVCC macros are required. Adding these 9 IEVCC macros to the previous counts (153 + 9). additional IEVCC macros (added ground) will be required according to the Q20000 Series design rules.

It will require engineering approval before design submission and could cause other problems later. One macro can drive 18 loads. Most macros in the Q2000 library will have a fan-in of one except for H-option macros that will have a higher fan-in (and larger cell size). Think about another solution! FAN-OUT LOADS The final step toward an estimate of circuit size requires that fan-out loads be examined. (See Figure A-10. adding a gate buffer tree such as two GT09S macros allows one primary input to drive 32 loads. Select lines to 2:1 MUX structure The select to the 2:1 MUX structure has 32 loads and will need buffering. No buffering is required for the IE93S macros that can drive 18 loads each. (This does not count the four fixed I/O signals for the AC Speed Monitor and the thermal diode that have pre-assigned PADs. Figure A-9 Added IEVCC Macro Note: Using less than the recommended number of added grounds is not a good idea.Q20080 array.) .) The added ground macro is shown in Figure A-9. Select lines for 16:1 MUX Select lines to each 16:1 have at most four loads. This is not always the case but should be considered when examining macro options.

Figure A-10 Buffer Tree for the 2:1 MUX (32 Loads) The other option is to switch the IE93S for an IE23D driver that can drive 32 loads directly. the signal goes to 64 flip/flops. eight GT09S macros were used to simplify the schematic design (eight pages are replicated). On the schematic. The AR pin for the FF46S is two loads and the AR pin for the FF10S is 1 load for a total of 96 loads. (See Figure A-11.) Figure A-11 Reset Signal Buffer Tree RESET STRUCTURE . The GT55D driver uses twice as much current as a GT09S macro and is twice as large. The IE23D driver uses twice as much current as an IE93S macro but would save the internal cells that the GT09S macros would have used. Since half as many are required. Reset loading RESET requires the same decision process. on comparing cell usage and power these two solutions are equivalent.ONE OPTION . In this case. Either six GT09S macros or three GT55D macros can provide the drive.

Four GT55D macros would provide the drive capability with full 40% derating down the path as shown in Figure A12. One is shown in Figure A-13. Two GT87D macros can be used. Clock trees have priority during layout. When the clock tree is to be constructed by the Place & Route software. In the near future. depending on the design constraints supplied to the Place & Route tool. derated. This structure is only one level in depth. Figure A-12 Clock Tree CLOCK STRUCTURE . approximating what the final clock tree behavior might be. The commands involve suggested buffer or macro to be used and clock tree depth. Current synthesis systems will create the necessary buffer trees to support the load being driven. for a total of 65 loads. Place & Route software today creates the clock tree structure based on the commands in a control script. The IE31H can drive 10 loads with a 40% derating. all timing analysis prior to the routing is done using a modeled clock. Floorplanners will incorporate this function. There are 64 loads from the flip/flops. Clock The clock is handled differently since all clock nets must be derated. The GT55D driver. Macro load limits are listed in the macro documentation. plus 1 load due to the parametric gate tree.Reset structures are often treated as clock structures without the need for speed. drives 19 loads and presents a fan-in load of two to the driving macro. Static Driver The static driver required to drive the always-on output enable inputs can handle 50 loads but 64 are required in this version of the design. .ONE OPTION Derating guidelines are part of the array design rules.

) The parity tree is shown in Figure A-8. Figure A-8 Parity Tree . high-drive options on various macros are used. If no one macro can handle the load to be driven. (The 78 data signals plus the clock are required. The speed of the gate tree is not important since testing is functional at 100ns intervals. The first estimate for the tree is to use eleven GT60S macros in a three-level structure to accommodate the 79 input signals. Parity tree A parity tree of all inputs (required for parametric VIL. then a buffer tree is constructed by the synthesis tool. an 8-input NOR macro. VIH testing) can be formed from NOR gates using the GT60L or GT60S. Rather. The L-option is slower and uses less power.Figure A-13 Static Driver Static driver is not a term that shows up in macro lists today.

Note: When vectors are written for this array. These are AMCC-specific vector design rules.SECOND PASS The revised estimate (one version of the solution) shows the circuit requirements as they are now understood.REVIEW OF SIZE . This fits into the Q20080 array that has 162 I/O cells and 2044 L cells. Table A-3 Second Sizing Estimates Number of Cells Required #macros 79 73 1 9 MACRO IE93S OE42S IE31H IEVCC CELLS 1 1 1 1 TOTAL 79 73 2 9 TOTAL I/O CELLS REQUIRED 162 10 11 10 4 2 32 32 MX21S GT60S GT09S GT55D GT87D FF10S FF46S 2 3 1 2 2 3 3 20 33 10 8 4 96 96 TOTAL L CELLS REQUIRED 267 Change OE42S to OE11S and delete the 2 GT87Ds. . This is a severely I/O-bound design (of course!). A design is either core-limited or I/O limited. they should be designed so that no more than 16-32 of the outputs switch at any one time.

If the clock is running at 500MHz. then the OE42S is not a correct choice if speed is to be maintained. The use of OE14S provides a cleaner solution (less skew) plus it frees internal cells. the outputs could be toggling slower. The truth is in the middle and is placement-dependent. and the 7 always-on enables could be driven by a GT08L NOR gate instead of a static driver macro.2GHz. The circuit uses nearly 8 Watts .much too high. One output pad can be used as the true signal and the other as the compliment. PROBLEMS • The OE42S is limited to a toggle frequency of 350MHz. . Neither is the OE11S! Insufficient added grounds are not a minor problem. The worst-case number of signal pins that could be required on a package for this circuit is 166 (162 signals plus the 4 fixed signals). The maximum frequency of the OE14S is 1. If not.Table A-4 AMCCERC Population ERC PACKAGE SIZE The minimum number of signal pins that should be available on a package for this circuit is 157 (162 signals plus the 4 fixed signals minus the 9 added grounds). • • ALTERNATIVE SOLUTION The differential output OE14S could be used in place of two OE42S macros and the GT87D driver (at least one) could be deleted. This reduces the OE42S macros from 73 to 9.

same conditions. power. what was provided.Another advantage is the reduced requirement for added grounds. . is estimated to be 5. the basic OE14S solution is the best pro-posed so far. FURTHER THOUGHT For cell usage.the algorithm defined by AMCC requires that two IEVCC macros be added. and added ground requirements. The 32 differential outputs count as 32 outputs and not as 64.) Reducing the GT08S macros to GT08L macros can further reduce power. The ninth IEVCC applies to the miscellaneous other outputs. The DC power computation for the OE14S version. Table A-5 OE42S Solution Table A-65 OE14S Solution IE93S 78 IE93S 78 OE42S 73 OE42S 9 OE14S 32 IE31H 1 IE31H 1 IEVCC 9 IEVCC 9 MX21S 10 MX21S 10 GT87D 2 GT87D 1 GT60S 11 GT09S 8 GT09S 8 GT55D 4 GT55D 4 FF10S 32 FF10S 32 FF46S 32 FF46S 32 POWER The DC power dissipation for the maximum worst-case MILITARY DC power for the OE42S version of the circuit was estimated to be over 8 Watts.88 Watts. (This number is based on the circuit as shown in the schematics and the February 1991 library specifications. There will be a warning issued by AMCCERC that there might not be sufficient added grounds for these miscellaneous outputs . reducing the requirement for this group to 8 added IEVCC. timing.

the options have different maximum frequency of operation numbers! This is often overlooked in choosing options. AC power computations required depend on the array series. .) The DC power computed by the AMCCERC program is summarized below. It uses GT60S macros in the gate tree instead of GT60L macros. Do the MUX and reset buffer trees need S-macros or could Loption macros be used? (Watch it .Table A-7 OE14S Solution Table A-8 OE14S Solution This version used GT87D instead of a GT08L. Remember AC power dissipation must be added to this.

THE SCHEMATICS Page 1 . Figure A-13) Page 3 .Table A-8b Macro Occurrence Report Continued Exercise Add a design objective to reduce power to 5 Watts or as close to it as possible and modify this circuit using the latest library information. Bi-squared MOS and CMOS. Buffer trees go to various pages. This same exercise was used in the AMCC training classes through several library releases.Clock tree.2:1 MUX selects and enable controls. bipolar.Using MX21S 4:1 MUX macros to built a 16:1 MUX. AAA is switch group tag. or one close to it. OE42S macros should be replaced and VLO signal deleted. OE42 should be changed. 6-bit input-output path. "40"s are FOD values. Note the inputs to the parametric gate tree. . Figure A-12. 2:1 MUX select tree. GT87D a static driver Page 2 .Chip Macro and added Ground (IEVCC for ECL VCC). It demonstrates nearly 85% of the array design rules. Constraints can drive area reduction. The frequency of operation requirement remains. Today's designers would create this circuit in Verilog or VHDL and a control script for the synthesis tool. Page 4 . was actually used for over eleven years with several technology libraries. The script can also set the priority for the different design constraints. Figure A-11. speed improvements or power reduction. (Figure A-10. RESET tree. This problem.

FF0905. etc. OE42S should be changed. Page 8 .this page should have been grouped with the other MUX page for better schematic set readability. Page 13 . Note output to parametric gate tree.Next four bits. AAA is the switch group tag (matches IEVCC on page 1). .to prevent duplicate names. Page 7 .Next four bits. Page 10 . Note how page references make it possible to trace the connections. (Figure A-8) Page 14 . Page 11 . FF0906.Next four bits. Page 12 . Group functions together.Next four bits.Page 5 . Note how the page number has been incorporated into the macro instance names .Last four bits for 32-bit registers. Page 9 .Next four bits.all inputs fed into a combinatorial gate tree and tied to one output.The second 16:1 MUX . PGATE is the GTO parameter value. (Figure A-7) .The parametric gate tree .Same as page 5 except for names.pipelined register: 2:1 MUX-D F/F FF46S feeds FF10S which drives OE14S. OE14S connection could be improved to remove need for VLO signal. Page 6 .

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