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2013-1339 (Reexamination Nos. 95/000,178 and 95/001,152)

IN THE

UNITED STATES COURT OF APPEALS FOR THE FEDERAL CIRCUIT ___________ RAMBUS, INC., v. MICRON TECHNOLOGY, INC., ___________

Appellant,

Appellee.

Appeal from the United States Patent and Trademark Office, Patent Trial and Appeal Board. ___________ REPLY BRIEF FOR APPELLANT RAMBUS INC. ___________ J. Michael Jakes James R. Barney Molly R. Silfen Aidan C. Skoyles FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP 901 New York Avenue, NW Washington, DC 20001 (202) 408-4000 October 7, 2013

Attorneys for Appellant Rambus Inc.

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TABLE OF CONTENTS I. II. INTRODUCTION ...........................................................................................1 REPLY TO MICRON’S ARGUMENTS ........................................................3 A. The Board May Not Rely on Its Own Presumed Expertise as a Substitute for Record Evidence When Deciding an Issue Affecting Patentability .................................................................3 The Board’s Conclusion that the “Precharge” Limitation Was Obvious in 1990 Is Not Supported by Substantial Evidence ................................................................................................4 1. The Board’s Construction of “Precharge Information” as “Non-Functional Descriptive Material” Was Erroneous ............................................................4 The Board Relied on Its Own Presumed Expertise Rather than Substantial Evidence in the Record.........................7 a. b. C. Bennett in View of Wicklund, Bowater, or Olson ...........7 iAPX in View of iRAM and Olson ................................17

B.

2.

The Board Erred in Finding that Synchronous DRAMs Were Obvious in 1990.........................................................................18 1. 2. 3. Rambus Did Not Waive the “Synchronous DRAM” Limitation by Appealing Only Dependent Claim 33 ................18 The Examiner Correctly Construed “Synchronous DRAM Device”.........................................................................21 The Board’s Finding that Bennett Renders Synchronous DRAMs Obvious Is Unsupported by Substantial Evidence .................................................................23 The Board’s Finding that iAPX and iRAM Render Synchronous DRAMs Obvious Is Unsupported by Substantial Evidence .................................................................25

4.

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D. III.

Micron’s Alternative Ground for Invalidity Based on JEDEC and Park Contradicts This Court’s Prior Decisions ...............27

CONCLUSION..............................................................................................31

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TABLE OF AUTHORITIES Page(s) FEDERAL CASES Ariad Pharmaceuticals, Inc. v. Eli Lilly & Co., 598 F.3d 1336 (Fed. Cir. 2010) (en banc) ..........................................................28 Bell Communications Research, Inc. v. Vitalink Communications Corp., 55 F.3d 615 (Fed. Cir. 1995) ..............................................................................21 Brand v. Miller, 487 F.3d 862 (Fed. Cir. 2007) ........................................................................4, 17 Broadcom Corp. v. Qualcomm Inc., 543 F.3d 683 (Fed. Cir. 2008) ............................................................................20 Celsis In Vitro, Inc. v. CellzDirect, Inc., 664 F.3d 922 (Fed. Cir. 2012) ............................................................................23 CIAS, Inc. v. Alliance Gaming Corp., 504 F.3d 1356 (Fed. Cir. 2007) ............................................................................ 5 Cimline, Inc. v. Crafco, Inc., 413 F. App’x 240 (Fed. Cir. 2011) .....................................................................20 Ex Parte Horito & Brown, No. 2010-009226, 2012 WL 4842863 (BPAI Sept. 27, 2012) ............................. 3 Hynix Semiconductor Inc. v. Rambus Inc., 645 F.3d 1336 (Fed. Cir. 2011) .........................................................................28 ICU Medical, Inc. v. Alaris Medical Systems, Inc., 558 F.3d 1368 (Fed. Cir. 2009) ..........................................................................28 In re Caveney, 761 F.2d 671 (Fed. Cir. 1985) .............................................................................. 3 In re Gartside, 203 F.3d 1305 (Fed. Cir. 2000) ........................................................10, 13, 15, 18 In re Jolley, 308 F.3d 1317 (Fed. Cir. 2002) ............................................................................4 iii

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In re Lowry, 32 F.3d 1579 (Fed. Cir. 1994) .............................................................................. 6 In re Ngai, 367 F.3d 1336 (Fed. Cir. 2004) ............................................................................ 6 In re Rambus Inc., 694 F.3d 42 (Fed. Cir. 2012) ..............................................................................21 Jet, Inc. v. Sewage Aeration Systems, 223 F.3d 1360 (Fed. Cir. 2000) ..........................................................................19 LizardTech, Inc. v. Earth Resource Mapping, Inc., 424 F.3d 1336 (Fed. Cir. 2005) ..........................................................................28 Rambus Inc. v. Hynix Semiconductor Inc., 2004 WL 2610012 (Nov. 15, 2004 N.D. Cal.) .................................................... 5 Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081 (Fed. Cir. 2003) ....................................................................28, 29 Rambus Inc. v. Rea, ___ F.3d ___, 2013 WL 5312505 (Fed. Cir. Sept. 24, 2013) .......................12, 16 Sage Products, Inc. v. Devon Industries, Inc., 126 F.3d 1420 (Fed. Cir. 1997) ........................................................................ 3-4 Verizon Services Corp. v. Vonage Holdings Corp., 503 F.3d 1295 (Fed. Cir. 2007) ..........................................................................20 FEDERAL STATUTES 35 U.S.C. § 315(b) (2002) .......................................................................................27 35 U.S.C. § 317(a) (2002) ........................................................................................27 FEDERAL RULE 37 C.F.R. § 41.77(b)(2) (2012) ................................................................................31

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I.

INTRODUCTION As Micron concedes, the base references lack at least two limitations

required by claim 33—(1) synchronous DRAM and (2) combining a read request and precharge information into a single operation code. (See Micron Br. 24-25 (admitting that the base references would need “modification” to include these limitations).) The examiner correctly found, based on substantial evidence in the record, that it would not have been obvious in 1990 to modify Bennett or iAPX to include both of these features. In contrast, the Board’s opposite conclusion lacks substantial evidence in the record. Much of Micron’s discussion of precharging is either factually unsupportable or irrelevant. For example, Micron repeatedly argues that

Wicklund, Bowater, and Olson—despite no disclosure of and, indeed, basic incompatibility with the concept—disclose “automatic precharge,” as taught in the ’120 patent. (Id. at 12-14, 38.) As the examiner found in a related proceeding, this is simply untrue. (See, e.g., A3553 (“Wicklund precharges prior to the writing of data that is at a new address and not automatically after data is written.” (emphasis added)).) Micron also trumpets the irrelevant fact that “precharge was a well-known feature prior to the filing of the ’120 patent.” (Micron Br. 22.) Yet Rambus has never suggested otherwise. What was not known, and what is not disclosed in any 1

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of the six references cited by the Board, was the concept of combining precharge information with a read instruction in a single operation code sent to a DRAM in advance of a read operation, as recited in claim 33. Because a read operation must be complete before any precharge operation can happen, this novel combination command relies on the DRAM itself to properly self-time a read followed by a precharge sequence when requested—a task that had always before been left to the DRAM’s controller. Regarding the “synchronous DRAM device” limitation, Micron

mischaracterizes Rambus’s argument. What Rambus has argued, and what the examiner correctly found, is that (1) Bennett does not disclose the use of DRAM as a memory User, and (2) if one skilled in the art in 1990 were to use DRAM as a memory User in Bennett, it would be as an array of asynchronous DRAMs with a dedicated controller and secondary bus, precisely as taught in Wicklund, Bowater, and Olson. As a fallback, Micron argues that Rambus somehow waived the “synchronous DRAM” argument by not appealing independent claim 26 and instead appealing only dependent claim 33. Yet claim 33 also includes the

“synchronous DRAM” limitation, and Rambus’s principal brief is replete with arguments proving that this issue has not been waived. In essence, Micron seeks to punish Rambus for doing what this Court has long encouraged appellants to do— 2

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narrow the issues for appeal. Micron cites no legal authority for its novel “waiver” argument. Finally, as an alternative ground for affirmance, Micron argues that the Board should have found that the ’120 patent was not entitled to its priority date, and that JEDEC and Park render claim 33 invalid. Micron is not entitled to raise this argument, however, because it was not part of its reexamination request. Moreover, the examiner and the Board properly found that the ’120 patent is entitled to its priority date. II. REPLY TO MICRON’S ARGUMENTS A. The Board May Not Rely on Its Own Presumed Expertise as a Substitute for Record Evidence When Deciding an Issue Affecting Patentability

Micron’s characterization of the Board’s role is incorrect. (Micron Br. 30-31.) As a reviewing body, “[t]he Board reviews facts found by the Examiner to determine whether those facts are supported by a preponderance of the evidence.” Ex Parte Horito & Brown, No. 2010-009226, 2012 WL 4842863, at *2 (BPAI Sept. 27, 2012) (citing In re Caveney, 761 F.2d 671, 674 (Fed. Cir. 1985)). A preponderance-of-the-evidence review is not the same as a de novo review. Thus, the Board cannot simply ignore findings of the examiner that it disagrees with; it must show that any such findings are unsupported by a preponderance of the evidence. Id.; see also Sage Prods., Inc. v. Devon Indus., Inc., 126 F.3d 1420,

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1426 (Fed. Cir. 1997) (“No matter how independent an appellate court’s review of an issue may be, it is still no more than that—a review.”). Micron contends this is merely a situation where “the evidence in the record will support several reasonable but contradictory conclusions.” (Micron Br. 34 (citing In re Jolley, 308 F.3d 1317, 1320 (Fed. Cir. 2002)).) But this is not such a situation because the examiner’s specific findings—i.e., that a person of ordinary skill in the art in 1990 would not have been motivated to modify Bennett or iAPX in the manner suggested by Micron—can only support nonobviousness. There is no “reasonable” conclusion of obviousness that can be drawn from the existing record, which includes the examiner’s findings and the unrebutted expert declarations submitted by Rambus. (Fed. Cir. 2007). B. The Board’s Conclusion that the “Precharge” Limitation Was Obvious in 1990 Is Not Supported by Substantial Evidence 1. The Board’s Construction of “Precharge Information” as “Non-Functional Descriptive Material” Was Erroneous See Brand v. Miller, 487 F.3d 862, 869

Micron states that “the Board’s non-functional descriptive interpretation of ‘precharge information’ . . . was raised by the Board as an alternative ground.” (Micron Br. 32 n.10.) Although this is true for the Board’s analysis of Bennett in view of Wicklund, Bowater, or Olson (see A59), it is not true for the Board’s

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analysis of iAPX in view of iRAM and Olson (see A62-63).

For the latter

rejection, the Board began with its flawed “nonfunctional” construction of “precharge information” and only gave the term substantive meaning in its alternative analysis. (Id.) Micron also claims “the Board did not conclude that the ‘precharge information’ limitation ‘need not be present in the prior art’ as Rambus suggest[s].” (Micron Br. 42.) This is incorrect. The Board specifically held that “[s]uch nonfunctional descriptive material . . . fails to render claim 33 patentably distinct over iAPX and iRAM (i.e., with or without the added teachings of Olson).” (A62 (emphasis added).) In other words, under its erroneous “nonfunctional” construction, the Board assumed that a reference such as iAPX or iRAM could anticipate claim 33 even without disclosing precharge information. In any event, Micron fails to explain how the Board’s “nonfunctional” construction is proper. The mere fact that claim 33 is an apparatus claim, as Micron notes, does not mean “precharge information” cannot be a substantive limitation. See, e.g., CIAS, Inc. v. Alliance Gaming Corp., 504 F.3d 1356, 1361-62 (Fed. Cir. 2007) (construing “unique authorized information” in an apparatus claim); see also Rambus Inc. v. Hynix Semiconductor Inc., 2004 WL 2610012, *5 (Nov. 15, 2004 N.D. Cal.) (construing “precharge information” in claim 33 as having substantive meaning). Moreover, Micron is wrong that “the operation of 5

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the claimed memory device does not change whether or not it receives any precharge information.” (Micron Br. 43.) To the contrary, the operation of the claimed memory device does change because, upon receiving precharge information along with a read request, the device has the ability to automatically precharge without blocking the bus and waiting for a separate control signal—a significant improvement over the prior art. Micron again cites In re Ngai, 367 F.3d 1336 (Fed. Cir. 2004)—a “printed matter” case—in support of the Board’s construction, yet it fails to address the holding of In re Lowry that “[t]he printed matter cases have no factual relevance where ‘the invention as defined by the claims requires that the information be processed not by the mind but by a machine, the computer,” 32 F.3d 1579, 1583 (Fed. Cir. 1994) (emphasis in original) (citation omitted). Here, Micron does not dispute that the claimed “precharge information” is processed not by a human but by an electronic memory device requiring precharge information to function. Nor does Micron dispute that the Board’s “nonfunctional” construction would render claim 33 superfluous, contrary to this Court’s claim-differentiation doctrine. (See Rambus Br. 51.) Accordingly, this Court should reject the Board’s “nonfunctional” construction of the “precharge information” limitation.

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2.

The Board Relied on Its Own Presumed Expertise Rather than Substantial Evidence in the Record

Micron contends “the Board based its decision [regarding the precharge limitation] on substantial evidence from the record,” citing six specific “factual findings” the Board allegedly made. (Micron Br. 33-34.) It is clear, however, that these alleged “factual findings” were based not on substantial evidence, but rather on the Board’s own presumed expertise. Moreover, key aspects of these alleged “findings” are wrong. a. Bennett in View of Wicklund, Bowater, or Olson

In addressing the proposed rejection of claim 33 based on Bennett in view of Wicklund, Bowater, or Olson, the Board’s entire “factual” analysis was as follows: [B]ased on this record, absent specific recent and relevant findings by the Examiner, Micron also persuasively demonstrates the obviousness of adding the precharge information as recited in claim 33 based on the further teachings of Wicklund, Bowater, or Olson. . . . Wicklund shows, in a similar fashion to the ’120 patent, that precharge normally (i.e., when the DRAM is not in page mode) occurs at the end of a read or write function, showing the obviousness of banding the two related functions into Bennett’s write code. (Compare Wicklund col. 3, ll. 45-52 with ’120 patent, ll. 16-24.) Also, Bennett discloses multiple functions in a code. (See Bennett Fig. 34 (read-modify-write code signifying multiple functions).)

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(A58.)1 Far from basing its analysis on substantial evidence in the record, the Board instead relied on the absence of “specific recent and relevant findings by the Examiner” on this topic. (Id.) It then proceeded to fill this alleged gap with its own “findings” based on Micron’s attorney arguments. Those alleged “findings,” however, are factually wrong and contrary to the record. It is first necessary to unpack the Board’s erroneous statement that “Wicklund shows . . . that precharge normally (i.e., when the DRAM is not in page mode) occurs at the end of a read or write function, showing the obviousness of banding the two related functions into Bennett’s write code.” (Id.) A major defect in this statement is hidden in the parenthetical, “(i.e., when the DRAM is not in page mode).” This statement is nonsensical because “page mode” and “normal mode” are Wicklund’s controller policies for operating a page-mode DRAM, not internal DRAM modes. Whether Wicklund’s controller is following a page-mode or normal-mode policy, it still accesses the DRAM using the same RAS and CAS signals, and must obey the same DRAM timing constraints. (See A1733-34[2:253:9].) Thus, precharging does not “normally” occur in Wicklund’s DRAMs “at the end of a read or write function,” as the Board erroneously asserted. Instead, precharge cannot be initiated in Wicklund until the read or write function is The remainder of the Board’s analysis was based on its erroneous legal conclusion that “precharge information as recited in claim 33, constitutes nonfunctional descriptive material.” (A59.) 8
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complete, and the Wicklund controller, not the asynchronous DRAM, determines the timing. Nothing in Wicklund (nor in Bowater or Olson) proposes changing this conventional, asynchronous DRAM operation such that a DRAM would “precharge normally (i.e., when the DRAM is not in page mode) . . . at the end of a read or write function.” The Board, relying entirely on Micron’s attorney argument, simply “found” a teaching in Wicklund that is actually not present in the reference. Indeed, as the examiner correctly found in the ’037 reexamination (referring to a write operation), “at best, Wicklund discloses that precharging occurs some time after the writing of data, however this does not disclose automatically precharging after writing data and wherein this precharging instruction came within the same operation code as the specifying of the sampling of the data to be written.” (A3538 (emphasis added); see also A3553 (“Wicklund precharges prior to the writing of data that is at a new address and not automatically after data is written.” (emphasis added)).) Given this understanding of Wicklund, there is simply no factual basis for the Board’s conclusion that Wicklund “show[s] the obviousness of banding the two related functions [i.e., a read request and precharge instruction] into Bennett’s write code.” (A58.) Indeed, that concept is entirely nonsensical in the context of Wicklund’s asynchronous system, which signals precharge using the opposite RAS signal as required during a read, making it impossible to combine the two signals. 9

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(See Rambus Br. 15-17.)

Thus, not surprisingly, the Board cites no expert

testimony and no examiner findings to support its erroneous conclusion. Instead, the Board cites only: (1) Wicklund at column 3, lines 45-52 (discussing irrelevant “refresh,” which the Board later claimed it was not relying on (see A26 (“the Board does not rely on refresh specifically”)); and (2) Bennett’s Figure 34 (A1357 (showing a read-modify-write command)). (A58.) These two isolated citations do not constitute substantial evidence supporting the Board’s obviousness conclusion based on Bennett in view of Wicklund. Regarding Bowater and Olson, although the Board cited these secondary references along with Wicklund in its decision (see A58), it never actually discussed them as part of the rejection of claim 33 over Bennett. (A58-59.) Accordingly, substantial evidence does not support any obviousness finding based on Bennett in view of Bowater or Olson. See In re Gartside, 203 F.3d 1305, 1314 (Fed. Cir. 2000) (“We have expressly held that the Board’s opinion must explicate its factual conclusions, enabling us to verify readily whether those conclusions are indeed supported by ‘substantial evidence’ contained within the record.”). In its rehearing decision, the Board repeated its assertion that, in the prior art, “precharge normally (i.e., when the DRAM is not in page mode) occurs at the end of a read or write function.” (A26.) For support, the Board cited only to its own prior decision rather than to anything in the record. And as noted above, the 10

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Board expressly abandoned one of its earlier “supporting” citations, namely its citation to Wicklund’s “refresh cycle.” (See id. (“the Board does not rely on refresh specifically”).) This leaves virtually nothing besides the Board’s own opinion to support the erroneous assertion that precharge “normally” occurs at the end of a read operation in the prior art (and, by inference, the DRAM has a way of knowing the controller policy in non-page mode)—a critical (but incorrect) assumption underpinning the Board’s entire obviousness analysis. In its rehearing decision, the Board also dismissed Rambus’s argument that, in the prior art, a read operation and precharging were accomplished using two separate, unrelated signals. (A27.) While acknowledging that these signals were indeed separate, the Board asserted that they were nevertheless “intimately related in the prior art with one normally following the other . . . .” (Id.) Again, this is factually incorrect and unsupported by substantial evidence, as explained above. In Wicklund, a read operation is not followed by precharging if the prediction algorithm determines that the next access will likely be in page mode. Thus, there is no evidence to support the Board’s assertion that read and precharging are “intimately related” in the prior art with “one normally following the other.” (Id.) Moreover, the Board erroneously ignored the unrebutted testimony of Mr. Murphy, who explained that a person of ordinary skill in the art in 1990 would not have modified Bennett in the manner suggested by Micron: 11

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The combination suggested by the Requester would not work since the processors in Bennett that issue reads and writes have no idea where the page boundaries are in the devices on the memory cards that they access. Even assuming that some of those devices are DRAMs, the processors would have no idea as to whether precharging should occur. (A2484.) In its rehearing decision, the Board dismissed this expert testimony as follows: Rambus . . . does not explain why ordinarily skilled artisans would have been unable to add additional logic which may have been required. Further, the claims at issue neither require a large system nor a page mode. In any event, a controller issuing a simple instruction involving a normal read and precharge would not have been required to be aware of page boundaries which might occur in page mode. (A27.) Notably, the Board cited nothing to support its opinion that a controller in a modified Bennett system “would not have been required to be aware of page boundaries.” (Id. (citing nothing).) Nor did the Board cite any evidence to support its sub silentio assertion that “ordinarily skilled artisans would have been []able to add additional logic which may have been required.” (Id.) Instead, the Board erroneously put the burden on Rambus to disprove this fact, directly contrary to this Court’s recent guidance. Rambus Inc. v. Rea, __ F.3d __, 2013 WL 5312505, at *6 (Fed. Cir. Sept. 24, 2013) (“The Board erroneously placed the burden on

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Rambus to prove that its claims were not obvious.”). Hence, this portion of the Board’s opinion is clearly unsupported by substantial evidence. Micron now attempts to overcome this lack of substantial evidence. First, it contends it did not need to submit its own rebuttal expert testimony because “the teachings in the prior art and other evidence provided any necessary rebuttal.” (Micron Br. 34.) But, as explained above, the Board did not rely on any such “other evidence” (see A27 (citing nothing)), so it is impossible to discern from the record the basis for the Board’s unsupported opinion that a modified Bennett system containing DRAM memory would not have needed to be aware of page boundaries. Cf. Gartside, 203 F.3d at 1314 (requiring the Board to “explicate its factual conclusions”). Next, Micron attempts to rebut Mr. Murphy’s expert testimony with its own attorney argument, asserting that Bennett discloses a Versatile Bus Interface and memory on the same chip, such that read and precharge instructions allegedly would have been generated from the same source. (Micron Br. 35.) This attorney argument, however, is based on Micron’s conflation, discussed infra § II.C, of DRAM memory chips and VLSICs. Bennett discloses attaching a very large-scale integrated circuit (VLSIC) directly to its primary bus, but that chip does not necessarily include memory at all—and certainly not DRAM. (A1640[101:50-54]

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(simply showing Bennett’s use of a synchronous bus connected to its Users, but none of those Users is a DRAM or even a memory chip); A2478[¶¶63-64].) Micron also asserts via attorney argument that “CPUs can and do send DRAM-specific instructions to memory devices,” citing Wicklund, Bowater, and iAPX. 2 (Micron Br. 36.) The cited portions of Wicklund and Bowater are

irrelevant, however, because they do not pertain to a CPU sending a precharge instruction to an individual DRAM, as the Board’s unsupported opinion would require. Instead, Micron points only to an irrelevant discussion of “refresh” in Wicklund (A1734[4:61-62]) and a timer “preset” value in Bowater (A1752[7:6265]). As for the cited portion of iAPX, it actually teaches away from CPU-control of DRAMs because the “added overhead” in such an arrangement would “limit the full CPU processing capabilities and overall system performance.” (A2156.) In any event, there is simply no evidence in the closed record suggesting that a person of ordinary skill in 1990, reading Bennett, would have been motivated to implement DRAM as a memory User and put each individual DRAM chip under CPU control and combine read instructions and precharge information into a single

Micron incorrectly states that Bennett sends “DRAM-specific instruction to memory devices.” (Micron Br. 36.) This is clearly false since Bennett does not disclose DRAMs at all, and Micron’s citation to “A1734(Bennett at 4:61-62)” (id.) is actually to Wicklund, not Bennett. 14

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operation code. Without such substantial evidence in the record, the Board’s obviousness rejection cannot stand. See Gartside, 203 F.3d at 1314. Micron next points to Bennett’s “embodiment of a simple interconnect where the only two devices connected to the Versatile Bus are a processor and a single slave memory device.” (Micron Br. 36.) According to Micron’s attorney argument, “in this simple two-device configuration, the processor must be aware of memory specific attributes, such as page boundaries . . . .” (Id. (emphasis added).) Yet there is no teaching in Bennett that this “single slave memory device” would include DRAM, let alone be a single DRAM chip. Instead, as Micron’s own expert in a prior litigation conceded, to the extent Bennett’s “slave memory” comprised DRAM, it would have taken the form of a memory card containing multiple DRAM chips and a memory controller. (A3683; see also A2442[¶105] (Mr. Murphy explaining same).) Thus, Micron’s reliance on the “single slave memory device” does not support its attorney argument that Bennett’s CPU would be aware of page boundaries in an individual DRAM chip. Micron also challenges Rambus’s argument that Wicklund, Bowater, and Olson teach away from the claimed invention. (Micron Br. 37.) Micron asserts that “Rambus cannot point to a single citation from the prior art that teaches away from combining a read instruction and precharge information into a single operation code.” (Id.) In fact, however, the very nature of these asynchronous 15

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prior-art systems teaches away from combining a read instruction with precharge information because these events must be separated in time and physically cannot be combined into a single instruction because they require conflicting signaling. (See Rambus Br. 15-17.) Micron does not deny this but, instead, improperly attempts to shift the burden to Rambus to prove the opposite: “Rambus . . . has not provided any evidence that it would have been impossible or even difficult to implement known memory controls in asynchronous systems into a synchronous system.” (Micron Br. 40.) Micron has it backwards. It was Micron’s and the Board’s burden to show that these modifications were feasible and would have been within the technical grasp of the skilled artisan in 1990. See Rambus,

2013 WL 5312505, at *6. Micron has pointed to no record evidence to support this burden. As a fallback, Micron points to the refresh cycle in Wicklund and the pagemode timer in Bowater and incorrectly asserts that “Micron argued—and the Board agreed—[that] it would have been obvious to provide an instruction with an operation code to automatically precharge while in page mode to prevent data from being corrupted.” (Micron Br. 39.) Yet there is no indication that the Board “agreed” with either argument. Indeed, the Board never mentioned Bowater’s page-mode timer in its opinion (A25-27; A58-59), and it expressly stated it was not

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relying on Wicklund’s refresh cycle (A26 (“the Board does not rely on refresh specifically”)). b. iAPX in View of iRAM and Olson

The Board’s “factual” analysis of iAPX in view of iRAM and Olson contains not a single citation to the record. (See A28-29; A62-63.) Nor does this “factual” analysis provide any explanation as to why the examiner’s opposite conclusion should be disregarded. (A28-29; A62-63.) This alone warrants

reversal of the Board’s iAPX/iRAM/Olson rejection. See Brand, 487 F.3d at 868 (“Under the substantial evidence standard of review, [the Court] search[es] for evidence, clearly set forth in the record below, to justify the conclusions that the Board has drawn.” (emphasis added)). Here, the Board merely set forth its own opinion, devoid of factual support (and indeed rebutted by the examiner’s findings), as to why it was allegedly obvious to a skilled artisan in 1990 to combine iAPX, iRAM, and Olson to arrive at the claimed invention. Micron responds, as it did below, with attorney argument. It notes that “Olson’s memory controller selectively activates control signals MEMPAGE and MEMCYCLE to control precharging of the memory” and concludes from this that “it would have been obvious to send this beneficial precharge information with the existing operation codes in Bennett or iAPX.” (Micron Br. 39-40.) But like the Board, Micron is unable to point to anything in the record to support this 17

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conclusion. For instance, Micron failed to elicit any expert testimony during the reexamination to support its attorney argument that the specific combination of iAPX with iRAM and Olson would have been obvious to a person of ordinary skill in the art in 1990. In contrast, Rambus submitted the expert testimony of Mr. Murphy showing that it would not have been obvious to combine a read instruction and precharge information in the same operation code in iAPX or iRAM because, inter alia, those two signals would have been generated by different parts of the system. (A2442[¶105]; A2467[¶29].) As with Bennett, the Board’s rebuttal of this

testimony must be rejected because the Board failed to cite any record evidence to support its opinion. See Gartside, 203 F.3d at 1314. C. The Board Erred in Finding that Synchronous DRAMs Were Obvious in 1990 1. Rambus Did Not Waive the “Synchronous DRAM” Limitation by Appealing Only Dependent Claim 33

Micron contends Rambus waived its right to rely on the “synchronous DRAM device” limitation in dependent claim 33 because it elected not to appeal independent claim 26, which also contains that limitation. (Micron Br. 44.) This is incorrect. By electing to appeal only dependent claim 33, Rambus did what this Court has long encouraged appellants to do—limit the issues for appeal. Specifically, in

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the current posture of the case, if this Court reverses the Board on “precharge,” it need not reach the “synchronous DRAM” limitation because claim 33 would be allowable based on the “precharge” limitation alone. The Court need only reach “synchronous DRAM” if it affirms the Board on “precharge.” In contrast, had Rambus also appealed claim 26, the Court would have been forced to address both limitations in any event. Thus, Rambus has narrowed the issues for appeal by presenting “synchronous DRAM” only as an alternative ground for reversal—it has not waived that limitation. Micron cites no authority for the proposition that appealing only a dependent claim in an inter partes reexamination precludes reliance on any limitations contained in the corresponding independent claim. Micron cites only

Jet, Inc. v. Sewage Aeration Systems, 223 F.3d 1360 (Fed. Cir. 2000), which is inapposite. In Jet, this Court held that “an earlier [trademark] infringement action does not bar, under the doctrine of claim preclusion, a later petition for cancellation.” Id. at 1365. The Court then remanded for a determination of whether issue preclusion might apply. Id. at 1365-66. But here, neither claim preclusion nor issue preclusion can apply because this is not a “later proceeding,” as Micron incorrectly asserts. (Micron Br. 44.) This appeal is part of the same reexamination proceeding in which Rambus has consistently asserted the “synchronous DRAM” argument for claim 33. 19

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By analogy, a patentee who asserts only a dependent claim against an accused infringer is not immediately barred from doing so merely because the corresponding independent claim is unasserted, even though the independent claim would necessarily be infringed if the dependent claim is infringed. In fact, this is a routine practice. See, e.g., Broadcom Corp. v. Qualcomm Inc., 543 F.3d 683, 688 (Fed. Cir. 2008) (patentee asserting only dependent claim); Verizon Servs. Corp. v. Vonage Holdings Corp., 503 F.3d 1295, 1299 (Fed. Cir. 2007) (same); Cimline, Inc. v. Crafco, Inc., 413 F. App’x 240, 241-42 (Fed. Cir. 2011) (unpublished) (same). Because Rambus elected to appeal only dependent claim 33 as a way to narrow the issues for appeal, and because it clearly did not intend to waive the “synchronous DRAM” limitation (indeed, Rambus dedicated a significant portion of its opening brief to that issue), a finding of waiver would be inappropriate. Micron is incorrect that “additional confusion” would result if this Court were to overturn the Board’s obviousness ruling for claim 33 based on “synchronous DRAM,” while leaving the Board’s rejection of claims 26 and 29 intact. In that scenario, claim 33 (but not claims 26 or 29) would be included in the reexamination certificate, and this Court’s “synchronous DRAM” ruling would be controlling precedent going forward, trumping any contrary ruling of the Board. There would be no “confusion,” as Micron asserts. 20

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2.

The Examiner Correctly Construed “Synchronous DRAM Device”

Micron contends the examiner erred in his claim construction of “synchronous dynamic random access memory [DRAM] device” as requiring a single, synchronous DRAM chip. (Micron Br. 45.) First, Micron argues the term is not limiting because it is recited only in the preamble. (Id.) But as the Board correctly held, “the memory device” appears in the body of the claim and clearly relies on the preamble for its antecedent basis. (A56 n.17.) Thus, the

“synchronous DRAM device” limitation breathes life into the body of the claim by defining what is later referred to as “the memory device.” Accordingly,

“synchronous DRAM device” is a limitation of the claim and cannot be ignored as Micron seeks to do. See Bell Commc’ns Research, Inc. v. Vitalink Commc’ns Corp., 55 F.3d 615, 621 (Fed. Cir. 1995). As a fallback, Micron contends the words “synchronous dynamic random access” merely modify “memory device,” which this Court construed in In re Rambus Inc., 694 F.3d 42, 46-49 (Fed. Cir. 2012), as not being limited to a single chip. But the intrinsic evidence—and the unrebutted findings of the examiner— show that “dynamic random access memory” or “DRAM” has a well-established meaning that refers to a chip. Indeed, the examiner specifically rejected the very argument Micron is now making, i.e., that a “synchronous DRAM device” can be a collection of DRAM chips connected to a memory controller, as would be 21

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encompassed by this Court’s construction of the broader term “synchronous memory device”: While the Examiner agrees that the term “memory device” is not limited to a single chip, the Examiner notes that with respect to “synchronous dynamic random access memory device,” the specification refers to this as a DRAM device. As will be further explained below a DRAM is disclosed to be a memory chip. The Requester . . . argues that a synchronous “dynamic random access memory device” is different than a synchronous DRAM chip, however nothing within the ’120 patent specification discloses that a dynamic random access memory device is not a chip but instead specifically calls a DRAM a chip (i.e., DRAM chip). (A1092.) The intrinsic record fully supports the examiner’s construction of “synchronous DRAM device.” For instance, the ’120 specification describes

registers that store “other information appropriate for the chip,” referring specifically to DRAM. (A101[4:21-34] (emphasis added).) The specification likewise uses “DRAM” and “chip” interchangeably in several other places. (See, e.g., A99[4:26-29]; A101[7:21-22, 7:34-35, 7:55-56]; A108[22:17-19];

A89[Fig. 8A].) Thus, unlike “synchronous memory device,” which under this Court’s construction can consist of multiple chips, a “synchronous DRAM device” is required by the specification to be a single chip, as the examiner correctly found and the Board agreed. (See Rambus Br. 9-10.)

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3.

The Board’s Finding that Bennett Renders Synchronous DRAMs Obvious Is Unsupported by Substantial Evidence

Like the Board, Micron conflates Bennett’s large memory with Bennett’s separate VLSICs, arguing that because a VLSIC is a chip connected directly to a bus, Bennett allegedly renders obvious a synchronous DRAM chip connected directly to a primary bus. (Micron Br. 5-6, 9, 24.) But in asserting that DRAMs were “ubiquitous” in 1990 and that Bennett disclosed synchronous chips (albeit not necessarily memory (see Rambus Br. 62)), Micron proves Rambus’s point, namely, if it were so obvious to create a synchronous DRAM, someone would have made such a device from known parts before 1990. This is different from a situation where different references each show different limitations of a claim. (See Micron Br. 46.) Here, a single limitation, “synchronous DRAM device,” is not shown in any reference. See Celsis In Vitro, Inc. v. CellzDirect, Inc., 664 F.3d 922, 927-28 (Fed. Cir. 2012) (finding “multicryopreservation” not taught by the art, even though cryopreservation was prevalent and the general concept of doing things multiple times was known). As in Celsis, the record here shows only that synchronous very large-scale integrated circuits (VLSIC) were taught in Bennett and that asynchronous DRAMs were known. It does not follow from this that synchronous DRAMs were obvious.

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Micron also incorrectly contends that “Rambus and its expert inexplicably assert that signals between the Versatile Bus Interface and the User would be asynchronous, even though Bennett expressly states otherwise.” (Micron Br. 7.) That has never been Rambus’s argument. What Rambus has argued—and the examiner correctly found—is that any implementation of DRAM as a “memory User” in Bennett would necessarily be as an array of asynchronous DRAM chips with their own separate controller. This was also the position of Micron’s own expert in a prior litigation. (A3683.) In this arrangement, although the

communications between Bennett’s CPU and the DRAM array’s controller could be synchronous, communications between the DRAM controller and each individual DRAM chip would be asynchronous, just like in the prior art. Finally, Micron compares Figure 1 of Bennett with Figure 2 of the ’120 patent and asserts they are “nearly identical,” allegedly because “Bennett’s User device corresponds to the ’120 Patent’s CPU, ROM, and DRAM . . . .” (Id. at 50.) Yet aside from the superficial fact that both figures illustrate “devices” connected to a bus, even a cursory comparison reveals a major difference. Bennett’s Figure 1 shows a “VLSI Circuit User Device” connected to the Versatile Bus, and there is no disclosure in Bennett that this VLSI device can be an individual DRAM chip. In contrast, Figure 2 of the ’120 patent illustrates a synchronous DRAM chip. 24

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Excerpts from A1336[Fig. 1] of Bennett (left) and A84[Fig. 2] of the ’120 patent (right). 4. The Board’s Finding that iAPX and iRAM Render Synchronous DRAMs Obvious Is Unsupported by Substantial Evidence

Like the Board, Micron completely ignores the unrebutted record evidence and the examiner’s specific findings showing that a person of ordinary skill in the art in 1990 would not have been motivated to combine iAPX and iRAM to arrive at a synchronous DRAM chip. This includes the unrebutted testimony of Intel’s architects of the iAPX system that the proposed modification would defeat the goal of iAPX “since the MCU [memory control unit] would have to be physically removed and placed into each individual iRAM.” (A1178; see also A1177.) It includes the extensive, unrebutted testimony of Mr. Murphy that the proposed combination would not have been feasible or obvious. (A2463-72.) It includes the finding of the European Patent Office that the “use of the term ‘synchronous’ 25

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[in iRAM] has nothing to do with a synchronous bus protocol controlled by a clock signal as claimed” (A3310[¶11]), which Micron does not dispute. And it includes the examiner’s specific findings that “the combination would not have been predictable and would teach away” from the claimed invention (A1179-80 (emphases added)) and that “the proposed integration would . . . render the iPAX 432 system inoperable” (A1180 (emphasis added)). Micron’s only response is to attack the allegedly “flawed premise that the memory array must be synchronous rather than the memory device (which encompasses both the MCU and the memory array).” (Micron Br. 52.) But this premise is not “flawed”—it is the same premise the examiner and Board adopted, i.e., that “synchronous DRAM device” requires a synchronous DRAM chip. Micron cannot, after the fact, change the Board’s claim construction in order to show that the Board’s decision was based on substantial evidence. Under the correct construction of “synchronous DRAM device,” Micron has not pointed to any substantial evidence supporting the Board’s decision. Indeed, Micron’s

myopic focus on an alternative construction of “synchronous DRAM device” that neither the examiner nor the Board actually used is a tacit admission that the Board’s opinion is unsupported under the proper construction.

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D.

Micron’s Alternative Ground for Invalidity Based on JEDEC and Park Contradicts This Court’s Prior Decisions

Without even addressing the merits of the references, Micron argues that JEDEC and Park render claim 33 invalid. As an initial matter, because that argument was not part of Micron’s request for reexamination, Micron does not have standing to raise it. Instead, Samsung (another requester) raised that

argument in its request for reexamination, and Micron is now attempting to adopt Samsung’s reexamination as its own, which is improper.3 See 35 U.S.C. §§ 315(b) (contemplating appeal only of issues raised by that requester), 317(a) (2002) (prohibiting third-party requester from concurrently pursuing two inter partes reexaminations of the same patent). Moreover, as the examiner and the Board correctly concluded, Rambus is entitled to its priority date, such that JEDEC and Park are not prior art. (A1142; A1146; A66-68.) Micron contends claim 33 is overbroad because it is not limited to one particular type of bus, a multiplexed bus, even though the claim is directed exclusively to features other than the bus. As the examiner and the Board correctly found, however, the original disclosure of the ’898 application is not limited to a multiplexed bus. (A67-68.) Indeed, this Court has already concluded the same

3

This argument is more fully explained in the briefing in two co-pending cases before this Court. See Appeal Nos. 2013-1224 and 2013-1228 (briefing scheduled to be completed by October 21, 2013). 27

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thing, a decision that is stare decisis on this issue. In Rambus Inc. v. Infineon Techs. AG, 318 F.3d 1081, 1091-95 (Fed. Cir. 2003), in the context of claim construction, this Court analyzed whether the disclosure of the ’898 application was limited to a multiplexed bus and found that “a multiplexing bus is only one of many inventions disclosed in the ’898 application,” id. at 1095. Micron asserts this Court’s analysis of the disclosure was eclipsed by a later hypothetical statement by this Court in Hynix Semiconductor Inc. v. Rambus Inc., 645 F.3d 1336, 1352-53 (Fed. Cir. 2011). (Micron Br. 54-55.) But Micron misreads the Hynix decision. In Hynix, this Court held that a jury was reasonable in finding that Rambus’s claims do, in fact, meet the written-description requirement without requiring a multiplexed bus. Hynix, 645 F.3d at 1351-53. Thus, the jury’s determination and this Court’s affirmance of it are themselves compelling evidence—and certainly provide substantial evidence to support the Board’s determination—that the claims meet the written-description requirement and are therefore entitled to their priority date. See Ariad Pharm., Inc. v. Eli Lilly & Co., 598 F.3d 1336, 1350-51 (Fed. Cir. 2010) (en banc) (written description requirement is a question of fact reviewed for substantial evidence). Indeed, this Court determined in Hynix that the jury’s fact-finding overcame any analogy to either ICU Medical or LizardTech. Hynix, 645 F.3d at 1352-53 (citing ICU Med., Inc. v. Alaris Med. Sys., Inc., 558 F.3d 1368 (Fed. Cir. 2009); LizardTech, Inc. v. 28

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Earth Res. Mapping, Inc., 424 F.3d 1336, 1344 (Fed. Cir. 2005)). Thus, each of this Court’s statements about the written description of the ’898 application supports the examiner’s and the Board’s holding. Contrary to Micron’s argument (Micron Br. 58-61), the original disclosure describes inventions that do not necessarily require a multiplexed bus, including synchronous memory devices, controllers for controlling such devices, and systems that include such devices. (A99-100[3:22-47, 4:38-42, 5:54-57]; A1605.) The specification goes on to describe numerous “object[s] of this invention,” only one of which is to a “multiplexed bus.” (A99[3:22-47] (referring to a “relatively narrow bus”).) For example, the specification discusses a bus interface for “large blocks of data” (A99[3:22-27]), or a clocking scheme allowing for “high speed clock signals to be sent along the bus with minimal clock skew” (A99[3:28-30]), neither of which necessarily requires a multiplexed bus. See also Infineon,

318 F.3d at 1095 (noting that “a multiplexing bus is only one of many inventions disclosed in the ’898 application”). The specification refers repeatedly and generically to a “bus,” without indicating whether the bus is multiplexed or not. (See, e.g., A99[4:38-39] (“bus lines are controlled-impedance, double-terminated lines”); A100[5:57] (“a bus [is connected] to an independent cache memory”).) Although the specification describes a “byte-wide, multiplexed data/address/control bus,” it is described 29

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simply as the “preferred bus architecture.” (A101[8:18-26].) The specification never limits further bus discussion to this preferred multiplexed architecture. And, as the Board recognized, one of skill in the art would recognize that “the ʼ898 application discloses other important aspects of the invention for use in generic bus systems.” (A67; see also A2418-20[¶¶30-34].) The original claims of the ’898 application also demonstrate that the inventors were in possession of generic bus claims. The Board correctly

recognized that certain original claims (73 and 91) required only a generic bus, not necessarily a “multiplexed bus.” (A68.) Claim 73, for example, required only a “bus subsystem” (A2576-77) and claim 91 required “a plurality of external bus lines” (A2586), but both were silent as to whether the claimed bus is multiplexed. Micron essentially complains that neither of these claims was directed to the bus itself (Micron Br. 60-61), but that assertion applies even more strongly to claim 33 on appeal, since it also does not recite a bus. (See A110[26:30-65].) Micron similarly states that only one prior-art reference (U.S. Patent No. 4,247,817 to Heller) discussed in the specification does not discuss a multiplexed bus and asserts that Heller is distinguishable because it is directed to parts of the invention other than the bus. (Micron Br. 62.) But claim 33, like Heller, is also directed to parts of the invention other than the bus. Thus, Micron’s alleged distinction actually proves Rambus’s point, that the invention claimed in claim 33 30

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is supported by the original specification and does not require a multiplexed bus. (See A68.) III. CONCLUSION For the foregoing reasons and those explained in Rambus’s opening brief, this Court should reverse the Board’s decision finding claim 33 of the ’120 patent invalid as obvious and reinstate the examiner’s finding of nonobviousness. 4

Dated: October 7, 2013

Respectfully submitted,

/s/ James R. Barney J. Michael Jakes James R. Barney Molly R. Silfen FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP 901 New York Avenue, NW Washington, DC 20001 (202) 408-4000 Attorneys for Appellant Rambus Inc.

4

Reversal is appropriate here because Rambus elected under 37 C.F.R. § 41.77(b)(2) (2012) to request rehearing by the Board “upon the same record” rather than reopen prosecution following the Board’s new grounds of rejection. Thus, if the Board’s decision is unsupported by substantial evidence in the existing record, the appropriate action is reversal rather than remand. 31

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CERTIFICATE OF COMPLIANCE I certify that the foregoing REPLY BRIEF FOR RAMBUS INC. contains 6,932 words as measured by the word-processing software used to prepare this brief.

Dated: October 7, 2013

Respectfully submitted,

/s/ James R. Barney J. Michael Jakes James R. Barney Molly R. Silfen FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP 901 New York Avenue, NW Washington, DC 20001 (202) 408-4000

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CERTIFICATE OF SERVICE I hereby certify that copies of the foregoing REPLY BRIEF FOR RAMBUS INC. were served upon registered counsel by operation of the Court’s CM/ECF system on this 7th day of October, 2013. Henry A. Petri, Jr. Novak Druce Connolly Bove + Quigg, LLP 1875 Eye Street, NW, 11th Floor Washington, DC 20001 henry.petri@novakdruce.com

/s/ Kay Wylie