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DESIGN AND DEVELOPMENT OF A STAND-ALONE MULTI-LEVEL INVERTER FOR PHOTOVOLTAIC (PV) APPLICATION

Report by:

ASSOC. PROF. DR. ZAINAL SALAM Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 UTM Skudai, Johor Darul Takzim

For

Research Vot No: 72342.

September 2003

ABSTRACT Multilevel voltage source inverter (VSI) has been recognized to be very attractive in high voltage dc to ac conversion. It offers several advantages compared to the conventional two-level inverter, namely reduced switching losses and better harmonic performance. This work proposed a new switching strategy for a particular multilevel topology, known as the modular structured multilevel inverter (MSMI). The proposed scheme is based on symmetric regular sampled unipolar PWM technique. Unlike other techniques proposed by other researchers, this method uses multiple modulating waveform with a single carrier. Mathematical equations that define the PWM switching instants is derived. The derived equations are verified by computer simulation. To justify the merits of the proposed modulation scheme, prediction on the output voltage harmonics using Fourier analysis is carried out. An experimental five-level MSMI test-rig is built to implement the proposed algorithm. Using this set-up, it was found that the derived equations could be easily implemented by a low-cost fixed-point microcontroller. Several tests to quantify the performance of the inverter under the proposed modulation scheme is carried out. The results obtained from these tests agree well with theoretical prediction.

(Keywords: inverter, power electronics, pulse-width modulation, multilevel)

ABSTRAK Penyongsang sumber voltan (VSI) bertahap diiktiraf amat sesuai digunakan dalam penukaran voltan tinggi DC ke AC. Ia memberikan beberapa kelebihan berbanding penyogsang dua tahap di mana kehilangan pensuisan dan harmonik dapat dikurangkan. Tesis ini mengusulkan satu strategi pensuisan untuk satu topologi penyongsang bertahap yang dikenali sebagai penyongsang bertahap struktur bermodul (MSMI). Skim pemodulatan ini adalah berasaskan teknik PWM satu kutub tersampel teratur simetri. Tidak seperti teknik yang diusulkan oleh penyelidikpenyelidik sebelum ini, kaedah ini menggunakan beberapa gelombang memodulat beserta isyarat pembawa tunggal. Hasilnya, satu persamaan matematik sesuai untuk pelaksanaan digital bagi skim tersebut diterbitkan. Persamaan yang diterbitkan itu ditentusahkan oleh simulasi komputer. Bagi menentukan kelebihan skim pemodulatan tersebut, telahan awal terhadap harmonik voltan keluaran mengunakan analisis Fourier telah dilakukan. Selanjutnya satu modul eksperimen untuk penyongsang lima-tahap struktur bermodul telah dibina untuk pengimplementasian algorithma yg diusulkan. Daripada ujikaji yang telah dijalankan, didapati bahawa persamaan yang diterbitkan dapat diiplementasikan secara digital dengan mudah menggunakan pengawal mikro berkos rendah. Beberapa ujian untuk mengenalpasti persembahan penyongsang menggunakan skim pemodulatan tersebut telah dilakukan. Didapati bahawa keputusan yang diperolehi disokong oleh teori. Katakunci: penyongsang, elektronik kuasa, penyongsang berbilang tahap, pemodulatan lebar denyut

Key Researchers: 1. 2. Assoc. Prof. Dr. Zainal b. Salam Mr. Mohd. Junaidi Abdul Aziz

Corresponding researcher: Assoc. Prof. Dr. Zainal b. Salam, Faculty of Electrical Engineering, 81310 UTM Skudai, Johor Bahru, Johor Darul Takzim E-mail : Tel. No. : Vote No. : zainals@fke.utm.my 07-5535206 72342

TABLE OF CONTENT CHAPTER I: INTRODUCTION 1.1 1.2 Overview Objective of Research CHAPTER II: NOVEL TECHNIQUE FOR PWM WAVEFORM GENERATION FOR MULTILEVEL INVERTERS 2.1 2.2 2.3 Review of Conventional Voltage Source Inverter Multilevel Inverters Topologies PWM Modulation Techniques for MSMI
2.3.1 2.3.1 The Proposed Modulation Scheme The Proposed Modulation Scheme

1 3

4 6 10 10 15

CHAPTER III: DESIGN AND CONSTRUCTION OF A MSMI PROTOTYPE 3.1 3.2 3.3 Introduction Siemens Microcontroller Generation of PWM Waveform
3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 PWM Module Standard PWM Generation (Edge Aligned PWM) Symmetrical PWM Generation (Center Aligned PWM) PEC (Peripheral Event Controller) Operation Generation of Square Wave Signal Generation of V1(k) and V2(k) Signals Ex-or Gate Gate Drive Circuit Power Circuit IGBT Switch Setting-up MCB167 and main subroutines

3.4

Functional Block Diagram


3.4.1 3.4.2 3.4.3 3.4.4

3.5 3.6

Flowchart of the program in generating PWM signals


3.5.1

Sample Waveforms CHAPTER IV: RESULTS AND ANALYSES

21 22 24 24 25 27 28 29 29 31 31 32 33 33 33 34 35

4.1 Introduction 4.2.1 Results


4.2.1 4.2.2 4.2.3 Inverter Output Voltage and Current Harmonic Spectrum Harmonics Performance at Higher Modulation Ratio

4.3 4.4

Generalized of Harmonics Table for Five-level Inverter Performance Indexs for the Proposed Modulation Scheme
4.4.1 Total Harmonic Distortion (THD)

38 38 38 41 45 49 50 51

4.4.2 4.4.3

Harmonic Loss Factor (HLF) Second Order Distortion Factor (DF2)

52 53

CHAPTER V: SUMMARY, CONTRIBUTIONS AND SUGGESTION FOR FURTHER WORK 5.1 5.2 5.3 Summary of the Research Contributions Suggestion for Further Work 55 56 57 58

REFERENCES

CHAPTER I

INTRODUCTION

1.1

Overview

The past decade has witness the growing interest in alternative sources of energy [15]. The so-called renewable energy such as the sun, geothermal, biomass and wind can never be exhausted. They cause less emission and therefore stand out as a potentially viable source of clean and limitless energy. However these renewable sources energyin particular the solar energy, requires rather sophisticated conversion techniques to make them usable to the end user. For example, the output of the photovoltaic (solar) panel is essentially dc; for it to be commercially viable, it needs to be converted to ac. This is necessary because the power utilisation is mostly in ac form. The technology to accomplish this conversionknown as inverter, is inevitably an integral part of the photovoltaic system. Technology-wise, inverter can be divided into two main types; Voltage Source Inverters (VSI) and Current Source Inverters (CSI). Both types have their own advantages and disadvantages and are reported extensively in literatures [6-9]. However VSI is more popular compared to CSI, especially in renewable energy system [6,7]. Several research works [8-12] have concluded that the transformer-less inverter is very attractive in renewable energy application due to reduced weight and size. In principal, a two-level PWM inverter with high switching frequency can be adequately used, but for high power application the switching losses can be prohibitive [13]. A large body of literature over the past decade has testified multilevel inverter viability especially for high power application [14-17]. Multilevel inverter has become an effective and practical solution for reducing switching losses in high power application. Recently several multilevel topologies have become very popular in renewable energy sources applications [18-19]. It is well known that multilevel voltage source inverters offer several advantages compared to their conventional counterparts. By synthesizing the ac output terminal voltage from several levels of

dc voltages, staircase output waveform can be produced. This allows for higher output voltage and simultaneously lowers the switches voltage stress. In addition, multilevel inverter is known to have better harmonic profile and thus the requirement of output filter is reduced. Generally the development of multilevel inverter system can be broadly divided into the two issues namely, power circuit topology and switching strategy. For circuit topology, three main types have been frequently cited in literature: (1) diodeclamped multilevel inverters (DCMI): (2) flying capacitor multilevel inverters (FCMI) and (3) modular structured multilevel inverters (MSMI). Abovementioned topologies have their specific advantages and disadvantages as detailed in [20-23]. The selection of appropriate topology depends on a particular application and the nature of the dc supply that feed the inverter. The second aspect that defines the inverter performance is the switching strategy. This is closely related to the harmonic profile of the inverter output waveform. The simplest scheme is the square wave, which has the poorest harmonic performance. This is followed by quasi-square wave, which offers a marginal improvement compared to the square wave inverter. The most popular switching technique is the Pulse Width Modulation (PWM), which is currently being implemented in majority of the VSIs. Historically, the development of PWM switching strategy was prompted by the natural sampled sinusoidal PWM technique introduced by Schonung and Stemmler in 1964 [25]. This analog technique is based on the physical comparison between a carrier signal and a pure sinusoidal modulating signal. Its digital version, i.e. the regular-sampling PWM was introduced by Bowes in 1975 [26]. It has simplified the PWM generation tremendously and has become the impetus for the proliferation of several important digital PWM techniques until the present day. Several currently popular PWM schemes are the Optimized PWM [26], Selective Harmonic Elimination PWM (SHEPWM) [27-28] and more recently the Space Vector PWM (SVPWM) [29-33].

Abovementioned modulation techniques were originally applied to the two-level inverter. However, it was discovered that by making some modifications they could also be suitably used for multilevel inverter. For multilevel sinusoidal PWM in particular, different methods of carrier arrangement namely Phase Opposition Disposition (POD), Phase Disposition (DP) and Alternatively in Phase Opposition Disposition (APOD) [20] have been suggested. All of these techniques employ multiple carriers with a single modulating waveform. Each method has its own unique spectra and specific applications [33-36]. In brief, the heart of any multilevel inverter is the selection of the power circuit topology and its associated switching strategy. The power circuit topology is dictated by a particular application and the nature of the dc supply that feed the inverter. The switching strategy will determine the harmonic performance of the output voltage waveform.

1.2

Objective of Research

As noted in the brief overview above, multilevel inverters have been used in power electronic applications for over a decade. Judging from the proliferation of literature in this subject, undoubtedly, research in this area is still very active. It triggers a lot of interest, particularly with the up-trend of the renewable energy resources. Research efforts in this area have contributes toward the development of several PWM schemes suitable for multilevel inverter application. Fundamentally, the choice of the PWM scheme will influence the complexity and performance of the inverter system. In this work the research will be focused on developing a new switching algorithm for the modular structured multilevel inverter. It will be based on the popular regular sampling PWM. Mathematical derivation will be carried out to obtain switching instants that can be programmed using a C167 microcontroller. A harmonic analysis is carried out to justify the performance of the inverter under the proposed switching strategy. In order to validate the performance of the inverter, a low-power test-rig will be constructed. The performance of the inverter is analysed and compared with the result obtained from theory and simulation.

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CHAPTER II

NOVEL TECHNIQUE FOR PWM WAVEFORM GENERATION FOR MULTILEVEL INVERTERS

2.1

Review of Conventional Voltage Source Inverter

Switch-mode dc-to-ac inverter is used in ac power supplies and ac motor drives with the objective to produce a sinusoidal ac output whose magnitude and frequency can both be controlled. In single-phase or three-phase ac systems there are two common inverter topologies used. First is the half-bridge or a single leg inverter, which is the simplest topology, as shown in Figure 2.1. It is used to produce a two-level squarewave output waveform using two semiconductor switches S1 and S2. A centertapped voltage source supply is needed; it may be possible to use a simple supply with two well-matched capacitors in series to provide the center tap. Another topology is known as the full-bridge inverter. It is used to synthesize a two-level or three-level square-wave output waveform but with double the amplitude compared to half-bridge. There are two inverter legs in a full-bridge topology as shown in Figure 2.2, namely leg a and leg b.

Vdc
2

S1

Vdc
Vdc
2

Load

S2

Figure 2.1: Half-bridge configuration.

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leg a

leg b

S1

S3

Vdc

Load

S4

S2

Figure 2.2: Full-bridge configuration. For each inverter leg, the top and bottom switches have to be complementary to avoid shoot-through fault, i.e. if the top switch is closed (on), the bottom must be open (off), and vice-versa. Both switches, S1 and S2 for half-bridge inverter are never turned on at the same time. Similarly for full-bridge inverter, both S1 and S4 should not be closed at the same time, nor should S2 and S3. To ensure the switches not closed at the same time, each gating signal should pass through a protection mechanisme known as a dead time circuit before it is fed to the switches gate [46,47]. A two-level output waveform of half bridge and three-level output waveform of full bridge single-phase voltage source inverter are shown in Figure 2.3 and 2.4, respectively.
VAO

Vdc
2

t Vdc
2

Figure 2.3: Two-level output waveform of half-bridge configuration.

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VAB Vdc

Vdc

Figure 2.4: Three-level output waveform of full-bridge configuration.

2.2 Multilevel Inverters Topologies Multilevel voltage source inverter (MVSI) is very attractive in high voltage and high power applications such as adjustable speed drives and electric utility applications. The development of MVSI began in the early 1980s when Nabae et al. [39] proposed a neutral-point clamped (NPC) PWM inverter. Since then several multilevel topologies have evolved. The general structure of the MVSI is to synthesize a sinusoidal voltage out of several levels of dc voltages [20]. The MVSI can therefore be described as a voltage synthesizer. The so-called multilevel starts from three levels. There are several advantages offered by the MVSI. In Voltage Source Inverter (VSI), the maximum voltage level output is determined by the voltage blocking capability of each device. By using a multilevel structure, the stress on each device can be reduced in proportional to the number of levels, thus the inverter can handle higher voltages [28]. As a result, an expensive and bulky step-up transformer can be avoided in various applications. There are three main topologies of multilevel inverters as cited in literatures: 1) Diode-Clamped Multilevel Inverter (DCMI) [20-23]. 2) Flying-Capacitor Multilevel Inverter (FCMI) [20,21]. 3) Modular Structured Multilevel Inverters (MSMI) [20,23]. The diode-clamped multilevel inverter uses capacitors in series to divide up the dc bus voltage into a set of voltage levels [20]. This topology is not very popular due to the need of large number high voltage rating diodes [20-23]. Furthermore, the voltage unbalance problem make this topology is unattractive to handle real power

13

flow control. The flying capacitor multilevel inverter, on the other hand, has the significant advantage that it eliminates the clamping diode problems present in the DCMI [20 However, FCMI has several technical difficulties that complicate its practical application for-high power converters. To maintain the charge balance in the capacitors, the dc-link capacitors need a controller, thus adding complexity to the control of the whole circuit. Furthermore, an excessive number of storage capacitors are required when the number of inverter levels is high. Higher level systems are more difficult to package and more expensive due to the bulky capacitors. Moreover, the switching losses will be high for real power transmission [20-21]. The cascaded multilevel inverter (MSMI) requires separate dc sources, and hence is well suited for various renewable energy sources such as photovoltaic, fuel cell and biomass. A single-phase N-level configuration of such inverter is shown in Figure 2.3. Each module consists of a separate dc source associated with a single-phase full-bridge inverter. The ac terminal voltage of each module is connected in series to form an output voltage, Vo. Figure 2.6 shows the synthesized voltage waveform of a seven-level Modular Structured Inverter with three separate dc sources. The output voltage is synthesized by the sum of each dc source from each module, i.e Vout = E1 + E2 + E3. By different combinations of the four switches, S1M through S4M, each module can generate three different voltage outputs, +E, -E, and zero. The ac output of each module is connected in series such that the synthesized voltage waveform is the sum of the inverter outputs. Note that the number of output phase voltage levels is defined in different way from those of two previous inverters. In this topology, the number of module (M), which is equal to the number of dc sources required, depends on the number of levels (N) of the MSMI. It is usually assumed that N is odd, as this would give an integer-valued M. The number of output phase voltage levels is defined by:

M=

N 1 2

(2.1)

14

S11 E1
+

S21 V1 Vphase (Vout)

S31

S41

Module 1 S12 E2
+ _

S22 V2

S32 Module 2

S42

S1M EM
+ _

S2M VM 0

S3M Module M

S4M

Figure 2.5: Single-phase structure of a MSMI

V0
3E

3E E3 t E2 t E1 t

Figure 2.6: Voltage waveform of a seven-level MSMI.

15

There are many possible switch combinations that can synthesis stair case waveform for MSMI. The number of switch combinations is proportional with the systems level (N). The relationship between the number of switch combinations and the systems level is expressed by [34]: Number of switch combinations = 2N-1. (2.2)

For example, the number of switch combinations for seven-level inverter is 27-1, which is 64 different configurations. Hence, the flexibility in voltage synthesizing for this topology is more than DCMI and FCMI. Table 2.1 lists a possible combination of the voltage levels and their corresponding switch states. Table 2.1: A possible switch combination for MSMI based seven-level inverter.
Load Voltage S11 S21 S31 S41 S12 S22 S32 S42 S13 S23 S33 S43 +3E +2E +E 0 -E -2E -3E

1
0 0

1
0 0 1

1
0 0 1

1
1 0 0 1 1 0 0 1 1 0 0

0
1 1 0

0
1 1 0 0 1 1 0 0 0 1 1

0 1 1
0 0

1 1
0 0

1
0 0 1

1
1 0 0

0
0 1 1

1 1
0 0

1
1 0 0 1

1
1 0 0

1
1 0 0

0
0 1 1

1
1 0

As illustrated in Figure 2.5, this topology requires the least number of components among all multilevel converters to achieve the same voltage levels. In addition this topology can avoid extra clamping diodes or voltage balancing capacitors. Moreover modularized circuit layout and packaging is possible because each level has a standard structure. However, with the need of separate dc sources for real power conversions, the application of cascaded inverter can be somewhat limited.

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2.3

PWM Modulation Techniques for MSMI

It is generally accepted that performance of an inverter, with any switching strategy is closely associated to the harmonic contents of its output voltage. Accordingly, power electronics researchers have proposed many novel control techniques to reduce and optimise the harmonic content in such waveforms. For multilevel inverter technology, there are several well-known PWM modulation techniques, which can be classified as follows: (1) selective harmonic elimination PWM (SHEPWM) [26,27]; (2) space vector PWM (SVPWM) [28-32]; and (3) sinusoidal PWM (SPWM) [33-38]. These multilevel modulation techniques are adapted from the well-established two-level PWM. Among the abovementioned techniques, the SPWM is the first and by far the most popular for traditional inverter [33]. Its popularity is partly due to its simplicity. The most common SPWM strategy for a two level output voltage is a comparison between sinusoidal with fundamental frequency modulating waveform against a high frequency carrier waveform. The switches turn on to the upper or the lower dc rail supply depending on whether the modulating waveform is greater or lower than the carrier waveform. By raising the carrier frequency, the output voltage harmonic can be moved to higher frequency, thus reducing the size of the output filters required to attenuate the harmonics. A wide variety of SPWM strategies have been proposed based on this principle as described in [33-38]. With certain modification, this technique can be implemented in multilevel inverters.

2.3.1 The Proposed Modulation Scheme The proposed modulation scheme for the MSMI is based on the classical unipolar PWM switching technique [46,47]. The main idea behind this method is to compare several modified sinusoidal modulation signals s(k) with a single triangular carrier signal c(k) as shown in Figure 2.7. These modified modulation signals have the same frequency (fo) and amplitude (Am). Since the modulation is symmetric, the sinusoidal modulation signals are sampled by the triangular carrier signal once in every carrier cycle. Intersection between the sampled modulation signals and the carrier signal defines the switching instant of the PWM pulses. In order to ensure quarter wave symmetry PWM output waveform, the starting point of the modulation signals ought to be phase shifted by half period of the carrier wave. The number of

17

modulation signals needed is equal to the number of modules in the MSMI [45]. Recall that the relationship between N and M for MSMI is described in equation (2.1), i.e.:

M=

N 1 2

The carrier signal is a train of triangular waveform with frequency fc and amplitude Ac. Equations (2.2) defines the modulation index mi for N-level inverter with M number of modules:

mi =

Am (N 1) Ac 2
Am MAc (2.2)

Therefore if Ac defined at a fixed p.u (1p.u), then mi ranges between 0 and 1, while Am ranges between 0 and M. The definition of the modulation ratio mf for multilevel inverter is similar to the conventional two-level output inverter, i.e.:

mf =

fc fo

(2.3)

Where fc is the frequency of the carrier signal and fo is the frequency of sinusoidal modulation signals.

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V(p.u)

c Tc

Ac

Am

e d

To
t(ms)

Legend a. Carrier signal c(k) b. Absolute sinusoidal modulation signal m1 (t). c. Modified sinusoidal modulation signal s1(k) of m1 (t). d. Shifted absolute sinusoidal modulation signal m2 (t). e. Modified sinusoidal modulation signal s2(k) of m2 (t). Figure 2.7: The modified sinusoidal modulation signals and a single carrier signal. To illustrate the principle of the proposed scheme, a five-level inverter at mi = 0.4 and mi = 0.8 is shown in Figure 2.8 and 2.9 respectively. For clarity, mf for both cases was arbitrary selected to 20. As mentioned above, the number of modulation signals for a five-level inverter is equal to the number of modules required. Thus two modulation signals namely s1(k) and s2(k) and single triangular carrier c(k) are involved in this modulation process. Recall that signals s1(k) and s2(k) are modified modulation signal of m1(k) and m2(k), respectively. Signal s2(k) actually is s1(k) that shifted down by the amplitude of triangular carrier signals Ac.

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V(p.u)

s2(k) (a)
V(p.u)

s1(k)

c( k )

(b)
V(p.u)

(c)
Vout(V)

(d)

t(ms)

Legend (a) (b) (c) (d) Modulation signals and carrier signal PWM pulses produced from comparison between s1(k) and c(k), V1(k) PWM pulses produced from comparison between s2(k) and c(k), V2(k) PWM output waveform

Figure 2.8: Principle of the proposed modulation scheme for mi = 0.4, mf = 20.

20

V(p.u)

s2(k) (a)
V(p.u)

s1(k)

c(k)

(b)
V(p.u)

(c)
Vout(V)

(d) Legend (a) (b) (c) (d)

t(ms)

Modulation signals and carrier signal PWM pulses produced from comparison between s1(k) and c(k), V1(k) PWM pulses produced from comparison between s2(k) and c(k), V2(k) PWM output waveform

Figure 2.9: Principle of the proposed modulation scheme for mi = 0.8 mf = 20. The plots in Figures 2.8 and 2.9 show the PWM pulses and the inverter output waveform in the modulation process. Pulses V1(k) is generated from the comparison between s1(k) and c(k), while V2(k) is from comparison between s2(k) and c(k). The comparison is designed such that if s1(k) is greater than c(k), a pulse-width V1(k) is generated. On the other hand, if s2(k) is greater than c(k), V2(k) is generated. If there is no intersection, the V1(k) and V2(k) remain at 0. It can also be seen in Figure 2.8 that if mi 0.5, only s1(k) and carrier signal c(k) is involved in the modulation

21

process. There is no intersection for s2(k). Therefore, the output pulse V2(k) is zero. The output voltage Vout is similar to the conventional three-level unipolar PWM case. For mi > 0.5, as depicted in Figure 2.9, both modulating signal s1(k) and s2(k) and carrier signal c(k) are involved. In this case, two modulating signals intersect the carrier and therefore V1(k) and V2(k) are generated. Since there are two modulating signals intersect with the carrier, it can be expected that the equation of the switching angles to be defined is not as straight forward as for mi 0.5 case. It is also important to note that modulation ratio mf, of the inverter must be selected to be even. This provision must be obeyed to ensure the output waveform obtained is quarter wave symmetry. With this assumption, the derivation for the switching angles equations is greatly simplified. It will be shown in the next Section that using the proposed modulation scheme, simple trigonometric equations to define the switching instant of inverter switches can be obtained. The derived equations can be suitably programmed using microprocessor for an online PWM waveform generation.

2.3.2

Derivation of the Switching Angle Equations

It is desirable to obtain mathematical expressions that define the switching instants for the inverter switches. The motivation of such exercise is to derive simple equations that can be programmed using digital technique. The ultimate aim is to generate the PWM pulses on-line without having to do physical comparison of the carrier and modulating signals. The initial derivation is based on a modular structured five-level inverter. Then by extending the result of five-level inverter equations, a general equation for N-level MSMI can be accomplished. The kth rising edge is defined as the intersection of the negative slope carrier c(k) and two set of modulating signals s1(k) and s2(k) as shown in Figure 2.10. The variable k represents a position of each modulated width pulses V1(k) and V2(k), initiated from k = 1,2,3mf. Due to symmetrical nature of the proposed PWM scheme, the intersection between the positive slope carrier c+(k) and the modulating

22

signals is not required in the derivation. It can be deduced from the rising edge equation, i.e. the intersection between c(k) and s1 (k) or s2 (k).

c(k)

s1(k)

2(3)

2(4)

2(5)

1(1) 1(2)

s2(k)

Figure 2.10: Intersection between single carrier and modulation signals in first quarter wave. Figure 2.10 shows the single carrier and two set of sampled modulation signals in generating five-level inverter output voltage for mi = 0.8, mf = 20. The straight-line equation for the carrier wave is denoted by c(k) for the negative slope. It can be expressed as:

Ac (k ) + hAc c (k ) = T c 2

(2.4)

k = 1, 2,3.... h = 1,3,5....
The relationship between Tc , fc , fo and mf can be written as follows:

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Tc =

1 fc

(2.5) (2.6)

fc = m f fo

Where Tc is a period of carrier signal, fc is a carrier frequency and fo is a modulating signal frequency. The symmetric regular sampled modulation signals s1k(k) and s2k(k) can be expressed as:
s1 (k ) = Am sin (i ) + mf s2 (k ) = Am sin (i ) + Ac m f i = 0,1, 2,3.... when the modulation signal intersect with c (k ) The angular frequency , in (2.6) and (2.7) is represented by:

(2.7)

(2.8)

= 2 f o
2 = mf

To mf

(2.9)

From arithmetic regression equation, Tn = a + (n 1)d Where; Tn = number at nth a = T1 = first number. d = increment/decrement of next number n = 1,2,3. (2.10)

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Using the arithmetic regression in (2.10) and realizing that k is equal to n, thus relationship between h and i with k can be rewritten as:
h = 1 + (k 1)2 h = 2k 1 i = 0 + (k 1)1 i = k 1

(2.11)

The kth raising edge ( 1 (k ) ) of PWM signal V1(k) is produced by the intersection between s1 (k) and c(k). This rising edge 1 (k ) is represented by:
Ac T c 2 (i ) + 1 (k ) + hAc = Am sin mf

1 (k ) =

Tc A (k 1) + h m sin 2 Ac mf Tc 2

(2.12)

A (k 1) + ( 2k 1) m sin Ac mf

Moreover, for intersection between s2(k) with c(k), every rising edge 2 (k ) of PWM signal V2(k) can be expressed as:
Ac T c 2 (i ) + 2 (k ) + hAc = Am sin mf

A c

2 (k ) =

Tc A (k 1) + (h + 1) m sin 2 Ac mf Tc 2 A (k 1) + 2k m sin Ac mf

(2.13)

25

From observation of equation (2.12) and (2.13), it can be seen that in equation (2.12) the h is alone while in (2.13), the h is added with 1. This relationship shows these equations actually can be generalized to produce N-level inverter, where M (k ) can be expressed as: Tc A (k 1) + (h + M 1) m sin 2 Ac mf A (k 1) + (2k + M 2) m sin Ac mf (2.14)

M (k ) =

Tc 2

Where M = 1,2,3and relationship between M and N for modular structured multilevel inverter is expressed by:

M=

N 1 2

(2.1)

For example, to produce a nine-level output voltage using modular structured inverter, equation (2.14) can be used to generate V1(k), V2(k), V3(k) and V4(k). Where V1(k) is generated from 1 (k ) , V2(k) from 2 (k ) , V3(k) from 3 (k ) and V4(k) from 4 (k ) respectively, they are rewritten below as: A (k 1) + (2k 1) m sin Ac mf A (k 1) + (2k ) m sin Ac mf

1 (k ) = 2 (k ) = 3 (k ) = 4 (k ) =

Tc 2 Tc 2

(215(a))

(2.15(b))

Tc A (k 1) + (2k + 1) m sin 2 Ac mf Tc A (k 1) + (2k + 2) m sin 2 Ac mf

(2.15(c))

(2.15(d))

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Using equation (2.1), the relationship between mi with Am and Ac for nine-level inverter is expressed by:

mi =

Am 4 Ac

(2.16)

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CHAPTER III

DESIGN AND CONSTRUCTION OF A MSMI PROTOTYPE

3.1

Introduction

This chapter describes the design and construction of a 5-level MSMI prototype inverter test-rig to verify the proposed PWM scheme described in previous Chapter. Figure 3.1 (a) shows the photograph of overall prototype arrangement, while Figure 3.1 (b) shows MCB 167 microcontroller, driver circuit and five-level MSMI power circuit.

Input power (dc power supplies)

MSMI module

Load

Figure 3.1 (a): Photograph of overall test-rig arrangement.

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MCB 167 microcontroller

Driver circuit

MSMI power circuit

Figure 3.1 (b): Photograph of MCB-167 microcontroller, driver circuit and MSMI power circuit.
3.2 Siemens Microcontroller

The PWM signal generation is performed by SAB-C167CR-LM micocontroller from Siemens. The microcontroller is a fast instruction fixed-point microprosessor. Block diagram in Figure 3.2 desribes the main features of the chip. Integrated on-chip peripherals such as Serial Port, bi-directional Parallel Port, Timers, PWM module and Peripheral Interfaces units make the interfacing task much easier and with higher reliablity. Some of the main features of SAB-C167CR-LM and its peripherals are summarized as follows [48]: The CPU is capabled of 100 ns minimum instruction cycle time, with most instruction executed in 1 cycle The external interrupt inputs are sampled every 50ns The CPU provides 56 separate interrupt nodes with 16 priority levels The CPU has two 16-channel Capture/Compare (CAPCOM) Units The CPU supports four independent high-speed Pulse Width Modulation signals with two independent time base For analog signal measurement, a 16-channel 10-bit A/D converter with programmable conversion time has been integrated on the CPU.

29

Figure 3.2: Block diagram of the SAB-C167CR-LM chip. The MCB-167 microcontroller evaluation board shown in Figure 3.3 is used to develop, debug and execute SAB-C167CR application programs. The board, manufactured by Keil Electronics has two RAM chips, Toshiba TC551001BPL-70L each of 131 kilobyte in size. A wire wrap field is available for additional application hardware construction on-board.

Figure 3.3: The MCB-167 microcontroller evaluation board.

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For short programs, Keil Vision provides a restricted version of debugger with 8kbyte code size limit. For small size program, it can be loaded using Siemens Bootstrap Loader Tool. However if the bigger program is to be executed, the Keil C166 Cross Compiler is required. The Keil C166 is not a universal C compiler; in fact it is a dedicated 166/167 C compiler that generates extremely fast and compact code. The Keil C166 Compiler implements the ANSI standard for the C language.

3.3

Generation of PWM Waveform

To obtain a five-level output voltage as described in Chapter II, three signals need to be generated, namely: 1. 2. 3. Fundamental frequency square wave (in this case, 50 Hz), PWM signal V1(k) PWM signal V2(k)

These signals can be generated using on chip PWM module. The use of this module eliminates the requirement for complicated external timers.

3.3.1

PWM Module

The Pulse Width Modulation Module consists of 4 independent PWM channels. Each channel (shown in Figure 3.4) has a 16-bit up/down counter PTx, a 16-bit period register PPx, a 16-bit pulse width register PWx with a shadow latch, two comparators, and the necessary control logic. The operation of all four channels is controlled by two common control registers, PWMCON0 and PWMCON1. The interrupt control and status is handled by one interrupt control register PWMIC, which is also common for all channels. The PWM Module of the C167CS allows the generation of up to 4 independent PWM signals. These PWM signals can be generated for a wide range of output frequencies, depending upon the CPU clock frequency (fCPU = 20MHz), the selected counter resolution (fCPU / 1 or fCPU / 64), the operating mode (edge/center aligned) and the required PWM resolution (1-bit 16-bit).

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Figure 3.4: PWM Channel block diagram. The PWM module in C167 provides four different operating modes, namely; Standard PWM generation (edge aligned PWM) Symmetrical PWM generation (center aligned PWM) Burst mode generation Single shot mode generation In this work, the required three signals can be generated using two operating modes. Standard PWM is selected to generate fundamental frequency square wave, meanwhile Symmetrical PWM is dedicated to generate Va and Vb.

3.3.2 Standard PWM Generation (Edge Aligned PWM)

Edge Aligned PWM is selected by clearing the respective bit PMx in register PWMCON1 to 0. In this mode the timer PTx of the respective PWM channel is always counting up until it reaches the value in the associated period shadow register. Upon the next count pulse the timer is reset to 0000H and continues counting up with subsequent count pulses. The PWM output signal is switched to high level when the timer contents are equal to or greater than the contents of the pulse width

32

shadow register. The signal is switched back to low level when the respective timer is reset to 0000H, i.e. below the pulse width shadow register. The period of the resulting PWM signal is determined by the value of the respective PPx shadow register plus 1, counted in units of the timer resolution as given by the equation below: PWM_PeriodMode0 = [PPx] + 1 (3.1)

The duty cycle of the PWM output signal is controlled by the value in the respective pulse width shadow register. This mechanism allows the selection of duty cycles from 0% to 100% including the boundaries. For a value of 0000H the output will remain at a high level, representing a duty cycle of 100%. For a value higher than the value in the period register the output will remain at a low level, which corresponds to a duty cycle of 0%.

Figure 3.5: Operation and Output Waveform in Edge Aligned PWM. Figure 3.5 illustrates the operation and output waveforms of a PWM channel in mode 0 for different values in the pulse width register. This mode is referred to as Edge

33

Aligned PWM, because the value in the pulse width (shadow) register only effects the positive edge of the output signal. The negative edge is always fixed and related to the clearing of the timer.

3.3.3

Symmetrical PWM Generation (Center Aligned PWM)

This mode is referred to as Center Aligned PWM, because the value in the pulse width (shadow) register effects both edges of the output signal symmetrically. Center Aligned PWM is selected by setting the respective bit PMx in register PWMCON1 to 1. In this mode the timer PTx of the respective PWM channel is counting up until it reaches the value in the associated period shadow register. Upon the next count pulse the count direction is reversed and the timer starts counting down with subsequent count pulses until it reaches the value 0000H. Upon the next count pulse the count direction is reversed again and the count cycle is repeated with the following count pulses. The PWM output signal is switched to a high level when the timer contents are equal to or greater than the contents of the pulse width shadow register while the timer is counting up. The signal is switched back to a low level when the respective timer has counted down to a value below the contents of the pulse width shadow register. So in mode 1 this PWM value controls both edges of the output signal. Note that in Center Aligned PWM operation the period of the PWM signal is twice the period of the timer: PWM_PeriodMode1 = 2 ([PPx]+ 1) (3.2)

Figure 3.6 illustrates the operation and output waveforms of a PWM channel in mode 1 for different values in the pulse width register.

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Figure 3.6: Operation and Output Waveform in Center Aligned PWM.

3.3.4 PEC (Peripheral Event Controller) Operation

For high frequency operation, extremely fast data transfer is required when a corresponding interrupt request occurs. Receiving interrupt signals from source pointer, PEC responses the request by moving a byte or word to the corresponding destination pointer within a single CPU cycle. Additionally it does not require saving and restoring the machine status. The C167 has 8 PEC channels which offers such fast interrupt data transfer capability. Each channel is controlled by the dedicated PEC channel Counter/Control register (PECCx) and a pair of pointers for source (SRCPx) and destination (DSTPx) of the transfer data. Either a byte or word is moved during PEC service cycle, it can be controlled by Byte/Word Transfer bit BWT. This selection controls the transferred data size and the increment step for the modified pointer. The PEC Transfer Count Field, COUNT controls the action of a respective PEC channel, where the content of bit field COUNT at the time the request is activated and select the action. COUNT may allow a specified number of PEC transfers, unlimited transfer or no PEC services at all.

35

The PEC transfer COUNT allows to service a specified number of requests by the respective PEC channel, and then activate the interrupt services routine when it reaches 00H. The interrupt services routine is associated with the priority level. After each PEC transfer the COUNT field is decremented and the request flag is cleared to indicate that the request has been serviced.

3.3.5

Generation of Square Wave Signal

In order to generate square wave signal, the Edge Aligned PWM operation mode is selected by clearing bit PMx in register PWMCON1 to 0 (Note that the available channel is 0,1,2 and 3, for this signal generation the selected channel is 3thus PM3 is set to 0). It is important to note that in generating PWM signal the selected channel must be the same for all registers. Thus the PWM Period Register (PPx) and the Pulse Width Register (PWx) are set to PP3 and PW3, respectively. Then the counter resolution is set to fCPU / 64 by setting PTI3 in register PWMCON0 to 1. This is compulsory in generating 50 Hz square wave because if the resolution is set to CPU clock (20MHz); the binary number of PP3 will be more than 16-bit, which is out of register limit. Where the new counter resolution to generate 50Hz square wave signal is set to fCPU / 64 (312.5kHz). PP3 is chosen to generate 50Hz square wave signal, which in clock-count, it can be written as: 312.5kHz 50 Hz

PP3 =

= 6250 clock-count

(3.3)

To generate 50Hz square wave signal, the Pulse Width Register (PWx) for this signal PW3, must be half of PP3, which is equal to 3125 clock-count.

3.3.6

Generation of V1(k) and V2(k) Signals

In order to generate V1(k) and V2(k) signals, Center Aligned PWM operation mode is selected by setting bit PMx in register PWMCON1 to 1. Since the PWM module of the SAB-C167CR-LM offers four channels in generating PWM signals, which channel 3 is used in generating 50Hz square wave, other three channels namely; 0,1 and 2 are dedicated in generating V1(k) and V2(k). To generate PWM signals V1(k)

36

and V2(k), channel 0 and 1 are chosen, respectively. While channel 2 is dedicated as input trigger for PECC6 in CAPCOM Units to generate PW1. This condition is required because only 1 interrupt is provided in PWM Module. This interrupt (PWMIC) is selected for channel 0 to generate V1(k). From above explanation, all registers dedicated in generating V1(k) and V2(k) can be expressed as:

PP0 = PP1= PP2 = period_reg, Where period_register is presented by:


period _ reg = fCPU f o 2m f
= 20 MHz 50 2 m f 200000 mf

(3.4)

Since the equation derived is in time domain, conversion to clock-count is compulsory. The conversion can be written as:
PWx = period _ reg ( period _ reg ( 2 k 1) E fCPU )

(3.5)

Pulse Width Register (PWx) in equation (3.7) is M (k ) in form of clock-count domain, while E represents the gating signal equations derived in Chapter III. Hence in generating signals V1(k) and V2(k), the Pulse Width Register PW0, PW1 and PW2 is written as:
T A PW0 = period _ reg period _ reg ( 2k 1) c (2k 1) m sin ( k 1) + 2 Ac mf 20 M (3.6)

T A PW1 = period _ reg period _ reg ( 2 k 1) c 2 k m sin ( k 1) + 20 M 2 A m c f

(3.7)

PW2 =

period _ reg 2

(3.8)

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3.4

Functional Block Diagram

The functional block diagram of the microcontroller ports, ex-or gate, IGBT gate drive and power circuit are shown in Figure 3.7. The PWM signals (V1(k) and V2(k)) and 50 Hz squarewave are generated by the PWM module and latched out via C167 microcontroller parallel ports P7.0, P7.1 and P7.3, respectively. The fast external interrupt signal for P7.2, which operates as input trigger for P7.1 is activated via port P.2.9. The enable signals for IGBT gate drive are also supplied by microcontroller via ports P2.0 through P2.3.

P2.0 P2.1 P2.2 P2.3 E1 S31 S41 C2 S11 S21 C1

P2.9 S 11 P7.0 P7.1 P7.2 P7.3 S 21 S 31 S 41 S 12 S 22 S 32 S 42

S 12 E2

S22

C3

S 32

S42

C4

Micro controller

EX-Or Gate

Gate Drive Circuit

Power Circuit

Figure 3.7: Functional Block Diagram

3.4.1

Ex-or Gate

The ex-or gate is required to generate gating signals for switches S12/S32 and S22/S42. The speed of the ex-or gate must be sufficiently high to ensure delay between PWM output signals of ex-or gate and fundamental signal are not very significant. The CD74ACT86E is the most suitable TTL to do the task. It is a high speed Si-gate CMOS device manufactured by Texas instrument. The maximum rise and fall time for the IC is only 10ns, which is more than adequate to execute the task. It has four ex-or gates integrated in the IC with 2 inputs and 1 output for each gate. Only two signals are need to produce from the IC, hence only two gates are used in the process.

R Load

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3.4.2

Gate Drive Circuit

An IGBT is a voltage-controlled device that needs a low firing signal to turn the device on and off. In this work each of the eight devices are switched using a gate drive circuit that designed in house [49]. Each gate-drive circuit requires 100mA and 12V as input to produce an isolated 15V output signal.

enable signal from micro controller

PWM signal from logic circuit

Dead time circuit

+15Vdc +12Vdc DC isolation circuit

-15Vdc

Signal isolation circuit

15Vdc gate signal (A) 15Vdc gate signal (A)

Figure 3.8: Block diagram of gate drive circuit. The gate drive circuit can be separated into three parts as depicted in Figure 3.8. Dead time circuit is added to each gate signal for protection against shoot-through in the inverter leg. The dc power supply for top and bottom IGBT of the same leg need to be isolated. This is achieved by a high frequency transformer, which is employed in dc isolation circuit. The PWM signals from logic circuit also need to be isolated to protect the controller board from any incoming surge or high voltage signals from power circuit. This is accomplished by a pair of optocouplers, which integrated in signal isolation circuit. The gate drive circuit provides a +15V and 15V of output voltage. This feature avoids the problem of Miller effect on the top switch when the bottom switch at the same leg suddenly turns on. For a modular structured five level inverter, four equivalent gate drive circuits is required to control eight IGBT switches.

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3.4.3

Power Circuit

As illustrated in Figure 3.7, two modules of cascaded inverter power circuit are required for a five-level inverter. Both modules are connected in series and constructed from IGBT switches and dc link capacitors.

3.4.4

IGBT Switch

Power switches used for the inverter are type IRG430CKD IGBTs, manufactured by International Rectifier. They come in a single unit with an anti parallel diode as shown in Figure 3.9. Some of the important ratings of this particular IGBT are shown in Table 3.1.

Figure 3.9: Structure of IGBT type IRG430CKD. Table 3.1: Ratings and specifications of IGBT type IRG430CKD. VCE (V) 600 VCE sat (V) 2.21 IC (cont at (A) 28 ICM Pulsed (A) 58 tr (ns) 42 tf max. (ns) 120 PD (at 25C)
(W)

25C)

100

VCE = collector-emitter voltage; VCE sat = collector-emitter saturated voltage; IC (cont at 25C) = collector current (flowing continuously at 25C); ICM = maximum collector pulsed current; tr = rise time; tf = maximum fall time.

3.5

Flowchart of the program in generating PWM signals

The flowchart of the PWM generation program is shown in Figure 3.10. After power-up the microcontroller board, initialization of all variables and peripheral ports take place. The resolution for each PWM channel is configured in the PWM

40

timer. The desired modulation index, mi and modulation ratio, mf is chosen by setting the value in the program. By resetting the switch of the board the operation is stopped.
START

Initialize variable

Initialize port, CAPCOM, PWM module, PEC and set all interrupt

Set the desired Modulation Index and Modulation Ratio

RESET

END

Figure 3.10: Flowchart for PWM generation program.

3.5.1

Setting-up MCB167 and main subroutines

This section is concerns about setting-up the MCB167 board and peripherals for the intended application. It involves the setting of the PWM Module, PWM Interrupt and Peripheral Event Controller. The subroutines in this section are briefly describes as follows: PWM_init(): In PWM Module, 3 channel is set at CPU clock and symmetrical PWM generation (centered aligned), while 1 channel is set to CPU/64 clock and standard PWM generation (edge aligned). PWM_PEC_init(): Since only one interrupt is provided by PWM Module, this interrupt (PWMIC) is dedicated for channel 0. PEC_init(): The peripheral event controller is set to respond an interrupt request for PWM Module in channel 1 using channel 2 as input trigger.

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3.6

Sample Waveforms

Output Waveforms From MCB167 Figure 3.11 (a) and 3.11 (b) shows the PWM waveforms generated from microcontroller MCB167 using the derived equation. In Figure 3.11 (a) the PWM signals V1(k), V2(k) and 50 Hz square waves for mi = 0.4, mf = 20 are depicted, while Figure 3.11 (b) show the same signals for mi = 0.8, mf = 20. The signals shown in the both figures are using time scale of 4ms/div and voltage scale of 5V/div. It can be observed that the signals generated from the microcontroller board are identical with the signals obtained in simulation work. Recall that PWM signal V2(k) only exist when mi is greater than 0.3. For mi less than 0.5, V2(k) is zero as evidently seen in both figures.

V1(k) V2(k) 50Hz square wave

(a)

V1(k) V2(k) 50Hz square wave

(b) Vertical scale 5V/div. Horizontal scale 2ms/div. Figure 3.11: PWM output signals from microcontroller port for (a) ma = 0.4, mf = 20 and (b) mi = 0.8, mf = 20.

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As perviously mentioned, to obtain signals for S21 and S22, signals V1(k) and V2(k) are ex-ored with the 50Hz square wave. Figure 3.12 (a) and 3.12 (b) represent the signals for gate drive S21 and S22 for mi = 0.4, mf = 20 and mi = 0.8, mf = 20, respectively.

S21

S22

(a)

S21

S22

(b) Vertical scale 5V/div. Horizontal scale 2ms/div. Figure 3.12: Signals for gate drive S21 and S22 (a) mi = 0.4, mf = 20 and (b) mi = 0.8, mf = 20. Figure 3.13 (a) and 3.13 (b) represent the gate drive signals of S11, S12, S21 and S22 for mi = 0.4, mf = 20 and mi = 0.8, mf = 20, respectively. It can be seen that the waveforms of square wave and PWM signals (S21 and S22) are identical with the output signal from microcontroller and digital circuit, respectively. However the

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amplitude of these signals are increased from 0V and +5V to -15V and +15V to drive the IGBT.

S11 S12 S21 S22

(a) S11 S12 S21 S22

(b) Vertical scale 20V/div. Horizontal scale 2ms/div. Figure 3.13: Signals of S11, S12, S21 and S22 for (a) mi = 0.4, mf = 20 and (b) mi = 0.8, mf = 20.

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CHAPTER IV RESULTS AND ANALYSES 4.1 Introduction

This chapter presents the practical results obtained from the MSMI prototype described in Chapter III. As a standard measure to evaluate the performance of inverter, analysis on the Total Harmonic Distortion (THD), Harmonic Loss Factor (HLF) and Second-order Distortion Factor (DF2) for a five-level MSMI is carried out. The analysis includes theoretical and practical results of five-level MSMI in comparison to conventional two-level inverter. The variations and differences between those results are explained. Finally the effectiveness and performance of the proposed modulation scheme when employed to MSMI is evaluated.

4.3 Results

This section presents the selected voltage output and current output waveforms for the five-level MSMI obtained from experimental test-rig. These results are compared to the simulation. The inverter input voltages are fixed at 100V dc for each module and the inverter load is a purely resistive.

4.2.1

Inverter Output Voltage and Current

Figure 4.1 (a) shows the oscilogram of the output voltage and current of the inverter for mi = 0.4 and mf = 20. The figure shows that the practical result obtained from test-rig is in good agreement with the simulation result, which is shown in Figure 4.1 (b). The output voltage and output current for practical and simulation results is about 56Vrms and 1.13Arms. For the case of mi = 0.8 and mf = 20 shown in Figures 4.2 (a) and 4.2 (b), the consistency between the practical and simulation results holds. For this case, the output voltage and output current for practical and simulation results is about 112Vrms and 2.26Arms, which is doubled compared to the previous case. Since the measurement is made under pure resistance load, the current waveforms are in phase with the voltage waveform, which is clearly shown by these results.

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Vout(V)

Iout(A)

Top trace: Vout. Vertical scale 100V/div. Bottom trace: Iout. Vertical scale 2A/div. Horizontal scale 2ms/div. Figure 4.1 (a): Practical result for mi = 0.4; mf = 20.

Top trace: Vout. Vertical scale 100V/div. Bottom trace: Iout. Vertical scale 2A/div. Horizontal scale 2ms/div. Figure 4.1 (b): Theoretical result for mi = 0.4; mf = 20.

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Vout(V)

Iout(A)

Top trace: Vout. Vertical scale 100V/div. Bottom trace: Iout. Vertical scale 2A/div. Horizontal scale 2ms/div. Figure 4.2 (a): Practical result for mi = 0.8; mf = 20.

Top trace: Vout. Vertical scale 100V/div. Bottom trace: Iout. Vertical scale 2A/div. Horizontal scale 2ms/div. Figure 4.2 (b): Theoretical result for mi = 0.8; mf = 20.

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4.2.2

Harmonic Spectrum

Performance of an inverter is determined by its harmonic content. This section presents the harmonic spectrum of a modular structured five-level inverter under different modulation indexes and ratios. Since the inverter has a pure resistive load, the harmonic spectrum for its output current is similar with the output voltage. Hence only harmonic spectrum of the latter is shown. For the case of mf = 20 and mi = 0.4, the practical result of output voltage harmonic spectrum are shown in Figures 4.3 (a). The theoretical harmonic spectrum is calculated using the derived equations in Chapter IV. The equations, namely (4.18) and (4.32) for the case when mi 0.5 and 0.5 < mi 1 respectively are subsequently programmed and plotted using MATLAB m-file. The theoretical spectrum for the similar case is shown in Figure 4.3 (b). By comparing Figures 4.3 (a) and 4.3 (b), it can be clearly observed that the harmonics incidences for mi 0.5 agree closely with theoretical predictions. The proposed modulation scheme produces only odd harmonic for even modulation ratio. Furthermore, harmonics at the carrier and the multiples of carrier frequency do not exist at all. These observations confirm the analysis, whereby it was concluded that for even modulation ratio, even harmonics are absent. The figures indicate that the magnitude of fundamental harmonic is 53.8Vrms for practical result and 54.56Vrms for simulation result. The tabulated results shown in Table 4.1 indicate that the first significant harmonic is located at the 19th. Practically, the magnitude of this harmonic is 24.8Vrms, which is 44.44% of the normalized fundamental. Using simulation, the magnitude is 24.7733Vrms and the ratio is 43.8%, which proves the validity of the drived equations. To demonstrate the concurrence between simulated and theoretical results, the value of the first group of significant harmonic order is tabulated in Table 4.1. It can be concluded that the results obtained from test-rig i.e. in a good agreement with the theoretical predictions.

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Vertical scale 10V/div. Horizontal scale 500Hz/div. Figure 4.3 (a): Practical harmonic spectrum of output voltage for mi = 0.4; mf = 20.

(n)

Vertical scale 10V/div. Horizontal scale 500Hz/div. Figure 4.3 (b): Theoretical harmonic spectrum of output voltage for mi = 0.4; mf = 20.

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Table 4.1: Predicted and measured values of the first group of significant harmonic order for mi = 0.4; mf = 20. Number of Harmonic order 17 19 21 23 25 850 950 1050 1150 1250 Frequency (Hz) Magnitude of harmonic (V) Simulation 8.0172 24.7733 19.7115 11.3250 1.8777 Measured 7.6 24.8 19.8 11.4 1.6

Note: Simulation values are defined from the harmonic figures (after zoomed). Measured readings are taken directly from numerical values of harmonics given by Tektronix TDS3054 osiloscope For the case of mf = 20; mi = 0.8, practical and theoretical results of the output voltage harmonic spectrum are illustrated in Figure 4.4 (a) and 4.4 (b), respectively. Again, it can be seen that as far as the harmonics incidences are concerned, the practical results agree with theory. The figures indicate that the magnitude of fundamental harmonic is 107Vrms for practical result and 113.12Vrms for simulation result The first significant harmonic is located at 19th with magnitude of 24.9087Vrms or 23.79% of the normalized fundamental. From the test-rig, the same harmonic is 27.6Vrms or 23.79% of the fundamental. Recall that for five-level inverter, mi = 0.4 is equivalent to mi = 0.8 for a three-level inverter. As concluded by Agelidis [36], for an equivalent modulation index, the significant harmonic of a five-level is half compared to a three-level inverter. Table 4.2 tabulates the predicted and numerical results of the first group of significant harmonics. The comparison shows that for 13th and 17th harmonic order, the error is quite significant. The possible explanation for this would be the assumptions that were made when deriving the equation. In the mathematical formulation, inverter input voltage is assumed a pure dc voltage, but in practice there are ripples in dc voltages obtained from power supply. However, other harmonics especially the first significant one exhibits small error. In general, the simulation and

50

practical results can be considered close enough to validate the correctness of the mathematical analysis.

Vertical scale 20V/div. Horizontal scale 500Hz/div. Figure 4.4 (a): Practical harmonic spectrum of output voltage for mi = 0.8; mf = 20.

(n)

Vertical scale 20V/div. Horizontal scale 500Hz/div. Figure 4.4 (b): Theoretical harmonic spectrum of output voltage for mi = 0.8; mf = 20.

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Table 4.2: Predicted and measured values of the first group of significant harmonic order for mi = 0.8; mf = 20. Number of Harmonic order 13 15 17 19 21 Frequency (Hz) 650 750 850 950 1050 Amplitude of harmonic (V) Simulation 3.5870 3.9801 1.1052 24.9087 17.4743 Measured 4.4 3.6 2.0 27.6 18.0

4.2.3

Harmonics Performance at Higher Modulation Ratio

To evaluate the modulation scheme performance at higher frequency, test at modulation ratio equal to 200 is carried out. This ratio corresponds to switching frequency of 10 kHz. The practical and simulation results for this case when modulation index equals 1.0 is shown in Figure 4.5 (a) and 4.5 (b), respectively. It can be seen that at high switching frequency, the practical result in a good agreement with the simulation result. The rms output voltage and output current for practical and simulation results is about 112V and 2.26A The respective harmonic spectrum, as illustrated in Figure 4.6 (a) and 4.6 (b), are also consistent with each other.

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Vout(V)

Iout(A)

Top trace: Vout. Vertical scale 100V/div. Bottom trace: Iout. Vertical scale 2A/div. Horizontal scale 2ms/div. Figure 4.5 (a): Practical result for mi = 1.0 mf = 200.

Top trace: Output voltage. Vertical scale 100V/div. Bottom trace: Output current. Vertical scale 2A/div. Horizontal scale 2ms/div. Figure 4.5 (b): Simulation result for mi = 1.0 mf = 200.

53

Vertical scale 20V/div. Horizontal scale 5kHz/div. Figure 4.6 (a): Practical harmonic spectrum of output voltage for mi = 1.0 and mf = 200.

(n)

Vertical scale 20V/div. Horizontal scale 5kHz/div. Figure 4.6 (b): Theoretical harmonic spectrum of output voltage for mi = 1.0 and mf = 200.

54

Figures 4.7 (a) and 4.7 (b) depict the spectra of the output voltages for mi = 1.0 and mf = 20. Comparing to the previous test, i.e mi = 1.0 and mf = 200, all the harmonics are shifted to higher frequencies in accordance to increase in the modulation ratio. This is consistent with the general PWM modulation theory. Numerically, it was found that first significant harmonic is slightly decreased when the modulation ratio is changed but the difference is relatively small. For this particular case, magnitude of the first significant harmonics are 13.81% and 10.74% compared to the fundamental harmonic for the mf = 20 and mf = 200, respectively. The increase of the former may be attributed to the overlaps that occur when the modulation ratio is insufficiently high.

Vertical scale 20V/div. Horizontal scale 500Hz/div. Figure 4.7 (a): Practical harmonic spectrum of output voltage for mi = 1.0 and mf = 20.

55

(n)

Vertical scale 20V/div. Horizontal scale 500Hz/div. Figure 4.7 (b): Theoretical harmonic spectrum of output voltage for mi = 1.0 and mf = 20.

4.3

Generalized of Harmonics Table for Five-level Inverter

The harmonics in the PWM inverter output voltage waveform appear as sidebands, clustered around the switching frequency and its multiples, i.e mf, 2mf, 3mf etc. This general pattern is true for all values of mi in the range 0 through 1.0. Table 4.3 attemps to generalize the harmonic amplitudes with respect to the fundamental voltage for a five-level inverter. The table is created using the calculated values from equation (4.18) and (4.32). As previously discussed, the amplitude of sidebands harmonic is somewhat larger when the inverter is switching at low frequency. The increase may be attributed to the overlaps that occur between the clusters when the modulation ratio is insufficiently high. From numerous trials, it was concluded that the minimum modulation ratio that guarantee no overlaps occurence is 30. Therefore, the table is sufficiently accurate for modulation ratio greater than 30. It can be observed that the amplitude of the fundamental component in the output voltage varies linearly with

56

mi. It also can be seen that the numbers of sidebands at the first significant harmonic group (mf), increased in proportional to mi.

Table 4.3: Generalized harmonics of voltage output for large mf in term of the normalized fundamental. mi Fundamental mf 1 mf 3 mf 5 mf 7 2mf 1 2mf 3 2mf 5 2mf 7 3mf 1 3mf 3 3mf 5 3mf 7 4mf 1 4mf 3 4mf 5 4mf 7 0.0262 0.0299 0.0204 0.0038 0.0035 0.0442 0.0105 0.0163 0.0265 0.0338 0.0286 0.0021 0.0055 0.0185 0.0157 0.0801 0.0339 0.0027 0.0523 0.0522 0.0445 0.2 0.2 0.1642 0.0109 0.4 0.4 0.1632 0.0656 0.0047 0.6 0.6 0.1079 0.0634 0.0624 0.0076 0.0245 0.0425 0.0455 0.0442 0.0384 0.0182 0.0045 0.0064 0.0161 0.0144 0.0088 0.0080 0.8 0.8 0.1542 0.0145 0.0454 0.0534 0.0049 0.0115 0.0375 0.0295 0.0155 0.0295 0.0145 0.0179 0.0071 0.0085 0.0118 0.0138 1.0 1.0 0.0998 0.0774 0.0010 0.0425 0.0221 0.0185 0.0091 0.0358 0.0152 0.0035 0.0112 0.0095 0.0075 0.0085 0.0022 0.0042

4.4

Performance Indexs for the Proposed Modulation Scheme

This section is dedicated to analyse the performance of five-level MSMI using the proposed modulation scheme. Analyses on Total Harmonic Distortion (THD), Harmonic Loss Factor (HLF) and Second Order Distortion Factor (DF2) are carried out. Practical and theoretical performance indexes of five-level MSMI using the proposed modulation scheme are compared with conventional two-level SPWM inverter.

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4.4.1

Total Harmonic Distortion (THD)

Total Harmonic Distortion (THD) is the most common power quality index to describe the quality of power electronic converter [49,50]. In general, all the output voltage of power electronic converters is not purely sinusoidal. The THD of the output voltage can be defined as:

THD =

V
n=2

2 h

V1

(4.1)

Where n denotes the harmonic order and 1 is the fundamental quantity. For inverter application, THD represents how close the ac output waveform with pure sinusoidal waveform. A high-quality inverter system should have low THD. Figure 4.8 shows the comparison of the THD between a five-level single-phase MSMI and a conventional two-level inverter configuration. The figure shows that for both cases, a poor THD are obtained when the inverter operated at low modulation index. This is to be expected because at mi 0.5, the MSMI essentially behaves like a conventional three-level inverter. A better THD is obtained when the inverter operated at higher modulation index. For example, at modulation index equals 1.0, it was found that THD for a MSMI inverter is very much better compared to a conventional two-level inverter.

THD
6 4 2 0 5-level MSMI (Practical) 5-level MSMI (Theoretical) 2-level PWM

0.2 6.6612 6.6521 6.6798

0.4 1.788 1.7341 3.2179

0.6 0.6575 0.6759 2.0147

0.8 0.4581 0.4462 1.3571

1 0.2631 0.2607 0.9154

mi

Figure 4.8: Variation of THD for five-level MSMI and two-level SPWM inverter configuration. Note: Data for two-level SPWM is obtained from Mohan et al [46].

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It is also worthwhile to note that for the MSMI, the calculated value of THD using the derived equations for the harmonics agree closely with the data obtained from the test-rig. For both cases, the calculation for THD is done by considering only the first four harmonic clusters.

4.4.2

Harmonic Loss Factor (HLF)

Another important quality index of PWM technique is related to losses in inverterfed ac drives. These losses represent harmonic copper loss and are quantified as harmonic loss factor (HLF) [26,51]. The harmonic equivalent circuit of an induction machine can be assumed to be its total leakage reactance at the harmonic frequency. Therefore harmonic current In is given by:

In =
Where: Vn Le N VL1

Vn 2 nfLe

(4.2)

harmonic voltage leakage inductance of the motor order of the harmonic inverter output voltage (determine by modulation index) In a variable speed ac drive it is necessary to main constant volt/hertz.

Therefore, the fundamental component of the inverter output voltage VL1 is proportional to the operating frequency f. Equation (4.2) can be rewritten taking Le as the p.u quantity:

I n

Vn nVL1

(4.3)

The HLF, which is proportional to total rms harmonic current, can be defined as [26]:
100

HLF =

VL1

Vn n =5 n

(4.4)

A good inverter-fed ac drive system should have a low HLF.

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Figure 4.9 shows the variation of HLF for single-phase five-level MSMI and a conventional two-level inverter. The figure shows that for both inverter types, a poor HLF are obtained when the inverter operated at low modulation index. However, at higher modulation index, the HLF improve tremendously. For example, at mi = 1.0, the HLF of the MSMI is reduced to about one third of the two-level inverter. The result is expected because in general, the HLF will follow the trend of THD.

HLF

35 30 25 20 15 10 5 0 0.2 29.824 30.208 31.399 0.4 7.929 7.731 14.755 0.6 2.719 2.881 8.864 0.8 2.102 2.063 5.745

mi

1 1.212 1.206 3.941

5-level MSMI (Practical) 5-level MSMI (Theoretical) 2-level SPWM

Figure 4.9: Variation of HLF for five-level MSMI and two-level SPWM inverter configuration. Note: Data for two-level SPWM is obtained from Mohan et al [46].

4.4.3

Second Order Distortion Factor (DF2)

Inverter power supplies such as uninterruptible power supplies (UPS) employ an L-C filter between the inverter and the load. The main purpose of this filter is to provide harmonic attenuation, which is proportional to the square of the order (n) of the harmonic. A distortion factor that represents total harmonic content at the output of a second-order filter as can be described as [26]:
100

DF2 =

VL1

Vn 2 n =5 n

(4.5)

For an inverter power supply a PWM scheme that results in minimum DF2 is desirable.

60

Figure 4.10 illustrates the DF2 variation for a single-phase five-level MSMI and a two-level conventional inverter. The figure demonstrates that the DF2 for five-level MSMI and two-level inverter is about equal when the modulation index is low. However as the index increasing, the DF2 for the MSMI reduces significantly compared to two-level inverter. At mi = 1.0, it can be observed that DF2 for MSMI is three times better than the two-level inverter.

1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 5-level MSMI (Practical) 5-level MSMI (Theoretical) Two-level SPWM 0.2 1.475 1.482 1.556 0.4 0.391 0.386 0.725 0.6 0.141 0.148 0.431 0.8 0.109 0.119 0.278 1 0.069 0.072 0.193

DF2

mi

Figure 4.10: Variation of DF2 for five-level MSMI and two-level SPWM inverter configuration. Note: Data for two-level SPWM is obtained from Mohan et al [46]. From the analyses for THD, HLF and DF2 above, it can be concluded that the performance of MSMI as far better than the conventional two-level inverter. It should noted that for purpose of simplicity analysis was carried for one particular value of modulation ratio i.e mf = 40. However, it was found that for other values of

mf (above 30), it trend does not change very much. This is in conformity with the
conclusion described in [26]. It also important to note that the number of harmonics considered in all calculation above is only up to the fourth cluster.

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CHAPTER V

SUMMARY, CONTRIBUTIONS AND SUGGESTION FOR FURTHER WORK

5.1

Summary of the Research

As a prelude to the report, a brief introduction on inverter that includes an overview of inverter power circuit topologies, switching strategies and modulation techniques has been presented. Several important multilevel inverter topologies namely Diode Clamped Multilevel Inverter (DCMI), Flying Capacitor Multilevel Inverter (FCMI) and Modular structured Multilevel Inverter (MSMI) basic structure have been described. Their merits and disadvantages have been discussed. The inverter topology selection basically depends on the application and the features of their dc sources. It was concluded that for application that requires separated dc sources such as renewable energy power inverter, MSMI is the most suitable choice. This topology does not suffer unbalance voltage problem and requires the least number of component compared to its rival. Several multilevel switching techniques proposed by previous researcher are discussed. However only sinusoidal pulse width modulation (SPWM) is explained in detail since it is directly related to this work. This PWM technique is simple and it promises significant improvement to the harmonic distortion when applied to multilevel inverter. Using unipolar regular sampling, a new PWM modulation scheme for MSMI is proposed. It is based on the intersection of several modified modulating waveforms with a single carrier waveform. In order to implement the switching technique into hardware, a 16-bit microcontroller (SIEMENS SAB-C167CR-LM) is chosen to generate the PWM pulses for a single-phase, five-level MSMI. Then a low-power test-rig has been constructed and the performance of the inverter with the proposed switching scheme is analyzed.

62

From the comparison between the practical and theoretical work, it can be concluded that the practical results are in close agreement with the theory. In harmonic analysis, it was found that only odd harmonic order is exists for the modulation scheme since the modulation ratio is limited to even number. The positions of the harmonics depend on the modulation ratio. All the harmonics are shifted to high frequencies when the modulation ratio increased. The amplitude of each harmonic depends on the modulation index, the better harmonic performance can be obtained when modulation index get closer to 1.0. It also found that for the same modulation index, the harmonics amplitude of five-level inverter is reduced to half compared to three-level inverter. Analyses on Total Harmonic Distortion (THD), Harmonic Loss Factor (HLF) and Second Order Distortion Factor (DF2) conclude that the harmonic performance of modular structured five-level inverter using the proposed modulation scheme is superior compared to conventional two-level inverter.

5.2

Contributions

The aim of the research is to develop a digital PWM scheme for multilevel inverter suitable for photovoltaic application. The proposed modulation scheme is based on symmetric regular sampling SPWM technique using multiple modulating signals with a single carrier. This study has led to two important contributions. The derived equations based on the proposed modulation scheme were proven suitable for an online microprocessor PWM generation. It has been shown that the gating signals for a five-level inverter can be easily generated using a fixed-point (integer) microprocecessor. The second contribution is the analytical method to obtain the Fourier coefficients for a five-level MSMI using the proposed modulation scheme. The harmonic spetra that resulted from the analysis was proven to be within good agreement with experimental work carried out on a five-level MSMI test-rig. From the theoretical and practical results, it can be seen that the harmonic spectrum produced from the proposed modulation scheme is very similar with Phase Opposition Disposition (POD) scheme proposed by previous researchers. This is because the end-results of both modulation techniques are quite similar although the approaches taken are significantly different. Traditional POD scheme uses a pure sinusoidal modulating signal modulated with several carrier signals, while the

63

proposed scheme is using a single carrier signal modulated with several modified sinusoidal modulating signals. There are some significant advantages with the newly proposed modulation technique. The trigonometric equations to generate the switching angles prove to be quite simple and can easily implemented using a fix point microprocessor. It is also shown by simulation that the same equation could be used to generate gating signals for N-level inverter. Therefore, it is anticipated that the proposed modulation technique can be employed to N-level inverter without any difficulty.

5.3

Suggestion for Further Work

The proposed switching algorithm is tested only for purely resistive load in linear modulation. To test the full capability of the developed system, a reactive load such as R-L load test and inverter-fed ac drive test should also be performed. The test should carry out in both modulation range, i.e linear and over modulation. A more sophisticated and high-resolution processor can be implemented on the inverter system. It is expected by using the floating-point processor such as DSP, the proposed swithing algorithm will produce more accurate results, especially at high modualtion ratio. It is also possible the derived equations be used in multi-phase and higher-level inverter. The general equation should be extended to other multilevel inverter topologies such as Diode Clamped Multilevel Inverter (DCMI) and Flying Capacitor Multilevel Inverter (FCMI).

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