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LMD18200 3A, 55V H-Bridge
Check for Samples: LMD18200

Delivers Up to 3A Continuous Output Operates at Supply Voltages Up to 55V Low RDS(ON) Typically 0.33Ω per Switch at 3A TTL and CMOS Compatible Inputs No “Shoot-Through” Current Thermal Warning Flag Output at 145°C Thermal Shutdown (Outputs Off) at 170°C Internal Clamp Diodes Shorted Load Protection Internal Charge Pump with External Bootstrap Capability

• • • • • DC and Stepper Motor Drives Position and Velocity Servomechanisms Factory Automation Robots Numerically Controlled Machinery Computer Printers and Plotters

• • • • • • • • • •

The LMD18200 is a 3A H-Bridge designed for motion control applications. The device is built using a multitechnology process which combines bipolar and CMOS control circuitry with DMOS power devices on the same monolithic structure. Ideal for driving DC and stepper motors; the LMD18200 accommodates peak output currents up to 6A. An innovative circuit which facilitates low-loss sensing of the output current has been implemented.

Functional Diagram

Figure 1. Functional Block Diagram of LMD18200



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Copyright © 1999–2013, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

ti. Texas Instruments Incorporated .LMD18200 SNVS091F – DECEMBER 1999 – REVISED APRIL 2013 www. 11-Lead TO-220 Package Top View See Package NDJ0011B 2 Submit Documentation Feedback Product Folder Links: LMD18200 Copyright © 1999– Connection Diagram Figure 2.

Human-body model.0°C/W and from junction to ambient (θJA) is 30°C/W. 5 VIN = −0. TJ(max) ESD Susceptibility (5) Storage Temperature. 4. Contact factory. Submit Documentation Feedback Product Folder Links: LMD18200 3 Copyright © 1999–2013. Regulation is calculated relative to the current sense output value with a 1A load. Pins = 3. DC and AC electrical specifications do not apply when operating the device beyond its rated operating conditions.5 kΩ resistor. The typical thermal resistance from junction to case (θJC) is 1. 4. 10 sec. Pin 6) Voltage at Pins 3. The maximum allowable power dissipation at any temperature is PD(max) = (TJ(max) − TA)/θJA. For ensured operation TJ(max) = 125°C. Texas Instruments Incorporated . DC and AC electrical specifications do not apply when operating the device beyond its rated operating conditions. See Application Information for details regarding current limiting.1 0.LMD18200 www.1V. The maximum power dissipation must be derated at elevated temperatures and is a function of TJ(max).5 −0. 5. and TA. please contact the Texas Instruments Sales Office/Distributors for availability and specifications. 4. Free Air) Junction Temperature. TJ VS Supply Voltage (1) −40°C to +125°C +12V to +55V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.6 1.45/0. 5 Pins 3. Duty Cycle < 5%). (1) Operating Ratings Junction Temperature. Output currents are pulsed (tW < 2 ms. 5 VIN = 12V. 100 pF discharged through a 1. TSTG Lead Temperature (Soldering.8 −10 2 12 10 Units Ω (max) Ω (max) V (max) V (min) V (max) μA (max) V (min) V (max) μA (max) μA (min) μA (max) % 377 (4) 325/300 425/450 ±9 1A ≤ IOUT ≤ 3A ±6 All limits are 100% production tested at 25°C. Temperature extreme limits are ensured via correlation using accepted SQC (Statistical Quality Control) methods. Boldface limits apply over the entire operating temperature range.38 1. Symbol RDS(ON) RDS(ON) VCLAMP VIL IIL VIH IIH Parameter Switch ON Resistance Switch ON Resistance Clamp Diode Forward Drop Logic Low Input Voltage Logic Low Input Current Logic High Input Voltage Logic High Input Current Current Sense Output Current Sense Linearity (1) (2) (3) (4) Conditions Output Current = 3A Output Current = 6A Clamp Current = 3A Pins 3. Selections for tighter tolerance are available.ti. 8 and 9 Voltage at Bootstrap Pins Continuous Output Current Power Dissipation (4) 60V 12V VOUT +16V 6A 3A 25W 3W 150°C 1500V −40°C to +150°C 300°C (Pins 1 and 11) (3) Peak Output Current (200 ms) Power Dissipation (TA = 25°C. If Military/Aerospace specified devices are required. (1) Electrical Characteristics The following specifications apply for VS = 42V.) (1) (2) (3) (4) (5) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Except Bootstrap pins (pins 1 and 11) which are protected to 1000V of ESD. Absolute Maximum Ratings (1) (2) Total Supply Voltage (VS. Pins = 3. −40°C ≤ TJ ≤ +125°C. 4.6 0. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. whichever is lower.40/0. (Average Outgoing Quality Level). or the number given in the Absolute Ratings.33 0.2 Limit 0. 4. θ SNVS091F – DECEMBER 1999 – REVISED APRIL 2013 These devices have limited built-in ESD protection. 5 IOUT = 1A (3) (2) (2) (2) Typ 0. all other limits are for TA = TJ = 25°C. All limits are used to calculate AOQL. unless otherwise specified.

2 170 13 300 300 25 10 Typ Limit 9 11 Units V (min) V (max) °C V μA (max) °C mA (max) ns ns 4 Submit Documentation Feedback Product Folder Links: LMD18200 Copyright © 1999–2013. IOUT = 3A Sinking Outputs. IOUT = 3A Bootstrap Capacitor = 10 nF Sourcing Outputs. IOUT = 3A Sinking Outputs. IOUT = 3A tpw tcpr Minimum Input Pulse Width Charge Pump Rise Time Pins 3. Boldface limits apply over the entire operating temperature range. IOUT = 3A Sinking Outputs.8V. all other limits are for TA = TJ = 25°C. IOUT = 3A tDoff toff Output Turn-Off Delay Times Output Turn-Off Switching Times Sourcing Outputs. Texas Instruments Incorporated . IL = 2 mA VF = 12V Outputs Turn OFF All Logic Inputs Low Sourcing Outputs. −40°C ≤ TJ ≤ +125°C. IOUT = 3A Sinking Outputs. Symbol Parameter Undervoltage Lockout TJW VF(ON) IF(OFF) TJSD IS tDon ton Warning Flag Temperature Flag Output Saturation Voltage Flag Output Leakage Shutdown Temperature Quiescent Supply Current Output Turn-On Delay Time Output Turn-On Switching Time Conditions Outputs turn OFF Pin 9 ≤ Electrical Characteristics (1) (continued) The following specifications apply for VS = 42V. unless otherwise specified. 4 and 5 No Bootstrap Capacitor 75 70 1 20 ns ns μs μs 100 80 200 200 ns ns ns ns 145 0.15 0.LMD18200 SNVS091F – DECEMBER 1999 – REVISED APRIL 2013 www. IL = 2 mA TJ = TJW. IOUT = 3A Bootstrap Capacitor = 10 nF Sourcing Outputs.ti.

Supply Current vs Frequency (VS = 42V) Figure 6.ti. Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMD18200 5 . Copyright © 1999–2013. RDS(ON) vs Supply Voltage Figure 4. Supply Current vs Temperature (VS = 42V) Figure SNVS091F – DECEMBER 1999 – REVISED APRIL 2013 Typical Performance Characteristics VSAT vs Flag Current RDS(ON) vs Temperature Figure 3.LMD18200 www. Supply Current vs Supply Voltage Figure 5. Figure 8.

LMD18200 SNVS091F – DECEMBER 1999 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Current Sense Output vs Load Current Current Sense Operating Region Figure 9. Texas Instruments Incorporated . 6 Submit Documentation Feedback Product Folder Links: LMD18200 Copyright © 1999–2013.ti. Figure 10.

com SNVS091F – DECEMBER 1999 – REVISED APRIL 2013 TEST CIRCUIT Switching Time Definitions Copyright © 1999–2013.ti.LMD18200 www. Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMD18200 7 .

Pin 5. in this case only a small bias current (approximately −1. The recommended capacitor (10 nF) is connected between pins 10 and 11. Source 2 Source 1.ti. Sink 2 Sink 1. Pin 9 becomes activelow at 145°C (junction temperature). CURRENT SENSE Output: This pin provides the sourcing current sensing output signal. Source 2 Source 1. therefore. which is typically 377 μA/A. Texas Instruments Incorporated . However the chip will not shut itself down until 170°C is reached at the junction. Pin 11. and is internally connected to the mounting tab. BRAKE Input: See Logic Truth Table. Pin 3) is used is determined by the format of the PWM Signal. with Pin 3 logic low. Pin 2. OUTPUT 1: Half H-bridge number 1 output. When braking is desired. Logic Truth Table PWM H H L H H L Dir H L X H L X Brake L L L H H H Source 1. both current sourcing output transistors are ON. Pin 3. All output transistors can be turned OFF by applying a logic high to Pin 4 and a logic low to PWM input Pin 5. both current sinking output transistors are ON. PWM Input: See Logic Truth Table. Pin 9. Source 2 Sink 1.LMD18200 SNVS091F – DECEMBER 1999 – REVISED APRIL 2013 www. VS Power Supply Pin 7. Pin 10. pin 5. This input is used to brake a motor by effectively shorting its terminals. Pin 4. BOOTSTRAP 2 Input: Bootstrap capacitor pin for Half H-bridge number 2. BOOTSTRAP 1 Input: Bootstrap capacitor pin for half H-bridge number 1. the direction of rotation of a motor load. Pin 8. GROUND Connection: This pin is the ground Pinout Description (See Test Circuit) Pin 1.5 mA) exists at each output pin. this input is taken to a logic high level and it is also necessary to apply logic high to PWM input. OUTPUT 2: Half H-bridge number 2 output. This input controls the direction of current flow between OUTPUT 1 and OUTPUT 2 (pins 2 and 10) and. THERMAL FLAG Output: This pin provides the thermal warning flag output signal. Sink 2 NONE Active Output Drivers 8 Submit Documentation Feedback Product Folder Links: LMD18200 Copyright © 1999–2013. How this input (and DIRECTION input. The drivers that short the motor are determined by the logic level at the DIRECTION input (Pin 3): with Pin 3 logic high. The recommended capacitor (10 nF) is connected between pins 1 and 2. Pin 6. DIRECTION Input: See Logic Truth Table.

Current delivered to the load is proportional to pulse width.ti. variable duty-cycle signal in which is encoded both direction and amplitude information (see Figure 11). it is good practice to avoid aligning the falling and rising edges of input SNVS091F – DECEMBER 1999 – REVISED APRIL 2013 APPLICATION INFORMATION TYPES OF PWM SIGNALS The LMD18200 readily interfaces with different forms of PWM signals. Figure 12. A conservative approach is be sure there is at least 500ns delay between the end of the first transition and the beginning of the second transition. Copyright © 1999–2013. See Figure 13. The (absolute) magnitude signal is duty-cycle modulated. Locked Anti-Phase PWM Control Sign/magnitude PWM consists of separate direction (sign) and amplitude (magnitude) signals (see Figure 12). Brake. A 50% duty-cycle PWM signal represents zero drive. For the LMD18200. For the LMD18200. and the absence of a pulse signal (a continuous logic low level) represents zero drive. Simple.LMD18200 www. Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMD18200 9 . locked anti-phase PWM consists of a single. Figure 11. the PWM signal drives the direction input (pin 3) and the PWM input (pin 5) is tied to logic high. Use of the part with two of the more popular forms of PWM is described in the following paragraphs. Sign/Magnitude PWM Control SIGNAL TRANSITION REQUIREMENTS To ensure proper internal logic performance. since the net value of voltage (integrated over one period) delivered to the load is zero. A delay of at least 1 µsec should be incorporated between transitions of the Direction. the DIRECTION input (pin 3) is driven by the sign signal and the PWM input (pin 5) is driven by the magnitude signal. and/or PWM input signals.

Therefore. When operating the chip at supply voltages above 40V a voltage suppressor (transorb) such as P6KE62A is recommended from supply to ground. and allows the user to set the logic high level of the output signal swing to match system Figure 13. Direction. such as reducing load currents or initiating an orderly system shutdown. For optimal accuracy and linearity of this signal. The interrupt service routine would then be designed to take appropriate steps. Note that when driving high load currents a greater amount of supply bypass capacitance (in general at least 100 μF per Amp of load current) is required to absorb the recirculating currents of the inductive loads. Transitions in Brake. SUPPLY BYPASSING During switching transitions the levels of fast current changes experienced may cause troublesome voltage transients across system stray inductance. Care should be taken to limit the transients on the supply pin below the Absolute Maximum Rating of the device. 10 Submit Documentation Feedback Product Folder Links: LMD18200 Copyright © 1999–2013. This permits a wired OR connection of thermal warning flag outputs from multiple LMD18200's. or less. USING THE THERMAL WARNING FLAG The THERMAL FLAG output (pin 9) is an open collector transistor. or PWM Must Be Separated By At Least 1 µsec USING THE CURRENT SENSE OUTPUT The CURRENT SENSE output (pin 8) has a sensitivity of 377 μA per ampere of output current.ti. Texas Instruments Incorporated . The maximum voltage compliance is 12V. The maximum voltage compliance on the flag pin is 12V. Typically the ceramic capacitor can be eliminated in the presence of the voltage suppressor.LMD18200 SNVS091F – DECEMBER 1999 – REVISED APRIL 2013 www. It should be noted that the recirculating currents (free wheeling currents) are ignored by the current sense circuitry. A 1 μF high-frequency ceramic capacitor is recommended. This output typically drives the interrupt input of a system controller. It is normally necessary to bypass the supply rail with a high quality capacitor(s) connected as close as possible to the VS Power Supply (Pin 6) and GROUND (Pin 7). only the currents in the upper sourcing outputs are sensed. the value of voltage generating resistor between pin 8 and ground should be chosen to limit the maximum voltage developed at pin 8 to 5V.

The most severe condition for any power device is a direct. Under these conditions the inductance of the motor (as well as any series inductance in the VCC supply line) serves to reduce the magnitude of a current surge to a safe level for the LMD18200. Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMD18200 11 . The switching action is accomplished by the power switches themselves Figure 15. This can create voltage transients on the VCC supply line and therefore proper supply bypassing techniques are required. With any power device it is important to consider the effects of the substantial surge currents through the device that may occur as a result of shorted loads.LMD18200 www. This condition can generate a surge of current through the power device on the order of 15 Amps and require the die and package to dissipate up to 500 Watts of power for the short time required for the protection circuitry to shut off the power device. the control circuitry will periodically try to turn the power device back on. This switching action is controlled by a continuously running internal 300 kHz oscillator. the LMD18200 provides for the use of external bootstrap capacitors. Figure 14. External 10 nF capacitors. an internal capacitor is alternately switched to ground and charged to about 14V. particularly at higher operating voltages (>30V) so some precautions are in order. INTERNAL CHARGE PUMP AND USE OF BOOTSTRAP CAPACITORS To turn on the high-side (sourcing) DMOS power devices. the device will cycle in and out of thermal shutdown. The rise time of this drive voltage is typically 20 μs which is suitable for operating frequencies up to 1 kHz. Proper heat sink design is essential and it is normally necessary to heat sink the VCC supply pin (pin 6) with 1 square inch of copper on the PCB. hard-wired (“screwdriver”) long term short from an output to ground. Once the device is shut down. While the fault remains however. the gate of each device must be driven approximately 8V more positive than the supply voltage. Copyright © 1999–2013. This feature allows the immediate return to normal operation in the event that the fault condition has been removed. The bootstrap principle is in essence a second charge pump whereby a large value capacitor is used which has enough energy to quickly charge the parasitic gate input capacitance of the power device resulting in much faster rise times. then switched to V supply thereby providing a gate drive voltage greater than V supply. As shown in Figure 14. To achieve this an internal charge pump is used to provide the gate drive voltage. connected from the outputs to the bootstrap pins of each high-side switch provide typically less than 100 ns rise times allowing switching frequencies up to 500 kHz.ti. This energy can be destructive. The protection circuitry monitors this increase in current (the threshold is set to approximately 10 Amps) and shuts off the power device as quickly as possible in the event of an overload SNVS091F – DECEMBER 1999 – REVISED APRIL 2013 CURRENT LIMITING Current limiting protection circuitry has been incorporated into the design of the LMD18200. In a typical motor driving application the most common overload faults are caused by shorted motor windings and locked rotors. Internal Charge Pump Circuitry For higher switching frequencies.

is important. once the transient has subsided. The duration of the Off-period is adjusted by the resistor and capacitor combination of the LM555. whenever the current through the motor exceeds the commanded current.ti. Each of the four switches in the LMD18200 have a built-in protection diode to clamp transient voltages exceeding the positive supply or ground to a safe diode voltage drop across the switch. These diodes must come out of conduction quickly and the power switches must be able to conduct the additional reverse recovery current of the diodes.LMD18200 SNVS091F – DECEMBER 1999 – REVISED APRIL 2013 Figure 15. 12 Submit Documentation Feedback Product Folder Links: LMD18200 Copyright © 1999–2013. TYPICAL APPLICATIONS FIXED OFF-TIME CONTROL This circuit controls the current through the motor by applying an average voltage equal to zero to the motor terminals for a fixed period of time. The reverse recovery time of the diodes protecting the sourcing power devices is typically only 70 ns with a reverse recovery current of 1A when tested with a full 6A of forward current through the diode. Texas Instruments Incorporated . This action causes the motor current to vary slightly about an externally controlled average level. The reverse recovery characteristics of these diodes. For the sinking devices the recovery time is typically 100 ns with 4A of reverse current under the same conditions. In this circuit the Sign/Magnitude mode of operation is implemented (see TYPES OF PWM SIGNALS). Bootstrap Circuitry INTERNAL PROTECTION DIODES A major consideration when switching current through inductive loads is protection of the switching power devices from the large voltage transients that occur.

LMD18200 www. Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMD18200 13 .com SNVS091F – DECEMBER 1999 – REVISED APRIL 2013 Figure 16.ti. Switching Waveforms Copyright © 1999–2013. Fixed Off-Time Control Figure 17.

Texas Instruments Incorporated . The relationship of peak motor current to adjustment voltage is shown in Figure 19. Locked Anti-Phase Control Regulates Torque Figure 19.LMD18200 SNVS091F – DECEMBER 1999 – REVISED APRIL 2013 TORQUE REGULATION Locked Anti-Phase Control of a brushed DC motor.ti. Current sense output of the LMD18200 provides load sensing. Peak Motor Current vs Adjustment Voltage 14 Submit Documentation Feedback Product Folder Links: LMD18200 Copyright © 1999–2013. The LM3524D is a general purpose PWM controller. Figure 18.

ti.LMD18200 www. Regulate Velocity with Tachometer Feedback Figure 21. Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LMD18200 15 . The relationship of motor speed to the speed adjustment control voltage is shown in Figure SNVS091F – DECEMBER 1999 – REVISED APRIL 2013 VELOCITY REGULATION Utilizes tachometer output from the motor to sense motor speed for a locked anti-phase control loop. Figure 20. Motor Speed vs Control Voltage Copyright © 1999–2013.

...............LMD18200 SNVS091F – DECEMBER 1999 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision E (April 2013) to Revision F • Page Changed layout of National Data Sheet to TI format .. Texas Instruments Incorporated ...................................... 15 16 Submit Documentation Feedback Product Folder Links: LMD18200 Copyright © 1999–2013................................ti.........

Samples may or may not be available. Device is in production to support existing customers. Where designed to be soldered at high temperatures. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. TI Pb-Free products are suitable for use in specified lead-free 11-Apr-2013 PACKAGING INFORMATION Orderable Device LMD18200T LMD18200T/LF14 LMD18200T/NOPB Status (1) Package Type Package Pins Package Drawing Qty TO-220 TO-220 TO-220 NDJ NDJ NDJ 11 11 11 20 23 20 Eco Plan (2) Lead/Ball Finish Call TI CU SN CU SN MSL Peak Temp (3) Op Temp (°C) -40 to 125 Top-Side Markings (4) Samples ACTIVE ACTIVE ACTIVE TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM Level-1-NA-UNLIM LMD18200T P+ LMD18200T P+ -40 to 125 LMD18200T P+ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. NRND: Not recommended for new designs. and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.The planned eco-friendly classification: Pb-Free (RoHS). or 2) lead-based die adhesive used between the die and leadframe. LIFEBUY: TI has announced that the device will be discontinued. (2) Eco Plan . PREVIEW: Device has been announced but is not in production. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances. but TI does not recommend using this part in a new design.The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications. including the requirement that lead not exceed 0. Pb-Free (RoHS Exempt). Peak for the latest availability information and additional product content details. OBSOLETE: TI has discontinued the production of the device. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.1% by weight in homogeneous materials. and makes no representation or warranty as to the accuracy of such information. TI and TI suppliers consider certain information to be proprietary.1% by weight in homogeneous material) (3) MSL. TI bases its knowledge and belief on information provided by third parties. and peak solder temperature. and thus CAS numbers and other limited information may not be available for release.ti. (4) Multiple Top-Side Markings will be inside parentheses. Efforts are underway to better integrate information from third parties. Addendum-Page 1 . -. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.PACKAGE OPTION ADDENDUM www. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package. TBD: The Pb-Free/Green conversion plan has not been defined. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible). or Green (RoHS & no Sb/Br) .ti. and a lifetime-buy period is in effect. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.please check http://www.


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