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19, 1510–1515

Thermal and competition

aware mapping for 3D

network-on-chip

Bixia Zhang

1

, Huaxi Gu

1a)

, Yintang Yang

2

, Kun Wang

3

,

and Zhengyu Wang

1

1

State Key Laboratory of ISN, Xidian University, Xi’an, 710071 China

2

Institute of Microelectronics, Xidian University, Xi’an, 710071 China

3

School of Computer Science, Xidian University, Xi’an, 710071 China

a) hxgu@xidian.edu.cn

Abstract: Three-dimensional network-on-chip (3D NoC), which

combines NoC with 3D IC technology, oﬀers several prominent ad-

vantages, including reduced overall interconnection length and design

ﬂexibility. However, it suﬀers from the high chip temperature prob-

lem. In the ciliated 3D Mesh architecture, the competition for the port

of the router is ﬁerce. A new temperature and network competition-

aware mapping algorithm is proposed to reduce the peak temperature

and decrease the network competition. The new algorithm can realize

the multi-objective mapping and ensure a lower time complexity. Sim-

ulation results show that our method achieves an appropriate balance

between peak temperature and network competition.

Keywords: thermal aware, competition aware, mapping, 3D network

on chip, ciliated 3D Mesh

Classiﬁcation: Integrated circuits

References

[1] K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, “3-D ICs: A

novel chip design for deep-submicrometer interconnect performance and

systems-on-chip integration,” Proc. IEEE, vol. 89, no. 5, pp. 602–633, May

2001.

[2] B. S. Feero and P. P. Pande, “Networks-on-Chip in a Three-Dimensional

Environment: A Performance Evaluation,” IEEE Trans. Comput., vol. 58,

no. 1, pp. 32–45, Jan. 2009.

[3] W. Hung, C. Addo-Quaye, T. Theocharides, Y. Xie, N. Vijaykrishnan,

and M. J. Irwin, “Thermal- aware IP virtualization and placement

for Networks-on-Chip architecture,” Proc. ICCD 2004, San Jose, USA,

pp. 430–437, Oct. 2004.

[4] M. Janidarmian, A. Khademzadeh, and M. Tavanpour, “Onyx: A new

heuristic bandwidth-constrained mapping of cores onto tile-based Network

on Chip,” IEICE Electron. Express, vol. 6, no. 1, pp. 1–7, Jan. 2009.

[5] C. Addo-Quaye, “Thermal-aware mapping and placement for 3-D NoC de-

signs,” International SOC Conference, Hilton Washington Dulles Airport,

Herndon, USA, pp. 25–28, Sept. 2005.

c

IEICE 2012

DOI: 10.1587/elex.9.1510

Received August 28, 2012

Accepted September 04, 2012

Published October 02, 2012

1510

IEICE Electronics Express, Vol.9, No.19, 1510–1515

[6] N. Kapadia and S. Pasricha, “A Power Delivery Network Aware Frame-

work for Synthesis of 3D Networks-on-Chip with Multiple Voltage Is-

lands,” Proc. 25th Int. Conf. VLSI Design, Hyderabad, India, pp. 262–267,

Jan. 2012.

[7] K. Skadron, M. R. Stan, W. Huang, and S. Velusamyl, “Temperature-

Aware Microarchitecture,” Proc. 30th ISCA, pp. 2–13, June 2003.

1 Introduction

With a rapidly growing number of transistors integrated on a single chip,

2D architecture technology is facing a lot of challenges. Simultaneously, the

technology of three dimensional integrated circuits (3D IC) develops rapidly

and enhances the system performance to a great extent [1]. Due to the

decrease in overall interconnection length in 3D, interconnect power is lower

than 2D chip. Moreover, it is possible that diﬀerent components are mixed

on one chip in 3D IC. Therefore, researchers combine 3D IC with NoC and

ﬁnally 3D NoC is proposed as a novel approach, which obtains signiﬁcant

performance improvements over many traditional solutions. However, 3D

NoC also has some disadvantages. The thermal management problem is the

most intractable one in 3D NoC. Due to the shorter vertical links and smaller

chip area, power density of 3D NoC becomes higher, which will increase the

chip temperature and result in thermal hotspots. As a result, designing an

eﬀective temperature control algorithm for 3D NoC is extremely urgent.

We choose ciliated 3D Mesh structure as our target network fabric, whose

energy consumption is lower than traditional 3D Mesh network [2]. However,

in ciliated 3D Mesh network, multiple IP cores are connected to a router.

Therefore, local IP cores and neighbor routers may compete for the same

output port of the router and it will cause more serious competition than

other 3D NoC architectures. That is to say, we also need to take the problem

of network competition into consideration.

2 Related works

In 2D NoC, various mapping algorithms have been proposed to map an ap-

plication onto diﬀerent topologies based on the speciﬁc metric(s) that should

be optimized. These metrics include the thermal balancing, minimizing the

hop count, etc. Hung et al [3] addressed NoC mapping problem with the aim

of reducing the peak temperature and minimizing the communication cost

by genetic algorithm. Janidarmian et al [4] employed Onyx algorithm for IP

core mapping to minimize hop count between IP cores.

Up to now, there are few papers which target to 3D NoC mapping. Addo-

Quaye presented an approach that used genetic algorithm to map an applica-

tion onto a 3D Mesh NoC architecture with the aim of minimizing the peak

temperature and communication cost [5]. Kapadia and Pasricha [6] proposed

a PDN-aware 3D NoC synthesis framework to minimize power while satis-

fying performance constraints. However, few papers target to the mapping

c

IEICE 2012

DOI: 10.1587/elex.9.1510

Received August 28, 2012

Accepted September 04, 2012

Published October 02, 2012

1511

IEICE Electronics Express, Vol.9, No.19, 1510–1515

problem that aims at optimizing the temperature and network competition.

3 Problem formulation

In our problem, the following inputs are given:

A Core Graph (CG) is a directed graph denoted by G(V, E). Each vertex

v

i

∈V represents an IP core, and each directed arc e

i,j

∈E represents the

communication from IP core v

i

to v

j

. The weight of edge e

i,j

, denoted by

w

i,j

∈W, signiﬁes the volume of data ﬂowing through the edge.

An Architecture Characterization Graph (ACG) is a directed graph de-

noted by G

(N,R,P). Each vertex n

i

∈N represents a node in the architec-

ture, R

i

∈R represents the i

th

router in the architecture, and r

k

i

represents

the k

th

port of the i

th

router, where k∈{0, 1, 2, 3} and 0, 1, 2, 3 are the North,

East, South, West port of the router, respectively. Each directed arc p

i,j

∈P

represents the communication path from the node n

i

to n

j

.

3.1 Temperature model

Skadron et al [7] developed a thermal model tool called HotSpot to model

thermal eﬀects at the IP core level and provided the newest detailed 3D

software edition in 2011. This edition shows that the transient temperature

of an IP core is determined by the transient power and the physical location

of the IP core and some thermal parameters. Finally, we can also obtain

the ﬁnal steady state temperature of each IP core. Based on above, Hung

et al proposed a temperature estimation method in [3]. The prominent idea

is that, the temperature of each IP core can be calculated by obtaining the

transfer thermal resistance and the power consumption of IP cores, where

the transfer thermal resistance R

i,j

of IP core with v

i

respect to v

j

as the

temperature rise at v

i

due to one unit of power dissipated at v

j

. Then the

temperature of each IP core can be calculated by the following equation:

T

1

T

2

.

.

.

.

.

.

.

.

.

T

m

=

R

t

11

R

t

12

· · · · · · R

t

1m

R

t

21

R

t

22

· · · · · · R

t

2m

.

.

.

.

.

. · · · · · ·

.

.

.

.

.

.

.

.

. · · · · · ·

.

.

.

.

.

.

.

.

. · · · · · ·

.

.

.

R

t

m1

R

t

m2

· · · · · · R

t

mm

P

1

P

2

.

.

.

.

.

.

.

.

.

P

m

(1)

where P

i

is the power consumed by IP core v

i

and T

i

is the temperature of

IP core v

i

. m is the total number of IP cores.

Then, the peak temperature of IP cores is given as follows:

T

max

= max{T

i

| i = 1, 2, · · · m} (2)

3.2 Network competition model

In ciliated 3D Mesh topology, a router can be connected to more than one

IP core. The problem of network competition is that multiple IP cores and

c

IEICE 2012

DOI: 10.1587/elex.9.1510

Received August 28, 2012

Accepted September 04, 2012

Published October 02, 2012

1512

IEICE Electronics Express, Vol.9, No.19, 1510–1515

neighbor routers may compete for the same output port of a router. There-

fore, the competition of the k

th

port of the i

th

router is given by

g(r

k

i

) = c(r

k

i

) ×e

c(r

k

i

)

(3)

where c(r

k

i

) is the number of input ports which compete for the current port.

Then, the total competition of the network is given by

C =

i

3

k=0

g(r

k

i

) (4)

3.3 Optimization model

With the model deﬁned above, the optimal mapping problem can be de-

scribed as

min{α ×T

max

+β ×C

} (5)

s.t.

∀v

i

∈ V, map (v

i

) ∈ N, ∀v

i

= v

j

∈ V, map (v

i

) = map (v

j

) ∈ N (6)

dis(map (v

i

) , map (v

j

)) ≤ σwherew

i,j

∈ W, w

i,j

= 0 (7)

where T

max

and C

**are the normalized peak temperature and network com-
**

petition. The normalization is necessary due to the potential large diﬀerence

between the absolute values of the two components. The parameters α and β

are weight factors which represent the importance of the components. Con-

dition (6) means that each IP core should be mapped onto one node and

no node can host more than one IP core. Condition (7) means that two IP

cores which need to communicate with each other should be mapped onto

two nodes within a limited distance so that the system energy consumption

will not be too high.

4 Thermal and competition aware mapping algorithm

As mentioned above, we want to map each IP core of a core graph onto

a network node of an architecture characterization graph. We propose our

thermal and competition aware mapping algorithm (TCAMAP) based on

ciliated 3D Mesh. In our algorithm, the ﬁrst step is to cluster IP cores

according to the number of layers of the chip and locate the network nodes

connected to the same router into a cluster. The second step is to realize

the network-on-chip mapping using genetic algorithm. The inputs of our

algorithm are a CG and an ACG.

4.1 Clustering

For simplicity, we restrict the routers to one layer. Then, this process contains

IP cores clustering and network nodes clustering. The ﬁrst step is to cluster

IP cores in a CG. We cluster IP cores according to their communication

volumes. In other words, IP cores with higher communication volume are

located in the same cluster. The number of clusters is equal to the number

of routers and the number of IP cores in each cluster is equal to the number

c

IEICE 2012

DOI: 10.1587/elex.9.1510

Received August 28, 2012

Accepted September 04, 2012

Published October 02, 2012

1513

IEICE Electronics Express, Vol.9, No.19, 1510–1515

of layers in ciliated 3D Mesh topology. The second step is to cluster network

nodes in an ACG. We use the same number of clusters and the same number

of nodes in each cluster as the ﬁrst step. Network nodes connected to the

same router are located in the same cluster.

4.2 Genetic algorithm

Based on the IP cores and network nodes clustering above, we accomplish the

network-on-chip mapping with genetic algorithm to obtain the best solution.

We deﬁne the following methods according to our problem:

1) Initialization: Our initial population consists of a set of chromosomes. A

valid chromosome is the one that makes a one-to-one mapping between an

IP core cluster and a network node cluster while satisfying the constraints.

2) Selection: We employ the roulette selection for ease of implementation.

We use a weighted linear combination of peak temperature and network com-

petition to determine the ﬁtness of a solution. The ﬁtness is given by the

following equation: fitness = 1/(α ×T

max

+β ×C

).

3) Crossover: Two chromosomes are chosen randomly to mate. For achieving

crossover of two chromosomes, a random crossover point is selected and then

genes of these two chromosomes are transposed over the crossover point to

produce two new chromosomes. Pc is the crossover probability.

4) Mutation: Each chromosome in the population has a probability to un-

dergo the mutation operation. Two genes are picked randomly from the se-

lected chromosome. Then, we exchange their IP core clusters to obtain two

new IP core clusters to improve population diversity. Pm is the mutation

probability.

The details of our TCAMAP mapping algorithm are illustrated in

Fig. 1 (a).

5 Simulation and results

We estimate the peak temperature and network competition performance of

our TCAMAP algorithm using two NoC applications, MPEG-4 and VOPD.

Simultaneously, we also give the average temperature performance. In each

application, we assume IP cores are homogeneous absolutely. With appro-

priate adjustments, our algorithm can be applied to any topology.

We use our TCAMAP algorithm and the HotSpot tool to generate a

solution population and obtain temperature and network competition infor-

mation of each solution. For each application, we adjusted our algorithm to

target a thermal aware mapping, or a network competition aware mapping or

the hybrid case. To calculate the temperatures of IP cores, we need to input

the physical location and the transient powers of each IP core. Fig. 1 (b)

shows the peak temperature and the average temperature obtained under

the three diﬀerent optimizations. We can see that the thermal aware op-

timization approach performs better than the others. Fig. 1 (c) shows the

network competition. We can also see that the hybrid approach achieves a

signiﬁcant reduction in network competition without a serious deterioration

c

IEICE 2012

DOI: 10.1587/elex.9.1510

Received August 28, 2012

Accepted September 04, 2012

Published October 02, 2012

1514

IEICE Electronics Express, Vol.9, No.19, 1510–1515

Fig. 1. (a) Pseudo code of TCAMAP (b) Peak and av-

erage temperature (c) network competition infor-

mation.

in temperature.

6 Conclusion

In this paper, we propose a temperature and competition aware algorithm,

TCAMAP, to map IP cores onto ciliated 3D Mesh NoC architecture. The

ﬁrst step is to cluster IP cores and network nodes, respectively. The second

step is to realize the one-to-one mapping between an IP core cluster and

a network node cluster using genetic algorithm. Simulation results show

that the thermal aware optimization approach can achieve the lowest peak

temperature, and the network competition aware optimization can obtain the

best network competition result. The hybrid case can achieve an appropriate

balance between peak temperature and network competition.

Acknowledgments

This work is supported partly by the National Science Foundation of China

under Grant No.60803038 and No.61070046, the special fund from State Key

Lab under Grant No.ISN1104001, the Fundamental Research Funds for the

Central Universities under Grant No.K50510010010, the 111 Project under

Grant No.B08038, and the fund from Science and Technology on Information

Transmission and Dissemination in Communication Networks Laboratory un-

der Grant No.ITD-U11009.

c

IEICE 2012

DOI: 10.1587/elex.9.1510

Received August 28, 2012

Accepted September 04, 2012

Published October 02, 2012

1515

An Efficient Routing Approach for Aggregated Data Transmission Along With Performance Improvement in Wireless Sensor Networks

by International Journal of Research in Engineering and Technology

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