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ECE 4130/6130: Advance VLSI Systems


MOSFET: A Circuit Designers
Perspective
Saibal Mukhopadhyay
School of Electrical & Computer Engineering
Georgia Institute of Technology
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Goals of this lecture
Intuitive understanding of device
operation
Introduction of basic device
equations
Capacitive behavior of MOSFET
Physical understanding of important
deep-submicron effects
Subthreshold conduction
Short-channel effect
Velocity saturation
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Purpose of this lecture
This is not a lecture on MOSFET physics
We will not study in this lecture/course:
Detail physics of MOSFET operation
Detail derivation of MOSFET equations
Threshold voltage equation
Current equations
Capacitance equations
But, we need to understand the basic principles and
know the equations to use them for circuit analysis
and design.
If you want to know the physics in more detail, please,
consult a book on device physics or ask the instructor
in office hours
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Reading Materials
Chapter 6: Introduction to VLSI Circuits
and Systems, Uyemura,
Chapter 3: Digital Integrated Circuits:
A Design Perspectives, J . M. Rabaey,
A. Chandrakasan, B. Nikolic
Lecture notes (posted in T-square,
under Resources/Lecture Slides)
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What is a Transistor?
V
GS

>
V
T
R
on
S
D
A Switch!
|V
GS
|
An MOS Transistor
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The MOS Transistor: Structure and Symbols
Polysilicon
Aluminum
D
S
G
G
S
D
NMOS
Enhancement PMOS Enhancement
B
B
7
Uyemura, Figure 6.1
nFET current and voltages.
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MOSFET Device:
A circuit designers perspective
Its a switch:
What is the controlling voltage?
Answer: Primarily, gate-to-source (Vgs) voltage
How much control voltage is necessary to turn
the switch on?
Answer: Threshold voltage (Vth or Vt or V
T
)
What and how much current flows through the
switch when it is on?
Answer: the drain-to-source (Ids) current, its value
depends on Vgs and Vds (drain-to-source volatge).
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Concept of Threshold Voltage
Initially, n-type source and drain is separated by p-
type body which inhibits electron flow.
A positive voltage at the gate reduces the hole and
increases the electron concentration at the surface
Vth is the minimum voltage required to obtain an
electron conc. > original hole conc. (~doping density)
in the surface.
This creates a channel (n-type) for electrons to flow
from source to drain.
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Computation of Threshold Voltage




2
ox B
th ms f
ox ox
gate silicon
bulk potential
workfunction
oxide depletion charge
difference
charge
Q Q
V
C C
|

= u + + +
( )
( )
10
ln ; , . ,
, . ~10
2 2
, 2 2
A
f
i
3
A i
B A d A si f
d si f A
N kT
k Boltzman constant T temp in Kelvin
q n
N doping density n intrinsic carrier conc cm
Q qN W qN
where W depletion width at thereshold qN
|
c |
c |

| |
= = =
|
\ .
= =
= =
= =
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Effect of substrate bias on Vth: Body Effect
A negative body-to-source voltage increases the
depletion region width => larger depletion charge =>
higher threshold voltage
Normally, body for NFET is connected to ground.
A non-zero V
BS
can happen either due to a bias applied
at the body or naturally in the circuit when source is not
at 0 .
G
D
S
bulk or body
or substrate
B
V
SB
+
-
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Computation of Vth with Body Effect
( )
( ) 0
0
0 0
2 2
2
2 2
,
2 ;
2
,
si A f BS
ox
th ms f
ox ox
th th f BS f
ox B
th ms f B BS
ox ox
si A
A
ox
q N V
Q
V
C C
V V V
where
Q Q
V Q depletion charge at zero V
C C
q N
body effect coeffecient N body doping
C
c |
|
| |
|
c

= u + + +
=> = +
= u + + + =
= = =
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Current in MOSFET
Ids-Vgs characteristics of a MOSFET
Uyemura, Fig. 6.12
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Current-Voltage Relations
MOSFET in active state has two regions:
linear (or resistive) and saturation
Quadratic
Relationship
0 0.5 1 1.5 2 2.5
0
1
2
3
4
5
6
x 10
-4
V
DS
(V)
I
D
(
A
)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive Saturation
V
DS
= V
GS
- V
T
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Transistor in Linear
A more detail analysis will apply the above concept to small
regions of length dl across the channel assuming the V
DS
changes linearly within the channel.
( )
( )


;
/ ( )
inversion ox gs th
D inversion r
r
DS
n n DS
D n ox gs th DS
Q qC V V
I Q WL t
t transit time L v
for small V
v E V L
I q W L C V V V

=
=
= =
= =
=

( ) ( )
2 ;
,
n
n
D n ox gs th DS DS ox ox ox
k
n n
I C W L V V V V C t
k process param design parameter
|
c
|
(
= =

= =

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Transistor in Saturation
For high V
ds
when the
channel potential at the drain
> V
gs
-V
th
, the channel
vanishes at the drain end and
pinch-off occurs.
The effective Vds saturates at
(Vgs-Vth)
Current also saturates
Small change happens due to
channel length modulation
( )
( )
( )
2
.
1
1
2
D n ox gs th ds
ch length modulation
I C W L V V V = +

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Models that will be used for Manual Analysis
D
G
S
I
D
( )
( )
( )
( )
( )
( )
2
:
0 ( )
:
2
:
1
1
2
(
gs th
D
gs th ds gs th
D n ox gs th DS DS
gs th ds gs th
D n ox gs th ds
cut off V V
I leakage current will be discussed later
linear V V and V V V
I C W L V V V V
satuartion V V and V V V
I C W L V V V
sometime for simplif


<
=
> <
(
=

> >
= +
( ) 0

)
2 2
th th f BS f
ication we will neglect
the channel length modulation term
V V V | | = +
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On Resistance of Transistor
( )
( )
( )
2
1
:
1
:
2


D
on DS
on
n ox gs th DS
on
n ox gs th
on
I
R V
linear region
R
C W L V V V
saturation
R
C W L V V
If channel length modulation is not present R
the transistor in saturation behaves as an ideal current source


c
=
c
=
(


=

=>
V
gs
>V
th
R
on
S
D
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The MOSFET Capacitance
n
+
n
+
L
eff
gate
source
substrate
drain
Junction capacitance
overlap
capacitance
Gate
capacitance
C
sb
C
db
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The MOSFET Capacitance
The gate capacitance is the gate voltage dependent
capacitance of the Metal-Oxide-Semiconductor
structure and depends on the oxide material and the
oxide thickness.
The overlap caps are between gate and source/drain
terminals. They are parasitic caps. and does not
contribute to the charge. The importance of the overlap
cap will be introduced later in Miller effect discussion.
The junction capacitances are due to p-n junction
between the n+ source/drain and p-type body (for
NFET). They are also parasitic capacitances and
depends on the junction doping and drain-to-body and
source-to-body biases.
All capacitances depends on the length and/or width of
the devices.
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The Gate and Overlap Capacitance
t
ox
n
+
n
+
Cross section
L
Gate oxide
x
ov
x
ov
L
d
Polysilicon gate
Top view
Gate-bulk
overlap
Source
n
+
Drain
n
+
W
Overlap
region
L
:
:
gate ox
ox
ov ox ov ov
ox
gate capacitance
C C WL WL
t
overlap capacitance
C C WX WX
t
c
c
= =
= =
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The Gate Capacitance: MOS Structure
For digital logic we are most interested in on (i.e.
inversion) and off (i.e. in accumulation or weak
depletion) devices.
Accu
mulation.
depletion.
inversion.
C
ox
C
ox
and
C
dep
in
series
C
ox and
C
inv
in
series
~ C
ox
G
a
t
e

c
a
p
a
c
i
t
a
n
c
e
Gate voltage
gate
oxide
substrate
:
gate ox
ox
gate capacitance C C WL WL
t
c
= =
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J unction (Diffusion) Capacitance
Bottom
Side wall
Side wall
Channel
Source
N
D
Channel-stop implant
N
A1
Substrate N
A
W
x
j
L
S
x
ov
x
ov
L
d
Polysilicon gate
Top view
Source
n
+
Drain
n
+
W
L
L
S
( )
2
&
Junction bottom sidewall j jsw
j S jsw S
j jsw
C C C C AREA C PERIMETER
C WL C W L
C C are technology and voltage dependent parameter
= + = +
= + +
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Voltage Dependence of J unction Capacitance
t
ox
n
+
L
Gate oxide
p
substrate=0
drain=V
DD
reverse-bias junction cap
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Model that will be used for Manual Analysis
D
S
B
C
OV
G
C
OV
C
DB C
SB
C
gate
( )
:
:
:
2
& are tech. param.
gate
ox
ov ov
ox
Junction j S jsw S
j jsw
gate capacitance
C WL
t
overlap capacitance
C WX
t
Junction capacitance
C C WL C W L
C C
c
c
=
=
= + +
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Transforming an nFET to a pFET.
Substrate is n-type (i.e. n-well) and source/drain are
p-type.
Current is carried by holes.
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Current and voltages in a pFET.
Source is at a higher potential than drain and
current flows from source-to-drain.
Threshold voltage is negative.
A negative Vgs and Vds is necessary for current
conduction
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How to analyze a PMOS Transistor?
-2.5 -2 -1.5 -1 -0.5 0
-1
-0.8
-0.6
-0.4
-0.2
0
x 10
-4
V
DS
(V)
I
D
(
A
)
One possibility: Assume all variables negative!
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
VGS = -2.5V
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PMOS Models for Manual Analysis
Consider the correct direction of current : i.e. source-to-drain.
Consider the correct polarities of Vth, Vgs and Vds: i.e Vth < 0,
Vg < Vs and Vd < Vs
Use the NFET current equations to evaluate the magnitude of
current considering the magnitude of the voltages.
Note: The body of PMOS is normally connected to V
DD
( )
( )
| )
( )
( )
( )
( )
2
: 0
:
2
:
1
1
2
gs th D
gs th ds gs th
D h ox gs th DS DS
gs th ds gs th
D h ox gs th ds
cut off V V I
linear V V and V V V
I C W L V V V V
satuartion V V and V V V
I C W L V V V


< => =
> <
(
=

> >
= +
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Sub-Threshold Conduction
0 0.5 1 1.5 2 2.5
10
-12
10
-10
10
-8
10
-6
10
-4
10
-2
V
GS
(V)
I
D
(
A
)
V
th
Exponential
When Vgs < Vth, a small current flows through the
transistor => subthreshold current
( )
0
1
gs th
DS
q V V
qV
nkT kT
D
I I e e

| |
=
|
|
\ .
A practical defn. of V
th
:
V
gs
necessary to obtain a
pre-defined current (I
th
)
A commonly used value:
I
th
= 300nA * (W/L)
Note at V
gs
=V
th
, I
0
=I
th
for
V
ds
>> kT/q
(V
ds
> 100mV)
I
0
=I
th
1
D
ox
C
n
C
= +
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Sub-Threshold Slope
( ) ( )
( ) ( )
2 1
gs D
gs 2 1
2
1
2
1
( ) is defined as the
V required for 1 decade change in I
V 10
10 10 1
gs gs gs
D D
q V V q V
D
nkT nkT
D
D
gs
D
D
ox
Subthreshold Slope S
for I I
I
e e
I
I nkT
V ln
q I
C nkT kT
S ln ln
q q C
A
A
=> A =
=> = =
| |
=> A =
|
\ .
| |
=> = = +
|
\ .
0 0
; 1 ~ 100
gs
th DS th
qV
qV qV qV
nkT nkT kT nkT
D C C ds
I I e I I e e I e forV mV

| |
= = >
|
|
\ .
0 0.5 1 1.5 2 2.5
10
-12
10
-10
10
-8
10
-6
10
-4
10
-2
V
GS
(V)
I
D
(
A
)
I
D2
=10
-8
(A)
I
D1
=10
-9
(A)
AV
gs
( )
. 10 ~60 / ( 1) ( 300 )

kT
Min S ln mV decade for n at room temp T K
q
Typical values 60 - 100 mV / decade
= = =
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Subthrshold Current
Lower Vth exponentially increases the current
but does not impact subth. Slope (a parallel shift
of Id-Vgs curve in the subth. region)
Higher temperature exponentially increases the
current and linearly increases the subth. slope
0 0.5 1 1.5 2 2.5
10
-12
10
-10
10
-8
10
-6
10
-4
10
-2
V
GS
(V)
I
D
(
A
)
Vth increasing
Temperature
S
u
b
t
h
.

l
e
a
k
a
g
e
exponential
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Short Channel Effect: Conceptual View
For shorter channel devices, a non-negligible fraction of the
depletion charge is contributed by source/drain.
Gate needs to deplete less amount of charge => thereshold
voltage reduces.
The source/drain contributions increase at a lower channel
length (Vt reduces with channel length reduction, Vt-roll off)
and at a higher drain bias (Vth reduces at a higher drain bias)
Vth reduction due to SCE increases the subthreshold current
=> A barrier to technology scaling
depletion
due to gate
depletion due to
source/drain region
depletion due to
source/drain region
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Short Channel Effect
channel length
V
t
h
Long-channel device
short-channel device
Vds
V
t
h
Long-channel device
short-channel device
Vth roll off
Drain induced
barrier lowering
(DIBL)
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Drain Induced Barrier Lowering (DIBL)
DIBL coefficient is
often computed as
mV change in Vth
due to 1V change in
Vds
0 0.5 1 1.5 2 2.5
10
-12
10
-10
10
-8
10
-6
10
-4
10
-2
V
GS
(V)
I
D
(
A
)
V
ds
increasing
Vth reducing
I
th


th
DIBL
ds
DIBL coeffecient
V
V
q
A
=
A
( ) ( )
( ) ( )
_ _ _
Simple models with effect for manual analysis:
1. @ @
2. @ @ ; ~0.1
th ds th ds DD DIBL DD ds
th ds th ds low DIBL ds ds low ds low
Vth DIBL
V V V V V V V
V V V V V V V V
q
q
= = +
=
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Reference Materials
For detail analysis of SCE and subthreshold
leakage current one can refer:
K. Roy, S. Mukhopadhyay, and H. Mahmoodi, Leakage
current mechanisms and leakage reduction techniques in
deep-submicron CMOS circuits, Proceeding of IEEE, vol.
91, no. 2, Feb. 2003, pp. 307-327.
For obtaining a quick understanding of SCE, subthreshold
leakage, and its impact in circuit design
Fundamentals of Modern VLSI Devices, by Yaun Taur , and
Tak H Ning, Cambridge University Press
For a detail understanding of the device physics behind short-
channel effect and leakage current.
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Velocity Saturation
(V/m)

c
= 1.5
u
n
(
m
/
s
)
u
sat
= 10
5
Constant mobility (slope = )
Constant velocity
In deep-submicron MOSFETs the electron (or hole) velocity
saturates for very high electric field
38
Perspective
Velocity saturation limits the saturation current in
short-channel MOSFET.
The saturation sets at a Vds lower than Vgs-Vth
(early saturation)
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Velocity Saturation and Saturation Current
For Vds > V
DS,sat
, the drain-
to-source field is higher
than the critical field (E
C
),
the electron velocity
saturates at v
sat.
simple model:

( )
D inversion r
r sat
D ox sat gs th
A
I Q WL t
t transit time L v
I qC v W V V
=
= =
=> =
For a detail analysis of velocity saturation
interested students can consult:
Fundamentals of Modern VLSI Devices, by Yaun
Taur , and Tak H Ning, Cambridge University Press
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Alpha-Power Law Model for Current
Short-channel limit: I
D,sat
is proportional to V
gs
-V
th
(linear)
Long-channel limit: I
D,sat
is proportional to (V
gs
-V
th
)
2
(quadratic).
The deep-submicron transistors are in between the two limits.
This is often modeled as using (alpha-power law model):
( )
, .
1 , 2 ,
1.3 1.4
D gs th
I V V where is an empirical constant
at short channel limit at long channel limit
for modern day transistors
o
o o
o o
o

= =
=
To study alpha-power law model and its use consult:
T. Sakurai, and A. R. Newton, Alpha-power law MOSFET model and its
applications to CMOS inverter delay and other formulas, IEEE Journal
of Solid-State Circuits, vol. 25, no. 2, Apr 1990, pp. 584-594.
K. A. Bowman, B.L Austin, J. C. Eble, X. Tang, and J.D. Meindl, A
physical alpha-power law MOSFET model, IEEE Journal of Solid-State
Circuits, vol. 34, no. 10, Oct. 1999, pp. 1410-1414