LTC1863/LTC1867 12-/16-Bit, 8-Channel 200ksps ADCs FEATURES

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DESCRIPTION
The LTC®1863/LTC1867 are pin-compatible, 8-channel 12-/16-bit A/D converters with serial I/O, and an internal reference. The ADCs typically draw only 1.3mA from a single 5V supply. The 8-channel input multiplexer can be configured for either single-ended or differential inputs and unipolar or bipolar conversions (or combinations thereof). The automatic nap and sleep modes benefit power sensitive applications. The LTC1867’s DC performance is outstanding with a ±2LSB INL specification and no missing codes over temperature. The signal-to-noise ratio (SNR) for the LTC1867 is typically 89dB, with the internal reference. Housed in a compact, narrow 16-pin SSOP package, the LTC1863/LTC1867 can be used in space-sensitive as well as low-power applications.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

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Sample Rate: 200ksps 16-Bit No Missing Codes and ±2LSB Max INL 8-Channel Multiplexer with: Single Ended or Differential Inputs and Unipolar or Bipolar Conversion Modes SPI/MICROWIRE™ Serial I/O Signal-to-Noise Ratio: 89dB Single 5V Operation On-Chip or External Reference Low Power: 1.3mA at 200ksps, 0.76mA at 100ksps Sleep Mode Automatic Nap Mode Between Conversions 16-Pin Narrow SSOP Package

APPLICATIONS
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Industrial Process Control High Speed Data Acquisition Battery Operated Systems Multiplexed Data Acquisition Systems Imaging Systems

BLOCK DIAGRAM
Integral Nonlinearity vs Output Code (LTC1867)
2.0
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM 1 2 3 4 5 6 7 8 LTC1863/LTC1867 16 V 15 DD GND 14 SDI 13 12-/16-BIT + SDO SERIAL 200ksps 12 PORT – SCK ADC 11 CS/CONV 10 VREF INTERNAL 2.5V REF 9
18637 BD

1.5 1.0
INL (LSB)

ANALOG INPUT MUX

0.5 0 –0.5 –1.0

REFCOMP

–1.5 –2.0 0 16384 32768 49152 OUTPUT CODE 65536
18637 GO1

18637fa

1

.. –0........... otherwise specifications are at TA = 25°C..... 300°C GN PACKAGE 16-LEAD NARROW PLASTIC SSOP TJMAX = 110°C......3V) VREF.. –0........ 2) PIN CONFIGURATION TOP VIEW CH0 1 CH1 2 CH2 3 CH3 4 CH4 5 CH5 6 CH6 7 CH7/COM 8 16 VDD 15 GND 14 SDI 13 SDO 12 SCK 11 CS/CONV 10 VREF 9 REFCOMP Supply Voltage (VDD) ... go to: http://www...........5 1.... CS/CONV) (Note 4) ...3V) Power Dissipation ......3V to (VDD + 0. –0....3V to (VDD + 0.LTC1863/LTC1867 ABSOLUTE MAXIMUM RATINGS (Note 1.... REFCOMP (Note 4) .74 ±3 ±4 ±1 ±1 ±0......–40°C to 85°C Storage Temperature Range .......5 ±96 ±96 ±32 ±64 ±2 ±2 ±4 ±4 3 –1 TYP MAX MIN 16 16 LTC1867A TYP MAX UNITS Bits Bits ±2 ±2.... *The temperature grade is identified by a label on the shipping container...... θJA = 95°C/W ORDER INFORMATION LEAD FREE FINISH LTC1863CGN#PBF LTC1863IGN#PBF LTC1867CGN#PBF LTC1867IGN#PBF LTC1867ACGN#PBF LTC1867AIGN #PBF TAPE AND REEL LTC1863CGN#TRPBF LTC1863IGN#TRPBF LTC1867CGN#TRPBF LTC1867IN#TRPBF LTC1867ACGN#TRPBF LTC1867AIGN#TRPBF PART MARKING* 1863 1863 1867 1867 1867 1867 PACKAGE DESCRIPTION 16-Lead Narrow Plastic SSOP 16-Lead Narrow Plastic SSOP 16-Lead Narrow Plastic SSOP 16-Lead Narrow Plastic SSOP 16-Lead Narrow Plastic SSOP 16-Lead Narrow Plastic SSOP TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges..75 0...... –65°C to 150°C Lead Temperature (Soldering... 500mW Operating Temperature Range LTC1863C/LTC1867C/LTC1867AC ............... For more information on lead free part marking.....5 ±6 ±6 l l LTC1867 MAX MIN 16 15 ±1 ±1 ±1 –2 0...... With external reference (Notes 5.. –0................ SCK...5 ±64 ±64 LSB LSB LSB LSBRMS LSB LSB LSB LSB ppm/°C LSB LSB 18637fa CONDITIONS l l l l l MIN 12 12 TYP Unipolar (Note 7) Bipolar 0..............3V to (VDD + 0...................... go to: http://www....– 0....3V to 10V Digital Output Voltage (SDO) ..1 2 .......com/tapeandreel/ CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range.....com/leadfree/ For more information on tape and reel specifications. 0°C to 70°C LTC1863I/LTC1867I/LTC1867AI .....74 ±32 ±64 ±2 ±2 ±0..linear..... Consult LTC Marketing for information on non-standard lead based finish parts..linear....3V to 6V Analog Input Voltage CH0-CH7/COM (Note 3) .3V) Digital Input Voltage (SDI... 6) LTC1863 PARAMETER Resolution No Missing Codes Integral Linearity Error Differential Linearity Error Transition Noise Offset Error Offset Error Match Offset Error Drift Gain Error Unipolar Bipolar Unipolar (Note 8) Bipolar Unipolar Bipolar ±0.... 10 sec)..............

43 6 4. (Note 5) LTC1863/LTC1867/LTC1867A SYMBOL VIH VIL IIN PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current CONDITIONS VDD = 5. CHX = 0V or VDD l μA INTERNAL REFERENCE CHARACTERISTICS PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance REFCOMP Output Voltage CONDITIONS IOUT = 0 IOUT = 0 4.1mA IOUT = 0 (Note 5) LTC1863/LTC1867/LTC1867A MIN 2.5 –100 1.LTC1863/LTC1867 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range.25V ⏐IOUT ⏐ ≤0.048 32 4 MAX UNITS V V pF pF μs Analog Input Range CIN t ACQ Analog Input Capacitance for CH0 to CH7/COM Sample-and-Hold Acquisition Time Input Leakage Current 1. otherwise specifications are at TA = 25°C.5 ±15 0.75V ≤ VDD ≤ 5.7 ±1 CONDITIONS MIN TYP MAX ±1 ±15 ±2.7 ±5 MIN LTC1867A TYP MAX ±2 UNITS LSB ppm/°C ppm/°C LSB DYNAMIC ACCURACY SYMBOL PARAMETER SNR S/(N+D) THD Signal-to-Noise Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Channel-to-Channel Isolation Full Power Bandwidth (Note 5) LTC1863 CONDITIONS 1kHz Input Signal 1kHz Input Signal. (Note 5) LTC1863/LTC1867/LTC1867A CONDITIONS Unipolar Mode (Note 9) Bipolar Mode Between Conversions (Sample Mode) During Conversions (Hold Mode) l l l MIN TYP 0-4.6 73.5 –94. otherwise specifications are at TA = 25°C.48 TYP 2.5 1.52 UNITS V ppm/°C mV/V kΩ V The l denotes the specifications which apply over the full operating temperature range.25V ±15 ±2.25V VDD = 4. 6) LTC1863 PARAMETER Gain Error Match Gain Error Tempco Power Supply Sensitivity Internal Reference External Reference VDD = 4.1 ±1 On Channels.4 TYP MAX 0. otherwise specifications are at TA = 25°C.8 ±10 UNITS V V μA 18637fa 3 . Up to 5th Harmonic 1kHz Input Signal 100kHz Input Signal –3dB Point MIN TYP 73.096 MAX 2.5 –94. With external reference (Notes 5.096 ±2.25 MAX LTC1867/LTC1867A MIN TYP 89 88 –95 –95 –117 1.75V VIN = 0V to VDD l l l DIGITAL INPUTS AND DIGITAL OUTPUTS MIN 2.75V – 5.25 MAX UNITS dB dB dB dB dB MHz Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal ANALOG INPUT SYMBOL PARAMETER The l denotes the specifications which apply over the full operating temperature range.7 ±5 MIN LTC1867 TYP MAX ±4 ±15 ±2.

75V.75V. (Note 5) LTC1863/LTC1867/LTC1867A SYMBOL CIN VOH VOL ISOURCE ISINK PARAMETER Digital Input Capacitance High Level Output Voltage (SDO) Low Level Output Voltage (SDO) Output Source Current Output Sink Current Hi-Z Output Leakage Hi-Z Output Capacitance Data Format VDD = 4.5 MAX 5.LTC1863/LTC1867 The l denotes the specifications which apply over the full operating temperature range. CVREF = 2. This product can handle input currents of greater than 100mA without latchup. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime Note 2: All voltage values are with respect to GND (unless otherwise noted). otherwise specifications are at TA = 25°C.75 4.6mA SDO = 0V SDO = VDD CS/CONV = High.5 40 5 15 10 1. IO = 160μA VDD = 4. IO = –10μA VDD = 4. Note 3: When these pin voltages are taken below GND or above VDD.8 3 9 UNITS V mA μA μA mW PDISS Power Dissipation TIMING CHARACTERISTICS SYMBOL fSAMPLE tCONV t ACQ fSCK t1 t2 t3 t4 t5 t6 t7 t8 PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time SCK Frequency CS/CONV High Time SDO Valid After SCK↓ SDO Valid Hold Time After SCK↓ SDO Valid After CS/CONV↓ SDI Setup Time Before SCK↑ SDI Hold Time After SCK↑ SLEEP Mode Wake-Up Time Bus Relinquish Time After CS/CONV↑ The l denotes the specifications which apply over the full operating temperature range.25 1.5 40 UNITS kHz μs μs MHz ns ns ns ns ns ns ms 1.75V. 18637fa 4 .2 6.4 V V mA mA ±10 15 Straight Binary Two’s Complement μA pF The l denotes the specifications which apply over the full operating temperature range.1 –32 19 MAX UNITS pF V V 4 0. (Note 5) LTC1863/LTC1867/LTC1867A SYMBOL VDD IDD PARAMETER Supply Voltage Supply Current CONDITIONS (Note 9) fSAMPLE = 200ksps NAP Mode SLEEP Mode l l l POWER REQUIREMENTS MIN 4.05 0. otherwise specifications are at TA = 25°C.1 100 13 11 10 –6 4 60 20 40 30 22 Short CS/CONV Pulse Mode CL = 25pF (Note 11) CL = 25pF CL = 25pF l l l l l l CREFCOMP = 10μF. (Note 5) LTC1863/LTC1867/LTC1867A CONDITIONS l l l MIN 200 TYP 3 MAX 3.74 0.75V.75 TYP 1.3 150 0. IO = –200μA VDD = 4. otherwise specifications are at TA = 25°C. SDO = 0V or VDD CS/CONV = High (Note 10) Unipolar Bipolar l l l l DIGITAL INPUTS AND DIGITAL OUTPUTS CONDITIONS MIN TYP 2 4.2μF CL = 25pF l ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. they will be clamped by internal diodes. IO = 1.

(Note 5) Note 4: When these pin voltages are taken below GND. Note 10: Guaranteed by design. Note 9: Recommended operating conditions.5 0 –0. they will be clamped by internal diodes.0 1. Note 6: Linearity.0 DNL (LSB) INL (LSB) 0. t r = tf = 5ns and VIN– = 2.5V. The deviation is measured from the center of the quantization band.5 –2.5V for bipolar mode unless otherwise specified.0 0 16384 32768 49152 OUTPUT CODE 65536 18637 GO2 Histogram for 4096 Conversions 2500 2152 2000 1500 1000 935 579 276 0 1 26 –2 –1 0 CODE 1 122 2 5 3 0 4 18637 GO3 –4 –3 4096 Points FFT Plot (fIN = 1kHz) 0 –20 –40 –60 –80 SNR = 88. Note 8: Unipolar offset is the offset voltage measured from +1/2LSB when the output code flickers between 0000 0000 0000 0000 and 0000 0000 0000 0001 for LTC1867 and between 0000 0000 0000 and 0000 0000 0001 for LTC1863. otherwise specifications are at TA = 25°C. fSAMPLE = 200ksps at 25°C.048V for bipolar mode is measured with respect to VIN– = 2. The INL and DNL are tested in bipolar mode.5 –1.LTC1863/LTC1867 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range. Bipolar offset is the offset voltage measured from –1/2LSB when output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 for LTC1867.8dB SINAD = 87.0 0 16384 32768 49152 OUTPUT CODE 65536 18637 GO1 Differential Nonlinearity vs Output Code 2.5 1. not subject to test. TYPICAL PERFORMANCE CHARACTERISTICS (LTC1867) Integral Nonlinearity vs Output Code 2.0 1. This product can handle input currents of greater than 100mA below GND without latchup. Note 5: VDD = 5V. These pins are not clamped to VDD.5 1. Note 11: t2 of 25ns maximum allows fSCK up to 20MHz for rising capture with 50% duty cycle and fSCK up to 40MHz for falling capture (with 3ns setup time for the receiving logic).5dB THD = 94dB fSAMPLE = 200ksps VREF = 0V REFCOMP = EXT 5V –80 –90 RESULTING AMPLITUDE ON SELECTED CHANNEL (dB) –100 –110 –120 Crosstalk vs Input Frequency AMPLITUDE (dB) AMPLITUDE (dB) ADJACENT PAIR –100 –120 –140 0 25 50 FREQUENCY (kHz) 18637 G04 –100 –120 –140 75 100 0 25 50 FREQUENCY (kHz) 18637 G05 NONADJACENT PAIR –130 –140 75 100 1 10 100 1000 ACTIVE CHANNEL INPUT FREQUENCY (kHz) 18637 G06 18637fa 5 . and between 0000 0000 0000 and 1111 1111 1111 for LTC1863. offset and gain error specifications apply for both unipolar and bipolar modes. REFCOMP = External 5V) SNR = 90dB SINAD = 88.5 0 –0. The input range of ±2.5 –2. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve.0 500 –1.0 –1.9dB THD = 95dB fSAMPLE = 200ksps INTERNAL REFERENCE 0 –20 –40 –60 –80 4096 Points FFT Plot (fIN = 1kHz.5 –1.0 COUNTS 0.

0 0.6 0.3 1.8 0.25 SUPPLY VOLTAGE (V) 5.5 1.1 1.4 1.5 1.3 1.4 DNL (LBS) INL (LBS) Differential Nonlinearity vs Output Code (LTC1863) 1.8 –1.0 1.6 0.4 –0.75 5.5 5.1 0 1 10 100 fSAMPLE (ksps) 1000 18637 G10 1.0 0.5 VDD = 5V fSAMPLE = 200ksps 1.4 SUPPLY CURRENT (mA) Supply Current vs Temperature VDD = 5V fSAMPLE = 200ksps SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 1.8 –1.8 0.6 –0.0 4.2 –0.0 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE 18637 G13 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE 18637 G14 18637fa 6 .4 0.5 Supply Current vs Supply Voltage 1.5 18637 G11 1.4 –0.0 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 18637 G12 Integral Nonlinearity vs Output Code (LTC1863) 1.0 4.0 0.2 –0.6 –0.2 1.2 0 –0.0 VDD = 5V 1.2 0.LTC1863/LTC1867 TYPICAL PERFORMANCE CHARACTERISTICS (LTC1867) Signal-to-Noise Ratio vs Frequency 100 90 80 AMPLITUDE (dB) AMPLITUDE (dB) 70 60 50 40 30 20 1 10 INPUT FREQUENCY (kHz) 100 18637 G07 Signal-to-(Noise + Distortion) vs Input Frequency 100 90 80 70 60 50 40 30 20 1 10 INPUT FREQUENCY (kHz) 100 18637 G08 Total Harmonic Distortion vs Input Frequency –20 –30 –40 AMPLITUDE (dB) –50 –60 –70 –80 –90 –100 1 10 INPUT FREQUENCY (kHz) 100 18637 G09 (LTC1863/LTC1867) Supply Current vs fSAMPLE 2.2 0 –0.

The A/D configuration word is shifted into this input. CH7/COM can be either a separate channel or the common minus input for the other channels.LTC1863/LTC1867 PIN FUNCTIONS CHO-CH7/COM (Pins 1-8): Analog Input Pins. Bypass to GND with 10μF tantalum capacitor in parallel with 0.2μF tantalum capacitor in parallel with 0. Analog inputs must be free of noise with respect to GND. Bypass to GND with 10μF tantalum capacitor in parallel with 0. SDI (Pin 14): Digital Data Input Pin.048V DIFFERENTIAL INPUTS + – CH0 CH1 CH2 CH3 VDD GND SDI LTC1863/ SDO LTC1867 SCK CS/CONV VREF REFCOMP 5V 4. To overdrive REFCOMP. SDO (Pin 13): Digital Data Output.096V SINGLE-ENDED INPUT + CH4 CH5 CH6 CH7/COM DIGITAL I/O 2. CS/CONV (Pin 11): This input provides the dual function of initiating conversions on the ADC and also frames the serial data transfer. This pin can also be used as an external reference buffer input for improved accuracy and drift. REFCOMP (Pin 9): Reference Buffer Output Pin. VDD (Pin 16): Analog and Digital Power Supply.2μF 4. Straight binary format for unipolar mode and two’s complement format for bipolar mode.1μF ceramic capacitor. VREF (Pin 10): 2. GND (Pin 15): Analog and Digital GND. The A/D conversion result is shifted out of this output. Bypass to GND with 2. tie VREF to GND.1μF ceramic capacitor.096V 10μF 18637 TCD TEST CIRCUITS Load Circuits for Access Timing 5V 3k DN 3k CL DN CL DN 3k CL DN CL Load Circuits for Output Float Delay 5V 3k (A) Hi-Z TO VOH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL 18637 TC01 (A) VOH TO Hi-Z (B) VOL TO Hi-Z 18637 TC02 18637fa 7 . TYPICAL CONNECTION DIAGRAM ±2.5V 2.1μF ceramic capacitor (4. SCK (Pin 12): Shift Clock.5V Reference Output.096V Nominal). This clock synchronizes the serial data transfer.

4V t3 2.4V 2. t6 (SDI Hold Time After SCK↑) t5 2.4V t6 0.4V SDO Hi-Z 2. the DAC output balances the analog input. 200ksps capacitive successive approximation A/D converter. In the acquire phase. and the analog input is acquired in preparation for the next conversion.4V 0. the internal differential 16-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB).4V 90% 10% Hi-Z 1867 TD APPLICATIONS INFORMATION Overview The LTC1863/LTC1867 are complete. Conversions are started by a rising edge on the CS/CONV input.4V 0.4V t7 (SLEEP Mode Wake-Up Time) t7 SCK 50% SLEEP BIT (SLP = 0) READ-IN CS/CONV 50% SDO CS/CONV t8 (BUS Relinquish Time) t8 2. a precision internal reference. During the conversion. t3 (SDO Valid Hold Time After SCK↓) t2 SCK 0.4V SDI 2. Once a conversion cycle has begun. it cannot be restarted.5μs will provide enough time for the sample-and-hold capacitors to acquire the analog signal. At the end of a conversion. The input is sucessively compared with the binary weighted charges supplied by the differential capacitive DAC.4V 0. Bit decisions are made by a low-power. Between conversions.LTC1863/LTC1867 TIMING DIAGRAMS t1 (For Short Pulse Mode) t1 CS/CONV 50% 50% t2 (SDO Valid Before SCK↑). low power multiplexed ADCs. differential comparator. the ADCs receive an input word for channel selection and output the conversion result.4V SDO t4 (SDO Valid After CONV↓) t4 CS/CONV SCK t5 (SDI Setup Time Before SCK↑). a configurable 8-channel analog input multiplexer (MUX) and a serial port for data transfer. The SAR contents (a 12-/16-bit data word) that represent the analog input are loaded into the 12-/16-bit output latches. 18637fa 8 . They consist of a 12-/16-bit. a minimum time of 1.4V 0.

CH7/COM Pin Is Used as COMMON) Channel Configuration SD 1 1 1 1 1 1 1 OS 0 0 0 0 1 1 1 S1 0 0 1 1 0 0 1 S0 0 1 0 1 0 1 0 COM 1 1 1 1 1 1 1 “+” CH0 CH2 CH4 CH6 CH1 CH3 CH5 “–” CH7/COM CH7/COM CH7/COM CH7/COM CH7/COM CH7/COM CH7/COM 18637fa CH7/COM (–) 9 . Table 1. CH7/COM Pin Is Used as CH7) SD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 OS 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 COM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Channel Configuration “+” “–” CH0 CH2 CH4 CH6 CH1 CH3 CH5 CH7 CH0 CH2 CH4 CH6 CH1 CH3 CH5 CH7 CH1 CH3 CH5 CH7 CH0 CH2 CH4 CH6 GND GND GND GND GND GND GND GND + (–) – (+) { + (–) – (+) { + (–) – (+) { + (–) – (+) { CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM + + + + + + + + CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM GND (–) 7 Single-Ended to CH7/COM Combinations of Differential and Single-Ended + + + + + + + CH0 CH1 CH2 CH3 CH4 CH5 CH6 + –{ – +{ + + + + CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7/COM GND (–) 18637 AI01 Table 2. Channel Configuration (When COM = 1. The input data word is defined as follows: SD OS S1 S0 COM UNI SLP SD = SINGLE/DIFFERENTIAL BIT OS = ODD/SIGN BIT S1 = ADDRESS SELECT BIT 1 S0 = ADDRESS SELECT BIT 0 COM = CH7/COM CONFIGURATION BIT UNI = UNIPOLAR/BIPOLAR BIT SLP = SLEEP MODE BIT Examples of Multiplexer Options 4 Differential 8 Single-Ended Changing the MUX Assignment “On the Fly” 1st Conversion 2nd Conversion + –{ + –{ CH2 CH3 CH4 CH5 CH7/COM (UNUSED) – + + + { { CH2 CH3 CH4 CH5 CH7/COM (–) 18637 AI02 Tables 1 and 2 show the configurations when COM = 0. and COM = 1.LTC1863/LTC1867 APPLICATIONS INFORMATION Analog Input Multiplexer The analog input multiplexer is controlled by a 7-bit input data word. Channel Configuration (When COM = 0.

7MHz. Good AC/DC specs. 10mA supply current. ±5V to ± 15V supplies. Regardless of the MUX configuration.7mA supply current ± 5V to ±15V supplies. In conversion mode. Good AC/DC specs. 300μA supply current. 18637fa 10 . CH1-GND. 6. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. 22V/μs 16-bit accurate amplifier LT1469 . etc) or in pairs (CH0 and CH1. 3.6MHz. The source impedance has to be kept low to avoid gain error and degradation in the AC performance. LT1007 .37MHz voltage feedback amplifier. LT1363 . Carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. If the source impedance of the driving circuit is low then the LTC1863/LTC1867 inputs can be driven directly.Dual LT1468 Input Filtering The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1863/LTC1867 noise and distortion.90MHz.3mA supply current.Dual and quad 50MHz voltage feedback amplifiers. CH4 and CH5. low power precision amplifier. Gain bandwidth product 0. 2. More detailed information is available in the Linear Technology data books or Linear Technology website. The capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. LT1227 .LTC1863/LTC1867 APPLICATIONS INFORMATION Driving the Analog Inputs The analog inputs of the LTC1863/LTC1867 are easy to drive.3mA supply current per amplifier. In addition. Figure 1 shows a 50Ω source resistor and a 2000pF capacitor to ground on the input will limit the input bandwidth to 1. LT1097 . the “+” and “–” inputs are sampled at the same instant. DC applications. More acquisition time should be allowed for a higher impedance source. The inputs draw only one small current spike while charging the sample-and-hold capacitors during the acquire mode.8mA supply current. Gain bandwidth product 8MHz. LT1360 .140MHz video current feedback amplifier. Metal film surface mount resistors are much less susceptible to both problems.50MHz voltage feedback amplifier. The following list is a summary of the op amps that are suitable for driving the LTC1863/LTC1867. CH7 can act as a COM pin for both single-ended and differential modes if the COM bit in the input word is high.Low noise precision amplifier. the analog inputs draw only a small leakage current. 6. A simple 1-pole RC filter is sufficient for many applications. Low noise and low distortion. Each of the analog inputs can be used as a singleended input relative to the GND pin (CH0-GND. LT1364/LT1365 . CH6 and CH7) for differential inputs. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. NPO and silver mica type dielectric capacitors have excellent linearity. ±5V to ±15V supplies. CH2 and CH3. Good AC/DC specs. ±5V to ±15V supplies. DC applications.Low cost. High quality capacitors and resistors should be used since these components can add distortion. For instance. LT1468 .

. The distribution is Gaussian and the RMS code transition noise is about 0. The output is band limited to frequencies from above DC and below half the sampling frequency. a signal-to-noise ratio of 90dB can be achieved. LTC1867 Histogram for 4096 Conversions 11 . Figure 3 shows a typical SINAD of 87.9dB THD = 95dB fSAMPLE = 200ksps INTERNAL REFERENCE REFCOMP 10μF 1867 F01a Figure 1a. the ADC’s spectral content can be examined for frequencies outside the fundamental. THD is expressed as: THD = 20 log V22 + V32 + V42 . LTC1867 Nonaveraged 4096 Point FFT Plot COUNTS 1500 Total Harmonic Distortion 935 579 1000 500 276 0 1 26 –2 –1 0 CODE 18637 GO3 122 1 2 5 3 0 4 Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself.. in Figure 2 the distribution of output codes is shown for a DC input that had been digitized 4096 times. Optional RC Input Filtering for Differential Inputs DC Performance One way of measuring the transition noise associated with a high resolution ADC is to use a technique where a DC signal is applied to the input of the ADC and the resulting output codes are collected over a large number of conversions.LTC1863/LTC1867 APPLICATIONS INFORMATION ANALOG INPUT 50Ω CH0 2000pF GND LTC1863/ LTC1867 Dynamic Performance FFT (Fast Fourier Transform) test techniques are used to test the ADC’s frequency response.8dB SINAD = 87. For example. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. 2500 2152 2000 AMPLITUDE (dB) –20 –40 –60 –80 –100 –120 –140 0 25 50 FREQUENCY (kHz) 18637 G04 75 100 Figure 3.74LSB. + VN2 V1 18637fa –4 –3 Figure 2.9dB with a 200kHz sampling rate and a 1kHz input. Optional RC Input Filtering for Single-Ended Input 1000pF 50Ω DIFFERENTIAL ANALOG INPUTS CH0 1000pF 50Ω CH1 1000pF REFCOMP 10μF 1867 F01b LTC1863/ LTC1867 Figure 1b. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm. distortion and noise at the rated throughput. Signal-to-Noise Ratio The Signal-to-Noise and Distortion Ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. When an external 5V is applied to REFCOMP (tie VREF to GND). 0 SNR = 88.

2.0 VREF + 10μF LTC1863/ LTC1867 9 REFCOMP 0.5μs.5V BANDGAP REFERENCE 4. CS/CONV.3mA and automatic 150μA nap mode between conversions. The ADC only keeps the VREF and REFCOMP voltages active when the part is in the automatic nap mode. over the full operating temperature range. A 6k resistor is in series with the output so that it can be easily overdriven by an external reference if better drift and/or accuracy are required as shown in Figure 4.1μs.5V.5 0. curvature corrected.638V to 4.5 VOUT 10 2. Internal Clock The internal clock is factory trimmed to achieve a typical conversion time of 3μs and a maximum conversion time. This reference amplifier compensation pin.096V at REFCOMP (Pin 9). temperature compensated.096V 10μF R2 R3 LTC1863/LTC1867 1867 F04a 15 GND The LTC1863/LTC1867 go into automatic nap mode when CS/CONV is held high after the conversion is complete.2μF 1. 3. Internal Reference The LTC1863/LTC1867 has an on-chip. Using the LT1019-2.0 VDD = 5V Figure 4a. must be bypassed with a 10μF ceramic or tantalum in parallel with a 0. After the conversion.LTC1863/LTC1867 APPLICATIONS INFORMATION where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. LT1867 Reference Circuit SUPPLY CURRENT (mA) 5V VIN LT1019A-2. The reference amplifier gains the VREF voltage by 1. A logic rising edge applied to the CS/CONV input will initiate a conversion. taking CS/CONV low will enable the serial port and the ADC will present digital data in two’s complement format in bipolar mode or straight binary format in unipolar mode. It is internally connected to a reference amplifier and is available at VREF (Pin 10). The slower the sample rate allows the power dissipation to be lower (see Figure 5).1μF 15 GND 1867 F04b 0 1 10 100 fSAMPLE (ksps) 1000 18637 G10 Figure 4b. the power dissipation drops with reduced sample rate. 10 VREF 2. through the SCK/SDO serial port. The typical acquisition time is 1. Supply Current vs fSAMPLE 18637fa 12 .5 as an External Reference Figure 5. With a typical operating current of 1.1μF ceramic for best noise performance. bandgap reference that is factory trimmed to 2.2μF 9 REFCOMP REFERENCE AMP R1 6k Digital Interface The LTC1863/LTC1867 have very simple digital interface that is enabled by the control input. REFCOMP.5 1. and a throughput sampling rate of 200ksps is tested and guaranteed. Automatic Nap Mode 2.

it is recommended to keep SCK. In particular. it cannot be restarted until the conversion is complete. In this mode (Example 2. Figures 8 and 9 are the transfer characteristics for the bipolar and unipolar mode. REFCOMP and VDD should be bypassed to this ground plane as close to the pin as possible.2μF/10μF bypass capacitors on VREF/ REFCOMP pins). Example 1. CS/CONV Starts a Conversion and Remains HIGH Until Next Data Transfer. tACQ 1/fSCK CS/CONV tCONV DON'T CARE NAP MODE NOT NEEDED FOR LTC1863 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DON'T CARE SDI Hi-Z DON'T CARE SD 0S S1 S0 COM UNI SLP DON'T CARE SDO (LTC1863) SDO (LTC1867) MSB D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1867 F06 Figure 6. After release from the SLEEP mode. With CS/CONV Remaining HIGH After the Conversion.LTC1863/LTC1867 APPLICATIONS INFORMATION If the CS/CONV returns low during a bit decision. the ADCs remain powered up. care should be taken not to run any digital signal alongside an analog signal. SDI. Example 1 (Figure 6) shows the LTC1863/LTC1867 operating in automatic nap mode with CS/CONV signal staying HIGH after the conversion. Communication with other devices on the bus should not coincide with the conversion period (tCONV ).e. the MSB bit will appear on SDO at the end of the conversion and the ADC will remain powered up. before the first bit decision) or after the conversion ends. Automatic Nap Modes Provides Power Reduction at Reduced Sample Rate. the ADC need 60ms to wake up (2. Sleep Mode If the SLP = 1 is selected in the input word. For best performance. Figure 7). If CS/CONV is low when the conversion ends. the low impedance of the common return for these bypass capacitors is essential to the low noise operation of the ADC. All analog inputs should be screened by GND. The rising edge transition of the CS/CONV will start a conversion. Automatic nap mode provides power reduction at reduced sample rate. even though these signals may be ignored by the serial interface (DON’T CARE). 18637fa 13 . VREF. Figures 6 and 7 show the timing diagrams for two types of CS/CONV pulses. Broad Layout and Bypassing To obtain the best performance. Timing and Control Conversion start is controlled by the CS/CONV digital input. Layout for the printed circuit board should ensure digital and analog signal lines are separated as much as possible. the ADC will enter SLEEP mode and draw only leakage current (provided that all the digital inputs stay at GND or VDD). it can create a small error. The width for these tracks should be as wide as possible. The ADCs can also operate with the CS/CONV signal returning LOW before the conversion ends. and SDO at a constant logic high or low during acquisition and conversion. Once initiated. a printed circuit board with a ground plane is required. For best performance ensure that the CS/CONV returns low either within 100ns after the conversion starts (i.

.111 111.000 000..110 000.LTC1863/LTC1867 APPLICATIONS INFORMATION CS/CONV tACQ NOT NEEDED FOR LTC1863 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DON'T CARE SDI DON'T CARE tCONV SD 0S S1 S0 COM UNI SLP DON'T CARE SDO (LTC1863) SDO (LTC1867) MSB = D11 Hi-Z tCONV MSB = D15 Hi-Z D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1867 F07 Figure 7.000 FS – 1LSB Figure 8.001 000.. LTC1863/LTC1867 Bipolar Transfer Characteristics (Two’s Complement) Figure 9...001 000.111 UNIPOLAR ZERO 011...000 111..111 111..001 100.096 1LSB = FS/2n 1LSB = (LTC1863) = 1mV 1LSB = (LTC1867) = 62... OUTPUT CODE (TWO’S COMPLIMENT) 011. With CS/CONV Returning LOW Before the Conversion... CS/CONV Starts a Conversion With Short Active HIGH Pulse........5μV 0V INPUT VOLTAGE (V) 1867 F09 100.000 011.110 BIPOLAR ZERO OUTPUT CODE 111.001 100....5μV –FS/2 –1 0V 1 LSB LSB INPUT VOLTAGE (V) FS/2 – 1LSB 1867 F08 100...110 FS = 4.111 011..110 FS = 4.... the ADC Remains Powered Up.. LTC1863/LTC1867 Unipolar Transfer Characteristics (Straight Binary) 18637fa 14 .. Example 2..096 1LSB = FS/2n 1LSB = (LTC1863) = 1mV 1LSB = (LTC1867) = 62.

152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH.0098 (0.203 – 0.150 Inch) (Reference LTC DWG # 05-08-1641) .012 (0.0250 (0.0688 (1. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2.LTC1863/LTC1867 PACKAGE DESCRIPTION GN Package 16-Lead Plastic SSOP (Narrow .009 (0.198) .229 – .249) .006" (0. DIMENSIONS ARE IN (MILLIMETERS) 3.254mm) PER SIDE 0° – 8° TYP 2 3 4 5 6 7 8 .050 (0. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.978) 16 15 14 13 12 11 10 9 .189 – .165 .249) . MOLD FLASH SHALL NOT EXCEED 0.150 – .801 – 4.244 (5.305) TYP .635) BSC GN16 (SSOP) 0204 18637fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable.75) .196* (4.005 .0015 .007 – .406 – 1.004 – .0165 ±.0098 (0. However. 15 .178 – 0.004 × 45° (0.817 – 6.229) REF .015 ± .150 – .35 – 1.010" (0.0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .008 – .045 ±.016 – .988) .810 – 3.0532 – .102 – 0.38 ± 0.157** (3. no responsibility is assumed for its use.10) .254 MIN . INTERLEAD FLASH SHALL NOT EXCEED 0.

1-/2-Channel 150ksps ADC in MSOP 18637fa 16 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0209 REV A • PRINTED IN USA 1630 McCarthy Blvd. Unipolar or Bipolar. 400ksps Serial ADC Micropower Precision Series Reference 16-Bit. SSOP-16 Package Bandgap. Programmable MUX and Sequencer.linear. 8-Channel. 10ppm/°C. 1.com © LINEAR TECHNOLOGY CORPORATION 2008 . 10ppm/°C.LTC1863/LTC1867 RELATED PARTS PART NUMBER LTC1417 LT1460 LT1468/LT1469 LTC1609 LT1790 LTC1850/LTC1851 LTC1852/LTC1853 LTC1860/LTC1861 LTC1864/LTC1865 DESCRIPTION 14-Bit. 5V Supply Parallel Output. 3V or 5V Supply 850μA at 250ksps. 200ksps Serial ADC Micropower Low Dropout Reference 10-Bit/12-Bit. 5V Supply 60μA Supply Current. 1-/2-Channel 250ksps ADC in MSOP COMMENTS 20mW. 10μA at 1ksps. CA 95035-7417 www. SO-8 and MSOP Packages 450μA at 150ksps. 22V/μs.. SOT-23 Package Parallel Output. 16-Bit. 16-Bit Accurate Op Amps Low Input Offset: 75μV/125μV LTC1860L/LTC1861L 3V. Internal Reference. Configurable Bipolar and Unipolar Input Ranges. 1-/2-Channel 250ksps ADC in MSOP 16-Bit. SO-8 and MSOP Packages Single/Dual 90MHz. SO-8 and MSOP Packages 450μA at 150ksps. 2μA at 1ksps. 2μA at 1ksps. SOT-23 Package 65mW. 130μA Supply Current. 12-Bit. 10μA at 1ksps. 8-Channel. 1-/2-Channel 150ksps ADC LTC1864L/LTC1865L 3V. Programmable MUX and Sequencer. Milpitas. SO-8 and MSOP Packages 850μA at 250ksps.25Msps ADC 10-Bit/12-Bit. 400ksps ADC 12-Bit.

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