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Finite State Machines

Finally! Some ENGINEERING!

Great - Theory!

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Dynamic Discipline: Discrete State, Time

IN

Comb. Logic
NEXT STATE

Comb. Logic
CURRENT STATE

OUT

Clock

Clock STATE NEXT


Clock Period 1 Clock Period 2 Clock Period 3
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Clock Period 4

Clock Period 5

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Today's Abstraction: Finite State Machine


A FINITE STATE MACHINE has
k STAT ES S 1 ... S k (one "initial") m IN PUT S I 1 ... I m n O UT PUT S O 1 ... O n T ransitio n R ules S'(s,i) fo r each state s a nd inpu t i O utput R ule s O ut(s) for ea ch state s

Clocked FSM

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FSM Example:
Lets build an ant. SENSORS: antennae L and R, each 1 if in contact with something. ACTUATORS: Forward Step F, one- degree turns TL and TR (left, right). GOAL: Make our ant smart enough to get out of a maze like:

STRATEGY: "Right antenna to the wall" approach.


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8 situations ants know how to deal with Situation A: Following wall on right, Right antenna just touching. Turn left a little, getting to Situation B: Following wall, antenna not quite touching. Turn right a little, look for wall (A) or possibly a break in the wall (C).

Ant Psychology

Situation C: a break in the wall. Turn right & step until we hit the perpendicular wall, as shown in

Situation D: Hit the new wall, back to A.

Situation E: frontal wall. Turn left until

Situation F, which we can treat like B. G: turn left until we don't touch.
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LOST: Go forward until we hit something.

State Transition Diagram:


LOST
F __ LR _ _ LR L+R

Ant Brain Synthesis: FSM Notation


L+R _ LR

EorG
TL R L

A
TL,F

__ LR

BorC
TR,F

_ R

C
TR,F

_ R

STATE LOST LOST .... A A A A BorC BorC ....


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NEW STATE LOST EorG .... BorC A EorG EorG C A ....


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OUTPUTS F F .... TL,F TL,F TL,F TL,F TR,F TR,F ....


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0 0 0 1 .... .... 0 0 1 1 0 0 .... 0 1 0 1 0 1 ....

Stylized FSM Implementation


(One) IMPLEMENTATION STRATEGY:

ROMs for NEXT STATE, OUTPUT Logic. ENCODE each state as unique value of some set of STATE VARIABLES... Fill in truth tables from TRANSITION DIAGRAM and OUTPUT SPECIFICATION.
ARBITRARY encoding may work... BUT Choice may effect COMPLEXITY, COST!

ROM

ROM

FSMs __________________ Encodes FSMs _________________

ROM
MAY COMBINE next state and output logic into single ROM:

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Example FSM Implementation


L,R INPUTS 2

ROM
X',Y',Z'

F, TR, TL OUTPUTS X,Y,Z (These are called

___________ ____________) State Assignment:


assign unique binary codes to states. X,Y,Z 000 000 .... 010 010 010 010 011 011 .... L 0 0 .... 0 0 1 1 0 0 .... R 0 1 .... 0 1 0 1 0 1 .... LOST EorG A BorC C X',Y',Z' 000 EorG .... BorC A EorG EorG C A ....
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=000 =001 =010 =011 =100 F TR 1 0 1 0 .... .... 1 0 1 0 1 0 1 0 1 1 1 1 .... .... TL 0 0 .... 1 1 1 1 0 0 ....

LOST .... A

BorC ....

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FSMs: Issues & Variations


OUTPUTS = State Variables: Nice when you can do it. INITIAL STATE: 000 in our example. Direct CLEAR input to register? MOORE vs. MEALY machines:

MOORE Machines: Outputs depend ONLY on current state. MEALY Machines: Outputs may depend on INPUTS as well as current state.
ROM ROM ROM

MOORE

MEALY

BUG in handout!

SYNCHRONY of INPUTs -- what assumptions? Nonsense states? Worse? UNASSIGNED STATES: What about 101 in example?
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What about those unused ROM locations -- eg, for xyz = 101, etc?
L+R L+R _ LR

Unreachable States

000
__ LR

001
_ _ LR R

010

__ LR

101 111 all

110

011

_ R

100

_ R

What does Ant do if it gets into this state? _______________

Unreachable states

Can't be reached from starting state by any input sequence May waste nearly 50% of ROM Might (depending on design) be entered on startup, or for illegal inputs... ... often its important to specify transitions out (eg to starting state). 6.004 Fall 97... L10 9/18/97 10

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FSM Party Games


1. What can you say about the number of states?
k k

ROM

______________________

2. Same question:

m States

n States

______________________
0 1

3. ADVENTURE: Here's an FSM. Can you discover its rules?

FSM

(see, eg, http://www.dtek.chalmers.se/~d9dax/laby/lab_lbcdaa.html)


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Whats My Transition Diagram?


3. ADVENTURE: Here's an FSM. Can you discover its rules?
1 0=OFF, 1=ON? 0 0 1 "1111" = Surprise! 0 0 0 0 0 1 1 1 vs.
0 1

FSM Party Games:

FSM

If you know NOTHING about the FSM, youre ____________________________! If you have a BOUND on the number of states, you can discover its _______________________________

k-state FSM: Every (reachable) state can be reached in < k steps.


BUT ... states may be _______________________________!
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FSM Metaphysics
1 0 0 1 0 0 0 0 0 1 1 1 vs.

ARE THEY DIFFERENT?

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FSM Equivalence
1 0 0 1 0 0 0 0 0 1 1 1 vs.

ARE THEY DIFFERENT? NOT in any practical sense! They are EXTERNALLY INDISTINGUISHABLE, hence interchangeable. New notion: FSMs EQUIVALENT iff every input sequence yields ______________________ output sequences.

ENGINEERING GOAL:

HAVE an FSM which works... WANT simplest equivalent FSM.


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FSM Simplification
GOAL: Given FSM, find reduced-state equivalent FSM. METHOD: Detect indistinguishable ("equivalent") states, merge into single state.

EXAMPLE:
1 0 0 0 0 0 1 1 1 1

DISCOVER that all of the "ON" states are EQUIVALENT, merge them to yield:
1 0 0 1

"________________________" algorithm: Iterative application of simplification rule until no further simplifications can be found.
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Equivalent State Reduction


O B S E R V A T IO N : S i - S j IF B O T H :

1. States have identical outputs; AND 2. Every input equivalent states. Reduction Strategy: Find pairs of equivalent states, MERGE them.

L+R

LOST
F __ LR

L+R

EorG
TL _ _ LR R L

A
TL,F

_ LR

__ LR

BorC
TR,F

_ R

C
TR,F

_ R

Any candidate pairs in our Ant Brain?


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Ant Brain Synthesis:


an evolutionary step Merge equivalent states BorC and C into a single new, combined state. REDUCED (4-state) Equivalent FSM:
L+R

LOST
F

L+R

EorG
TL _ _ LR R __ LR L

A
TL,F

_ LR

__ LR

BorC
TR,F _ R

Behaves exactly as previous (5-state) FSM, but requires half the ROM in its implementation!
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Ant Brain: Circuit Diagram


INPUTS i

ROM
s

OUTPUTS

STATE (Hmmm, looks a lot like the circuit of the Bldg 36 Elevator Controller...)

ROM Size (bits) = ________________________________

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Most REAL digital sequential systems are FSMs:

States vs. Bits

Registers Counters RAM chips Cash machines Video games Personal computers Mainframe processors.
FSM view of system state identifies STATES ; Alternative MEMORY view of system state identifies BITS. NUMBER OF STATES can grow EXPONENTIALLY with hardware:

Add 1 flip flop => DOUBLE number of states k-bit memory has 2 states!
GENERALLY:

FSM view useful for optimizing SIMPLE devices; MEMORY view useful for designing large systems.
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What makes a Bee pig out?

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Consciousness Explained?
Bee awareness of being on the road...
Is a bee conscious of its distance from home? What dictates the bees feeding behavior -Social responsibility? Peer pressure? Level of hunger?

Apparent answer:
One combinational input bit (FOOD HERE); and One state bit (got here via air).

Is this a single bit of consciousness?


Insects: a few bits of consciousness How many bits for an ant? A guppy? An MIT Prof?

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Finite State Machines:


an important abstraction FORMAL MODEL: Substantial literature, theoretical results. PRACTICAL IMPACT: Major engineering tool... ... You'll see FSMs for the rest of your life! Can you believe this guy? I'll never see an FSM! No, not with that dumb hat.

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