Instruction Processing

LC-3 Instruction Processing
Textbook chapter 4 CMPE 12 Summer 2008
Phases of Instruction Processing

Fetch instruction from memory Decode instruction Evaluate address Fetch operands from memory Execute operation Store result
CMPE12 Summer 2008 Slides by ADB 2
Phases of Instruction Processing

Six basic phases of instruction processing F D EA OP EX S

Instruction fetch Instruction decode Evaluate address Fetch operands Execute Store result
Notes
Not all phases are needed by every instruction But all instructions will go through F and D Phases may take more than one clock cycle
CMPE12 Summer 2008 Slides by ADB
Phases: Fetch
Load next instruction (at address stored in PC) from memory into Instruction Register (IR). Copy contents of PC into MAR. Send read signal to memory. Copy contents of MDR into IR. Then increment PC, so that it points to the next instruction in sequence. PC becomes PC+1.
F D EA OP EX S
4
Phases: Decode
First identify the opcode In LC-3, this is always the first four bits of instruction. A 4-to-16 decoder asserts a control line corresponding to the desired opcode. Depending on opcode, identify other operands from the remaining bits Example:
F D EA OP EX S
5
for LDR, last six bits is offset for ADD, last three bits is second source operand
Phases: Evaluate Address
For instructions that require memory access, compute address used for access Examples: add offset to base register (as in LDR) add offset to PC add offset to zero
F D EA OP EX S
Phases: Fetch Operands
Obtain source operands needed to perform the operation Examples:
F D EA OP EX S
load data from memory (LDR) read data from register file (ADD)
Phases: Execute
Perform the operation, using the source operands Examples: send operands to ALU and assert ADD signal
F D EA OP EX S
Phases: Store Result

Write results to destination (register or memory) Examples: result of ADD is placed in destination register result of memory load is placed in destination register for store instruction, data is stored to memory
F D EA OP EX S
write address to MAR, data to MDR assert WRITE signal to memory
LC-3 Data Path
Filled arrow = info to be processed Unfilled arrow = control signal
10
Data Path Components: Global Bus

What is a bus? Global bus: Special set of wires that carry a 16bit signal to many components Inputs to the bus are tri-state buffers that only place a signal on the bus when they are enabled Only one device speaks on the bus at any given time
Control unit decides which signal drives the bus Control unit write-enables the destination device
11
Any number of components can read the bus
Tri-State Buffer

Tri-state buffer allows some outputs to be turned off Places them in high-impedance or high-Z state Outputs can have one of three values Zero (0) One (1) Z (no output)
12
Global Bus
What is a bus?
13
Memory, MAR, MDR
Control and data registers for memory and I/O devices MAR (Memory Address Register) Holds the last address accessed MDR (Memory Data Register) Holds the last data read Control signal for read/write
ALU
Inputs: one of the following Register file Immediate field
Sign-extended bits from IR
Output goes to bus, and then used by Condition code logic Register file Memory
17
Register File

Two read addresses (SR1, SR2) One write address (DR) Inputs: one of the following Result of ALU operation Memory read Outputs: Two 16-bit outputs used by ALU

ALU instructions Data for store instructions passes through ALU

19
PC and PCMUX
PC and PCMUX Program Counter and the PC multiplexer Input to PC: one of the following (controlled by PCMUX) PC+1 from the fetch stage Output of address adder (for branches and jumps) Global bus for trap instructions
MAR and MARMUX
Inputs to MAR: one of the following (controlled by MARMUX) Output of address adder (for loads and stores) Zero-extended IR[7:0] for trap instructions
23
Condition Codes

Input The global bus Output N, Z, P signals Registers set only when control unit enables them (LD.CC) Certain instructions set the codes
ADD, AND, NOT, LD, LDI, LDR, LEA
24
Data Path Components: Finite State Machine
On each machine cycle, FSM changes control signals for next phase of instruction processing
Who drives the bus?

GatePC,
GateALU,
Which registers are write-enabled?

LD.IR,
LD.REG,
Which operation should the ALU perorm?

ALUK
Logic includes opcode decoder, etc.
25
10
Finite State Machine
On each machine cycle, FSM changes control signals for next phase of instruction processing Who drives the bus?
GatePC, GateALU,
Which registers are writeenabled?
LD.IR, LD.REG,
Which operation should the ALU perorm?
ALUK
Logic includes opcode decoder, etc.
Tracing the Data Path Through the LC-3
Example 1
ADD R2, R0, R1 STR R3, R5, xB BRz ENDLOOP
Example 2
Example 3
27
11
Example 1: 1a. Fetch (step 1)

x30A2 add R2,R0,R1
System bus:
28
Example 1: 1b. Fetch (step 2)

x30A2 add R2,R0,R1
System bus:
29
12
Example 1: 2. Instruction Decode

x30A2 add R2,R0,R1
System bus:
30
Example 1: 3. Evaluate Address

x30A2 add R2,R0,R1
System bus:
31
13
Example 1: 4. Fetch Operands

x30A2 add R2,R0,R1 R0 = R1 = R2 =
System bus:
32
Example 1: 5. Execute
x30A2 add R2,R0,R1 R0 = R1 = R2 =
System bus:
33
14
Example 1: 6. Store Results

x30A2 add R2,R0,R1 R0 = R1 = R2 =
System bus:
34
Example 2:
x3117 STR R3,R5,xB R3 = R5 =
1. Instruction fetch (1st step)

15
Example 2:
x3117 STR R3,R5,xB R3 = R5 =
1. Instruction fetch (2nd step)

Example 2:
x3117 STR R3,R5,xB R3 = R5 =
2. Instruction decode
16
Example 2:
x3117 STR R3,R5,xB R3 = R5 =
3. Evaluate address
Example 2:
x3117 STR R3,R5,xB R3 = R5 =
4. Fetch operands
17
Example 2:
x3117 STR R3,R5,xB R3 = R5 =
5. Execute
Example 2:
x3117 STR R3,R5,xB R3 = R5 =
6. Store results
18
Example 3:
x3040 BRZ EndLoop EndLoop =
1. Instruction fetch (1st step)

Example 3:
2. Instruction fetch (2nd step)

19
Example 3:
2. Instruction decode
Example 3:
3. Evaluate address
20
Example 3:
4. Fetch operands
Example 3:
5. Execute
21
Example 3:
6. Store results
Recommended exercises:

Ex 4.8, 4.10 Ex 4.13 and 4.16 (a little bit more advanced)
49
22
Full LC3 instruction set
50
23

Instruction Processing

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Instruction Processing

Uploaded by

Copyright:

Available Formats

LC-3 Instruction Processing

Textbook chapter 4 CMPE 12 Summer 2008

Phases of Instruction Processing

Phases of Instruction Processing

Six basic phases of instruction processing F D EA OP EX S

CMPE12 Summer 2008 Slides by ADB

CMPE12 Summer 2008 Slides by ADB

CMPE12 Summer 2008 Slides by ADB

Phases: Evaluate Address

CMPE12 Summer 2008 Slides by ADB

Phases: Fetch Operands

Obtain source operands needed to perform the operation Examples:

CMPE12 Summer 2008 Slides by ADB

CMPE12 Summer 2008 Slides by ADB

Phases: Store Result

write address to MAR, data to MDR assert WRITE signal to memory

CMPE12 Summer 2008 Slides by ADB

LC-3 Data Path

Filled arrow = info to be processed Unfilled arrow = control signal

CMPE12 Summer 2008 Slides by ADB

Data Path Components: Global Bus

Any number of components can read the bus

CMPE12 Summer 2008 Slides by ADB

CMPE12 Summer 2008 Slides by ADB

CMPE12 Summer 2008 Slides by ADB

Memory, MAR, MDR

Inputs: one of the following Register file Immediate field

Sign-extended bits from IR

CMPE12 Summer 2008 Slides by ADB

ALU instructions Data for store instructions passes through ALU

CMPE12 Summer 2008 Slides by ADB

MAR and MARMUX

CMPE12 Summer 2008 Slides by ADB

ADD, AND, NOT, LD, LDI, LDR, LEA

CMPE12 Summer 2008 Slides by ADB

Data Path Components: Finite State Machine

Who drives the bus?

Which registers are write-enabled?

Which operation should the ALU perorm?

Logic includes opcode decoder, etc.

CMPE12 Summer 2008 Slides by ADB

Finite State Machine

Which registers are writeenabled?

Which operation should the ALU perorm?

Logic includes opcode decoder, etc.

CMPE12 Summer 2008 Slides by ADB 26

Tracing the Data Path Through the LC-3

ADD R2, R0, R1 STR R3, R5, xB BRz ENDLOOP

CMPE12 Summer 2008 Slides by ADB

Example 1: 1a. Fetch (step 1)

CMPE12 Summer 2008 Slides by ADB

Example 1: 1b. Fetch (step 2)

CMPE12 Summer 2008 Slides by ADB

Example 1: 2. Instruction Decode

CMPE12 Summer 2008 Slides by ADB

Example 1: 3. Evaluate Address

CMPE12 Summer 2008 Slides by ADB

Example 1: 4. Fetch Operands

CMPE12 Summer 2008 Slides by ADB

CMPE12 Summer 2008 Slides by ADB

Example 1: 6. Store Results

CMPE12 Summer 2008 Slides by ADB

1. Instruction fetch (1st step)

1. Instruction fetch (2nd step)