You are on page 1of 7


Jeethendra Kumar P K KamalJeeth Instrumentation and Service Unit, Bangalore 560 094

Abstract From the output and transconductance characteristics curves of n-channel JFET maximum drain current IDSS and pinch-off voltage Vp is determined. The variation of drain source resistance with gate voltage and variation of transconductance with gate voltage is studied. The amplification factor is calculated.

The junction field effect transistor JFET is a unipolar device. Only one type of charge carriers (majority carriers) is involved in conduction in JFET. The JFET or FET differs from a bipolar transistor in several ways. The most important being, in a bipolar transistor the small input (base) current controls the large output (collector) current, making it a current controlled device. In the case of a FET, it is the input voltage that controls the output current making it a voltage-controlled device. The output drain current is controlled by the electric field across conductivity region from which the name field effect transistor has been derived. There are two types of FETs. The Junction FET in which the control electrode or gate is isolated from the conducting channel by a reverse biased junction and in the insulated gate field effect transistor (or MOS FET) a layer of silicon dioxide is used to insulate the control electrode. Figure-1 shows n-channel JFET, a silicon bar of n-type semiconductor material with two islands of p-type material embedded in the sides. The lower end of the device is called the source because free electrons enter the device at this point. The upper end is known as drain because free electrons leave from here. The
Drain n-bar D Sheild G p S N-Channel JFETSchmatic Symbol Source G D BFW/10/11/61 Bottom View S

Gate p

N-Channel JFETStructure

Figure-1, JFET n-Channel two p-regions are internally connected and are called the gate. A small space is left between the two p-regions it is through this narrow channel that the free electrons pass as they move from source to drain. Figure-2 shows the schematic symbol of an n-channel JFET. For a pChannel JFET the arrow at the gate is reversed. The normal way of biasing the FET by applying DC voltage across n-channel with positive to drain and negative to source. The gate controls the flow of current by placing it at negative potential. At low Drain-Source voltage (VDS) the depletion regions are thin and the current increases with the voltage linearly. As VDS increases the two depletion layers come closer (but never touch each other) and drain current thereafter remains the same. This voltage where the depletion layers come very close is known as pinch off voltage (Vp) or VGSOFF. Beyond the pinch off voltage the drain current saturates. This maximum saturated current is denoted IDSS. Placing the gate at -ve potential with respect to source, the depletions regional are drawn more deeply into the channel and therefore the drain current drops and attains saturation earlier. The variation in drain current with gate voltage is known as drain curve or output characteristics curves [1,2]. The drain current is given by : VGS VGS-VDS ID = IDSS[(1- ------- )2 (1 - -------------- )2 ] 1 VP VP

With VDS constant, a curve is obtained by plotting VGS verses drain current ID. This curve is called the transconductance curve. The input (VGS) is voltage output is current (ID) hence transfer gain is transconductance gm and it is given by : -2 IDSS gmo = ---------2 VP Where gmo is the maximum value of transconductance (VGS=0) IDSS is the maximum drain-source current with (VGS=0) VP is the pinch-off voltage

Knowing gmo, transconductance at is calculated at different VGS using the relation VGS gm = gmo[ 1- ------ ] 3 VP

The transconductance curve is a parabolic curve as per this equation. The other parameter associated with FET is the drain source resistance and its variation with source gate voltage.

VGS Rds = Rds (on) / [ 1 - ------] 4 Vp Where 5 2IDSS -Vp Rds (on) = ---------


Apparatus Used
FET characteristics experimental setup consisting of dual power supplies, digital dc voltmeter 0-20V, digital dc milliammeter 0-20mA



VGS -5V-0 G


VDD -5-0V

Figure-2, Circuit diagram for FET characteristics

Experimental Procedure
1. The n- channel JFET BFW10 is connected as shown in Figure 2. The gate is shorted to source by reducing gate voltage to zero. 2. With gate and source shorted (VGS = 0) VDS is applied, across the drains and source. Drain current current ID is noted in Table-1. 3. Trial is repeated varying VDS in suitable steps up to maximum of 8V. The corresponding drain current is recorded in Table-1. 4. Experiment is repeated by adjusting the VGS =-1V, -2V and 3V. The corresponding reading are tabulated in Table-1. A VDS versus ID graph is drawn as shown in Figure-3. 5. Now the drain source voltage is set to 2Volts. Gate source voltage is set to zero. The ID value is noted and recorded in Table-2.

6. Trial is repeated by varying VGS in steps 0.5 volts until drain current becomes zero. The voltage at which drain current becomes zero is noted. It is the pinch-off voltage Vp. Care is take to see the drain source voltage remains the constant (2V) throughout the trial. 7. A graph is drawn taking VDS along the X-axis and ID along Y-axis. The graph is shown in figure 3. This is the transconductance curve. From the curve IDSS corresponding to maximum drain current at VGS=0 is noted and gmo is calculated. 8. Using Equation- 3, gm is calculated for various values of VGS and tabulated in Table-3. And a graph is drawn taking VGS along X-axis and gm along Y-axis as shown in Figure-4. 9. Using equation 5 Rds(on) is calculated and compared with the value measured using digital multimeter. Rds is calculated at different VGS using equation-4 and listed in Table3. A graph is drawn taking VGS along X-axis Rds as shown in Figure-5.





14 12 Drain Current (mA) 10 8 6 4 2 0 0 2 4 6 8 10 Drain Source Voltage (V)

Figure-3, Output Characteristics of BFW10 Table-1 Variation of drain current with source drain voltage Drain Current (ID) mA VDS(V) VGS =0 VGS =-1V VGS = -2V VGS = -3V 0.1 1.12 0.7 0.42 0.03 0.2 1.92 1.3 0.82 0.04 0.3 2.7 1.8 1.18 0.05 0.4 3.3 2.3 1.55 0.06 0.5 4.0 2.8 1.8 0.06 0.6 4.6 3.2 2.1 0.065 0.7 5.6 3.6 2.3 0.065 0.8 5.8 4 2.5 0.07 0.9 6.2 4.3 2.65 0.08 1.0 6.7 4.7 2.8 0.08

1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.5 3.0 3.5 4.0 4.5 8V

7.2 7.7 8.2 8.6 8.8 9 9.4 9.7 10 10.2 11.2 11.8 12.2 12.5 12.5 12.5

4.95 5.4 5.6 5.8 6 6.2 6.3 6.5 6.6 6.8 7.2 7.5 7.7 7.8 7.9 7.9 Table-2 VGS (V) ID (mA) 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 12.2 9.2 6.8 4.7 2.9 1.4 0.4 0

2.9 3.0 3.1 3.15 3.25 3.3 3.35 3.4 3.45 3.45 3.55 3.6 3.65 3.70 3.7 3.7

0.08 0.08 0.08 0.08 0.08 0.08 0.08 0.08 0.085 0.085 0.09 0.095 0.1 0.1 0.1 0.1

ID Variation

gm Variation 15

Drain Current (mA)

12 9 6 3 0 -4 -3 -2 Gate-Source Voltage (V) -1 0

Figure-4, Tranconductance Curve

VGS(V) 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5

Table-3 RDS (OHMS) GM (M MHO) 140 6.97 163 6.01 196 4.98 245 3.98 326 3.00 490 2.00 980 0.99 0

= GM RDS 0.980 0.978 0.980 0.980 0.978 0.980 0.980 -

Drain Source Resistance (Ohms)

1400 1200 1000 800 600 400 200 0 -4 -3 -2 Gate Source Voltage (V) -1 0

Figure-5, Drain Source Resistance Variation Results The results obtained are tabulated in Table-4 Table-4 Experimental. 12.2 -3.5V 118 7 mho 0.98

Parameter IDSS Vp


Theoretical <20 <-8V 200 <12 -

1. The output characteristics curves of the JFET resemble that of transistor characteristics in which the base current is replaced by gate source voltage proving that JFET is a voltage controlled device. 2. The transconductance curve cuts the Y-axis at maximum drain current IDSS and it cuts the X-axis at Vp. 3. The variation in Tranconductance with gate source voltage is linear and the drain source resistance varies exponentially and at pinch off voltage it tends to infinity at pinch of voltage hence at pinchoff ID=0.

1. P,Malvono, Electronic Principles TMD Ed 3rd Ed, 1987 p-.321. 2. W Goswng, W G Townsend, J Watson, Field Effect Electronics, Butterworth London p18