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Content Addressable Memories (CAMs) (Associative Memories)

Content Addressable Memories (CAMs)

CAM high-level block diagram

Match operations

Navedena je samo adresa najveeg prioriteta

U "Mask" registru je "1" na bitskim pozicijama na kojima se proverava slaganje sadraja

Asociativna elija realizovana MOS tranzistorima


Operacija WRITE 0 WRITE 1 MASK WRITE READ 0 READ 1 ISPITIVANJE 0 ISPITIVANJE 1 Mask ISPITIV. NEAKTIVNO IL 0 0 0 0 0 V V V 0 SLII V V V V V 000 0 /Z V0 VVVV0 0 X Z 0 VVVV0 V0 X komentar

kroz Z tece struja 300 A kroz /Z tece struja 300 A neslaganje: kroz SLII tece 100 A neslaganje: kroz SLII tece 100 A

V- : slaba logika jedinica (linija preko otpornika R vezana na +V) 0- : slaba logika nula (linija preko otpornika R vezana na potencijal mase)

(SLII - Selektorska linija i Ispitni izlaz) 4

Read Write 0 Masked WR Inter.0 Standby Write 1 Iner.1 Mask Iner.

+V

Data OUT

+V

Data Read OUT Write 1 Masked WR Inter.1 Standby Write 0 Iner.0 Mask Iner.

+V

Data OUT

+V

IL /Z RD, WR Interrogate Out - Flag Interrogate IL GND RD, WR Interrogate Out - Flag Interrogate +V /Z SLII Z +V SLII Z /Z

IL Z /Z SLII

IL Z +V Interrogate RD, WR, Standby GND SLII

GND

IL /Z RD, WR Interrogate Interrogate Out - Flag GND +V SLII Z /Z

IL Z SLII

Organizacija CAM-e
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Static CAM CMOS Memory Cell


Bit Word CAM CAM M6

Bit

Bit

Bit Bit M4 M8 M9 M7 M5 Bit

Word CAM CAM

Word Match

S M3

int

S M2 M1

Wired-NOR Match Line

CAM Structure
WL<0> WL<1> WL<2> WL<3> Hit match<0> match<1> match<2> match<3> Read/Write Circuitry match/write data bit WL bit word line<0> of data array

precharge/match match
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Review: A Typical Memory Hierarchy

By taking advantage of the principle of locality:


z z

Present the user with as much memory as is available in the cheapest technology. Provide access at the speed offered by the fastest technology.

On-Chip Components Control Instr Data Cache Cache ITLB DTLB Second Level Cache (SRAM) eDRAM Main Memory (DRAM) Secondary Memory (Disk)

RegFile

Datapath

Speed (ns): Size (bytes): Cost:

.1s 100s highest

1s
Ks

10s 10Ks

100s Ms

1,000s Ts lowest
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Irwin&Vijay, PSU, 2002

CSE477 L25 Memory Peripheral.8

Caches

Address issued by the data path has to be mapped (in hardware) into a cache address
tag which word in the cache block

which cache block in the set

Cache block (aka line) unit of read/write information in cache Cache mapping strategies
z

Direct mapped
- A word can be in only one block in the cache, so only have to compare its tag against that bloc ks tag

Block set associative


- A word can be in two (or four or eight ), so have to compare its tag against the tags of those two (or four or eight ) cache blocks

Fully associative
- A word can be in any block in the cache, so have to compare its tag against the tags of all of the blocks in the cache
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CSE477 L25 Memory Peripheral.9

Irwin&Vijay, PSU, 2002

Two-Way Block Set Associative Cache


Set 1 Address issued by CPU Tag Data Set 2 Tag Data

Hit
CSE477 L25 Memory Peripheral.10

Desired word
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Irwin&Vijay, PSU, 2002

Translation Lookaside Buffers (TLBs)

Small caches used to speed up address translation in processors with virtual memory All addresses have to be translated before cache access I$ can be virtually indexed/virtually tagged

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CSE477 L25 Memory Peripheral.11 Irwin&Vijay, PSU, 2002

TLB Structure
Address issued by CPU (page size = index bits + byte select bits)

VA Tag

PA

Tag Data

Tag Data

Hit

Most TLBs are small (<= 256 entries) and thus fully associative content addressable memories (CAMs)

Hit

Desired word
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