Vol 2, Issue 9

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Vol 2, Issue 9

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Asst. Professor Department of Electrical Engineering1, Department of Electronics Engineering2 SR Group of Institution,Jhansi ashishee@gmail.com1,ashish.aitm@gmail.com2

Abstract:-Selecting the proper ADC for a particular application appears to be a formidable task, considering the thousands of converters currently in the market. A direct approach is to go right to the selection guides and parametric search engines, such as those available on the Analog Devices website. Choices are based upon the sampling rate, resolution, power supply voltage, and other important properties. But its usually not enough. How does one deal with a multiplicity of apparent best choices? Thus here this paper elaborates operating principles of architectures & the classification based on their characteristics such as Throughput, Resolution, Latency, Capability and Suitability for a particular application. Keywords: Analog to digital converter, Throughput, Resolution, Flash architecture, Sigma Delta architecture, Pipelined architecture, Successive Approximation architecture Introduction:-The most popular ADC architectures available today are f l a s h (all decisions made simultaneously), pipelined (with multiple flash stages), successive approximations (sometimes called SAR because a successive approximation (shift register) is the key defining element) and s i g m a d e l t a ( ), a charge-balancing type. All A/D converters require one or more steps involving comparison of an input signal with a reference. A very large percentage of these applications can be filled by successive approximation (SAR), sigma delta and pipelined ADCs. A basic understanding of these, the three most popular ADC architectures and their relationship to the market segments is a useful supplement to the selection guides and search engines. The classification in Figure 1 shows in a general way how these application segments and the associated typical architectures relate to ADC resolution (vertical axis) and sampling rate (horizontal axis). The dashed lines represent the approximate state of t he art in mid -2005. Even t hough t he various architectures have specifications with a good deal of overlap, the applications themselves are key to choosing the specific architecture required. All A/D converters require one or more steps involving comparison of an input signal with a reference. Figure 1.2 shows qualitatively how flash, pipelined, and SAR architectures differ with respect to the number of comparators used vs. the number of comparison cycles needed to perform a conversion.

Figure1.2. Trade off between decision cycles and comparators 2. Converter and their Architectures: 2.1. FLASH CONVERTERS Conceptually, the flash architecture (illustrated in Figure 2.1) is quite straightforward: a set of 2n 1 comparators is used to directly measure an analog signal to a resolution of n bits. For a 4-bit flash ADC, the analog input is fed into 15 comparators, each of which is biased to compare the input to a discrete transition value. These values are spaced one leastsignificant bit (LSB = FS/2n) apart. The comparator outputs simultaneously present 2n1 discrete digital output states. If for example the input is just above 1/4 of full scale, all comparators biased to less than 1/4

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full scale will output a digital 1, and the others will output a digital 0. Together, these outputs can be read much like a liquid thermometer. The final step is to level-decode the result into binary form.

In principle, a pipelined converter with p pipeline stages, each with an m-bit flash converter, can produce a highspeed ADC with a resolution of n = p m bits using p (2m1) comparators. For example, a 2-stage pipelined converter with 8-bit resolution requires 30 comparators, and a 4-stage 16-bit ADC requires only 60 comparators. In practice, however, a few additional bits are generated to provide for error correction.

Figure2.2. A Single Pipeline converter Figure2.1. Flash Architecture Implications & Design Consideration: The flash architecture has the advantage of being very fast, because the conversion occurs in a single ADC cycle. The disadvantage of this approach is that it requires a large number of comparators that are carefully matched and properly biased to ensure that the results are linear. Since the number of comparators needed for an n-bit resolution ADC is equal to 2n1, limits of physical integration and input loading keep the maximum resolution fairly low. For example, a 4-bit ADC requires 15 comparators, an 8-bit ADC requires 255 comparators, and a 16-bit ADC would require 65,535 comparators. 2.2. PIPELINED CONVERTERS The Pipelined (or pipelined-flash) architecture effectively overcomes the limitations of the flash architecture. A pipelined converter divides the conversion task into several consecutive stages. Each of these stages, as shown in Figure 2.2, consists of a sample-and- hold circuit, an m-bit ADC (e.g., a flash converter), and an m-bit D/A converter (DAC). First the sample and hold circuit of the first stage acquires the signal. The m-bit flash converter then converts the sampled signal to digital data. The conversion result forms the most significant bits of the digital output. This same digital output is fed into an m-bit digital-to-analog converter, and its output is subtracted from the original sampled signal. The residual analog signal is then amplified and sent on to the next stage in the pipeline to be sampled and converted as it was in the first stage. This process is repeated through as many stages as are necessary to achieve the desired resolution. Implications & Design Consideration: Pipelined converters achieve higher resolutions than flash converters containing a similar number of comparators. This comes at the price of increasing the total conversion time from one cycle to p cycles. But since each stage samples and holds its input, p conversions can be underway simultaneously. The total throughput can therefore be equal to the throughput of a flash converter, i.e., one conversion per cycle. The difference is that for the pipelined converter, we have now introduced latency equal to p cycles. Another limitation of the pipelined architecture is that the conversion process generally requires a clock with a fixed period. Converting rapidly varying on-periodic signals on a traditional pipelined converter can be difficult because the pipeline typically runs at a periodic rate. 2.3. SUCCESSIVE APPROXIMATION CONVERTERS The successive-approximations architecture can be thought of as being orthogonal to the flash architecture. While a flash converter uses many comparators to convert in a single cycle; a SAR converter, shown in Figure 2.3, conceptually uses a single comparator over many cycles to make its conversion. The SAR converter works like an old-fashioned balance scale. On one side of the scale, we place the sampled unknown quantity. On the other side, we place a weight (generated by the SAR and DAC) that has the value of 1/2 of full-scale and compare the two values. This first weight represents the most significant bit (MSB). If the unknown quantity is larger, the 1/2-scale weight

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is retained; if the unknown quantity is smaller, it is removed. This series of steps is repeated n times, using successively smaller weights in binary progression (e.g., 1/4, 1/8, 1/16, 1/32 . . . 1/2 n of full scale) until the desired resolution, n, is attained. Each weight represents a binary bit, with the largest representing the most significant bit, and the smallest representing the least significant bit.

fast SAR converters are capable of under sampling, the faster pipelined converters tend to be more effective at it. 2.4. SIGMA-DELTA CONVERTERS The sigma-delta architecture takes a fundamentally different approach than those outlined above. In its most basic form, a sigma- delta converter consists of an integrator, a comparator, and a single- bit DAC, as shown in Figure 2.4.The output of the DAC is subtracted from the input signal. The resulting signal is then integrated, and the integrator output voltage is converted to a single-bit digital output (1 or 0) by the comparator. The resulting bit becomes the input to the DAC, and the DACs output is subtracted from the ADC input signal, etc. This closed-loop process is carried out at a very high oversampled rate. The digital data coming from the ADC is a stream of ones and zeros, and the value of the signal is proportional to the density of digital ones coming from the comparator. This bit stream data is then digitally filtered and decimated to result in a binaryformat output.

Figure2.3. Successive Approximation Architecture Implications & Design Consideration: A SAR converter can use a single comparator to realize a high resolution ADC. But it requires n comparison cycles to achieve n-bit resolution, compared to p cycles for a pipelined converter and 1 cycle for a flash converter. Since a successive-approximations converter uses a fairly simple architecture employing a single SAR, comparator, and DAC, and the conversion is not complete until all weights have been tested, only one conversion is processed during n comparison cycles. For this reason, SAR converters are more often used at lower speeds in higher-resolution applications. SAR converters are also well suited for applications that have non-periodic inputs, since conversions can be started at will. This feature makes the SAR architecture ideal for converting a series of timeindependent signals. A single SAR converter and an input multiplexer are typically less expensive to implement than several sigma-delta converters. With dither noise present, SAR and pipelined converters can use averaging to increase the effective resolution of the converter: for every doubling of sample rate, the effective resolution improves by 3 dB or 1/2 bit. One consideration when using a SAR or pipelined converter is aliasing. The process of sampling a signal leads to aliasingthe frequency-domain reflection of signals about the sampling frequency. In most applications, aliasing is an unwanted effect that requires a low-pass anti-alias filter ahead of the ADC to remove high frequency noise components, which would be aliased into the pass band. However under sampling can put aliasing to good use, most often in communications applications, to convert a highfrequency signal to a lower frequency. Under sampling is effective as long as the total bandwidth of a signal meets the Nyquist criterion (less than one-half the sampling rate), and the converter has sufficient acquisition and signal sampling performance at the higher frequencies where the signal resides. While

Figure2.4. Sigma-Delta Architecture Implications & Design Consideration: One of the most advantageous features of the sigma-delta architecture is the capability of noise shaping, a phenomenon by which much of the low-frequency noise is effectively pushed up to higher frequencies and out of the band of interest. As a result, the sigmadelta architecture has been very popular for designing low-bandwidth high-resolution ADCs for precision measurement. Also, since the input is sampled at a high oversampled rate, unlike the other architectures described in this paper, the requirement for external anti-alias filtering is greatly relaxed. A limitation of this architecture is its latency, which is substantially greater than that of the other types. Because of oversampling and latency, sigma-delta converters are not often used in multiplexed signal applications. To avoid interference between multiplexed signals, a delay at least equal to the decimators total delay must occur between conversions. These characteristics can be improved in sophisticated sigma-delta ADC designs by using multiple integrator stages and/or multi-bit DACs. 3. Application Examples

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The following three examples illustrate some of the issues described above. Example 1: Multiple Inputs, 16-Bit Resolution Consider an application that requires 16-bit resolution for 4 independent signals with bandwidths of dc to 15 kHz, 15 kHz, 15 kHz, and 45 kHz. The total throughput required to sample these signals under the N yquist criterion is (2 15 + 2 15 + 2 15 + 2 45) kSPS = 180 kSPS. At first glance, the SAR-type AD974, the sigma-delta AD7722, and the pipelined/sigma-delta AD9260 all have the required total throughput capability. But, as has been discussed above, the inherent latency of sigma-delta converters limits their effective throughput when they must continually acquire new signals by multiplexing. Effective multiplexed throughput can be defined as the total throughput of a converter when two or more independent signals are multiplexed. The following table compares the total throughput and effective throughput for each converter and indicates the number of converters of its type that would be needed to serve in this application. ARCHITECTURE EFFECTIVE MULTIPLEXED THROUGHPUT TOTAL THROUGHPUT (16-BIT RESOLUTION)

AD9260 combines pipeline and sigma-delta techniques. Its throughput rate of 2.5 MSPS makes it ideal for higher throughput single channel systems. But in this application, its settling time of 13.35 ms limits its effective throughput to 75 kSPS. To use the AD9260 in this application would require at least 3 converters. Note that if the AD9260 were purely a pipelined flash converter, a single converter would have had the required throughput, assuming that the inputs are periodic. Example 2: Single Input, 16-Bit Resolution Consider now an application that converts a single 90-kHz bandwidth input at 16-bit resolution. In this case, all three converters from the first example would work well. Here the choice among converters would be made on other considerations, including ac and dc performance, system-level considerations (e.g., Is there a great benefit to the anti-alias performance of sigma- delta converters in this application?), latency, and cost. Example 3: Multiple Inputs, 14-Bit Resolution Consider an application in which 16 inputs, each with a dc to 100-kHz bandwidth, are converted with a resolution of at least 14 bits. Three converters suitable for this application include the SAR- type AD7865, the sigma-deltaAD7722, and the pipelinedAD9240. The total throughput required under the Nyquist criterion is 2 100 kHz 16 = 3.2 MSPS. The following table shows the throughput for each converter. Of the three converters, only the AD9240 has the throughput needed to convert all 16 channels. The AD7865 has sufficient throughput for 2 inputs per converter. To use the AD7865 in this application, 8 converters would be needed. The AD7722 would need to be used in a converter-per-channel implementation; thus 16 converters would be required. While not exhaustive, the following table summarizes and rank (in a generalized sense) the relative advantages of flash, pipelined, SAR, and sigma-delta architectures. A rank of 1 in a performance category indicates that the architecture is inherently better than the others for that category. An * indicates that the architecture has the capability or characteristic listed. CHARACTE RSTIC Throughput Resolution Latency FLA SH 1 4 1 PIPELI NED 2 3 3 SA R 3 2 2 SIGM ADEL TA 4 1 4

75 kSPS

Whether converting a single input or several multiplexed inputs, the AD974 achieves a throughput rate of up to 200 kSPS. Since the application requires a total throughput of 180 kSPS, the AD974s performance is sufficient. In fact, this is exactly the type of application that the AD974 was designed for: in addition to the SAR converter and reference, it also contains an integrated 4-channel multiplexer. The AD7722 and AD9260 both face the challenges confronted by sigma-delta converters in multiplexing several inputs. The AD7722s throughput is 195 kSPS when sampling a single signal, but it drops to just 2.3 kSPS when converting multiple signals, due to the settling time which results from oversampling and filtering. To use the AD7723 in this application, four converters (one per channel) would be needed. The

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Suitability for converting multiple signals per ADC Capability to convert nonperiodic multiplexed signals Simplified anti-aliasing Can under sample Can increase resolution through averaging 1 2 1 3

radar, and communications applicationsincluding IF sampling, software radio, base stations, and set-top boxesand consumer electronics equipment, such as digital cameras, display electronics, DVDs, enhanced definition TVs, and high-definition TVs. References 1. Walt Kester, Editor, data conversion handbook Published by Newnes, an imprint of Elsevier, 2005, ISBN: 0 -7506 -7841-0.See in particular Chapter 3, Data Converter Architectures.In addition to detailed discussions of the various ADC and DAC architectures themselves, the chapter also includes historical aspects. 2. Walt Jung, Editon,op-amp application handbook Published by Newnes, an imprint of Elsevier, 2005, ISBN: 0 -7506 -7844 -5. 3. For more information on products or applications, please visit the Analog Devices, Inc., website: http://www.analog.com. 4.Scholtens, P. C. S., Smola, D., Vertragt, M. (2005): Systematic power reduction and performance analysis of mismatch limited ADC designs, International symposium on low power electronics and design pp. 7883. 5.Yoo, J., Lee, D., Choi, K., Kim, J. (2002): A power and resolution adaptive flash analog-todigital converter, International symposium on low power electronics and design pp. 233 236. 6. Tangel, A., Choi, K. (2004): The CMOS inverter as a comparator in ADC designs. Analog Integrated Circuits and Signal Processing. 7. Sundstrm, T., Alvandpou, A. (2009): A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS, Journal of Analog Integrated Circuits and Signal Processing, pp 09251030 (Print) 1573-1979 (Online). 8. Hwang, Y., Huang, P., Hwang, B., Chen, J. (2009): An efficient power reduction technique for CMOS flash analog-to-digital converters. Analog Integrated Circuit Signal Processing 61:pp. 271278 DOI 10.1007/s10470-009-9309-7. 9. Zhang, C., Shao, Z., (2009): Analysis and simulation of distributed T/H with averaging technique in folding and interpolating A/D converters, Int. J. Circ. Theory. Appl. Published online in Wiley InterScience, DOI: 10.1002/cta.603. 10. Gumenyuk, A. S., Bocharov, Y. I., (2008): Power-Reduction Techniques for CMOS Pipelined ADCs, Russian Microelectronics, Vol. 37, No. 4, pp. 253263. 11. Ross, S.W., Sinha, S. (2007): A Pipeline Analogue to Digital Converter in 0.35 m CMOS, EUROCON 2007 The International Conference on Computer as a Tool, Warsaw, September 9-12. 12. Lu, C., Lee, T., (2007): A 10-bit 60-MS/s LowPower CMOS Pipelined Analog-to-Digital Converter, IEEE Transactions on Circuits and SystemsII: Express Briefs, VOL. 54, NO. 8. 13. Hwang, Y., Chen, J., Wu, S., Liao, L., Tsai C (2007): A new pipelined analog-to-digital converter

* * *

* * *

* * *

* * *

Conclusion We have discussed here the flash, pipelined, successive approximation & sigma delta architecturesthose most widely used in modern integrated circuit ADCs. Flash type architecture is best suited for fast processing of conversion though the large number of comparators makes it costly & completive as compared to others while Successive -approximation is the architecture of choice for nearly all multiplexed data acquisition systems, as well as many instrumentation applications. The SAR ADC is relatively easy to use, has no pipeline delay, and is available with resolutions to 18 bits and sampling rates up to 3 MSPS. For a wide variety of industrial measurement applications, the sigma - delta ADC is ideal; it is available in resolutions from 12 bits to 24 bits. Sigma- delta ADCs are suitable for a wide variety of sensor- conditioning, energy-monitoring, and motor-control applications. In many cases, the high resolution and the addition of on - chip PGAs allow a direct connection between the sensor and the ADC without the need for an instrumentation amplifier or other conditioning circuitry. The sigma-delta ADC and DAC, easily integrated into ICs containing a high degree of digital functionality, also dominate the voice band and audio markets. The inherent oversampling in these converters greatly relaxes the requirements on the ADC antialiasing filter and the DAC reconstruction filter. For sampling rates greater than approximately 5 MSPS, the pipelined architecture dominates. These applications typically require resolutions up to 14 bits with high SFDR and SNR at sampling frequencies ranging from 5 MSPS to greater than 100 MSPS. This class of ADCs is used in many types of instrumentation, including digital oscilloscopes, spectrum analyzers, and medical imaging. Other applications are video,

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using current conveyors, Analog Integr Circ Sig Process 50:213220 DOI 10.1007/s10470-0079031-2. 14. Rarbi, F., Dzahini, F. (2008) :A low power 12bit and 30-MS/s pipeline analog to digital converter in 0.35m CMOS, IEEExplore. 15. Behnam, S., Sharif, B.M. (2009): Linearity analysis in pipeline A/D converters, Int. J. Circ. Theory, 37, pp.764780. 16. Mingjun, F., Junyan, R., Ning, L., Fan, Y., Jun, X. (2010): A 1.8-V 11-bit 40-MS/s 21-mW pipelined ADC, Analog Integr Circ Sig Process DOI 10.1007/s10470-010-9453-0. 17. Siva, R. K., Baghini, S. M., Mukherjee, J. (2009): Current-Mode CMOS Pipelined ADC, IEEExplore.

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