You are on page 1of 3

U LYA R.

K ARPUZCU S EPTEMBER 2013

C URRICULUM V IT
C ONTACT I NFORMATION

4-155 Keller Hall 200 Union St. S.E., Minneapolis, MN, 55455 http://www.ece.umn.edu/ukarpuzc

Ofce: (612) 626-7203 e-mail: ukarpuzc@umn.edu

R ESEARCH I NTERESTS B ACKGROUND

Computer architecture, impact of process technology on computing, energy-efcient architectures, near-threshold voltage computing, variation-aware architectures, hardware reliability. University of Minnesota Twin Cities, USA Assistant Professor in Electrical and Computer Engineering (ECE) Graduate Faculty in Computer Science and Engineering (CSci) University of Illinois at Urbana-Champaign (UIUC), USA Ph.D. in Electrical and Computer Engineering Dissertation: Novel Many-core Architectures for Energy-efciency Advisor: Prof. Josep Torrellas M.S. in Electrical and Computer Engineering Thesis: Managing Many-core Aging Advisor: Prof. Josep Torrellas U), Turkiye Istanbul Teknik Universitesi (IT B.S. (Double Major) in Computer Engineering June 2005 Thesis: Automatic Verilog Code Generation Through Grammatical Evolution Advisor: Prof. S ima Etaner Uyar B.S. in Electronics and Telecommunication Engineering June 2004 Thesis: Analysis of Low Offset Current Differencing Input Stages of Current Mode Circuits Advisor: Prof. Ali Toker Osterreichisches Sankt Georgs Kolleg (Austrian School), Istanbul, Turkiye 1992-2000 August 2012 since August 2012 since April 2013

December 2009

P UBLICATIONS

[1] Ulya R. Karpuzcu, Nam Sung Kim, and Josep Torrellas. Coping With Parametric Variation at Near-Threshold Voltages. IEEE Micro Special Issue on Reliability, July/August 2013. [2] Abhishek Sinkar, Hamid Ghasemi, Michael Schulte, Ulya R. Karpuzcu, and Nam Sung Kim. Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, May 2013. [3] Ulya R. Karpuzcu, Abhishek Sinkar, Nam Sung Kim, and Josep Torrellas. Toward EnergyEfcient Many-Cores for Near-threshold Voltage Computing. In IEEE/ACM International Symposium on High Performance Computer Architecture, HPCA, February 2013. [4] Ulya R. Karpuzcu, Krishna Kolluru, Nam Sung Kim, and Josep Torrellas. VARIUS-NTV: A Microarchitectural Model to Capture the Increased Sensitivity of Many-Cores to Process Variations at Near-Threshold Voltages. In IEEE International Conference on Dependable Systems and Networks, DSN, June 2012. [5] Brian Greskamp, Ulya R. Karpuzcu, and Josep Torrellas. LeadOut: Composing Low Overhead Frequency Enhancing Techniques for Single Thread Performance in Congurable Multicores. In IEEE/ACM International Symposium on High Performance Computer Architecture, HPCA, January 2010. [6] Ulya R. Karpuzcu, Brian Greskamp, and Josep Torrellas. The BubbleWrap Many-Core: Popping Cores for Sequential Acceleration. In IEEE/ACM International Symposium on Microarchitecture, MICRO, December 2009. Recipient of The Best Paper Award. [7] Brian Greskamp, Ulya R. Karpuzcu, and Josep Torrellas. BubbleWrap: Popping CMP Cores for Per-Thread Performance. In Wild & Crazy Ideas Session at IEEE/ACM International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS, March 2009. Recipient of The Best Idea Award.

U LYA R. K ARPUZCU S EPTEMBER 2013

C URRICULUM V IT

PAGE 2

[8] Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey Cook, Josep Torrellas, Deming Chen, and Craig Zilles. BlueShift: Designing Processors for Timing Speculation from the Ground Up. In IEEE/ACM International Symposium on High Performance Computer Architecture, HPCA, February 2009. [9] Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu, Siva Kumar Sastry Hari, and Sarita Adve. Accurate Microarchitecture-level Fault Modeling for Studying Wear-out Faults. In IEEE/ACM International Symposium on High Performance Computer Architecture, HPCA, February 2009. [10] Ulya R. Karpuzcu. Automatic Verilog Code Generation Through Grammatical Evolution. In Genetic and Evolutionary Computation Conference, GECCO, Undergraduate Student Workshop, 2005.
R ESEARCH E XPERIENCE

Graduate Research Assistant, i-acoma Group, UIUC May 2008 - August 2012 Advisor: Prof. Josep Torrellas Near-threshold Voltage Computing (NTC) (Fall 2009 ): Exploring ()architectural implications of NTC, which facilitates energy-efcient execution for throughput-critical applications by reducing the supply voltage to a value only slightly higher than the threshold voltage. To quantitatively characterize the higher sensitivity of NTC to parametric variation, introduced a ()architectural model [4]. To mitigate the impact of variation with simple hardware, proposed an NTC manycore of a single voltage domain chip-wide [3]. Techniques to Push-back the Many-core Power Wall (Fall 2008 ): Exploring ()architectural implications of increasing chip power density over technology generations, specically dark silicon. Introduced the BubbleWrap many-core [6, 7], a novel architecture trading off processor aging rate for energy-efciency. Received the Best Paper Award at MICRO 2009 [6] and the Best Idea Award at the Wild & Crazy Ideas Session at ASPLOS 2009 [7]. Timing Speculation (Summer-Fall 2008): Contributed to the development of the BlueShift CAD approach [8], which provides performance enhancement for timing speculation microarchitectures, and to the assessment of how timing speculation relates to dynamic voltage and frequency scaling to accelerate single-thread execution in lightly-loaded chip multiprocessors [5]. Graduate Research Intern, Intel Labs, Hillsboro, OR, USA Summer 2011 Mentor: Dr. Chris Wilkerson Developed an analytical model and simulation infrastructure to assess the impact of supply voltage noise at near-threshold voltages. Graduate Research Intern, AMD Research, Austin, TX, USA Summer 2009 Mentor: Dr. Jaewoong Chung To provide basic compiler support for AMDs ASF (Advanced Synchronization Facility), developed a shim software layer mapping the transactional memory branch of gccs runtime to ASF ISA. US Patent Application 20120124563, Compiler Support Technique for Hardware Transactional Memory Systems, J. Chung, U. Karpuzcu, D. Christie, M. P.Hohmuth, S. Diestelhorst, M. T. Pohlack. Date of ling: November, 2010. Fulbright Fellow, ECE, UIUC August 2006 May 2008 Advisor: Prof. Sarita Adve Developed the initial version of SWATSim[9], a hierarchical fault-injection infrastructure to study system-level manifestations of permanent faults. By application of SWATSim, assessed the accuracy of state-of-the-art ()architectural models for permanent faults. U ETA Foundation ASIC Design Center, Istanbul, Undergraduate Intern, IT Turkiye Summer 2003 Mentor: Prof. Ali Zeki Designed a Miller OTA and a frequency divider.

T EACHING E XPERIENCE

Instructor, ECE, University of Minnesota EE4363/CSci4203 Computer Architecture EE5364/CSci5204 Advanced Computer Architecture Guest Lecturer & Teaching Assistant, ECE, UIUC ECE/CS533 Parallel Computer Architecture

Fall 2013 Fall 2012 Spring 2009

U LYA R. K ARPUZCU S EPTEMBER 2013 TALKS

C URRICULUM V IT

PAGE 3

Near-threshold Voltage Computing: A Systems Perspective, Computer Science & Engineering Colloquia Lecture Series, University of Minnesota, September 2013. Toward Energy-Efcient Many-Cores for Near-threshold Voltage Computing, International Symposium on High Performance Computer Architecture, HPCA, Shenzhen, China, February 2013. V ARIUS-NTV: Capturing the Increased Sensitivity of Manycores to Process Variations at Near-Threshold Voltages, First Workshop on Near-threshold Voltage Computing (colocated with MICRO), Vancouver, BC, Canada, December 2012. V ARIUS-NTV: A Microarchitectural Model to Capture the Increased Sensitivity of Many-Cores to Process Variations at Near-Threshold Voltages, International Conference on Dependable Systems and Networks, DSN, Boston, MA, USA, June 2012. Novel Many-Core Architectures for Energy-Efciency, Department of Information Technology and Electrical Engineering, ETH Zurich, April 2012. Department of Computer Science, ETH Zurich, March 2012. Department of Electrical and Computer Engineering, University of Minnesota, March 2012. Department of Computer Engineering, Brown University, February 2012. Department of Computer Science and Engineering, Arizona State University, February 2012. Coping with the Larger Impact of Process Variations in Near-Threshold Computing, Intel Labs, Hillsboro, OR, USA, December 2010. Pushing Back the Many-Core Power Wall, Architecture Highlights 2010 IBM Architecture PIC Student Workshop, IBM T. J. Watson Research Center, Yorktown Heights, NY, USA, October 2010. LeadOut: Composing Low Overhead Frequency Enhancing Techniques for Single Thread Performance in Congurable Multicores, International Symposium on High Performance Computer Architecture, HPCA, Bangalore, India, January 2010. The BubbleWrap Many-Core: Popping Cores for Sequential Acceleration, International Symposium on Microarchitecture, MICRO, New York, NY, USA, December 2009. Automatic Verilog Code Generation Through Grammatical Evolution, Genetic and Evolutionary Computation Conference, GECCO, Undergraduate Student Workshop, Washington DC, USA, June 2005.

S ERVICE

Technical Program Committee Member International Symposium on High Performance Computer Architecture (HPCA), 2014 International Symposium on Parallel Architectures and Compilation Techniques (PACT), 2014 First Workshop on Near-threshold Voltage Computing (colocated with MICRO), 2012 Co-organizer First Workshop on Near-threshold Voltage Computing (colocated with MICRO), 2012 External Reviewer ACM/IEEE International Symposium on Computer Architecture (ISCA): 2010, 2012 ACM/IEEE International Symposium on Microarchitecture (MICRO): 2010, 2012 ACM/IEEE International Symposium on High Performance Computer Architecture (HPCA): 2010, 2011 ACM/IEEE International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS): 2012 ACM/IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT): 2011, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED): 2012 IEEE Journal of Solid State Circuits: 2010 IEEE Transactions on Computers: 2012 IEEE Transactions on Very Large Scale Integration Systems: 2013 IEEE Design and Test of Computers: 2013 ACM Computing Surveys: 2013 ACM Transactions on Parallel Computing: 2013 Registration Chair ACM/IEEE International Symposium on Computer Architecture (ISCA), 2014