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Reg. No.

Question Paper Code : 11269

B.E./B.Tech. DEGREE EXAMINATION, APRIL/MAY 2011 Sixth Semester Computer Science and Engineering

CS 2354 ADVANCED COMPUTER ARCHITECTURE (Regulation 2008) Time : Three hours Answer ALL questions

1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

What is loop unrolling? and what are its advantages?

Differentiate between static and dynamic branch prediction approaches. What is fine-grained multithreading and what is the advantage and disadvantages of fine-grained multithreading? What a VLIW processor?

What is sequential consistency?

State the advantages of threading.

Differentiate between write-through cache and snoopy cache. Compare SDRAM with DRAM.

What is multicore processor and what are the application areas of multi-core processors? What is a Cell Processor? PART B (5 16 = 80 marks) (16)

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11. (a) (b) (i)

Briefly describe any techniques to reduce the control hazard stalls. Or

Discuss about any two compiler techniques for exposing ILP in detail. (8) Explain how ILP is achieved using dynamic scheduling. (8)

(ii)

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PART A (10 2 = 20 marks)

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Maximum : 100 marks

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12.

(a)

(i) (ii)

Describe the architectural features of IA 64 Processors in detail. (10) Explain the architecture of a typical VLIW processor in detail. Or

(b)

(i) (ii)

Describe the architectural features of Itanium Processor.

13.

(a)

(i)

Describe the basic structure of a centralized shared-memory multiprocessor in detail. (6) Describe the implementation of directory-based cache coherence protocol. (10) Or

(ii)

(b)

(i)

(ii) 14. (a) (i)

Describe sequential and relaxed consistency model.

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Or Or 2

What are the advantages and disadvantages of distributed-memory Multiprocessors? Describe the basic structure of a distributedmemory multiprocessor in detail. (8) (8)

With suitable diagram, explain how virtual address is mapped to L2 cache address. (10) Discuss about the steps to be followed in designing I/O system.

(ii)

Explain how instruction level parallelism is achieved in EPIC processor. (6)

(b)

Describe the optimizations techniques used in compilers to reduce cache miss rate. (16) (i) (ii) Describe the features of SUN CMP architecture in detail. (6)

15.

(a)

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What are Multi Core processors? Explain how a multi core processors works. (10)

(b)

(i)

Discuss about the SMT kernel structure in detail. Describe the architecture of the IBM Cell Processor in detail.

(ii)

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(6) (10) (6) (8) (8)

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