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Prashant Gurjar, Rashmi Solanki Pooja Kansliwal UG Scholar, Dept. EC, GGITM, Bhopal, India Email: prashantgurjar84@gmail. .com

ABSTRACT

This paper is primarily deals the constructio on of high speed adder circuit using Hardware Description L Language (HDL) in the platform Xilinx ISE 9.2i and impl lement them on Field Programmable Gate Arrays (FPGAs) to analyze the this investigation design parameters. The motivation behind t is that an adder is a very basic building bloc ck of Arithmetic Logic Unit (ALU) and would be a lim miting factor in performance of Central Processing Unit (CP PU). In the past, thorough exami ination of the algorithms with the respect to particular technology has only been partially done. The merit of the new technology is to be evaluated by its ability to efficiently implement the computational algorithms. In the other words, the technology is developed with the aim to e efficiently serve the computation. The reverse path; evaluat ting the merit of the algorithms should also be taken. T Therefore, it is important to develop computational structu ures that fit well into the execution model of the processor an nd are optimized for the current technology. In such a case, optimization of s the critical path the algorithms is performed globally across of its implementation. In this research article, we have e simulated and der, ripple carry synthesized the various adders like full add adder, carry-look ahead adder, carry-skip p adder, carry – select adder and carry-save adder by using VHDL and Xilinx ISE 9.2i. The simulated results are verified and the functionality of high speed adders and the parameters like area and speed is analyzed. Finally this p paper concludes that the carry-save adder is the more efficie ent in speed and area consumption. KEYWORDS: High Speed Adder, Field d Programmable Gate Array, Carry Skip Adder, Carry Sele ect Adder, Carry Save Adder.

**Mahendra Vucha Asst. Prof, Dept. EC, GGITM, Bhopal, India Email: Mahendra.1548@gm mail.com
**

other kinds of processors, adders are used not only in the ALU(s), but also in other parts of o the processor, where they are used to calculate addresses, table indices, and many more.

1.2 CONCEPT OF ADDERS

Consider two binary variables x and d y. the binary sum is denoted by x+y, such that 0+0 = 0 0+1 = 1 1+0 = 1 1+ +1 = 10 Here, the result in the last case is a binary b 10(i.e., 2 inbase 10). The sum of two numbers can be out of the range of the digits in binary set. This, of course e, is the origin of the concept of a carry out. In the binary sum 1+1, the result 10 is viewed as a 0 with a 1 shifted to th he left to give a “carryout is 1”.

1.3 HALF ADDER

A half adder is a logic circuit th hat performs one-digit addition. It requires two inputs, and th he output is the sum of

r Figure 1. Half adder the inputs. The logic diagram of HA is i shown in figure 1. ry numbers A and B. It A HA adds two one-bit binar has two outputs, S and C (the value C theoretically carried on to the next addition).The simpl lest half-adder design, shown in figure 1, incorporates an a XOR gate for S and an AND gate for C. The Boolean eq quation and Truth table of half adder is shown bellow. …(i) S = A XOR B …… C = A AND B …… …(ii) or half adder Table 1. Truth table fo Input A 0 0 1 1 B 0 1 0 1 C 0 0 0 1 Output S 0 1 1 0

1.

INTRODUCTION

Digital computer ALU is an aspect of logic c design with the objective of developing appropriate algorit thms in order to achieve an efficient utilization of the avai ilable hardware. The hardware can only perform a relativ vely simple and primitive set of Boolean operations an ndthe arithmetic operations are based on a hierarchy of ope erations that are built by using algorithms against the h hardware. Since, ultimately, speed, power and utilization o of ALU are the most often used measures of the efficiency o of an algorithm.

1.1 WHAT IS AN ADDER

In digital electronics, adder is a di igital circuit that performs addition of two numbers. In many y computers and

(2) The T Carry Look-ahead Logic. which generates Si.4 FULL ADDER A Full Adder (FA) is a logical circuit th hat performs an addition operation on three binary digits. the i-th bit ts of operands A and B and a carry signal from the preceding g adder stage are Figure 4: Carry Lookah head adder . At the i-th bit position.Ci Here. 3. often written as A. COMPLEX ADDERS: The reference to eve of adding single bits. Figure 2. This is Adder (RCA). adding two nbit words yields an n-bit sum and a carry y-out bit Cn. and a carry. The structure of CLA for 4-bit adderis shown in figure 4.The carry-looka broken up in two modules: (1) The Pa artial Full Adder.Bi and Pi = (Ai⊕ Bi) Si = Ai ⊕ Bi ⊕ Ci = Pi⊕ Ci. si.1 RIPPLE CARRY ADDER: A ripple carry adder for N-b bit numbers is implemented by concatenating N full adde ers as shown on Figure 3.The carry is carried from lower bit adder to h higher bit adder. Pi and Gi.1. which generates the carry-out t bits. which are both binary digits. Carry look k ahead logic uses the concepts of generating (G) and prop pagating (P) carries. Ci+1 = Gi + Pi. Its work is based on two signals called d P and G for each bit position. A one-bit full adder ad dds three one-bit numbers. Gi = Ai. The RCA is shown in coming from the previous full adder. wh hich allows fast design time. of a ripple carry adder is simple. figure. since the delay to add two numbers depen nds on the logarithm of the size of the operands. In genera al.2 CARRY . to the next adder stage. since the carry signal “ripple” from the least s The layout significant bit position to the most significant.The HA and the sum A and B are connected to the input of first H of first HA is connected as one input al long with Ci to second HA and it give SUM output. the adders are classified. Based on carry transfer from LSB to MSB B. The logical diagram of full adder is shown in figure 2. 2. B. Full adder or values carried A FA adds binary numbers and accounts fo in as well as out. However. Ripple carry y adder 2. and Ci is a bit carried in (in the eory from a past addition). let’s extend it to adding binary words. The CLA adder is th fastest schemes used for the addition n of two numbers. The circuit produces a two-b bit output sum typically represented by the signals Co (Car rry) and S(Sum). s called a Ripple Carry ci+1. B are the operands. OR (CiAND A) Co = (A AND B) OR (B AND Ci) O ……(iv) dder Table 2. since each full adder must wait for the carry bit which is . the Boolean equation and truth table is show wn bellow. and Ci he ere A.LOOK AHEAD ADDER A A significant speed improvement in the implementation of a parallel adder was introduced by a Carry-Look aheadheoretically one of the Adder (CLA). The full adder produces a sum and a carry value. C The Si and Ci+1 represent the sum and carry from ith full ahead adder can be adder respectively. The P and G are shown bellow. PFA. Truth table for full ad A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 Cout 0 0 0 1 0 1 1 1 Sum 0 1 1 0 1 0 0 1 A FA can be constructed by cascading of two HA. 2. used to generate the i-th bit of the sum. the ripple carry add der is relatively slow. S = A XOR B XOR Ci ……(iii) Figure 3. The logical OR of first ARRY output of and second HAs carry outputs a gives CA FA.

All of them have th decreasing the computation time and diff fferent tradeoffs. [2]. Carry Select t Adder The higher order bits a7 a6 a5 a4 and b7b6 b5 b4 are used as he sum with a carry in two 4-bit adders. IMPLEMENTATION OF HSA: The alternate approaches for designing High Speed Adders (HSA) have been designed in the literature he objective of [1]. 3. consider r an 8-bit adder that is split into two 4-bit groups. propagate signal Pi is the carry out of an ad dder with a carry input of ONE and the group generate Gi signal is the carry O.The design speeds up the addition of the e word by allowing the upper and lower portions of the sum to be calculated s that it requires an simultaneously.i+3). since the group the equation for the carry out of the group. The price paid is additional word adder. while the other adder does the same only it has a carry-in value of C=1. carry-in is automatically send to the next g The name “carry-skip” is due to the f fact that if the condition P(i. However. The carry-out bit C8 is also selected by b the MUX array. If all the pi signals within the group are pi = 1. the output from the tage output of AND gate is ORed with Ci+4 to produce a st Carry = Ci+4 + P(i. Adder calculates th of C=0.2 CARRY – SELECT ADDER The Carry Select Adder (CSL LA) divides the words to be added into blocks and forms tw wo sums for each block in parallel (one with a carry in of ZER RO and the other with a carry in of ONE) The carry out is computed using . Carry skip adder n the carry-out of As shown in the figure 5. This paper examines few of them bellow. while a then the result of C=0 adder are sent value of C4=1 selects the result of C= =1 adder for S7 S6 S5 S4. then the carry-in bit is Ci= 1.i+3) = Pi+3. adds them and de. if P(i. The upper 8-bits are computed plexer (MUX) is conditionally using two CSLAs. The name ‘carry-save’ arises from the fact that t we save the carry out words instead of using it immediatel ly to calculate the final sum.i+3) = 0. . Ci Figure 6.i+3) = 1. if P(i. [3]. This is a accomplished by using Carry-Propagate pi signals within a group of bits. the condition p. The full adder is used as 3:2 where it starts with bits from 3 bits words.P i+1.i+3). a set of multi iplexers and associated interconnect wiring. The e carry bit C4 from the first adder is used as the select signal to MUX. t third input with While it is usually associates the a carry in. 3. As a concrete example. Both sets of o results are used as inputs to an array of 2:1 MUXs. exist for the carry to bypass the entire group P(i. Pi+2. This speeds-up out of an adder with a carry input of ZERO ary for selection the computation of the carry signal necessa in the next block. Ci is true and then the carry y-in bit skips the block entirely.3. it could equally well be used as a “regular” 3 reduction network value. An n-bit carry save then has an output that is 2-bits wid adder can be build by using n separ rate adders. 3.3 CARRY – SAVE ADDE ER Carry – save adder are based on the e idea that a full adder Figure 5. t to the output.1 CARRY – SKIP ADDER Since the Cin-to-Cout represents the long gest path in the ripple-carry-adder an obvious attempt is to accelerate carry propagation through the adder. A multip then used to select the valid result. ve Adder Figure7. [4]. If C4 = 0.Carry Sav really has three inputs and produces two outputs as shown.Pi Using the individual propagate values. Carry-save adders are useful in i situations where we need to add more than two numb bers. The fig gure 6 shows the block diagram of CSA. Since the design automatically avoids the delay in the carry-out bits. The lowe er order bits a3 a2 a1 a0 and b3 b2 b1 b0 are fed into the 4-bit a adder to produce the sum bits S3 S2 S1S0 and a carry-out bit C4 as shown. then the group is determined by the value of Ci+4. then the group group of adders. The design beco omes viable if speed is more important than area consumptio on.

081 ns 15.642 ns Carry-select 24 22/768 16 3.806 ns 38. 2. The simulation helps to verify the design and the synthesis report gives the speed and area of the design.67 s 141820 KB 11.806 ns 38.326 ns 16.34 s 175948 KB 17. 6 Parameter XOR (1-bit) No.2i is used to simulate and synthesize the design.163 ns Carry-Save 31 10/768 3 3. The table 3.77 s 140796 KB 14.66 s 134356 KB 12 ns 11.774 ns 29.721ns 7. 3.623 ns 21.555 s 140796 KB 14. In this research. Finally.402 ns 26.No. 1. The comparison table is shown in bellow. 2.163 ns 23.4 RESULT AND DISCUSSIONS The design of high speed adders is necessary to increase the computation speed of ALU and it supports to design of high speed processor. 5 and Figure 8 shows synthesis report of 32 –bit adder. 16-bit adders: Table 4: synthesis report of 16-bit adders S. 4. 5.440 ns 9.067 ns 7. Xilinx ISE 9. The RTL code has been written in VHDL.859 ns 14.665 ns Carry-skip 64 42/960 27 4.824ns .824ns FPGA device xc3s500e-5-ft256 and captured the real time speed and area of the designs.The figure 8 represents the comparison chart by taking speed in MHz on Y axis and various adders on X axis.59 s 174988 KB 23. synthesis report of 16 – bit adder. 4.71 s 167716 KB 6. 5.721ns 7.623 ns 21.No. the hardware implementation of various adders has been done to analyze the speed and area. 3.842 ns Carry-select 48 51/768 20 3.859 ns 14.69 ns Carry-skip 32 21/960 15 4.103ns 1.68 s 174924 KB 23.103ns 1. 1. synthesis report of 8 – bit adder and speed comparison of various adders respectively.40 s 134356 KB 14.69 ns Carry-look ahead 32 18/960 18 3. 6 Parameter XOR (1-bit) No.067 ns 7. the VLSI implemented designs are targeted to the COMPARISON OF ADDERS: 32-bit adders: Table 3: synthesis report of 32-bit adders S.316 ns 5.665 ns Carry-look ahead 64 37/960 34 4. of Slices Levels of Logic CPU Processing Time Memory Usage Logic Delay Route Delay Total Delay Ripple carry 32 37/960 34 4. 4. of Slices Levels of Logic CPU Processing Time Memory Usage Logic Delay Route Delay Total Delay Ripple carry 16 18/960 18 3.855 ns Carry-Save 31 19/768 3 2.97s 133404 KB 6.

1995.2 8-bit adders: Table 5: Synthesis report of 8-bit adders S. San Fransisco. In this paper. MA.54 ns Carry-select 12 11/768 9 2. Oxford University Press. New York. Norwell. Patterson and John L. 1998.Rabaey. 2nd edition.Performance Microprocessor. Computer Design and Architecture. REFERENCES [1]Bruce Shriver and Bennett Smith. NJ. 4th Edition. Feldman and Charles T.No.8 25. Uyemura. IEEE Computer society Press. 3. Los Alamitos.254 ns 3. ripple carry adder.721ns 7. NJ. Oxford University Press.171 ns 4. MA. 16-bit adders and 32-bit adders. New York.286 ns 11. Digital Integrated Circuit Design. McGraw-Hill. 1996. Lowpower Digital VLSI Design. [2] James M. Norwell. [4] BehroozParhami. carry-skip adder.Bit adder 32-Bit adder Ripple carry Carry-look ahead Carry-skip Carry-select Carry-save Figure 8.032 ns 13. Speed (in MHz) comparison chart of adders 5.977 ns 6.824ns 100 80 60 40 20 0 8 . 1. MorganKoufmann Publishers. Computer Architecture. Hennessy. CONCLUSION The research article describes about the hardware implementation of high speed adders. 6 Parameter XOR (1-bit) No.44 s 139772 Kb 9. CMOS Logic Circuit Design. [7] AbdellatifBellaouar and Mohamed I. of Slices Levels of Logic CPU Processing Time Memory Usage Logic Delay Route Delay Total Delay Ripple carry 8 9/960 10 3. .945 s 134356 Kb 8. Kluwer Academic Publishers.8 37. New York. 1994. this paper concludes that the carry-save adder is the efficient adder in speed and area consumption. The Anatomy of a High. 2.4 127. Kluwer Academic Publishers.2i platform and their parameters are captured. Table 6: Speed & Area analysis for 32 – bit adder Adder Ripple Carry Adder Carry-look ahead adder Carry-skip adder Carry-select adder Carry-save adder Speed ( MHz) 25. A comprehensive. 1996.203 ns Carry-look ahead 16 9/960 10 3. carry –select adder and carry.save adeer have been simulated and synthesized on Xilinx ISE 9.203 ns Carry-skip 16 11/960 9 3.945 ns 15. From the table 5. 2000.171 ns 4.3.5. Finally. [8] William Stallings. Upper Saddle River. [9] John P. Upper Saddle River.922 ns Carry-Save 15 5/768 3 3.032 ns 13. Prentice Hall. Computer Arithmetic. CA. carry-look ahead adder.Bit adder 16 .103ns 1.8 Area ( XOR gate) 32 64 64 48 63 6.Elmasry. 5.2 33. [5] David A.453 s 139772 Kb 9. [3] Ken Martin. The analysis in table 6 for 32 – bit adder is shown below. Digital Integrated Circuits. Retter.70 133404KB 6. 1999. in depth treatment of the subject. 1998. [6] Jan M. Prentice Hall. 2000.44 s 140796 Kb 8. the various adders like full adder. the captured parameters like speed and area are compared for 8 –bit. 4. Computer Organization & Design.

Her areas of interest are Embedded System Design. 8. 1993. India. for her academic support. P). Digital System Design and Embedded System Design. PoojaKansliwalworkingfor herB. who has been the driving force behind this paper.[10] Neil H. EC Dept. MA. of Electronics and Communication Engineering.P).. India. AUTHORS BIOGRAPHY PrashantGurjarworkingfor hisB. GGITM. RashmiSolankiworkingfor herB. Dept. India.. NJ. Mahendra Vucha received his B. Dept. Mrs. 2nd edition. Bhopal (M.E degree at Gyan Ganga Institute of Technology and Management. HOD. of Electronics and communication Engineering. Hyderabad in 2007 and M. Analog Circuit design. Principles of CMOS VLSI Design. Weste and Kamran Eshraghian. Prentice Hall PTR. never seemed to lose faith that the paper would be eventually completed. His areas of interest are Embedded System Design and VLSI Technologies. Bhopal in 2009. . Modern VLSI Design. ACKNOWLEDGEMENT The authors would like to express my gratitude to the following people for their support in the work leading to this report: Dr. Mahendra Vucha. my classmate and friend. of Electronics and communication Engineering. of Electronics and communication Engineering. 1998. India. 2nd edition. AshutoshAgrawal. Dept. provided much inspiration to usthrough out of this paper. Mr. D degree at MANIT and also working as Asst. Bhopal (M. P). 7. Upper Saddle River. Prof in Gyan Ganga Institute of Tech & Mgmt. EC Dept. Bhopal (M. Tech degree in VLSI and Embedded System Design from MANIT. P). Bhopal. [11] Wayne Wolf. Bhopal (M. Dept. Principal.E degree at Gyan Ganga Institute of Technology and Management. Her areas of interest are Embedded System Design. His areas of interest are Hardware Software Co-Design.S. GGITM. professor. P.. &project guide. Tech in Electronics & Communication Engineering from JNTU. Venkataramu. Addision-Wesley.. VibhaTiwari. He is currently working for his Ph. Asst. Reading. India.E.E degree at Gyan Ganga Institute of Technology and Management.

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