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CompTIA A+ Lesson 5 -Understanding Motherboards bus system

T his night Lesson Topic is about Mother bus system f irst of all let we learn what is BUS . A bus is the path through which a device sends its data so that it can communicate with the CPU and/or other devices. For example, a PCI device, such as an audio card, will send its data through the PCI bus. Each device will have an access point to the bus using a particular kind of interf ace. T he word interface ref ers not only to the physical port the devices plug into, but to the electrical operating parameters and the communication f ormat as well. Typically, each bus has a uniquely shaped interf ace to prevent you f rom damaging your devices by plugging them into the wrong ports . BUS can be f ound in 2 common parts : Internal : T he internal bus, also known as internal data bus, memory bus, system bus or Front-Side-Bus, connects all the internal components of a computer, such as CPU and memory, to the motherboard. Internal data buses are also ref erred to as a local bus, because they are intended to connect to local devices. T his bus is typically rather quick and is independent of the rest of the computer operations. External bus : T he external bus, or expansion bus, is made up of the electronic pathways that connect the dif f erent external devices, such as printer etc., to the computer.

Common Motherboard Internal BUS : 1. Front Side Bus (FSB) & Back side BUS (BSB) 2. System & I/O BUS 3. AGP BUS 4. ISA & PCI BUS 5. USB BUS 6. Address bus 7. Control BUS Front side BUS (FSB ) : T he Front Side Bus is the interf ace between the CPU and the motherboard, specif ically the North Bridge/Memory Controller Hub

Back Side Bus (BSB): T he backside bus is the microprocessor bus that connects the CPU to a Level 2 cache. Typically, a backside bus runs at a f aster clock speed than the f rontside bus that connects the CPU to main memory. For example, the Pentium Pro microprocessor actually consists of two chips one contains the CPU and the primary cache, and the second contains the secondary cache. A backside bus connects the two chips at the same clock rate as the CPU itself (at least 200 MHz). In contrast, the f rontside bus runs at only a f raction of the CPU clock speed.

System & I/O BUS : On older computers, the local bus, which was the only bus, was used f or the CPU, RAM and I/O (input/output) components. All components on the local bus used the same clock speed. In the late 80s we saw the separation of the system bus f rom the I/O bus allowing them to run at dif f erent speeds. T he system bus (also called the f rontside bus, memory bus, local bus or host bus) is what connects the CPU to main memory on the motherboard. I/O buses are those that connect the CPU and RAM with all other components, and the I/O buses branch of f of the system bus. I/O buses operate on a speed which is lower than the system bus speed. PCs of f er several types of I/O buses which include the ISA bus, PCI bus, AGP bus and USB bus.

ISA & PCI BUS : Short f or Industry Standard Architecture bus, the ISA bus architecture was used in the IBM PC/XT and PC/AT. T he AT version of the bus is called the AT bus and became a de f acto industry standard. Starting in the early 90s, ISA began to be replaced by the PCI (Peripheral Component Interconnect) local bus architecture. T he PCI standard was developed by Intel Corp. On modern PCs, the PCI bus is the central (or main) I/O bus. Its used f or connecting adapters such as hard disks, sound cards, network cards and graphics cards (although now AGP is more common f or 3-D graphics). PCI is a 64-bit bus, though it is usually implemented as a 32-bit bus, and it can run at clock speeds of 33 or 66 MHz. At 32-bits and 33 MHz, it yields a throughput rate of 133 MBps (at 66 MHz 266 MBps). T he vast majority of todays PCs implement a PCI bus that runs at a maximum speed of 33 MHz.

AGP Bus : Short f or Accelerated Graphics Port, an interf ace specif ication developed by Intel Corporation. AGP is based on PCI, but is designed especially f or the throughput demands of 3-D graphics. Rather than using the PCI bus f or graphics data, AGP introduces a dedicated point-to-point channel so that the graphics controller can directly access main memory. T he AGP channel is 32-bits wide and runs at 66 MHz. T his translates into a total bandwidth of 266 MBps, as opposed to the PCI bandwidth of 133 MBps. AGP also supports optional f aster modes and allows 3-D textures to be stored in main memoryrather than video memory.

USB Bus :Short f or Universal Serial Bus, an external bus standard that supports data transf er rates of 12 Mbps. A single USB port can be used to connect up to 127 peripheral devices, such as mice, modems, and keyboards. USB also supports Plug-and-Playinstallation and hot plugging.

Address bus : is a computer bus (a series of lines connecting two or more devices) that is used to specif y a physical address. When a processor or DMA-enabled device needs to read or write to a memory location, it specif ies that memory location on the address bus (the value to be read or written is sent on the data bus). T he width of the address bus determines the amount of memory a system can address. For example, a system with a 32-bit address bus can address 232 (4,294,967,296) memory locations. If each memory address holds one byte, the addressable memory space is 4 GB. Control BUS : control bus is (part of ) a computer bus, used by CPUs f or communicating with other devices within the computer. While the address bus carries the inf ormation on which device the CPU is communicating with and the data bus carries the actual data being processed, the control bus carries commands f rom the CPU and returns status signals f rom the devices. For example if the data is being read or written to the device the appropriate line (read or write) will be active (logic zero).

Memory BUS : memory bus is the computer bus which connects the main memory to the memory controller in computer systems. Originally, general-purpose buses like VMEbus and the S-100 bus were used, but to reduce latency, modern memory buses are designed to connect directly to DRAM chips, and thus are designed by chip standards bodies such as JEDEC. Examples are the various generations of SDRAM, and serial point-to-point buses like SLDRAM and RDRAM. An exception is the Fully Buf f ered DIMM which, despite being caref ully designed to minimize the ef f ect, has been criticized f or its higher latency.

T he dif f erences between computer busses break down into these categories: Data width

Cycle rate Device management Type T he data width and cycle rate are used to determine the bandwidth, or the total amount of data that the bus can transmit. An 8-bit bus (1-byte data width) that operates at a cycle rate of 1,000 MHz (1,000,000 times per second) can transf er 8 Mbps (1 MBps). T he device-management specif ication indicates the maximum number of supported devices and the dif f iculty of conf iguring them. T here are two types of bus communications, serial and parallel. On a parallel bus, all devices have their own interf ace to the bus, which is the norm. Serial devices are tied together in, well, a series; the last one has to talk through the f irst one. T his can cause obvious perf ormance problems. T hese busses typically are used in conditions where data throughput isnt critical. Bus contention : in computer design, is an undesirable state of the bus in which more than one device on the bus attempts to place values on the bus at the same time. Most bus architectures require their devices f ollow an arbitration protocol caref ully designed to make the likelihood of contention negligible. However, when devices on the bus have logic errors, manuf acturing def ects or are driven beyond their design speeds, arbitration may break down and contention may result. Contention may also arise on systems which have a programmable memory mapping and when illegal values are written to the registers controlling the mapping. Contention can lead to erroneous operation, and in unusual cases, damage to the hardwaresuch as f using of the bus wiring.Bus contention is sometimes countered by buf f ering the output of memorymapped devices. However, it has been noted that high impedance f rom one device will still interf ere with the bus values of other devices. Currently, no standard solution exists f or data-bus contention between memory devices, such as EEPROM and SRAM. External Bus Interface , usually shortened to EBI, is a computer bus f or interf acing small peripheral devices like f lash memory with the processor. It is used to expand the internal bus of the processor to enable connection with external memories or other peripherals. EBI can be used to share I/O pins controlling memory devices that are connected to two dif f erent memory controllers. Use of EBI reduces the total number of system pins required causing the system cost to come down. EBI manuf acturers include Barco[1] and Freescale Semiconductor .