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Next Generation OP07 Ultralow Offset Voltage Operational Amplifier OP77

FEATURES
Outstanding gain linearity Ultrahigh gain, 5000 V/mV min Low VOS over temperature, 55 V max Excellent TCVOS, 0.3 V/C max High PSRR, 3 V/V max Low power consumption, 60 mW max Fits OP07, 725,108A/308A, 741 sockets Available in die form

PIN CONNECTIONS
VOS TRIM 1 IN 2 +IN 3 V 4

OP77

8 7 6

VOS TRIM V+ OUT


00320-001

TOP VIEW 5 NC (Not to Scale)

NC = NO CONNECT

Figure 1. 8-Pin Hermetic DIP_Q-8 (Z Suffix)

VOS TRIM VOS TRIM


1 8

V+
7

OP77

IN

OUT

5 4

+IN

NC

4V (CASE)
00320-002

TOP VIEW (Not to Scale) NC = NO CONNECT

Figure 2. TO-99 (J Suffix)

GENERAL DESCRIPTION
The OP77 significantly advances the state-of-the-art in precision op amps. The outstanding gain of 10,000,000 or more for the OP77 is maintained over the full 10 V output range. This exceptional gain-linearity eliminates incorrectable system nonlinearities common in previous monolithic op amps and provides superior performance in high closed-loop gain applications. Low initial VOS drift and rapid stabilization time, combined with only 50 mW of power consumption, are significant improvements over previous designs. These characteristics, plus the exceptional TCVOS of 0.3 V/C maximum and the low VOS of 25 V maximum, eliminates the need for VOS adjustment and increases system accuracy over temperature. A PSRR of 3 V/V (110 dB) and CMRR of 1.0 V/V maximum virtually eliminate errors caused by power supply drifts and common-mode signals. This combination of outstanding characteristics makes the OP77 ideally suited for high resolution instrumentation and other tight error budget systems.

Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 20022010 Analog Devices, Inc. All rights reserved.

OP77 TABLE OF CONTENTS


Features .............................................................................................. 1 Pin Connections ............................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Electrical Specifications ............................................................... 3 Wafer Test Limits .......................................................................... 4 Typical Electrical Characteristics ............................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Resistance .......................................................................6 ESD Caution...................................................................................6 Typical Performance Characteristics ..............................................7 Test Circuits ..................................................................................... 10 Applications..................................................................................... 11 Precision Current Sinks ............................................................. 12 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 16

REVISION HISTORY
4/10Rev. D to Rev. E Removed Figure 33 and Two Subsequent Paragraphs ............... 12 6/09Rev. C to Rev. D Changes to Figure 1 and Figure 2 ................................................... 1 Changes to Table 1 ............................................................................ 3 Removed Endnote 1 and Endnote 2 in Table 3 ............................ 4 Changes to Figure 16 ........................................................................ 9 Changes to Figure 31 and Figure 32 ............................................. 12 Changes to Figure 38 ...................................................................... 14 Moved Figure 39 ............................................................................. 14 10/02Rev. B to Rev. C Edits to Specifications ...................................................................... 2 Figure 2 Caption Changed ............................................................ 10 Figure 3 Caption Changed ............................................................ 10 Edits to Figure 10 ............................................................................ 11 Updated Outline Dimensions ....................................................... 15 2/02Rev. A to Rev. B Remove 8-Lead SO PIN Connection Diagrams ........................... 1 Changes to Absolute Maximum Rating......................................... 2 Remove OP77B column from Specifications ................................ 2 Remove OP77B column from Electrical Characteristics ........ 3, 5 Remove OP77G column from Wafer Test Limits......................... 6 Remove OP77G column from Typical Electrical Characteristics6

Rev. E | Page 2 of 16

OP77
ELECTRICAL SPECIFICATIONS
@ VS = 15 V, TA = 25C, unless otherwise noted. Table 1.
Parameter INPUT OFFSET VOLTAGE LONG-TERM STABILITY 1 INPUT OFFSET CURRENT INPUT BIAS CURRENT INPUT NOISE VOLTAGE 2 INPUT NOISE VOLTAGE DENSITY Symbol VOS VOS/time IOS IB enp-p en Conditions Min OP77E Typ 10 0.3 0.3 +1.2 0.35 10.3 10.0 9.6 14 0.32 0.14 0.12 45 200 14 0.1 0.7 12,000 14.0 13.0 12.5 0.3 0.6 60 50 3.5 3 Max 25 1.5 +2.0 0.6 18.0 13.0 11.0 30 0.80 0.23 0.17 Min OP77F Typ 20 0.4 0.3 +1.2 0.38 10.5 10.2 9.8 15 0.35 0.15 0.13 45 200 14 0.1 0.7 6000 14.0 13.0 12.5 0.3 0.6 60 50 3.5 3 Max 60 2.8 +2.8 0.65 20.0 13.5 11.5 35 0.90 0.27 0.18 Unit V V/Mo nA nA Vp-p nV/Hz

0.2 0.1 Hz to 10 Hz fO = 10 Hz fO = 100 Hz2 fO = 1000 Hz 0.1 Hz to 10 Hz fO = 10 Hz fO = 100 Hz2 fO = 1000 Hz 26 13 VCM = 13 V VS = 3 V to 18 V RL 2 k VO = 10 V RL 10 k RL 2 k RL 1 k RL 2 k AVCL + 1 VS = 15 V, no load VS = 3 V, no load Rp = 20 kn

0.2

INPUT NOISE CURRENT2 INPUT NOISE CURRENT DENSITY

inp-p in

pAp-p pAHz

INPUT RESISTANCE Differential Mode 3 Common Mode INPUT VOLTAGE RANGE COMMON-MODE REJECTION RATIO POWER SUPPLY REJECTION RATIO LARGE-SIGNAL VOLTAGE GAIN OUTPUT VOLTAGE SWING

RIN RINCM IVR CMRR PSRR AVO VO

18.5 13 1.0 3.0 2000 13.5 12.5 12.0 0.1 0.4 60 4.5

1.6 3.0

5000 13.5 12.5 12.0 0.1 0.4

M G V V/V V/V V/mV V

SLEW RATE2 CLOSED-LOOP BANDWIDTH2 OPEN-LOOP OUTPUT RESISTANCE POWER CONSUMPTION OFFSET ADJUSTMENT RANGE
1

SR BW RO Pd

60 4.5

V/s MHz mW mV

Long-term input offset voltage stability refers to the averaged trend line of VOS vs. time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 V. 2 Sample tested. 3 Guaranteed by design.

Rev. E | Page 3 of 16

OP77
@ VS = 15 V, 25C TA +85C for OP77FJ and OP77E/OP77F, unless otherwise noted. Table 2.
Parameter INPUT OFFSET VOLTAGE AVERAGE INPUT OFFSET VOLTAGE DRIFT 1 INPUT OFFSET CURRENT AVERAGE INPUT OFFSET CURRENT DRIFT 2 INPUT BIAS CURRENT AVERAGE INPUT BIAS CURRENT DRIFT2 INPUT VOLTAGE RANGE COMMON-MODE REJECTION RATIO POWER SUPPLY REJECTION RATIO LARGE-SIGNAL VOLTAGE GAIN OUTPUT VOLTAGE SWING POWER CONSUMPTION
1 2

Symbol VOS TCVOS IOS TCIOS IB TCIB IVR CMRR PSRR AVO VO Pd

Conditions

VCM = 13 V VS = 3 V to 18 V RL 2 k VO = 10 V RL 2 k VS = 15 V, no load

OP77E Typ 10 0.1 0.5 1.5 0.2 +2.4 8 13.0 13.5 0.1 1.0 2000 6000 Min 12 13.0 60

Max 45 0.3 2.2 4.0 +4.0 40 1.0 3.0

OP77F Typ 20 0.2 0.5 1.5 0.2 +2.4 15 13.0 13.5 0.1 1.0 1000 4000 Min 12 13.0 60

Max 100 0.6 4.5 85 +6.0 60 3.0 5.0

Unit V V/C nA pA/C nA pA/C V pV/V V/V V/mV V mW

75

75

OP77E: TCVOS is 100% tested on J and Z packages. Guaranteed by end-point limits.

WAFER TEST LIMITS


@ VS = 15 V, TA = 25C, for OP77NBC devices, unless otherwise noted. Table 3.
Parameter INPUT OFFSET VOLTAGE INPUT OFFSET CURRENT INPUT BIAS CURRENT INPUT RESISTANCE Differential Mode INPUT VOLTAGE RANGE COMMON-MODE REJECTION RATIO POWER SUPPLY REJECTION RATIO OUTPUT VOLTAGE SWING Symbol VOS IOS IB RIN IVR CMRR PSRR VO Conditions OP77NBC Limit 40 2.0 2 26 13 1 3 13.5 12.5 12.0 2000 30 60 Unit V max nA max nA max M min V min V/V max V/V max V min

LARGE-SIGNAL VOLTAGE GAIN DIFFERENTIAL INPUT VOLTAGE POWER CONSUMPTION

AVO

VCM = 13 V VS = 3 V to 18 V RL = 10 k RL = 2 k RL = 1 k RL = 2 k VO = 10 V VO = 0 V

V/mV min V max mW max

Pd

Rev. E | Page 4 of 16

OP77
TYPICAL ELECTRICAL CHARACTERISTICS
@ VS = 15 V, TA = 25C, unless otherwise noted. Table 4.
Parameter AVERAGE INPUT OFFSET VOLTAGE DRIFT NULLED INPUT OFFSET VOLTAGE DRIFT AVERAGE INPUT OFFSET CURRENT DRIFT SLEW RATE BANDWIDTH Symbol TCVOS TCVOSn TCIOS SR BW Conditions RS = 50 RS = 50 , RP = 20 k RL 2 k AVCL + 1 OP77NBC Limit 0.1 0.1 0.5 0.3 0.6 Unit V/C V/C pA/C V/s MHz

Rev. E | Page 5 of 16

OP77 ABSOLUTE MAXIMUM RATINGS


Table 5.
Parameter Supply Voltage Differential Input Voltage Input Voltage2 Output Short-Circuit Duration Storage Temperature Range Operating Temperature Range Junction Temperature (TJ) Lead Temperature (Soldering, 60 sec)
1

Rating 22 V 30 V 22 V Indefinite 65C to +150C 25C to +85C 65C to +150C 300C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE
Table 6.
Package Type 8-Pin TO-99 H-08 (J Suffix) 8-Lead Hermetic CERDIP Q-8 (Z Suffix)
1

Absolute Maximum Ratings apply to both dice and packaged parts, unless otherwise noted. 2 For supply voltages less than 22 V, the absolute maximum input voltage is equal to the supply voltage.

JA1 150 148

JC 18 16

Unit C/W C/W

JA is specified for worst-case mounting conditions, i.e., JA is specified for a device in socket for the TO-99 and CERDIP packages.

ESD CAUTION

Rev. E | Page 6 of 16

OP77 TYPICAL PERFORMANCE CHARACTERISTICS


2 VS = 15V TA = 25C RL = 10k 1

30 J, Z PACKAGES +0.3V/C

CHANGE IN OFFSET VOLTAGE (V)

20

INPUT VOLTAGE (V) (NULLED TO 0V @ VOUT = 0V)

10

S.D.

MEAN

10

20 0.3V/C

00320-004

0 OUTPUT VOLTAGE (V)

10

35

15

5 25 45 65 TEMPERATURE (C)

85

105

125

Figure 3. Gain Linearity (Input Voltage vs. Output Voltage)


25 4 VS = 15V 20

Figure 6. Untrimmed Offset Voltage vs. Temperature


VS = 15V TA = 25C

CHANGE IN INPUT OFFSET VOLTAGE (V)

3 2 1 0 1 2 3

OPEN-LOOP GAIN (V/V)

15

10

00320-005

35

15

5 25 45 65 TEMPERATURE (C)

85

105

125

0.5 1.0 1.5 2.0 2.5 3.0 TIME AFTER POWER SUPPLY TURN-ON (Minutes)

3.5

Figure 4. Open-Loop Gain vs. Temperature


16 TA = 25C RL = 2k
25 30

Figure 7. Warm-Up Drift

VS = 15V

ABSOLUTE CHANGE IN INPUT OFFSET VOLTAGE (V)

OPEN-LOOP GAIN (V/V)

12

DEVICE IMMERSED IN 70C OIL BATH (20 UNITS) 20

15 MAXIMUM

10

AVERAGE 5 MIMIMUM

00320-006

5 10 15 POWER SUPPLY VOLTAGE (V)

20

10

20 30 40 TIME (Seconds)

50

60

70

Figure 5. Open-Loop Gain vs. Power Supply Voltage

Figure 8. Offset Voltage Change Due to Thermal Shock

Rev. E | Page 7 of 16

00320-009

0 10

00320-008

0 55

00320-007

2 10

30 55

OP77
100 VS = 15V TA = 25C 80 130 TA = 25C 120

CLOSED-LOOP GAIN (dB)

110 60

PSRR (dB)

100

40

90 80

20

70

00320-010

100

1k

10k 100k FREQUENCY (Hz)

1M

10M

10 100 FREQUENCY (Hz)

1k

10k

Figure 9. Closed-Loop Response for Various Gain Configurations


160 140 120 100 80 60 40 20
00320-011

Figure 12. PSRR vs. Frequency


4 VS = 15V

0 VS = 15V TA = 25C
INPUT BIAS CURRENT (nA)

OPEN-LOOP GAIN (dB)

45

PHASE (Degrees)

90

135

0.1

10 100 1k FREQUENCY (Hz)

10k

100k

50

25

0 25 50 TEMPERATURE (C)

75

100

125

Figure 10. Open-Loop Gain/Phase Response


150 TA = 25C 140
INPUT OFFSET CURRENT (nA)
1.5 2.0

Figure 13. Input Bias Current vs. Temperature


VS = 15V

130 CMMR (dB) 120

1.0

110 100 90

0.5

10

100 1k FREQUENCY (Hz)

10k

100k

00320-012

50

25

0 25 50 TEMPERATURE (C)

75

100

125

Figure 11. CMRR vs. Frequency

Figure 14. Input Offset Current vs. Temperature

Rev. E | Page 8 of 16

00320-015

80

0 75

00320-014

0 0.01

180 1M

0 75

00320-013

20 10

60 0.1

OP77
10 VS = 15V TA = 25C
POWER CONSUMPTION (mW)

100 TA = 25C

RMS NOISE (mV)

10

00320-016

1k FREQUENCY (Hz)

10k

100k

10 20 30 TOTAL SUPPLY VOLTAGE V+ TO V (V)

40

Figure 15. Input Wideband Noise vs. Bandwidth (0.1 Hz to Frequency Indicated)

Figure 18. Power Consumption vs. Power Supply

1k

RS1 = RS2 = 200k THERMAL NOISE OF SOURCE RESISTORS INCLUDED

20 VS = 15V TA = 25C VIN = 10mV 15


MAXIMUM OUTPUT (V)

INPUT NOISE VOLTAGE (nV/ Hz)

POSITIVE SWING NEGATIVE SWING

EXCLUDED 100

10

10

RS = 0

5
VS = 15V TA = 25C
00320-017

10 FREQUENCY (Hz)

100

1k

1k LOAD RESISTANCE TO GROUND ()

10k

Figure 16. Total Input Noise Voltage vs. Frequency

Figure 19. Maximum Output Voltage vs. Load Resistance

32 28

40
OUTPUT SHORT-CIRCUIT CURRENT (mA)
VS = 15V TA = 25C

VS = 15V TA = 25C 35

PEAK-TO-PEAK AMPLITUDE (V)

24 20 16 12 8 4
00320-018

30

25

20

10k 100k FREQUENCY (Hz)

1M

1 2 3 TIME FROM OUTPUT BEING SHORTENED (Minutes)

Figure 17. Maximum Output Swing vs. Frequency

Figure 20. Output Short-Circuit Current vs. Time

Rev. E | Page 9 of 16

00320-021

0 1k

15

00320-020

0 100

00320-019

0.1 100

OP77 TEST CIRCUITS


200k 50

TYPICAL PRECISION OP AMP 10k 100k 1M VX 10 VX RL 10V 0V +10V VY

OP77
VOS = VO 4000

VO
00320-022

VIN = 10V

Figure 21. Typical Offset Voltage Test Circuit

2.5M V+ 100 100 2 3 7 3.3k

AVO 650V/mV RL = 2k NOTES 1. GAIN NOT CONSISTANT. CAUSES NONLINEAR ERRORS. 2. AVO SPEC IS ONLY PART OF THE SOLUTION. 3. CHECK SPECIFICATION TABLE 1 AND TABLE 2 FOR PERFORMANCE.
OUTPUT 4.7F (10Hz FILTER) VO 25,000
00320-023

OP77
4 V

Figure 25. Open-Loop Gain Linearity

INPUT REFERRED NOISE =

Figure 22. Typical Low-Frequency Noise Test Circuit

20k INPUT + 2 3 1 8

V+

Actual open-loop voltage gain can vary greatly at various output voltages. All automated testers use endpoint testing and therefore only show the average gain. This causes errors in high closedloop gain circuits. Because this is difficult for manufacturers to test, users should make their own evaluations. This simple test circuit makes it easy. An ideal op amp would show a horizontal scope trace.
VY

OP77
4 V

7 6

OUTPUT
00320-024

Figure 23. Optional Offset Nulling Circuit


10V 0V +10V VX

100k +18V +
00320-027

10F

10

Figure 26. Output Gain Linearity Trace


2 3 10k 10k 7 0.1F 6

OP77
4 10

0.1F

This is the output gain linearity trace for the new OP77. The output trace is virtually horizontal at all points, assuring extremely high gain accuracy. The average open-loop gain is truly impressiveapproximately 10,000,000.
00320-025

10F 18V

NOTES *1 PER BOARD

Figure 24. Burn-In Circuit

Rev. E | Page 10 of 16

00320-026

OP77 APPLICATIONS
R2 1M +15V 0.1F R1 1k 2 3 R3 1k 7

R3 +15V R1 R2 2 3

VIN
6

2N2222

OP77E

OP77

6 2N2907 R5 R4 15V IOUT < 100mA


00320-031

4 0.1F
00320-028

R4 1M 15V

IOUT = VIN

( R1R3 R5 )

Figure 27. Precision High-Gain Differential Amplifier

GIVEN R3 = R4 + R5, R1 = R2

The high gain, gain linearity, CMRR, and low TCVOS of the OP77 make it possible to obtain performance not previously available in single-stage, very high-gain amplifier applications.

Figure 30. 100 mA Current Source

These current sources can supply both positive and negative current into a grounded load. Note that

R1 R3 must equal . In this example, with a R2 R4 10 mV differential signal, the maximum errors are as listed in Table 7.
For best CMR, Table 7. Maximum Errors
Type Common-Mode Voltage Gain Linearity, Worst Case TCVOS TCIOS
RF 10F +15V 0.1F RS INPUT 2 3 7

R4 + 1 R5 R2 ZO = R5 + R 4 R3 R2 R1
R5 + R 4 R2

Amount 0.01%/V 0.02% 0.003%/C 0.008%/C

And that for ZO to be infinite

must =

R3 R1

OP77

100

OUTPUT CLOAD
00320-029

4 0.1F

15V

Figure 28. Isolating Large Capacitive Loads

This circuit reduces maximum slew rate but allows driving capacitive loads of any size without instability. Because the boon resistor is inside the feedback loop, its effect on output impedance is reduced to insignificance by the high open-loop gain of the OP77.
R3 1k R1 100k

VIN

2 3

OP77
R4 990

IOUT < 15mA


00320-030

R2 100k

R5 10

Figure 29. Basic Current Source


Rev. E | Page 11 of 16

OP77
PRECISION CURRENT SINKS
V+ RL IO VIN IO = VIN R1 VIN > 0V FULL SCALE OF 1V. IO = 1A/V
R1

OP77
VIN

200 IRF520 IO = IO RL V VIN R1 VIN > 0V

OP77

200 IRF520

00320-032

R1 1 1W

Figure 32. Positive Current Source

Figure 31. Positive Current Sink

The simple high-current sinks, shown Figure 31 and Figure 32, require the load to float between the power supply and the sink. In these circuits, the high gain, high CMRR, and low TCVOS of the OP77 ensure high accuracy. The high gain and low TCVOS ensure accurate operation with inputs from microvolts to volts. In Figure 33, the signal always appears as a common-mode signal to the op amps. The OP77EZ CMRR of 1 V/V ensures errors of less than 2 ppm.

1k +15V +15V 0.1F 2 3 7 C1 30pF D1 1N4148 D2 6 2N4393 R3 2k 3 2

1k

0.1F 7

OP77E

OP77E

VOUT 0 < VOUT < 10V

VIN

15V 15V

Figure 33. Precision Absolute Value Amplifier

15V + 2 10F 2 2

REF-01
VO 4 6

REF-01
VO 4 6

REF-01
VO 4 6

100

OP77

VOUT

100 100 0.1F


00320-036

Figure 34. Low Noise Precision Reference

Rev. E | Page 12 of 16

00320-035

4 0.1F

4 0.1F

00320-033

OP77
Figure 34 relies upon low TCVOS of the OP77 and noise combined with very high CMRR to provide precision buffering of the averaged REF-01 voltage outputs. In Figure 35, CH must be of polystyrene, Teflon*, or polyethylene to minimize dielectric absorption and leakage. The droop rate is determined by the size of CH and the bias current of the AD820.
*Teflon is a registered trademark of the Dupont Company
1k

+15V 0.1F 2 1k 3 7

1N4148

+15V 0.1F 2 7

OP77

2N930 1k 3 CH RESET

VIN

AD820

VOUT

4 0.1F

4 0.1F

15V

15V

Figure 35. Precision Positive Peak Detector

Rev. E | Page 13 of 16

00320-037

OP77
CC
+15V 0.1F

+15V 0.1F RS 1k VTH VIN R1 2k 2 3 7

RF 100k

2 VIN VO

6 5

Ra 50k 1.5k Rb1

Rc

OP77

D1 1N4148 VOUT

TRIM

REF-02
TEMP GND 4 3

4 0.1F
00320-038

OP77
0.1F

VOUT

Rbp 15V
00320-039

15V

Figure 36. Precision Threshold Detector/Amplifier

Figure 37. Precision Temperature Sensor

When VIN < VTH, amplifier output swings negative, reversing the biasing diode D1. VO = VTH if RL= when VIN > VTH, the loop closes,

Table 8. Resistor Values


TCVOUT Slope (S) Temperature Range Output Voltage Range Zero-Scale Ra (1% Resistor) Rb1 (1% Resistor) Rbp (Potentiometer) Rc (1% Resistor) 10 mV/C 55C to +125C 0.55 V to +1.25 V 0 V @ 0C 9.09 k 1.5 k 200 5.11 k 100 mV/C 55C to +125C 5.5 V to +12.5V 0 V @ 0C 15 k 1.82 k 500 84.5 k 10 mV/F 67F to +257C 0.67 V to +2.57V 0 V @ 0F 7.5 k 1.21 k 200 8.25 k

RF VO = VTH + (VIN VTH ) 1 + R S


CC is selected to smooth the response of the loop.

7 V+ R2A1 R1A (OPTIONAL NULL) 1 8 R2B1 C1 R1B Q9 Q7 Q5 NONINVERTING 3 INPUT INVERTING 2 INPUT R3 Q1 R4 Q21 Q22 Q23 Q24 Q2 Q3 Q6 Q8 Q4 Q27 Q26 Q25 Q14 4 V
1R2A AND

R7 Q19 Q10 Q11 Q12 C3 R5 Q15 Q18 R6 R8


00320-003

R9 Q17 Q16 R10 Q20

6 OUTPUT

C2

Q13

R2B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY.

Figure 38. Simplified Schematic

Rev. E | Page 14 of 16

OP77 OUTLINE DIMENSIONS


0.005 (0.13) MIN
8

0.055 (1.40) MAX


5

0.310 (7.87) 0.220 (5.59)


1 4

0.100 (2.54) BSC 0.405 (10.29) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING PLANE 15 0 0.015 (0.38) 0.008 (0.20) 0.320 (8.13) 0.290 (7.37)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 39. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8) Dimensions shown in inches and (millimeters)

REFERENCE PLANE 0.5000 (12.70) MIN 0.2500 (6.35) MIN 0.0500 (1.27) MAX

0.1850 (4.70) 0.1650 (4.19)

0.1000 (2.54) BSC 5

0.1600 (4.06) 0.1400 (3.56) 6 7

0.3700 (9.40) 0.3350 (8.51)

0.3350 (8.51) 0.3050 (7.75)

4 0.2000 (5.08) BSC 3 2 0.0190 (0.48) 0.0160 (0.41) 0.0210 (0.53) 0.0160 (0.41) BASE & SEATING PLANE 0.1000 (2.54) BSC 1

0.0450 (1.14) 0.0270 (0.69)

0.0400 (1.02) MAX 0.0400 (1.02) 0.0100 (0.25)

0.0340 (0.86) 0.0280 (0.71)


45 BSC

COMPLIANT TO JEDEC STANDARDS MO-002-AK CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 40. 8-Pin Metal Header [TO-99] (H-08) Dimensions shown in inches and (millimeters)

Rev. E | Page 15 of 16

022306-A

OP77
ORDERING GUIDE
Model 1 OP77FJ OP77FJZ OP77EZ OP77FZ OP77NBC
1

Temperature Range 25C to +85C 25C to +85C 25C to +85C 25C to +85C

Package Description 8-Pin Metal Header [TO-99] 8-Pin Metal Header [TO-99] 8-Lead Ceramic Dual In-Line Package [CERDIP] 8-Lead Ceramic Dual In-Line Package [CERDIP] Die

Package Option H-08 (J Suffix) H-08 (J Suffix) Q-8 (Z Suffix) Q-8 (Z Suffix)

Z = RoHS Compliant Part.

20022010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00320-0-4/10(E)

Rev. E | Page 16 of 16