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design

Edited by Bill Travis and Anne Watson Swager


ideas
Dual-voltage supply powers SIM card
Larry Suppan, Maxim Integrated Products, Sunnyvale, CA
lobal-system-for-mobile-com-

G
L1
munication phones have a 10 mH
Figure 1 INPUT
subscriber-identification 1.8 TO 11V
module (SIM) that allows local wireless + C
1
100 mF IN LX
providers to recognize the user and his or
her billing information. Although most PS
+ C2
SIMs are changing to 3V operation, they 100 mF
also accommodate 5V as well during the
transition. IC1 in Figure 1 combines a ON IC1
9 3 OR
OFF ONA OUT 5V
step-up dc/dc converter with a linear reg- OFF ONB
MAXIM R1
MAX1672 + C4
ulator, allowing it to regulate up or down ON 5
3/5 300k
4.7 mF
5V
for a range of input voltages. It offers 3V
6
PGI FB
hardware-selectable fixed outputs of 3.3 0.8A ILIM
R2
0.5A 100k
and 5V; however, 3.3V is out of spec for
REF PG0
a 3V SIM card. With properly chosen
C3
R1/R2/R3 values, you can switch the reg- 0.1 mF PGND GND R3
470k/150k
ulated output between 3 and 5V (or any
other two outputs within the allowed
range) by applying digital control to the
power-good input (PGI). The power-
good output (PGO), the output of an in- You can obtain a regulated 3 or 5V output, according to digital control applied to the power-good
ternal comparator, then changes the IC’s input (PGI).
feedback by grounding the node between
R2 and R3. If the power-good com-
Figure 2
parator is in use, you can imple- L1
ment the digital control using the 3/5 in- 10 mH
INPUT
put and an external MOSFET (Figure 2). 1.8 TO 11V

(DI #2468) C1 + R3
IN LX
100 mF 6
PGI
To Vote For This Design, PS
R4 + C2
Circle No. 315 100 mF

Dual-voltage supply powers SIM card ........113 ON OUT


9 3 OR
OFF ONA IC1
MAXIM + C4 5V
Design formulas simplify classic OFF ONB R1 R5
ON MAX1672 300k 1M 4.7 mF
V/I converter ......................................................114 3V
5
3/5 7 LOW-BATTERY-
5V PG0 DETECTOR
Rail-to-rail op amp provides R2
ILIM OUTPUT
biasing in RF amp ............................................114 OUTPUT LEVELS; 100k
10
NOT LOGIC LEVELS REF FB
Circuit multiplexes automotive sensors ......116
C3 R2 Q1
PGND GND
0.1 mF 2N7002
Analog switch acts as dc/dc converter........118 100k

Circuit provides message


on disabled phone line ..................................120
Optocoupler isolates shift registers..............122
Tack a log taper onto a digital
potentiometer....................................................124 This circuit provides the same outputs as the circuit in Figure 1 without tying up the internal
power-good comparator.

www.ednmag.com January 20, 2000 | edn 113


design
ideas
Design formulas simplify classic V/I converter
Dudley Nye, Nye Engineering Co, Fort Lauderdale, FL
igure 1 shows a classic voltage-to- determine the unselected resistor after

F current(V/I) converter. You can se-


lect the resistor values such that the
output current in the load, RL, varies only
substituting the applicable terms
from Equation 1. For example,
you can solve Equation 1 for R2 when
Figure 1 R2

with the input voltage, VIN, and is inde- IL520 mA, R15100 kV, RX50.1 kV, and R1
+
pendent of RL. The circuit is widely used VIN54V yields R2549.9 kV. Now, let RX

in industrial instruments for supplying R45100 kV and, with Equation 2, solve _ IL

a 4- to 20-mA signal. The circuit has its for R3 as follows: R35(49.9 kV10.1 RL

limitations, however, because the resistor kV)550 kV. This example configures a R3

values must be quite accurate to obtain a design for the popular current source of
true current source. The literature de- 4 to 20 mA. In a second example, if RX
scribing the circuit provides design meth- changes from 100 to 400V, the feedback Design formulas make this classic V/I converter
ods that are for special cases or are for ap- changes fourfold, and you would expect easy to use.
proximate designs. This Design Idea gives that the output current would change
two simple design formulas you can use fourfold, to 1 to 5 mA. You can check the second example above results in the fol-
to determine the component values that result by substituting in the general for- lowing expression:
produce a true current source. It also pro- mula for the output current: VIN
vides a general formula for the output IL = 75.25 . (4)
current, IL, for any selection of resistor IL = VIN (KR 2 + R X ) / 0 .06 R L + 59.96
values, not just the constant-current se-    R1 + R 2  With RL50.2 kV and VIN54V, IL5
lection. R L R1 + R 2 + R X  1R1 • 5.019 mA. Then, with VIN50.8V, IL5
For a true current output, IL, as a func-    R2  1.003 mA. Thus, after changing the feed-
tion of the input voltage, VIN, you must (3) back resistor by 4-to-1, you still have cur-
 KR 2 + R X   
satisfy the following two equations:    + R X (R1 + R 2 ) , rents close to the 1- to 5-mA standard.
 V  R   R2    Note also that IL55.02 mA when RL50V;
IL =  IN   2 + 1 . (1) thus, the circuit is still almost a perfect
 R1   R X  R
where K = 1 + 3 . current source. This result is unique, as
R4 you can convert from 4 to 20 ma to 1 to
R 
R 3 = (R 2 + R X ) 4  . (2) When the complete coefficient (the 5 mA by changing only one resistor. You
 R1  terms inside the square brackets) of RL can configure the less used standard of 10
In Equation 1, you can arbitrarily se- equals zero, a true current source results, to 50 mA by making RX5100/2.5540V.
lect any four of the terms and then de- and equations 1 and 2 are valid. Note (DI #2471)
termine the fifth term by solving the re- that substituting the values from the first
sulting equation. In Equation 2, you can example above forces the coefficient to To Vote For This Design,
arbitrarily select either R3 or R4 and then zero. Substituting the values from the Circle No. 316

Rail-to-rail op amp provides biasing in RF amp


Frank Cox, Linear Technology Corp, Milpitas, CA
t is often useful to monitor the dc output. Inductors at both the input and have an inverting gain of 13 dB; the result

I level of an RF signal. However, most


RF systems use capacitive coupling;
thus, the dc information is lost. The cir-
the output of the op amp isolate the am-
plifier from the RF signal. The isolation
is good practice, because frequencies
is a total gain of approximately 26 dB and
a noninverted signal. IC1 and IC2 have a
3-dB bandwidth of approximately 2
cuit in Figure 1 is an RF amplifier com- higher than the bandwidth of the op amp GHz. The 1.5-nF blocking capacitors set
prising two monolithic microwave inte- can undergo rectification in the amplifi- the low-frequency cutoff at 2 MHz.
grated circuits (MMICs), IC1 and IC2, er’s input stages, thereby introducing off- IC1 and IC2 have a 1-dB compression
and a quad rail-to-rail op amp (IC3, an set. MMICs IC1 and IC2 are Hewlett- point of 4 dBm, or 1V p-p, into 50V, al-
LT1633). IC3A restores the dc level at the Packard HP MSA-0785 devices, which lowing for an input level as high as 18 mV
114 edn | January 20, 2000 www.ednmag.com
design
ideas
rms. The maximum output current of 5V
IC3A, typically 40 mA with a sin- 5V
Figure 1
gle 5V supply, limits the dc level 5.1
5V 5.1 5V
on the output to 2V into 50V. The out-
put saturation (low) voltage of the
2N3906 2 2N3906
LT1633, typically 40 mV, sets the mini- 2 IC3C
226 IC3B 226 0.1 mF
0.1 mF 1
4 LT1633
mum pedestal voltage. IC1 and IC2 use 1
4 LT1633
+
+
constant-current bias sources to stabilize
10k 10k
their gain with respect to temperature. 10 nF
Two other sections of the quad op amp, 220 mH
220 mH 10 nF
IC3B and IC3C, form active 22-mA current 1.5 nF IC1 IC2 1.5 nF
sources. You can make the voltage di- VIN HP MSA- HP MSA- VOUT
viders on the noninverting inputs of IC3B 0785
1.5 nF
0785

and IC3C adjustable to trim the gain of 3.9 mH 3.9 mH


the RF amplifier. The rail-to-rail inputs +
of IC3 allow the circuit to operate to with- 1
IC3A
50 4 LT1633
in 110 mV of the positive rail. (DI #2467) 2
1k

To Vote For This Design, A simple op-amp-follower circuit with the aid of inductive blocking restores the dc level of an RF
Circle No. 317 signal.

Circuit multiplexes automotive sensors


Adil Ansari, Delphi-Delco Electronics, Kokomo, IN
ften, a mC limits the number of in- hicle- and engine-speed sensors. The cir- by sharing one input-capture line of the

O put-capture lines to accommodate


the various types of automotive
sensors with pulsed outputs, such as ve-
cuit in Figure 1 uses discrete components
to multiplex two sensors with open-col-
lector outputs into a single output, there-
mC. The mC selects the sensor whose out-
put you will measure. You can apply this
approach to sensors whose outputs are

12V
C1
0.1 mF
Figure 1

R1 R2 R3 R4
1k 1k 1k 1k

MUXED_OUT
D1 Q1B
R5 3 5 R6
SENSOR 1 1N4148 MPQ3906 SENSOR 2
1k 1k
1 2 2 6 2 1
Q1A
MPQ3906 12V D2
12V 1 1N4148
7

1 Q1D
R8 8 R7 R9
D3
1k 1k 14 MPQ3906 R11 1k
Q1C 5.1V 1k
9 13
MPQ3906 2
R10
Q2 1k Q3
10 12
BS170 BS170
SELECT
12V 12V
R12
FROM
10k
mC

You can multiplex the output signals from two sensors into one input-capture line in a mC.

116 edn | January 20, 2000 www.ednmag.com


design
ideas
amenable to time-sharing and do not re- MUXED_OUT. Therefore, when the Se- es synchronized with the Sensor 2 input.
quire continuous monitoring, such as lect input is low, MUXED_OUT pro- You can change the values of R1, R4, R5,
position sensors. In Figure 1, Sensor 1 duces pulses that are inverted but syn- and R6 to meet the sensors’ requirements.
and Sensor 2 are outputs from two sen- chronized with the Sensor 1 pulses. At the D3 clamps MUXED_OUT to CMOS/
sors using npn transistors with open-col- same time, Q3 and Q1D are on, turning off TTL levels. The use of the MPQ3906,
lector outputs. To enable Sensor 1 or Sen- Q1B and disabling the Sensor 2 input. containing four pnp transistors in one
sor 2, Q1A or Q1B , respectively, must turn Similarly, when Select goes high, Q2 package, minimizes the number of com-
on. A logic-low signal from the mC on the and Q1C turn on, turning off Q1A and dis- ponents. Similarly, you can obtain arrays
Select input turns off Q2 and Q1C. When abling the Sensor 1 input. At the same of 1-kV resistors in a single package. (DI
Sensor 1 input goes low, D1 forward-bi- time, Q3 and Q1D turn off, allowing the #2469)
ases, and Q1A turns on, providing a high Sensor 2 signal to turn Q1B on and off
signal on MUXED_OUT. When Sensor 1 when Sensor 2 switches on (low) and off
input turns off (high-impedance state), (high-impedance state), respectively. To Vote For This Design,
Q1A turns off, providing a low signal on Therefore, MUXED_OUT produce puls- Circle No. 318

Analog switch acts as dc/dc converter


John P Skurla, Advanced Linear Devices Inc, Sunnyvale, CA

any low-current devices that of an additional 25V-converter function. these applications, typical negative- volt-

M require 65V supplies can operate


reliably in a single 5V power-sup-
ply environment if you use an appropri-
Many companies manufacture dc/dc-
converter ICs and modules in a variety of
power ratings and footprints. However,
age requirements range from 24 to 26V
with a supply current of 1 mA, and re-
quirements for the 25V supply are gen-
ate localized dc/dc converter to generate these typical dc/dc converters can be erally noncritical.
the 25V bias. Often, the capabilities and overkill for simple, single-chip applica- A lower cost alternative to conven-
advantages of these 5V ICs far outweigh tions that require only a negative bias tional dc/dc converter modules for gen-
the minor inconvenience and added costs voltage with low operating currents. For erating negative dc voltages from a posi-

CLK
7 kHz
ALD4213
1 74HC4316
IN1 IN2 16 1 16
Figure 1 V+
2 D1 D2 15 15
V+ CLK
2
V+ 14
3 S1 S2 3
13
4 13
V2 V+ V+
C1 + 4
5 GND
10 mF +
12 10 mF
5
6 S4 S3 CLK
11
6 2VOUT

7
7 D4 D3 10
2VOUT 8 10
8 IN4 IN3 9
9
C2 10 mF
+

(a) (b)
+
10 mF
NOTES:
< <
2V_V+_5V.
CLK IS CMOS LOGIC LEVEL WITH FREQUENCY OF 5 TO 500 kHz.
V+ IS THE DC-TO-DC INPUT.
2VOUT IS THE DC-TO-DC OUTPUT.

Using an analog switch with two external capacitors and an external clock is a viable way to produce 25V from a 5V input for low-power, 25V needs.
One approach uses only one phase of the clock (a); a second approach requires both phases (b).

118 edn | January 20, 2000 www.ednmag.com


design
ideas
tive supply uses a low-cost quad- semi- ic gates inside the ALD4213 analog 74HC4316 quad analog switch with lev-
conductor analog switch and an onboard switch provide the logic translation to el translator (Figure 1b). The circuit is
system clock (Figure 1a). This type of convert a single 5V input to a 65V logic similar to the circuit in Figure 1a but has
voltage converter generates a low-pow- swing. different pin connections. This circuit
er, negative bias voltage from a 5V input. The circuit closes two switches, S1 and also requires both phases of the clock.
This circuit emulates charge-pump dc/dc S4, under clock control. During the first You can use an additional inverting log-
converters, which are suitable for gener- half of a clock cycle, C1 charges up to a ic gate to generate both clock phases if
ating an output voltage whose polarity is voltage equal to the input voltage, V+. necessary. The recommended input is a
opposite that of the input voltage. Two The next half-cycle of the clock control logic clock that has a useful frequency
charge-storage capacitors are also neces- opens S1 and S4 and closes S2 and S3. C1 range of 5 to 500 kHz.
sary, as with conventional converters. now connects across C2 through S2 and Figure 1a’s single-phase design costs
Unlike the conventional self-contained S3, and the charge on C1 subsequently less than $1 in large quantities. The cost
dc/dc converter approach, this circuit re- transfers to C2 until the voltage across of the circuit in Figure 1b can be less than
quires a single external clock input to se- both C1 and C2 is equal. Notice the “in- half the cost of the circuit in Figure 1a
quence the switches on and off and ap- verted” polarity across C2, which forces provided that both clock phases exist and
proximately the same amount of pc- the output voltage on C2 to be V2, or the that you don’t have to add an external
board space. You can tap this clock from opposite of V1. logic-gate inverter. You can also integrate
any 5V logic-gate output with continu- Each subsequent clock cycle, which analog-switching inverters with other
ous, regular periods of 5- to 500-kHz sig- again begins with the closing of S1 and S4, analog functions in a custom ASIC; the
nals. causes C1 to charge up from the previous ALD4213 and ALD500A are compatible
Charge-pump converters operate by voltage to V1. After many repeated clock with the company’s library of standard
first charging up one capacitor and al- cycles, the voltage on C2 remains charged cells. (DI #2476)
ternately transferring that charge to an- to a value equal to the negative of V1, or
other capacitor using a switching circuit. close to it; it performs the function of a
The switching circuit in Figure 1a alter- voltage inverter, which is more com-
nately charges and discharges C1 and C2 monly called a converter.
to generate a 25V output from a 5V in- An alternative analog-switch-based To Vote For This Design,
put. Integrated level translators and log- converter uses the industry-standard Circle No. 319

Circuit provides message on disabled phone line


Kevin Kelley, BAE Systems, Greenlawn, NY
hone companies often disconnect

P a misbehaving phone line


from a complainant’s resi-
dence for troubleshooting purposes.
Figure 1
KEY-CHAIN
VOICE RECORDER
C2 +
47 mF
1
TOSHIBA
TLP332
5

4
200k

With the problem between the residence 2

and the central office, the residence is left (6V)


BATT+ 0.47 mF
with a dead phone line and no visible re- C1 1k
1N914
0.47 mF
pairman while the line is under repair. (0V)
BATT2 SPKR+ 2N2222A
The circuit in Figure 1 adapts a small key-
PLAY 200k
chain voice recorder to the Tip and Ring
TIP
lines of a phone line that has been dis-
connected from the central office. The RING
purpose is to play a prerecorded message
into any phone on the line when its re- Dead phone line? You can send a prerecorded message to any phone on the defunct line.
ceiver goes off-hook. A Radio Shack key-
chain voice-memo recorder (part num- powers the phone line with its internal (2), Speaker (1 or 2), and the Play but-
ber 63-945) or a similar device provides 6V batteries. You open and modify the ton contact. You can disconnect the in-
solid-state voice-message storage and recorder to bring four signals out to the ternal speaker to save power.
playback in a small package and also external circuit: Battery (1), Battery With all phones on-hook, phone-line
120 edn | January 20, 2000 www.ednmag.com
design
ideas
current is near zero, keeping the opto- transistor. The transistor provides a high ton. The message plays once in its en-
coupler off and its transistor open with ac impedance between C1 and the bat- tirety every time a receiver goes off-hook.
the voltage at Pin 5 at the battery voltage. tery, allowing audio-signal transfer to the C2 prevents any clicks at the end of the
The Tip and Ring lines are at 6 and 0V, line, and provides a low dc resistance to message from restarting the sequence if
respectively, to power the phones on the maximize the low battery voltage to the the receiver goes on-hook before the
line (Most phones operate on as little as phones. The transistor current turns the message ends. (DI #2472)
3V.) Battery drain in this condition is optocoupler on, and the voltage on Pin
minimal. When a receiver goes off-hook, 5 drops to near 0V. This negative edge
the line impedance drops, and several generates a low pulse into the Play con- To Vote For This Design,
milliamps flow through the saturated tact, as if you had pressed the Play but- Circle No. 320

Optocoupler isolates shift registers


Jim Hartmann, Silent Knight LLC, Maple Grove, MN
onventional shift registers, and strobe. Two NAND gates form an RS load the first bit of the next sequence. In

C such as the 74HC595, require data-,


clock-, and strobe-logic signals. The
circuit in Figure 1 needs only two logic
latch that captures the data state for the
serial input (SERIN). Two more NAND
gates form an AND to combine the two
this case, the optocoupler that turns off
last determines the RS latch state for the
first bit. You can also ignore the extra
signals to isolate and control shift-regis- pulse sources into the SRCK shift clock. clock; it has no effect on the output. Low
ter devices. For each transmitted bit and Finally, a NOR gate (or four more NAND power consumption is possible by keep-
one of the two optocouplers receives a gates) produces the RCK strobe. You can ing the pulses as short as possible by lim-
short drive pulse: one optocoupler for a cascade the shift-register devices as nec- iting the LED current and the updating
high transmitted bit and the other for a essary. rate. For example, with 40-msec pulses
low bit and After pulsing all the bits, the You have no timing constraints on the and 1-msec period, the average drive cur-
circuit a final concurrent 1 and 0 pulse signals other than observing the maxi- rent is 80 mA. (DI #2470)
strobes the data into the output registers. mum data rate of the optocouplers and
Two logic-gate packages on the isolated ensuring an off period between pulses.
side of the circuit decode the two nega- The final latch pulse also generates an ex- To Vote For This Design,
tive pulse signals back into data, clock, tra rising SRCK edge that you can use to Circle No. 321
IC1A IC1B
B1 1 4
3 6
2 5 SRCK
5V B0
74HC00 74HC00
Figure 1 IC3
IC5
R7 13 15
A4N28 10k IC1C G QA
9 12 1
8 RCK QB
PULSE FOR 2
10 SERIN QC
"1" BITS 10 3
5V SRCLR QD
74HC00 11 4
5V SRCK QE
PULSE BOTH 5
TO UPDATE QF
IC1D 14 SER QG 6
LATCHES. IC4 R8 12
A4N28 11 7
10k QH
13 9
PULSE FOR QHP
"0"' BITS 74HC00 74HC595

IC2A IC6
2 13 15
1 G QA
3 RCK 12 1
RCK QB
74HC02 2
QC
10 SRCLR QD 3
5V
11 4
SRCK QE
QF 5
14 SER QG 6
7
QH
9
QHP
74HC595

ADDITIONAL DEVICES

Optocouplers allow you to isolate and control shift registers with only two logic signals.

122 edn | January 20, 2000 www.ednmag.com


design
ideas
Tack a log taper onto a digital potentiometer
Hank Zumbahlen, Analog Devices, Campbell, CA
t’s sometimes convenient to have the parallel combination of R2 and RPAD.

I digital control of the volume level in


an audio system. The use of
multiplying DACs (MDACs) is Figure 1
VIN

RPOT
RPAD
VOUT
You define a ratio, r, which is RPOT/RPAD
(RPOT5R11R2). By adjusting the value of
RPAD, you can modify r, which adjusts the
problematic because of the switching taper, or the attenuation-versus-digital-
noise of the ladder network. This noise (a) input code to suit the application. The
comes from the bit switches injecting following expression gives the transfer
charge into the signal when they turn on function of the potentiometer:
and off. Audio engineers have dubbed VIN
R1
R2 RPAD VOUT
this noise “zipper noise” from the sound VOUT R 2 R PAD
that results from dynamically adjusting =
(b) VIN R1 + R 2 R PAD
the volume (gain riding). An alternative
to an MDAC in this application is a dig-
ital potentiometer, such as the Analog Adding a pad resistor to a digital potentiometer Figure 2 shows the attenuation curves
Devices AD52XX, AD84XX, or AD7376. imparts a logarithmic-like taper to the device. for three values of a pad resistor. As you
You can think of the digital potentiome- can see, this trick doesn’t give a taper that
ter as a tapped resistor string. It generates within a small percentage of the range of is so many decibels per step, but it does
less noise because fewer switches change the potentiometer. This constraint lim- allow for better low-level settability. You
state. In addition, you can connect the its the adjustability of the volume setting. must address a couple of issues. The first
three terminals of the potentiometer any- The ear responds logarithmically; the is that the end-to-end resistance of the
where within the common-mode range volume control should respond similar- potentiometer changes with the digital
of the circuit (the supply-voltage range), ly. The primary reason for having only a code. It varies from the potentiometer re-
unlike an MDAC, which generally uses linear taper is the manufacturing prob- sistance at one end (with the wiper at the
ground as reference. lems that the large range of resistance val- lower end) to the value of the pad resist-
The primary drawback with using the ues for a log taper cause. By adding a pad ance in parallel with the potentiometer
digital potentiometer for volume control resistor from the wiper of the poten- resistance at the other end. If you config-
is that it currently comes with only a lin- tiometer to one end (Figure 1a), you can ure the circuit as a typical attenuator and
ear taper. With a linear taper, if the to simulate a log taper. If you split the po- drive it from a low-impedance source, the
“wiper” is at the midpoint, the signal is tentiometer into two resistors, R1 and R2, low pad resistance should not present a
only 6 dB less than the maximum. Thus, you can redraw the circuit as in Figure major problem. If, however, you are try-
most of the adjustment range occurs 1b. The output voltage then depends on ing to obtain a set resistance value to de-
termine a time constant (or any other ap-
plication in which the resistor value is
1.2000 critical), this approach may not work
Figure 2 well. The second issue involves overvolt-
1.0000 age. The three terminals of the poten-
tiometer can be anywhere within the
0.8000 supply range of the IC, which is 5V for
VOUT the AD52XX and 615V for the AD72XX
0.6000
VIN family. If you apply overvoltage to one of
R=0.25 the pins, even in a transient condition,
0.4000
R=0.1 the IC could latch up because of a para-
R=0.025
0.2000 sitic substrate SCR. (DI #2473)

0.0000
1 33 65 129 161 193 225
TAP

It’s not log, but it’s close. These curves approximate what you can obtain from an audio-taper To Vote For This Design,
potentiometer. Circle No. 322

124 edn | January 20, 2000 www.ednmag.com


design
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Design Idea Entry Blank
Entry blank must accompany all entries. $100 Cash Award for all published Design Ideas. An additional $100 Cash Award for
the winning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.

To: Design Ideas Editor, EDN Magazine Entry blank must accompany all entries. (A separate entry
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I hereby submit my Design Ideas entry. entered must be submitted exclusively to EDN, must not be
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126 edn | January 20, 2000 www.ednmag.com