An Adaptive Approach to Dependable Circuits for a Digital Power Control

Aromhack SAYSANASONGKHAM and Kenta IMAI
Graduate School of System Design Tokyo Metropolitan University 6-6, Asahigaoka, Hino Tokyo 191-0065, Japan Email: {dola, imaikenta}@iel.sd.tmu.ac.jp

Masayuki ARAI and Satoshi FUKUMOTO
Faculty of System Design Tokyo Metropolitan University 6-6, Asahigaoka, Hino Tokyo 191-0065, Japan Email: {m-arai, s-fuku}@tmu.ac.jp

Keiji WADA
School of Science and Engineering Faculty of Urban Liberal Arts Tokyo Metropolitan University 1-2, Minamioosawa, Hachioji Tokyo 192-0397, Japan Email: kj-wada@tmu.ac.jp

Abstract—Recently, a microcomputer and a FPGA are apt to be used for control of the power conversion circuits because of their capability to simplify the parameter resetting and also their flexibility on the basis of programming by software. On the other hand, the control circuits are getting extremely close to the high current main circuit. Thus the electro-magnetic radiation generated nearby the high current pulse may affect the control circuit as transient faults. In this study, we focus on transient noise caused by switching activities of a DC-DC converter and propose a dependable digital power control circuit by FPGA. The basic idea is to keep the sampling times as far away from the switching times as possible to avoid the effects of transient noise. A control circuit, with the proposed method applied, is designed and its effectiveness is shown by simulations.

of the proposed method are presented by designing the digital power control circuit and executing spice simulations.

II.

FAULT M ODEL

As a first step of our study, we target on a buck DC-DC converter which is broadly used in various electronic devices. Specifically, we aim to propose a dependable digital power control circuit on a FPGA for the converter. A block figure of the buck DC-DC converter is shown on Fig.1.
Output Feedback

I.

I NTRODUCTION

Recently, energy saving and ecological issues have catched attentions from people around the globe. Of all others, efficient transformation of the switch mode power supply such as DCDC converter, AC-DC converter and so on are playing one of the crucial rolls for energy saving and miniaturization of electronic devices. Conventionally, usage of analog control parts in the control circuit of a converter such as operating amplifiers is very common. However, with high flexibility and parameters’ configurability, digital control circuit has become more favorable and several researches are showing significant progresses [1]. On the other hand, while the power converter circuits get smaller and highly integrated, control circuits and gate driver circuits are getting extremely close to the high current main circuit. Thus the electromagnetic radiation generated nearby the high current pulse may affect the control circuit and the neighboring circuits as transient faults [2]. Above all, digital control circuits are more vulnerable to noise than analog control circuits. This is because all operations in microcomputers and FPGAs are based on sample values. In this research, we focus on transient noise caused by switching activities of a DC-DC converter and propose a dependable digital power control circuit by FPGA. The fault model is based on the fault-injection experiments on a FPGA board, which is conducted in our previous research [3]. Accordingly, a fault-tolerant method is proposed regarding the fault model. Furthermore, the implementation and evaluations

Load

PWM Generator

Error Amplifier Noise

Parasitic LC Resonance etc.

Fig. 1: DC-DC converter.

In the switching device, the existence of the parasitic LC resonance is the main cause for noise to be generated during switching activities. During the switching activity, specifically at the point where the switch is turned on/off, noise is generated by the resonance phenomenon with the energy stored in the components of the parasitic LC. The resonant current will continue with a constant period of time and an attenuation behavior as shown on Fig.2. This high frequency noise can either be radiative noise or conductive noise and from our previous research [3]. We can assume that it will likely propagate to the input line of the error amplifier as shown on Fig.1. Furthermore, In this research, we suppose that the sampling frequency is basically equivalent to the switching frequency. Hence, there will be one sampling point in each switching cycle.

978-1-4799-0181-4/13/$31.00 ©2013 IEEE

2010. we utilize the fact that the occurrence timing of the noise is acquirable since the current cycle’s switching timing is decided at the previous switching cycle by the controller of the converter. the sampling time will be taken just before the pulse undershoot to avoid overshoot noise as shown on Fig. Wada. .5 5 4.6. C-024. the controller might get effected by errors of sampling values. Time E Pulse Width 0 Fig.5 50 51 52 53 54 III.5 2 1. M. When the duty cycle is over 50%.5 0 0 10 20 30 40 50 10mSecs/div Time Fig. because the sampling interval is not constant. The output voltage is correctly converged to the expected voltage 5v indicating the success noise avoidance of the control circuit. 53rd. the circuit can definitely escape from the absolute malfunction state.5 0 0 10 20 30 40 50 10mSecs/div Sampling Time Fig. implementation of the proposed method on a DC-AC converter is also one of our next goal. ” FIT2012. E 1 0. Wada. D29(9).5 2 1. Yokoyama. K. “Analysis of a Near Field Noise Voltage Caused by a Pulse Current on Power Electronics Circuits. pp.5v when samplings times are taken at the 50th. the voltage outputs vary from 3. ” The transactions of the Institute of Electrical Engineers of Japan. Conversely. 52nd. K.5 3 2.317-318.4. By implementing this method.5 4 Switching Cycle 3. Voltage 4 3. The simulation of the DC-DC converter with the proposed dependable digital power control circuit is shown on Fig.859-865. “Current Control for Utility Interactive Inverter Using Multisampling Method Based on FPGA. K.5 Voltage Cn-1 Sampling Time Cn Sampling Time Cn+1 Time 3 2. Resonant Current Period 5. S.5. In addition. we can at least avoid noise affection that has a duration less than 50% of the switching cycle. 3: Sampling time when duty cycle is over 50%. Y. 5: The voltage outputs of the DC-DC converter with a conventional digital power control when noises are input.As shown on Fig. 2009. Z. K. Ariga. R EFERENCES [1] T. Komiyama. 51st. 5 Voltage Pulse Width 0 4. 2012. Fukumoto. IV. Therefore. Imai. ” The transactions of the Institute of Electrical Engineers of Japan. The sampling time is chosen base on the duty cycles. pp. Our future work include implementation of the proposed method on the FPGA of the digital power control on a DCDC converter and its evaluations at the actual environment. T RANSIENT-FAULT T OLERANT M ETHOD In our proposed method. Shimada. 2: Noise current.7v to 5. pp. E VALUATION AND F UTURE W ORK [2] [3] Let us show the effects of out scheme by the circuit design and spice simulations. the sampling point will be taken just before the pulse overshoot to avoid undershoot noise as shown on Fig. We then adaptively tune the sampling times to avoid the noise at the pulse overshoots and undershoots. “Experimental Evaluation of Transient Faults on Logic Circuit in HIghly Electromagnetic Environments. when the duty cycle is under 50%. 6: The voltage output of the DC-DC converter with digital power control and fault-tolerant method implemented when noises are input. However. Nagashima. Cn Cn+1 Sampling Time Time Voltage Switching Cycle Cn-1 Sampling Time Sampling Time Fig.5 1 0.5 Fig. and the 54th clock after the pulse overshoot.3. 4: Sampling time when duty cycle is lower than 50%. D130. Atai. E. On the other hand. there were noise affection at the sampling times.51-59.

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