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DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Year/sem

:

Date :

**Sub.code & Title :
**

SL.NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 REG.NO 60122210001 60122210002 60122210003 60122210004 60122210005 60122210006 60122210007 60122210008 60122110006 60122110010 60122020009 6013221501 6013221502 6013221503 6013221505 6013221506 60122110005 NAME H.FAISAL AHAMED M.RAFIUDEEN T.SUMAN S.VENKATESH D.VETRIVEL N.VETRIVEL S.BANUPRIYA R.S.SUBASHINI R.VIVEKA G.PRABHAVATHY B.AKILA K.ALMAS ALI E.AZARUDEEN G .GANGADHARAN S.NAVEENRAJ J. VIVEK K.TAMILARASAN SIGNATURE

INTERNAL EXAMINER

EXTERNAL EXAMINER

PRIST UNIVERSITY

code Subject : : : Date : ALLOCATION OF MARKS 1. 3. 2. CIRCUIT DIAGRAM / LOGIC DIAGRAM CONNECTION EXECUTION RESULT & GRAPH VIVA – - 30 30 20 10 10 TOTOL 100 INTERNAL EXAMINER EXTERNAL EXAMINER PRIST UNIVERSITY ASOOR CAMPUS – KUMBAKONAM . 4. 5.ASOOR CAMPUS – KUMBAKONAM DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING Year/sem Sub.

CHITRA B.SATHESHPRABU T.BANUPRIYA NAME Date : SIGNATURE INTERNAL EXAMINER EXTERNAL EXAMINER PRIST UNIVERSITY ASOOR CAMPUS – KUMBAKONAM DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING .ANITHA L.DEPARTMENT OF COMPUTER SCIENCE ENGINEERING Year/sem Sub.NO 60122110002 60122110003 60122110004 60122110007 60122110008 60122110009 G.MARIYAPPAN B.NO 1 2 3 4 5 6 : : : REG.SUGANYA M.code Subject SL.

CIRCUIT DIAGRAM / LOGIC DIAGRAM CONNECTION EXECUTION RESULT & GRAPH VIVA – - 30 30 20 10 10 TOTOL 100 INTERNAL EXAMINER EXTERNAL EXAMINER .code Subject : : : Date : ALLOCATION OF MARKS 1. 5.Year/sem Sub. 3. 2. 4.

To design and implementation of 2 bit magnitude comparator using logic gates 5.To design and implementation of adders and subtractors using logic gates 2. SIPO. To design and implementation of encoder and decoder using logic gates 8.code & Title : 1. To design and implementation of asynchronous up/down counter . To design and implementation of parity checker / generator using logic gates 6. To design and implementation of 4 bit binary adder / subtractor 4.PISO and PIPO shift registers using flip-flop 9. To design and implementation of multiplexer and demultiplexer using logic gates 7. To design and implementation of code converter using logic gates 3. To design and implementation of SISO .PRIST UNIVERSITY ASOOR CAMPUS – KUMBAKONAM DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING SYLLABUS Year/sem : Date : Sub. To construct and verification of 4 bit ripple counter 10.

To design and implementation of SISO . To construct and verification of 4 bit ripple counter 10.PISO and PIPO shift registers using flip-flop 9. To design and implementation of asynchronous up/down counter . To design and implementation of multiplexer and demultiplexer using logic gates 7. To design and implementation of 4 bit binary adder / subtractor 4. To design and implementation of parity checker / generator using logic gates 6. To design and implementation of code converter using logic gates 3. SIPO. To design and implementation of 2 bit magnitude comparator using logic gates 5.1. To design and implementation of encoder and decoder using logic gates 8.To design and implementation of adders and subtractors using logic gates 2.

PRIST UNIVERSITY ASOOR CAMPUS – KUMBAKONAM DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING QUESTIONS Year/sem : Date : Sub. To design and implementation of encoder and decoder using logic gates 8. To design and implementation of multiplexer and demultiplexer using logic gates 7. To design and implementation of code converter using logic gates 3. To design and implementation of SISO .To design and implementation of adders and subtractors using logic gates 2. To design and implementation of 4 bit binary adder / subtractor 4.PISO and PIPO shift registers using flip-flop INTERNAL EXAMINER EXTERNAL EXAMINER . To design and implementation of 2 bit magnitude comparator using logic gates 5. To design and implementation of parity checker / generator using logic gates 6.code & Title : 1. SIPO.

To design and construct BJT common collector amplifier using voltage Divider bias (self bias) (a) Measurement of gain (b) Plot the frequency response & determination of gain bandwidth protect. (c) Plot the frequency response 2. (a) Wave forms at input and output without bias (b) Measurement of gain.To construct and test the performance of darlington amplifier using BJT (a) Measurement of gain and input resistance (b) Plot the frequency response & determination of gain bandwidth protect 5.Half wave Rectifier with simple capacitor filter (a) Plot the load regulation characteristics (b) Measurement of dc voltage under load and ripple factor .PRIST UNIVERSITY ASOOR CAMPUS – KUMBAKONAM DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING Year/sem : Date : Sub. 4. To design and construct BJT common emitter amplifier using voltage divider bias (self bias) with and without bypassed emitter resistor (a)Measurement of gain (b)plot the frequency response & determination of gain bandwidth protect 3. To construct and test the performance of power supply circuit. To construct and test the performance of fixed bias amplifier circuit using BJT.code & title : 1.

To design and implementation of 2 bit magnitude comparator using logic gates 11.PISO and PIPO shift registers using flip-flop INTERNAL EXAMINER EXTERNAL EXAMINER . . To design and implementation of 4 bit binary adder / subtractor 10. To design and implementation of parity checker / generator using logic gates 12. To design and implementation of adders and subtractors using logic gates 8. To design and implementation of SISO .full wave Rectifier with simple capacitor filter (a) Plot the load regulation characteristics (b) Measurement of dc voltage under load and ripple factor 7. To construct and test the performance of power supply circuit. To design and implementation of encoder and decoder using logic gates 14. To design and implementation of multiplexer and demultiplexer using logic gates 13.6. SIPO. To design and implementation of code converter using logic gates (a) Binary to gray (b) BCD to Excess-3 code 9.

(a) Wave forms at input and output without bias (b) Measurement of gain.1. To construct and test the performance of fixed bias amplifier circuit using BJT. To design and construct BJT common emitter amplifier using voltage divider bias (self bias) with and without bypassed emitter resistor (a)Measurement of gain (b)plot the frequency response & determination of gain bandwidth protect 3.To construct and test the performance of darlington amplifier using BJT (a) Measurement of gain and input resistance (b) Plot the frequency response & determination of gain bandwidth protect 5. 4. © Plot the frequency response 2. To construct and test the performance of power supply circuit.Half wave Rectifier with simple capacitor filter . To design and construct BJT common collector amplifier using voltage Divider bias (self bias) (a)Measurement of gain (b)Plot the frequency response & determination of gain bandwidth protect.

. To design and implementation of parity checker / generator using logic gates 12. To design and implementation of encoder and decoder using logic gates 14.(a) Plot the load regulation characteristics (b)Measurement of dc voltage under load and ripple factor 6. To design and implementation of SISO . To design and implementation of adders and subtractors using logic gates 8. To construct and test the performance of power supply circuit. To design and implementation of multiplexer and demultiplexer using logic gates 13. To design and implementation of code converter using logic gates (a) Binary to gray (b) BCD to Excess-3 code 9.PISO and PIPO shift registers using flip-flop . To design and implementation of 4 bit binary adder / subtractor 10.full wave Rectifier with simple capacitor filter (a)Plot the load regulation characteristics (b)Measurement of dc voltage under load and ripple factor 7. To design and implementation of 2 bit magnitude comparator using logic gates 11. SIPO.

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