2013-1623

United States Court of Appeals
for the Federal Circuit




IN RE RAMBUS, INC.





Appeal from the United States Patent and Trademark Office, Patent
Trial and Appeal Board in Reexamination No. 95/001,169.
BRIEF FOR APPELLANT RAMBUS, INC.

GREG GARDELLA
SCOTT MCKEOWN
OBLON, SPIVAK, MCCLELLAND,
MAIER & NEUSTADT, L.L.P.
1940 Duke Street
Alexandria, VA 22314
(703) 413-3000

Attorneys for Appellant
Rambus, Inc.

NOVEMBER 4, 2013




COUNSEL PRESS, LLC (202) 783-7288 * (888) 277-3259
Case: 13-1623 Document: 10 Page: 1 Filed: 11/04/2013

CERTIFICATE OF INTEREST

Counsel for Appellant Rambus, Inc. certifies the following:

1. The full name of every party or amicus represented by me is:

Rambus, Inc.

2. The name of the real party in interest (if the party named in the caption is not
the real party in interest) represented by me is:

N/A

3. All parent corporations and any publicly held companies that own 10 percent or
more of the stock of the party or amicus curiae represented by me are:

N/A

4. The names of all law firms and the partners or associates that appeared for the
party or amicus now represented by me in the trial court or agency or are expected
to appear in this court are:

Greg Gardella
Scott A. McKeown
OBLON, SPIVAK, MCCLELLAND, MAIER & NEUSTADT, L.L.P.

Kara F. Stoll
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER, LLP

Robert Greene Sterne
STERNE, KESSLER, GOLDSTEIN & FOX, PLLC

November 4, 2013 /s/Greg Gardella


i
Case: 13-1623 Document: 10 Page: 2 Filed: 11/04/2013

TABLE OF CONTENTS
Page

CERTIFICATE OF INTEREST ................................................................................. i
TABLE OF AUTHORITIES .................................................................................... iv
TABLE OF ABBREVIATIONS ............................................................................... v
STATEMENT OF RELATED CASES .................................................................... vi
JURISDICTIONAL STATEMENT .......................................................................... 1
STATEMENT OF THE ISSUES............................................................................... 1
STATEMENT OF THE CASE .................................................................................. 2
STATEMENT OF FACTS ........................................................................................ 3
I. The Claimed Method Provides Bus Flexibility by Having the
DRAM Wait for the Strobe Signal to Begin Receiving the Data ................. 3
II. All of the Rejections Rely Upon Either Hayes or Farmwald as
Meeting the Recited “Strobe Signal” ............................................................ 6
III. Hayes’ Data Strobe Signal Does Not Cause or Initiate the Data
Transfer ......................................................................................................... 7
IV. Farmwald’s TrncvrRW Signal Not Cause or Initiate the Data
Transfer ......................................................................................................... 9
V. The Sole Purpose of Farmwald’s Transceiver Hub is to Serve as a
Bridge Between a Single Port or Node and Multiple Memory Chips ........ 10
SUMMARY OF THE ARGUMENT ...................................................................... 12
STANDARD OF REVIEW ..................................................................................... 14
ARGUMENT ........................................................................................................... 15
I. Neither Hayes Nor Farmwald Meets the Claim Language Under the
Broadest Reasonable Interpretation of “Strobe Signal” ............................. 15
A. Under the Broadest Reasonable Interpretation the Strobe Signal
Must Cause or Initiate the Data Transfer ............................................... 15
ii
Case: 13-1623 Document: 10 Page: 3 Filed: 11/04/2013

B. Under a Reasonable Claim Construction Neither Hayes Nor
Farmwald Discloses the Claimed Strobe Signal .................................... 18
1. Hayes’ Data Strobe Provides Only Status Information and
Does Not Cause or Initiate the Data Transfer .................................. 19
2. Farmwald’s TrncvrRW Signal Also Provides Only Status
Information and Does Not Cause or Initiate the Data Transfer ....... 20
II. Hayes Fails to Meet the Independent Claims for the Additional
Reason that the Recited “Delaying” or “Deferring” Cannot Be
Reasonably Interpreted as Encompassing Merely Incidental or
Inherent Delay ............................................................................................. 21
III. The Rejections Based on Farmwald Fail for the Additional Reason
that It Would Be Nonsensical to Incorporate Farmwald’s
Transceiver Hub onto a Peripheral Memory Device .................................. 23
IV. Neither Hayes Nor Farmwald Teaches Spacing the Write and Strobe
Signals by Two or More Clock Cycles as Recited in Dependent ............... 24
A. Each of the Proposed Combinations Based on Hayes Uses a
Single Clock Cycle to Separate the Command Information from
the Alleged Strobe .................................................................................. 25
B. The Rejection Based on Farmwald Mistakenly Relies on
Disclosure Associated With an Unrelated Embodiment ....................... 27
CONCLUSION ........................................................................................................ 28
ADDENDUM
Decision on Appeal before the Board of Patent Appeals and
Interferences, January 24, 2012 ........................................................................ A1
Rehearing Decision on Appeal before the Patent Trial and
Appeal Board, February 13, 2013 .................................................................. A131
Patent at Issue: U.S. Patent No. 6,591,353 .................................................... A186
CERTIFICATE OF SERVICE
CERTIFICATE OF COMPLIANCE

iii
Case: 13-1623 Document: 10 Page: 4 Filed: 11/04/2013

iv
TABLE OF AUTHORITIES

Page(s)
FEDERAL CASES

In re Abbott Diabetes Care Inc.,
696 F.3d. 1142 (Fed. Cir. 2012)..................................................................... 17, 18
Consolidated Edison Co. v. NLRB,
305 U.S. 197 (1938) ............................................................................................ 14
In Re Baker Hughes,
215 F.3d 1297 (Fed. Cir. 2000) ......................................................................... 14
In re Kotzab,
217 F.3d 1365 (Fed. Cir. 2009) ............................................................................ 14
Rambus Inc. v. Rea,
2013 U.S. App. LEXIS 13284, 2013 WL 3242241
(Fed. Cir. June 28, 2013) ........................................................................ 16, 17, 18

FEDERAL STATUTES AND RULES
28 U.S.C. § 1295 ........................................................................................................ 1
35 U.S.C. § 103 ...................................................................................................... 6, 7
35 U.S.C. § 134 .......................................................................................................... 1

ADMINISTRATIVE AGENCY DECISIONS AND MATERIALS

Decision on Appeal, Appeal 2011-010623, Reexamination
Control No. 95/001,169, Patent 6,591,353 (January 24, 2012) ........................passim
Decision on Appeal, Appeal 2013-000562, Reexamination
Control No. 95/001,169, Patent 6,591,353 (February 13, 2013) ......................passim

Case: 13-1623 Document: 10 Page: 5 Filed: 11/04/2013


TABLE OF ABBREVIATIONS

A_____ Cited page(s) of the Appendix
PTO United States Patent and Trademark Office
PTAB Patent Trial and Appeal Board
CRU Central Reexamination Unit
‘353 patent U.S. Patent No. 6,591,353
‘914 patent U.S. Patent No. 5,748,914
‘109 patent U.S. Patent No. 7,287,109
Hayes U.S. Patent No. 5,218,684 to Hayes
Farmwald U.S. Patent No. 5,319,755 to Farmwald
Lu Lu, The Future of DRAMs, 1988 IEEE Inter. Solid-State Cir.
Conf. (ISSCC), Digest Tech. Papers, 98-99 (Feb. 1988) or
iRAM iRAM, Memory Components Handbook, Intel. Corp., Ch. 1, 3
(1985).

v
Case: 13-1623 Document: 10 Page: 6 Filed: 11/04/2013

vi
STATEMENT OF RELATED CASES

This appeal involves a patent which is directly related to the patent which
was the subject of Rambus, Inc. v. Rea, Appeal No. 2012-1480, decided June 28,
2013. More particularly, the patents involved in this appeal and Appeal No. 2012-
1480 are in the same family, share the same specification and claim benefit to the
same parent patent. The present appeal involves United States Patent No.
6,591,353 which is a continuation of United States Patent No. 5,748,914. Appeal
No. 2012-1480 involved United States Patent No. 7,287,109, which is a divisional
of United States Patent No. 5,748,914.
Case: 13-1623 Document: 10 Page: 7 Filed: 11/04/2013

JURISDICTIONAL STATEMENT
The Patent Trial and Appeal Board had jurisdiction over the inter partes
reexamination under 35 U.S.C. § 134(b). The PTAB entered its final decision on
appeal on February 13, 2013. This timely appeal was filed on July 23, 2013. This
Court has jurisdiction under 28 U.S.C. § 1295(a)(4)(A) (as amended by the Leahy-
Smith America Invents Act, Sec. 7(c)(2), Pub. L. 112-29, 125 Stat. 314 (effective
Sept. 16, 2011)).
STATEMENT OF THE ISSUES
1. Whether the PTAB erred by finding that U.S. Patent No. 5,218,684 to Hayes
teaches a “strobe signal” as recited in claims 1-26 of the ‘353 patent.
2. Whether the PTAB erred by finding that U.S. Patent No. 5,319,755 to
Farmwald teaches a “strobe signal” as recited in claims 1-26 of the ‘353
patent.
3. Whether the PTAB erred by finding that Hayes teaches the “deferring
sampling” step of independent claim 1, the “delaying for a first time period”
step of independent claim 11, and the recitation in independent claim 19 that
the strobe signal is “is delayed relative to the write command by a first time
period.”

1
Case: 13-1623 Document: 10 Page: 8 Filed: 11/04/2013

4. Whether the PTAB erred by finding that it would have been obvious to
incorporate the transceiver hub of Farmwald into the systems disclosed in
Lu, The Future of DRAMs, 1988 IEEE Inter. Solid-State Cir. Conf. (ISSCC),
Digest Tech. Papers, 98-99 (Feb. 1988) or iRAM, Memory Components
Handbook, Intel. Corp., Ch. 1, 3 (1985).
5. Whether the PTAB erred by finding that the proposed combinations
demonstrate an interval spanning a plurality of clock cycles of an external
clock signal as recited in dependent claim 26.
STATEMENT OF THE CASE
This is an appeal from a decision by the PTAB in an inter partes
reexamination of U.S. Patent 6,591,353. The PTAB maintained the Examiner’s
rejection of claims 1, 5, 7, 11, 14, 19, and 23 under Hayes and reversed the
Examiner’s decision not to reject claims 1 through 26 on other grounds. Rambus
appeals claims 1 through 26. The third party requester NVidia filed on October 3,
2013 a statement indicating that it was withdrawing from the present appeal.


2
Case: 13-1623 Document: 10 Page: 9 Filed: 11/04/2013

STATEMENT OF FACTS
I. The Claimed Method Provides Bus Flexibility by Having the DRAM
Wait for the Strobe Signal to Begin Receiving the Data

The ‘353 patent is directed to systems and methods for increasing the
efficiency of communication between a memory controller and a memory device.
The claims of the '353 patent specifically allow for the decoupling of the timing of
the command control information, e.g. a write command, from the timing of the
data transfer, e.g. the sampling of data by a memory device. A214 at 10:13-38;
A213 at 8:53-67. To decouple the command control information from the timing
of the data transfer operation, the specification teaches that after a memory
controller issues a write command to a memory device, the memory controller
separately sends a "strobe signal" at a later time to initiate the sampling of write
data. A213 at 8:53-67.
The decoupling achieved through sending a strobe signal "separate from and
subsequent to" the command control information results in improved operation of
the memory system. A213 at 8:55-59. For example, decoupling the timing of the
command control information from the timing of the data transfer allows improved
interleaving of data and control information that can maximize pin utilization
without placing latency requirements upon the DRAM core that are difficult or
expensive to satisfy. A214-15 at 10:55-11:18. Interleave refers to the relative
3
Case: 13-1623 Document: 10 Page: 10 Filed: 11/04/2013

ordering of data, requests and control signals that are associated multiple
transactions. A213 at 7:52-53.
Figure 8 of the '353 patent (A197, reproduced below) illustrates the
functionality of improved interleaving during a write transaction.

As illustrated in Figure 8, at step 802, the controller transmits a wakeup signal to
the memory device. At step 804, the controller transmits control information to the
memory device, specifying, for example, a write operation. At step 806, the
controller separately transmits a strobe signal that indicates when data should be
4
ITR'''"'' W,,,,,'€iGM" OM THE aus
CONTROL LINE

[
TRANSMIT COMMAND CONTROl
INFORMATION ON THE BUS CONTROL
LINE "NO DATA BUS

..
..
Jl1Il
TRANSMIT ADDRESSES
SERIALLY ON THE BUS
TRANSMIT STROBE SIGNAL
ENABLE LINE
ON THE BUS CONTROL LINE
il2
illa
ill
TRANSMIT DATA ON THE
TRANSMIT TERMINATE
DATA BUS
SIGNAL ON THE BUS
CONTROL LINE
Figure 8
Case: 13-1623 Document: 10 Page: 11 Filed: 11/04/2013

sampled in the case of a write operation. As discussed within the specification of
the ‘353 Patent:
To allow dynamic interleave adjustment, there is no fixed
time period between the execution of steps 804 and 806.
Rather, the controller is free to adjust the timing of step 806
relative to the timing of step 804 as needed to provide the
desired interleave (e.g., to provide time to transmit the
command control information for other transactions between
execution of steps 804 and 806).
A213 at 7:53-60. The write data is transmitted over the data bus at step 814. In
some embodiments, the controller separately transmits a terminate signal at step
816. In performing a number of transactions such as the one illustrated in Figure 8
above in an interleaved fashion while varying the delay between the transmission
of command control information in step 804 and transmission of the strobe signal
in step 810 from transaction to transaction, a memory controller can “increase the
utilization of the channel” and “can adapt… to the changing demands being placed
on the bus to minimize latency.” A215 at 11:61-64.
Focusing on the claimed "strobe signal," the specification states that "the
data transfer control information includes data transfer start information (a ‘strobe
signal’) sent from the controller to indicate when the DRAM is to begin sending
data" in a read operation and when to sample data in a write operation. A213 at
8:60-63. The '353 patent also states that "the data transfer control information
which controls the timing of the data transfer ... is sent separately from the
5
Case: 13-1623 Document: 10 Page: 12 Filed: 11/04/2013

command control information to which it corresponds." A214 at 10:27-30. Thus,
the claimed signal itself indicates when the DRAM is to begin sampling data.
A984-85 at ¶¶ 20-24.
II. All of the Rejections Rely Upon Either Hayes or Farmwald as
Meeting the Recited “Strobe Signal”

The CRU’s right of appeal notice maintained only the rejection of claims 1,
5, 7, 11, 14, 19 and 23 allegedly as anticipated by Hayes under 35 US.C. §102(b).
A1024. NVIDIA cross-appealed the abandoned rejections, including §103
rejections based on Hayes and §103 rejections based on Farmwald ‘755.
The Patent Trial and Appeal Board (PTAB) maintained the Examiner’s
rejection of claims 1, 5, 7, 11, 14, 19 and 23 under Hayes and reversed the
Examiner’s decision not to reject claims 1 through 26. A2. The PTAB Decision
set forth the following new grounds of rejection:
• New Ground #1- Claims 2, 6, 10, 17, 25 and 26 as obvious under 35
U.S.C. § 103(a), based on Hayes in view of Bennett.
• New Ground #2 - Claims 3, 4, 12, 13, 21 -13, 33 and 34 as obvious
under 35 U.S.C. § 103(a) based on Hayes, Bennett and Inagaki.
• New Ground #3 - Claims 2-10, 12-14, 16, 17 and 20-26 as obvious
under 35 U.S.C. § 103(a) based on Hayes with Ohshima.
• New Ground #4 - Claims 1-14, 16, 17 and 19-26 as obvious under 35
U.S.C. § 103(a) based on Kushiyama, Hayes and Lu.
• New Ground #5 - Claims 1-4, 6-9, 11-13, 15-16, 18-22 and 24-26 as
obvious under 35 U.S.C. § 103(a) based on Farmwald ‘755 and Lu.
6
Case: 13-1623 Document: 10 Page: 13 Filed: 11/04/2013

• New Ground #6 - Claims 1-4, 6-9, 11-13, 15-16, 18-22 and 24-26 as
obvious under 35 U.S.C. § 103(a) based on Farmwald ‘755 and
iRAM.
Each of the foregoing rejections relies upon either Hayes or Farmwald as
meeting the “strobe signal” limitation recited in each independent claim. A136 et
seq.
III. Hayes’ Data Strobe Signal Does Not Cause or Initiate the Data Transfer

U.S. Patent No. 5,218,684 to Hayes discloses an asynchronous system that
includes a memory controller that interfaces with asynchronous memory devices.
A806 at 4:1-4; A806 at 4:22-24; A807 at 6:1-20. Specifically, Hayes relates to "a
method and apparatus for configuring additional memory used with a stand-alone
digital computer system including a single board central processing unit and
limited onboard memory.” A805 at 1:11-14. The configuration of Hayes is
“adaptable to accommodate and effectively utilize additional memory that is not of
a pre-determined size and also that is not physically restricted to be connected in
any specific backplane slot." A805 at 1:11-19. To add additional memory, Hayes
describes a number of additional external memory array boards that may be added
to the system. A802 at FIG. 6. Each memory array board may be connected to the
separate central processing unit board by a memory array bus. Id.
7
Case: 13-1623 Document: 10 Page: 14 Filed: 11/04/2013

In reference to Figure 2 Hayes describes the communication between the
master (bus controller) and slave (memory):
[For a write cycle, t]he bus master ...
drives data onto DAL 31:0] and asserts
DS [data strobe col. 7, 1. 56], indicating
that the data is valid on DAL [31:0]. If no
error occurs, the slave device reads the
data, and the external logic asserts RDY.
If an error occurs, external logic asserts
ERR, which aborts the bus cycle. This
causes the processor 10 to execute a
machine check. Finally, the bus master
deasserts AS and DS to end the cycle.
A809 at 9:58-65.

Hayes also describes how the assertion and
deassertion of the DS (data strobe) provides
timing for read and write operations as follows:
The Data Strobe line (DS) provides timing information for data
transfers. During a read cycle or an interrupt acknowledge cycle, the
bus master asserts DS to indicate that it is ready to receive incoming
data. The bus master then deasserts DS to indicate that it has received
and latched the incoming data. During a write cycle, the bus master
asserts DS to indicate that DAL [31 :0] contains valid write data. The
bus master then deasserts DS to indicate that it is about to remove the
write data from DAL [31 :0]. A808 at 7:56-65.

In its decision on appeal, the PTAB did not find that the strobe causes or
initiates the sampling. Rather, the PTAB held that the claims were broad enough
8
Case: 13-1623 Document: 10 Page: 15 Filed: 11/04/2013

to cover Hayes because the data is sampled subsequent to the assertion of DS
signal:
Since claim 1 neither requires an immediate response, nor precludes
an infrequent (abnormal) or optional interrupt (such as by Hayes's
ERR system), even if Hayes delays sampling after the DS, in light of
the '353 patent, the DS constitutes a strobe signal as recited in the
independent claims because Hayes discloses that data is normally read
by the slave memory device after DS during a write cycle. (H2, H4.)”
A22 (emphasis added).

Indeed, Hayes’ DS signal does not in fact cause or initiate data sampling.
The DS signal provides only status information; it is not a transitory signal that
initiates an event. A975-76.
IV. Farmwald’s TrncvrRW Signal Not Cause or Initiate the Data Transfer

U.S. Patent No. 5,319,755 to Farmwald, owned by Rambus, describes a
system where a write request is provided to the memory device and in response to
that request, the memory device will sample data after a “device-internal access
phase” (e.g., delay time) has transpired. A244-46 at 8:56-12:24. In one
embodiment disclosed by Farmwald, a transceiver is provided to address the
problem of the physical limitation on the number of memory devices that can be
connected to a single bus by coupling an additional (local) bus to the master
(transceiver) bus via the transceiver. A250-51 at 20:47-22:31.
9
Case: 13-1623 Document: 10 Page: 16 Filed: 11/04/2013

As was the case with Hayes, the PTAB did not find that TrncvrRW signal
causes or initiates data sampling. Rather, the PTAB merely found that there is a
delay between the TrncvrRW signal and the data sampling:
In a related finding, the '623 Board Decision finds that "the '353
patent describes a delay between the strobe signal and sampling" and
that "Rambus corroborates NVIDIA's point and describes a similar
delay between the data and the strobe." A170.

The TrncvrRW signal disclosed in Farmwald '755 does not cause or initiate
the sampling of data. The TrncvrRW signal is not provided to the memory
devices and is not used to indicate to either the transceiver device or the memory
devices when to initiate sampling of data. A1720-22.
V. The Sole Purpose of Farmwald’s Transceiver Hub is to Serve as a
Bridge Between a Single Port or Node and Multiple Memory Chips

Farmwald’s transceiver acts as a hub that allows a single port or node to be
coupled to multiple memory devices or chips. The CRU Examiner summarized the
relevant teaching of Farmwald as follows:
A person of skill in the art would understand that while a transceiver
could be used with a single memory device, the reason for using the
transceiver embodiment is to have the ability to expand the memory
capacity by adding more memory devices to the primary bus(es) as
needed. A1037-38.

The Examiner’s reasoning can be more fully appreciated in the context of a
modern example of a transceiver-type device – a USB hub. The Murphy
10
Case: 13-1623 Document: 10 Page: 17 Filed: 11/04/2013

declaration explains that the Farmwald transceivers 19 (below left) operate much
like a commonplace USB hub or port replicator (below right). See id.


The transceivers, like USB hubs, enable multiple devices to be plugged into a
single addressable port or node. See id. Given this, it would be nonsensical to
incorporate a transceiver or hub into one of the slave or peripheral devices. Doing
so would prevent the transceiver/hub from performing its sole purpose – to act as a
bridge which enables many devices to plug into a single port or node. A1735 at ¶
34.

11
Case: 13-1623 Document: 10 Page: 18 Filed: 11/04/2013

SUMMARY OF THE ARGUMENT
The PTAB’s construction of the term “strobe signal” is unreasonably broad.
The PTAB held that the recited strobe signal need not cause or initiate the
sampling: “something other than, or, in addition to, the disclosed strobe signal (i.e.,
perhaps stored or pre-programmed clock delay times) govern the actual timing of
any data transmission after the data strobe.” A145. This interpretation is
substantially broader than this Court’s interpretation of the term in connection with
the recent appeal of ‘109 patent, which shares a common specification with the
‘353 patent. The Federal Circuit found that
[t]he patent specification makes clear that “signal” is being used
in a narrower sense as a start indicator for the DRAM to begin
an operation. . . . In the strobe embodiment, the memory
controller then transmits a separate “strobe signal” to the
DRAM, which causes the DRAM to execute the operation
immediately (with a minimal inherent delay). As the Board
noted, the benefit of this invention “stems from latency
minimization, resulting in a relatively free data bus for other
data transfers—i.e., the command control information tells the
[DRAM] to pre-fetch the desired data . . . and the [DRAM] then
waits for the strobe signal to send the data. (emphasis added)

The PTAB’s interpretation ignores the requirement that the strobe signal causes or
initiates the sampling and for that reason is thus unreasonably broad.
Under a reasonable claim construction, the asserted references fail to
disclose the claimed “strobe signal” because the references do not cause or initiate
the sampling. The PTAB appears to concede that Hayes’ data strobe does not
12
Case: 13-1623 Document: 10 Page: 19 Filed: 11/04/2013

cause the sampling as required by the proper interpretation of the claims (“Since
claim 1 neither requires an immediate response, nor precludes an infrequent
(abnormal) or optional interrupt (such as by Hayes's ERR system), even if Hayes
delays sampling after the DS, in light of the '353 patent, the DS constitutes a strobe
signal as recited in the independent claims because Hayes discloses that data is
normally read by the slave memory device after DS during a write cycle. (H2,
H4.)” A22. With regard to Farmwald, the PTAB likewise appears to concede that
the TrncvrRW signal does not cause data sampling. Rather, the PTAB merely
finds that there is a delay between the TrncvrRW signal and the data sampling.
Because neither the DS signal in Hayes nor the TrncvrRW signal in Farmwald
"cause the memory devices to sample data" as required by the "strobe signal"
recitation in the independent claims, none of the rejections set forth a prima facie
case of unpatentability.
The rejections based on Hayes fail for the additional reason that the
independent claims’ recitation of “delaying” or “deferring” cannot be reasonably
interpreted as encompassing incidental or inherent delay in an asynchronous
system. As noted above, the rejections based on Hayes are premised merely on the
finding that Hayes’ sampling occurs after the DS signal. Inherent delay is
insufficient to meet the express recitation of “delaying” or “deferring.”
13
Case: 13-1623 Document: 10 Page: 20 Filed: 11/04/2013

The rejections based on Farmwald fail for the additional reason that it would
be nonsensical to incorporate Farmwald’s transceiver hub onto the memory chips.
The Examiner correctly held that the “[a] person of skill in the art would
understand that while a transceiver could be used with a single memory device, the
reason for using the transceiver embodiment is to have the ability to expand the
memory capacity by adding more memory devices to the primary bus(es) as
needed.” A skilled artisan would have seen no apparent reason to incorporate the
transceiver hub into a peripheral device because the very purpose of a hub is to
bridge or interconnect multiple peripheral devices and in order to do so it must be
an architecturally distinct component.
Dependent claim 26 is patentable for the additional reason that neither Hayes
nor Farmwald teaches spacing the write and strobe signals by two or more clock
cycles. The proposed combinations fail to demonstrate an interval spanning a
plurality of clock cycles of an external clock signal, as recited by claim 26.
STANDARD OF REVIEW
The Board’s factual findings are reviewed for substantial evidence and the
Board’s legal conclusions are reviewed de novo. In re Kotzab, 217 F.3d 1365,
1369 (Fed. Cir. 2009). “Substantial evidence” is “such relevant evidence as a
reasonable mind might accept as adequate to support a conclusion.” Consolidated
Edison Co. v. NLRB, 305 U.S. 197, 229 (1938). The Board’s claim construction is
reviewed without deference. In Re Baker Hughes, 215 F.3d 1297, 1301 (Fed. Cir.
2000).
14
Case: 13-1623 Document: 10 Page: 21 Filed: 11/04/2013

ARGUMENT
I. Neither Hayes Nor Farmwald Meets the Claim Language Under the
Broadest Reasonable Interpretation of “Strobe Signal”

The PTAB has given a key claim term – strobe signal – an unreasonably
broad interpretation and for that reason incorrectly concluded that Hayes’ DS
signal or Farmwald’s TrncvrRW signal meets this limitation. The Federal Circuit
recently noted in connection with a related appeal that the “strobe signal”
described in the specification “causes the DRAM to execute the operation
immediately (with a minimal inherent delay).” A1195. Under this reasonable
construction neither Hayes nor Farmwald meet the “strobe signal” limitation.
A. Under the Broadest Reasonable Interpretation the Strobe Signal
Must Cause or Initiate the Data Transfer

The PTAB held that the claimed “strobe signal” need not cause or initiate
the data transfer. In response to Rambus’ argument that “Hayes's slave memory
device does not sample data in response to Hayes's DS signal” the PTAB held that
[s]ince claim 1 neither requires an immediate response, nor
precludes an infrequent (abnormal) or optional interrupt (such
as by Hayes's ERR system), even if Hayes delays sampling
after the DS, in light of the '353 patent, the DS constitutes a
strobe signal as recited in the independent claims because
Hayes discloses that data is normally read by the slave memory
device after DS during a write cycle. A22 (emphasis added).
15
Case: 13-1623 Document: 10 Page: 22 Filed: 11/04/2013

Similarly, in response to Rambus’ argument that “the TrncvrRW signal disclosed
in Farmwald '755 does not ‘cause the memory devices to sample data as required
by the "strobe signal" recited in the independent claims” the PTAB found that
Rambus does not explain how [the ‘353 patent] disclosure
limits further the recited requirement in claim 11 for the "strobe
signal to initiate sampling" . . . The TrncvrRW signal logically
contains "data transfer start information" since it indicates valid
data to a slave after which the memory device begins to sample
the data. A169-70 (emphasis added).
Accordingly, both the rejections based on Hayes and the rejections based on
Farmwald are premised on an interpretation of the term “strobe signal” which
requires no causal relationship between the strobe signal and the initiation of the
data transfer. In other words, the PTAB held that the recited “data strobe” need not
cause, trigger or initiate the data sampling or transfer.
This interpretation is substantially broader than this Court’s interpretation of
the term in connection with the recent appeal of a parent of the ‘353 Patent. In
Rambus Inc. v. Rea, 2013 U.S. App. LEXIS 13284, 5, 2013 WL 3242241 (Fed.
Cir. June 28, 2013), this Court addressed the ‘109 patent which shares a common
specification with the ‘353 patent. This Court found that:
[t]he patent specification makes clear that “signal” is being used
in a narrower sense as a start indicator for the DRAM to begin
an operation. . . . In the strobe embodiment, the memory
controller then transmits a separate "strobe signal" to the
DRAM, which causes the DRAM to execute the operation
16
Case: 13-1623 Document: 10 Page: 23 Filed: 11/04/2013

immediately (with a minimal inherent delay). J.A. 4; '109
Patent col. 8 l. 63-col. 9 l. 7; '109 Patent col. 9 ll. 41-46. As the
Board noted, the benefit of this invention "stems from latency
minimization, resulting in a relatively free data bus for other
data transfers—i.e., the command control information tells the
[DRAM] to pre-fetch the desired data . . . and the [DRAM] then
waits for the strobe signal to send the data."
Rambus Inc. v. Rea, 2013 U.S. App. LEXIS 13284, 5, 2013 WL 3242241 (Fed.
Cir. June 28, 2013, emphasis added) (nonprecedential). This Court thus found –
correctly – that the “strobe signal” triggers or initiates the data sampling or
transfer.
The usage of the term “strobe signal” in the context of claims comports with
the Federal Circuit’s finding. For example, independent claim 1, drafted from the
view of the memory device, recites that data is sampled “in response to detecting
the external strobe signal”, while independent claim 11, drafted from the view of
the memory controller, recites “issuing the strobe signal to the memory device to
initiate sampling[.]” A229-30.
This case is on all fours with In re Abbott Diabetes in which this Court
found that the PTAB erred by interpreting “electrochemical sensor” as including
sensors with external cables or wires. In re Abbott Diabetes Care Inc. 696 F.3d.
1142, 1148-50 (Fed.Cir. 2012). The context of the claims in Abbott “suggest[ed]
connectivity without the inclusion of cables or wires” just as the context of the
claims in the ‘353 patent suggest that the data sampling is in response to the strobe
17
Case: 13-1623 Document: 10 Page: 24 Filed: 11/04/2013

signal. Id. at 1149. In Abbott this Court found even more important that “every
embodiment disclosed in the specification shows an electrochemical sensor
without external cables or wires”; in the ‘353 patent, in every strobe signal
embodiment the data sampling is in response to the strobe signal. This Court
found in Abbott that the specification need not include any explicit disclaimer of
cables or wires; the ‘353 patent likewise does not expressly disclaim signals which
do not trigger or initiate the data transfer but this Court nevertheless correctly
understood that the specification “causes the DRAM to execute the operation
immediately (with a minimal inherent delay).” A1195.
B. Under a Reasonable Claim Construction Neither Hayes Nor
Farmwald Discloses the Claimed Strobe Signal
As found by the Federal Circuit in Rambus Inc. v. Rea, the “strobe signal” as
used in the specification refers to a signal causing immediate execution of a
memory operation.
1
Rambus submits that the broadest reasonable interpretation of
the term “strobe signal” is “a signal used to trigger a memory device to execute an
operation immediately (with a minimal inherent delay).” Under this proper
interpretation, Hayes and Farmwald fail to meet the claim.

1
“[A] separate ‘strobe signal’ to the DRAM… causes the DRAM to execute the
operation immediately (with a minimal inherent delay).” J.A. 4; '109 Patent col. 8
l. 63-col. 9 l. 7; '109 Patent col. 9 ll. 41-46. Rambus Inc. v. Rea, 2013 U.S. App.
LEXIS 13284, 5, 2013 WL 3242241 (Fed. Cir. June 28, 2013).
18
Case: 13-1623 Document: 10 Page: 25 Filed: 11/04/2013

1. Hayes’ Data Strobe Provides Only Status Information and
Does Not Cause or Initiate the Data Transfer

The data strobe (DS) of Hayes provides only status information; it is not a
transitory signal that initiates an event. A947-48. The DS, rather, is a back-plane
signal asserted while valid write data is available on the data and address lines,
then deasserted when the write data is removed. A997-98 at ¶¶ 67-69. After
asserting DS and before data is sampled, an error check is completed. A809 at
9:60-63; A1732 at ¶ 24.
The PTAB appears to concede that Hayes’ DS does not initiate the
immediate sampling as required by the proper interpretation of the claims: “Since
claim 1 neither requires an immediate response, nor precludes an infrequent
(abnormal) or optional interrupt (such as by Hayes's ERR system), even if Hayes
delays sampling after the DS, in light of the '353 patent, the DS constitutes a strobe
signal as recited in the independent claims because Hayes discloses that data is
normally read by the slave memory device after DS during a write cycle.” A22
(emphasis added).
Because the term “strobe signal” under the broadest reasonable
interpretation must cause or initiate the data transfer, Hayes cannot meet this
limitation. Hayes discloses at most an inherent or incidental delay; Hayes’ DS
signal does not cause or initiate the data sampling.
19
Case: 13-1623 Document: 10 Page: 26 Filed: 11/04/2013

2. Farmwald’s TrncvrRW Signal Also Provides Only Status
Information and Does Not Cause or Initiate the Data
Transfer
The TrncvrRW signal of Farmwald provides status information used by a
transceiver device to make forwarding decisions, e.g., whether the information on
the transceiver bus should be forwarded to the devices on its primary bus. A1005
at ¶104. This functionality permits additional peripheral devices, such as memory
sticks, to be coupled to transceiver bus. A35; A250-51 at 20:48-21:17; A251 at
22:11-31.
Neither the Examiner nor the PTAB found that TrncvrRW signal of
Farmwald causes or initiates data sampling. A39-40. Rather, the Board found that
the time delay specified in the op code of the request packet controls or initiates the
sampling of data, not the TrncvrRW signal. A35.
Indeed, the TrncvrRW signal disclosed in Farmwald does not cause the
memory devices to sample data as required by the "strobe signal" recitation in the
independent claims. A1694. As recognized by the Examiner,
[T]he [section regarding the TrncvrRW control signal] does not
state that the memory device should begin sampling. Although
the memory device would have to [have] already sampled data
prior to this step, this citation does not state that the memory
device should start sampling only that the transceiver should
forward data to the transceiver bus.
20
Case: 13-1623 Document: 10 Page: 27 Filed: 11/04/2013

A1042-43. Accordingly, Farmwald’s TrncvrRW signal does not cause or initiate
the data transfer.
Because the term “strobe signal” under the broadest reasonable
interpretation must cause or initiate the data transfer, Farmwald cannot meet this
limitation. Farmwald, like Hayes, discloses at most inherent or incidental delay.
II. Hayes Fails to Meet the Independent Claims for the Additional Reason
that the Recited “Delaying” or “Deferring” Cannot Be Reasonably
Interpreted as Encompassing Merely Incidental or Inherent Delay

The independent claims variously recite that the data sampling is “deferred”
or “delayed” until receipt of the strobe signal. A229-30. Claim 1 recites
“deferring sampling… until an external strobe signal is detected.” A229. Claim
11 recites “delaying for a first time period after issuing the write command.”
A230. Claim 19 recites that the strobe signal is “delayed relative to the write
command.” A230.
The terms “delay” and “defer” as used in the claims of the ‘353 Patent
plainly indicate a purposeful delay provided to improve the performance of the
memory device. A229 at 39:61-67; A230 at 41:29-41; A230 at 42:17-24. The
specification of the ‘353 Patent teaches that after a memory controller issues a
write command to a memory device, the memory controller separately sends a
"strobe signal" at a later time to initiate the sampling of data. A213 at 8:53-67.
The delay feature allows the controller “to adjust the time between the
21
Case: 13-1623 Document: 10 Page: 28 Filed: 11/04/2013

transmission of a request packet of a transaction and the transmission of data
involved in the transaction… [providing the controller an opportunity to] delay the
transmission of data to allow the channel to be used for other purposes prior to the
transmission of data.” A221 at 23:15-20 (emphasis added). In a particular
example, “the strobe signal for transaction 0 is sent three clock cycles after the
request packet for transaction 0” while “the strobe signal for transaction 3 is not
sent until 24 clock cycles after the request packet for transaction 3” to allow for
interleaving of various other information on the bus. A221 at 23:20-34.
The foregoing usage of the terms “delay” or “defer” in the ‘353 specification
match common dictionary definitions for the terms, such as “postpone”, “put off
action”, “detain”, or “hinder for a time.” A1740-45. A “delay” or “deferral” must
be deliberate and intended to accomplish a specific purpose.
Accordingly, the claim terms “deferring” or “delaying” require under the
broadest reasonable interpretation a purposeful delay provided to improve the
performance of the memory device. The terms “deferring” or “delaying” cannot be
reasonably interpreted to embrace incidental or inherent delay.
Hayes fails to teach any sort of purposeful “delay” or “deferral” between the
purported write command and the sampling of data. A998-99 at ¶¶72-74.
Significantly, the PTAB did not make any such finding. Rather, the PTAB
decision merely is premised on the finding that Hayes’ sampling occurs after the
22
Case: 13-1623 Document: 10 Page: 29 Filed: 11/04/2013

DS signal: “Hayes discloses that data is normally read by the slave memory device
after DS during a write cycle.” A22.
III. The Rejections Based on Farmwald Fail for the Additional Reason
that It Would Be Nonsensical to Incorporate Farmwald’s Transceiver
Hub onto a Peripheral Memory Device
The Examiner correctly held that the “[a] person of skill in the art would
understand that while a transceiver could be used with a single memory device, the
reason for using the transceiver embodiment is to have the ability to expand the
memory capacity by adding more memory devices to the primary bus(es) as
needed. (Murphy Supp. Dec. at 34.)” A1037-38.
The Examiner’s (sound) reasoning can be more fully appreciated in the
context of a modern example of a transceiver-type device – a USB hub. The
Farmwald transceivers 19 (below left) operate much like a commonplace USB hub
or port replicator (below right). A236 at FIG. 9. The transceivers, like USB hubs,
enable multiple devices to be plugged into a single addressable port or node.
A1734 at ¶ 33.

Given this, it would be nonsensical to incorporate a transceiver or hub into
one of the peripheral or slave devices. A1734-35 at ¶¶ 33-35. Doing so would
23
Case: 13-1623 Document: 10 Page: 30 Filed: 11/04/2013

prevent the transceiver/hub from performing its sole purpose – to act as a bridge
which enables many devices to plug into a single port or node. A1735 at ¶¶ 34-35.
The Examiner concurs, finding “the Patent Owner's arguments [are] persuasive in
that combining the transceiver with the memory device would defeat the purpose
of the separate transceiver in '755 Farmwald.” A1041. A skilled artisan would
have seen no apparent reason to incorporate the transceiver hub of Farmwald into
the memory devices taught in Lu or iRAM.
Moreover, incorporating transceiver hub into the memory device would
substantially impede or slow memory access while providing no discernible
offsetting advantage. A1736 at ¶ 40. As noted by Mr. Murphy, Farmwald '755
states that “[t]he high speed of the buses means that the transceivers will need to be
pipelined, and will require an additional one or two cycle delay for data to pass
through the transceiver in either direction.” A251 at 21:27-34; A1736 at ¶ 40.
Accordingly, the rejections based on Farmwald should be reversed for the
additional and independent reason that incorporating Farmwald’s transceiver hub
onto a peripheral memory device would have been, with respect, nonsensical.
IV. Neither Hayes Nor Farmwald Teaches Spacing the Write and Strobe
Signals by Two or More Clock Cycles as Recited in Dependent
Claim 26
According to dependent claim 26, a strobe signal is delayed relative to the
write command by a first time period which “elapses during an interval spanning a
24
Case: 13-1623 Document: 10 Page: 31 Filed: 11/04/2013

plurality of clock cycles of an external clock signal.” A230 at 42:52-53. Claim 26
thus describes an initial clock cycle carrying the write command being separated
from a subsequent clock cycle carrying the strobe signal by at least two intervening
cycles of the external clock.
A. Each of the Proposed Combinations Based on Hayes Uses a Single
Clock Cycle to Separate the Command Information from the
Alleged Strobe
The Hayes-based rejections of claim 26 include combinations of (a) Hayes
with Bennett, (b) Hayes with Ohshima, and (c) Kushiyama with Hayes and Lu.
A1220; A1230-31; A1241-42. Each of these combinations results in a method in
which a single clock cycle separates the command information from the alleged
strobe.
Turning first to Hayes and Bennett, the PTAB relies on Bennett’s FIG. 26
for its teaching of a pipelined transaction queue. A1220. However, as shown at
right, the ID/Function (e.g., write command) lags
the data by a single clock cycle. A1259 at FIG. 26.
According to Hayes, the DS signal (the alleged
“strobe signal”) is asserted when data is driven onto
the data lines. A809 at 9:54-60.
Kushiyama and Ohshima, having illustrations of the same operation timing
diagrams, are each relied upon for the shared teaching concerning the delay
25
Case: 13-1623 Document: 10 Page: 32 Filed: 11/04/2013

between the request packet and the data packet. A1230-31; A1241-42; A1657 at
FIGs 3(a)-3(d); A1753 at FIGS. 15(a) – 15(d). However, the present rejections are
improperly based upon timing diagrams related to read hit and read miss
operations. A1657 at FIGs 3(a)-3(d); A1753 at FIGS. 15(a) – 15(d). According to
the write timing diagrams provided by Kushiyama and Ohshima, presented in
FIGS. 15(c), 15(d) and 3(c), 3(d) respectively (reproduced below), the request
packet is separated from the data packet by a single clock cycle. A1657; A1753.

Lu includes no relevant technical teachings and fails to cure the deficiency
in the proposed Kushiyama, Hayes, and Lu combination. A166-75.
Consequently, the proffered combinations do not result in a method in which
an initial clock cycle referencing the write command is separated from a
subsequent clock cycle referencing the strobe signal by at least two intervening
cycles of the external clock as recited in dependent claim 26.
26
Case: 13-1623 Document: 10 Page: 33 Filed: 11/04/2013

B. The Rejection Based on Farmwald Mistakenly Relies on
Disclosure Associated With an Unrelated Embodiment
The remaining rejection of dependent claim 26 cites a portion of Farmwald
which describes a delay register that provides preprogrammed or hard wired fixed
response times. A1651. However, this delay register functionality is separate and
distinct from the proposed TrncvrRW (“strobe signal”) embodiment as envisioned
by the pending rejections of the independent claims, in which the TrncvrRW
signal, rather than the delay time provided by the request packet, indicates the
timing of the data sampling. A42; A1640.
In the embodiment of Farmwald relied upon by the PTAB as meeting the
recitation of claim 26, the memory controller does not provide any signal to the
memory device that indicates when the memory device is to begin sampling data.
A1002 at ¶ 93. Rather, upon receiving a request from the memory controller, the
memory device will proceed to sample data after a delay time has transpired. Id.
Accordingly, the teaching of Farmwald relied upon to meet claim 26 is
mutually exclusive with the teaching relied upon to meet the independent claim.
Farmwald thus does not establish a prima facie case of obviousness of dependent
claim 26. There are no teachings in Lu or iRAM, which are applied in
combination with Farmwald, which remedy this deficiency.


27
Case: 13-1623 Document: 10 Page: 34 Filed: 11/04/2013

28
CONCLUSION
This Court should reverse the PTAB’s finding that claims 1 through 26 are
unpatentable in view of the cited references.

Respectfully submitted,

Dated: November 4, 2013 /s/ Greg H. Gardella
Greg H. Gardella
Scott A. McKeown
OBLON SPIVAK LLP
1940 Duke Street
Alexandria, Virginia 22314
(703) 413-3000
ggardella@oblon.com
smckeown@oblon.com

Attorneys for Appellant
Rambus, Inc.
Case: 13-1623 Document: 10 Page: 35 Filed: 11/04/2013








ADDENDUM

Case: 13-1623 Document: 10 Page: 36 Filed: 11/04/2013
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
Inter Partes
NVIDIA, CORP.
Requestor, Appellant & Respondent
v.
RAMBUS, INC.
Patent Owner, Respondent & Cross-Appellant
Appeal 2011-010623
Reexamination Control No. 95/001,169
United States Patent 6,591,353 B1
Technology Center 3900
Before ALLEN R. MacDONALD, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.
EASTHOM, Administrative Patent Judge.
DECISION ON APPEAL
A1
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
Inter Partes
NVIDIA, CORP.
Requestor, Appellant & Respondent
v.
RAMBUS, INC.
Patent Owner, Respondent & Cross-Appellant
Appeal 2011-010623
Reexamination Control No. 95/001,169
United States Patent 6,591,353 Bl
Technology Center 3900
Before ALLEN R. MacDONALD, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.
EASTHOM, Administrative Patent Judge.
DECISION ON APPEAL
D
Case: 13-1623 Document: 10 Page: 37 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
This proceeding arose from NVDIA's request for an inter partes
reexamination of the Rambus's patent, U.S. 6,591,353 Bl to Barth et aI.,
Protocol For Communication with Dynamic Memory (July 8, 22, 2003).
Third-party Requestor NVIDIA appeals under 35 U.S.C. §§ 134(b) and 306
from the Examiner's Right of Appeal Notice (RAN) confirming claims 2-4,
6,8-10, 12, 13, 15-18,20-22 and 24-26 of the '353 patent under
reexamination. (See Req. App. Br. 3, 5 (appealing claims 1-26).) Patent
Owner Rambus cross-appeals from the Examiner's RAN finally rejecting
claims 1,5,7, 11, 14, 19 and 23. (P.O. Cr. App. Br. 5.) Requestor NVIDIA
and Patent Owner Rambus also filed Respondent Briefs (Req. Resp. Br.;
P.O. Resp. Br.) and Rebuttal Briefs (Req. Reb. Br.; P.O. Reb. Br.) We have
jurisdiction under 35 U.S.C. 35 U.S.C. §§ 6, 134, and 315.
We AFFIRM-IN-PART, affirming the Examiner's decision to
maintain the rejection of claims 1, 5, 7, 11, 14, 19, and 23 cross-appealed by
Rambus, and reversing the Examiner's decision not to reject claims 1-26
appealed by NVIDIA. We decline to reach some of the proposed rejections.
STATEMENT OF THE CASE
Rambus refers to several related judicial and other proceedings
including inter partes and ex parte reexaminations, International Trade
Commission proceedings, and Federal District Court and Circuit Court
proceedings in their briefs. (P.O. Cr. App. Br. 4.) An oral hearing of this
appeal transpired at the BP AI on October 19, 2011 and was transcribed.
A2
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
This proceeding arose from NVDIA's request for an inter partes
reexamination of the Rambus's patent, U.S. 6,591,353 Bl to Barth et al.,
Protocol For Communication with Dynamic Memory (July 8,22,2003).
Third-party Requestor NVIDIA appeals under 35 U.S.C. §§ l34(b) and 306
from the Examiner's Right of Appeal Notice (RAN) confirming claims 2-4,
6,8-10, 12, 13, 15-18,20-22 and 24-26 of the '353 patent under
reexamination. (See Req. App. Br. 3, 5 (appealing claims 1-26).) Patent
Owner Rambus cross-appeals from the Examiner's RAN finally rejecting
claims 1,5,7,11,14,19 and 23. (P.O. Cr. App. Br. 5.) RequestorNVIDIA
and Patent Owner Rambus also filed Respondent Briefs (Req. Resp. Br.;
P.O. Resp. Br.) and Rebuttal Briefs (Req. Reb. Br.; P.O. Reb. Br.) We have
jurisdiction under 35 U.S.C. 35 U.S.C. §§ 6, l34, and 315.
We AFFIRM-IN-PART, affirming the Examiner's decision to
maintain the rejection of claims 1, 5, 7, 11, 14, 19, and 23 cross-appealed by
Rambus, and reversing the Examiner's decision not to reject claims 1-26
appealed by NVIDIA. We decline to reach some of the proposed rejections.
STATEMENT OF THE CASE
Rambus refers to several related judicial and other proceedings
including inter partes and ex parte reexaminations, International Trade
Commission proceedings, and Federal District Court and Circuit Court
proceedings in their briefs. (P.O. Cr. App. Br. 4.) An oral hearing of this
appeal transpired at the BP AI on October 19, 2011 and was transcribed.
D
Case: 13-1623 Document: 10 Page: 38 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
The '353 Patent (Factual Findings)
Pl. The '353 patent states that the "present invention relates to
dynamic random access memory (DRAM), and more specifically to a
method and apparatus for controlling data transfers to and from a dynamic
random access memory." (Col. I,ll. 11-14.) More generally, "[t]he present
invention provides a method and apparatus for performing data transfers
within a computer system." (Col. 3, 11. 63-64.) "A memory device reads ...
control information on the bus." (Col. 4, 11. 6-7.)
P2. The '353 patent describes a related prior art system at Figure 4
which sends data in packets to memory: "The request packet format ...
communicate [ s] between master devices, such as processors, and slave
devices, such as memories." (Col. 2, 11. 49-52.) Figures 2 and 4 are
reproduced below:
Processor
f"
or
"'"
t---
2: Memory , .
,.,..
Controller ....
k

r
!
I
io-...... -----
DRAM
Row Address ]
1

l
Sen se/Resto re
t
-1
Column Address Column Amplifiers
I
r
 

!
RAS leAS
TransmitIReceive ....-:1-
j Control
................ \
---
...........
Address
,\
. ......,--_. \----
Data
...... *:
Figure 2
(Prior Art)
3
\
A3
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
The '353 Patent (Factual Findings)
Pl. The '353 patent states that the "present invention relates to
dynamic random access memory (DRAM), and more specifically to a
method and apparatus for controlling data transfers to and from a dynamic
random access memory." (Col. 1,11. 11-14.) More generally, "[t]he present
invention provides a method and apparatus for performing data transfers
within a computer system." (Col. 3,11. 63-64.) "A memory device reads ...
control information on the bus." (Col. 4, 11. 6-7.)
P2. The '353 patent describes a related prior art system at Figure 4
which sends data in packets to memory: "The request packet format ...
communicate[s] between master devices, such as processors, and slave
devices, such as memories." (Col. 2, 11. 49-52.) Figures 2 and 4 are
reproduced below:
r---1
,----
Processor
~ ~ ±
or
Memot)'
Controller
""i--" ...r-
~
T
~
l
fo---+----------
DRAM
Row Addre.$$ ]
1
Memory Core
l
Sen seARestore ~
-4 Column Address· Column AmplifJers
I
• I ~ I ReadJWrtte -
RAS I CAS TransmitIRecelve . .   : ~
j Control
........... ................ \ ..
-
Address
,\
. ......,......_. \-.---
Data
...... * :,
Figure 2
(Prior Art)
3
D
\
Case: 13-1623 Document: 10 Page: 39 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
CPU DRAM
------
BUS IN1EHFACE 1M' BUS iNTERFACE
RESETOliT
.JI
I I
I ! !
I
I
I
r
I
... 1
I

I
- - "1-
r
1-
- -
+
I !
I

I
I
---4
-
Rtf
i
i
._l ...

-
i
i
i
!
,
i
i
I
1
DRAM DRAM
BUS INTERFACE Rll) BUS INTERFACE IRfTl
!L
I
!
!
I L
I
! I
!
I
,
! 1
--
!
I
I
- ...
i
- -..
t
-
- -
I
LLLr -------------· .. --1

II
i
Figure 4
(Prior Art)
I
1 i
I I
-j--+----
i
+.
_.
1
,
....... ••• nL ••• __
c--
RESETIN
aUSDATA!8j



BUSDATA [1]
BUSOATAIOJ
BuseR
BUS ENABLE
CLOCKt
CLOCK2
VREF
GND
VOD
Both figures depicted above show a DRAM device connected to a bus
via a "bus interface of the DRAM receiver" (col. 2, 1. 65). (The depicted
interface "RlT" in Figure 4 implies a receiver/transmitter - see infra P4.)
The '353 patent also refers to communication between "slave devices
coupled to the bus" connected to the bus lines. (Col. 2, 11. 53-59.)
P3. The '353 patent disclaims any implied claim limitations based on
disclosed embodiments:
In the foregoing specification, the invention has been
described with reference to specific embodiments thereof. It
will, however, be evident that various modifications and
changes may be made thereto without departing from the
broader spirit and scope of the invention. The specification and
4
A4
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
GPU DRAM
   
EiM BUS iNTERFACE RtT
RESET OUT
-.J III I I! II
!
l'
I 11 I
, nl,.,

-:. I
- -
-
I
I ! I
I
i
I
!

!
,
I
-
!
i
1
-
DRA.M DRAM
BUS INTERFACE 1i<T) BUSINTERFACEIRm
!! II !
!
!! ! I I
f---
! I
I
,
I:
!
!
-= ...
,
-.
..!J -
t
-
- -., -
-+
--------------"--; +1
!
Figure 4
(Prior Art)
I I
1
.. ..........
I
l
-1---1----
!
f.
_.
1
..
.
RESETIN
BUSDATAjllJ
SUSDAlA til
BUSD/HAIO]
BUSCTl
6USENABLE
CLOCKt
CLQCIQ
VREF
GND
vOD
Both figures depicted above show a DRAM device connected to a bus
via a "bus interface of the DRAM receiver" (col. 2, 1. 65). (The depicted
interface "RlT" in Figure 4 implies a receiver/transmitter - see infra P4.)
The '353 patent also refers to communication between "slave devices
coupled to the bus" connected to the bus lines. (Col. 2, 11. 53-59.)
P3. The '353 patent disclaims any implied claim limitations based on
disclosed embodiments:
In the foregoing specification, the invention has been
described with reference to specific embodiments thereof. It
will, however, be evident that various modifications and
changes may be made thereto without departing from the
broader spirit and scope of the invention. The specification and
4
D
Case: 13-1623 Document: 10 Page: 40 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
drawings are accordingly, to be regarded in an illustrative rather
than a restrictive sense.
(Col. 24, 11. 3-9.)
P4. In addition to memory arrays, the memory devices in the
'353 patent comprise control logic 1910, a receiver 620, a transmitter 616,
and a clock generator 618. (See Fig. 6, col. 5, 1.61 to col. 6, 1. 20.)
Definitions
D. A "device" is defined as "[a] circuit or logical group of circuits
resident on one or more boards capable of interacting with other such
devices through the bus." IEEE Standard Dictionary of Electrical and
Electronics Terms 257 (1988). (Req. Resp. Br. 5 (citing Ex. 7).)
E. A "DRAM" definition follows:
A volatile store in which the fundamental storage devices are
capacitors arranged in matrix formation. Associated with each capacitor are
field-effect transistors which act as switches when data is put into the store
or withdrawn from it. To prevent loss of data as the capacitors discharge
through the inevitable leakage paths, their charges are regularly 'topped up'
- a process known as refreshing. Despite the need for refreshing the
dynamic RAM is simpler, more compact and cheaper than a static RAM
and, although its speed is lower, is more widely used.
Newnes Dictionary of Electronics, Newnes (1999) at
http://www.credoreference.com!entry Ibhelecl dynamic_random_access_mem
ory_dram (last visited Oct. 20, 2011) (emphasis added).
The Claims
Exemplary claims of the '353 patent under reexamination follow:
1. A method of operation in a memory device that includes a plurality
of memory cells, the method comprising:
receiving a command to sample data;
5
A5
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
drawings are accordingly, to be regarded in an illustrative rather
than a restrictive sense.
(Col. 24, 11. 3-9.)
P4. In addition to memory arrays, the memory devices in the
'353 patent comprise control logic 1910, a receiver 620, a transmitter 616,
and a clock generator 618. (See Fig. 6, col. 5,1.61 to col. 6,1. 20.)
Definitions
D. A "device" is defined as "[a] circuit or logical group of circuits
resident on one or more boards capable of interacting with other such
devices through the bus." IEEE Standard Dictionary of Electrical and
Electronics Terms 257 (1988). (Req. Resp. Br. 5 (citing Ex. 7).)
E. A "DRAM" definition follows:
A volatile store in which the fundamental storage devices are
capacitors arranged in matrix formation. Associated with each capacitor are
field-effect transistors which act as switches when data is put into the store
or withdrawn from it. To prevent loss of data as the capacitors discharge
through the inevitable leakage paths, their charges are regularly 'topped up'
- a process known as refreshing. Despite the need for refreshing the
dynamic RAM is simpler, more compact and cheaper than a static RAM
and, although its speed is lower, is more widely used.
Newnes Dictionwy qf Hlectronics, Newnes (1999) at
http://www.credoreference.com/entry/bhelec/dynamic_random_access_mem
ory_dram (last visited Oct. 20, 2011 ) (emphasis added).
The Claims
Exemplary claims of the '353 patent under reexamination follow:
1. A method of operation in a memory device that includes a plurality
of memory cells, the method comprising:
receiving a command to sample data;
5
D
Case: 13-1623 Document: 10 Page: 41 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
deferring sampling a first portion of the data until an external strobe
signal is detected; and
sampling the first portion of the data from an external signal line in
response to detecting the external strobe signal.
2. The method of claim 1, wherein the first portion of the data is
sampled synchronously with respect to an external clock signal.
5. The method of claim 1, further comprising:
detecting an external terminate signal; and
sampling additional portions of the data during a time interval
between detection of the external strobe signal and detection of the external
terminate signal.
11. A method of controlling a memory device that includes a plurality
of memory cells, the method comprising:
issuing a first write command to the memory device, the memory
device being configured to defer sampling data that corresponds to the first
write command until a strobe signal is detected;
delaying for a first time period after issuing the write command; and
after delaying for the first time period, issuing the strobe signal to the
memory device to initiate sampling of a first portion of the data by the
memory device.
19. A memory device having a plurality of memory cells, the memory
device comprising:
a plurality of input receiver circuits to receive a write command and
sample data that corresponds to the write command in response to detecting
a strobe signal that is delayed relative to the write command by a first time
period.
PRINCIPLES OF LAW
In reexaminations of non-expired patents, claims are given the
"broadest reasonable construction consistent with the specification." See
In re Yamamoto, 740 F.2d 1569, 1571 (Fed. Circ. 1984) (not addressing
expired patents). In all cases, "the words of a claim 'are generally given
6
A6
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
deferring sampling a first portion of the data until an external strobe
signal is detected; and
sampling the first portion of the data from an external signal line in
response to detecting the external strobe signal.
2. The method of claim 1, wherein the first portion of the data is
sampled synchronously with respect to an external clock signal.
5. The method of claim 1, further comprising:
detecting an external terminate signal; and
sampling additional portions of the data during a time interval
between detection of the external strobe signal and detection of the external
terminate signal.
11. A method of controlling a memory device that includes a plurality
of memory cells, the method comprising:
issuing a first write conmland to the memory device, the memory
device being configured to defer sampling data that corresponds to the first
write command until a strobe signal is detected;
delaying for a first time period after issuing the write command; and
after delaying for the first time period, issuing the strobe signal to the
memory device to initiate sampling of a first portion ofthe data by the
memory device.
19. A memory device having a plurality of memory cells, the memory
device comprising:
a plurality of input receiver circuits to receive a write command and
sample data that corresponds to the write command in response to detecting
a strobe signal that is delayed relative to the write command by a first time
period.
PRINCIPLES OF LAW
In reexaminations of non-expired patents, claims are given the
"broadest reasonable construction consistent with the specification." See
In re Yamamoto, 740 F.2d 1569, 1571 (Fed. Circ. 1984) (not addressing
expired patents). In all cases, "the words of a claim 'are generally given
6
D
Case: 13-1623 Document: 10 Page: 42 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
their ordinary and customary meaning'" Phillips v. AWH Corp., 415 F.3d
1303, 1312 (Fed. Cir. 2005) (en banc) (internal citations omitted), with the
caveat that claims "must be read in view of the specification .... [T]he
specification 'is always highly relevant to the claim construction analysis.
Usually, it is dispositive; it is the single best guide to the meaning of a
disputed term. '" Id. at 1315 (Fed. Cir. 2005) (en banc) (citation omitted).
"Even when the specification describes only a single embodiment, the
claims of the patent will not be read restrictively unless the patentee has
demonstrated a clear intention to limit the claim scope using 'words or
expressions of manifest exclusion or restriction'." Leibel-Flarsheim Co. v.
Medrad, Inc., 358 F.3d 898, 906 (Fed. Cir. 2004) (citation omitted). "We
have cautioned against reading limitations into a claim from the preferred
embodiment described in the specification, even it is the only embodiment
described, absent clear disclaimer in the specification." In re Am. Acad. Of
Science Tech. Ctr., 367 F.3d 1359, 1369 (Fed. Cir. 2004).
RAMBUS's CROSS APPEAL
Rejection on Cross-Appeal
Claims 1,5,7, 11, 14, 19, and 23 as anticipated under 35 U.S.C.
§ 102(b) based Hayes et aI., U.S. Patent 5,218,684 (June 8,1993) ("Hayes").
Issues
Patent owner Rambus contends that Hayes does not disclose sending a
strobe signal or a terminate signal to a memory device, which according to
7
A7
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
their ordinary and customary meaning'" Phillips v. AWH Corp., 415 F.3d
l303, l3l2 (Fed. Cir. 2005) (en bane) (internal citations omitted), with the
caveat that claims "must be read in view of the specification .... [T]he
specification 'is always highly relevant to the claim construction analysis.
Usually, it is dispositive; it is the single best guide to the meaning of a
disputed term. '" Id. at 1315 (Fed. Cir. 2005) (en bane) (citation omitted).
"Even when the specification describes only a single embodiment, the
claims of the patent will not be read restrictively unless the patentee has
demonstrated a clear intention to limit the claim scope using 'words or
expressions of manifest exclusion or restriction'." Leibel-Flarsheim Co. v.
Medrad, Inc., 358 F.3d 898, 906 (Fed. Cir. 2004) (citation omitted). "We
have cautioned against reading limitations into a claim from the preferred
embodiment described in the specification, even it is the only embodiment
described, absent clear disclaimer in the specification." In re Am. Acad. Of
Science Tech. Ctr., 367 F.3d l359, l369 (Fed. Cir. 2004).
RAMBUS's CROSS APPEAL
Rejection on Cross-Appeal
Claims 1, 5,7, 11, 14, 19, and 23 as anticipated under 35 U.S.c.
§ 102(b) based Hayes et al., U.S. Patent 5,218,684 (June 8, 1993) ("Hayes").
Issues
Patent owner Rambus contends that Hayes does not disclose sending a
strobe signal or a terminate signal to a memory device, which according to
7
D
Case: 13-1623 Document: 10 Page: 43 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
Rambus, must be a single chip (see e.g., P.O. Cr. App. Br. 11, 16,28-30),
thereby raising the following issues:
Did Rambus demonstrate the Examiner erred in finding that Hayes
anticipates claims 1, 11, and 23 which recite a strobe signal and a memory
device?
Did Rambus demonstrate the Examiner erred in finding that Hayes
anticipates claims 5, 14, and 24 which require sampling additional data
portions between a strobe and terminate signal?
Hayes -Factual Findings
HI. Figure 2 from Hayes is depicted below:
FIG. 2
i l'fWo/IIf!6I :

mEs w¢
   
I
! ILlS COI<ITMl 1
!.
  &!1!r!9: ----i
j I
i--- --l
:
ita
i
Figure 2 shows the slave (i.e., a memory board - see infra H5)
controlled, inter alia, by a write signal and a data strobe (DS) signal (see
infra H2) from the bus master via local data and address lines <31 :0>.
8
A8
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Rambus, must be a single chip (see e.g., P.O. Cr. App. Br. 11, 16,28-30),
thereby raising the following issues:
Did Rambus demonstrate the Examiner erred in finding that Hayes
anticipates claims 1, 11, and 23 which recite a strobe signal and a memory
device?
Did Rambus demonstrate the Examiner erred in finding that Hayes
anticipates claims 5, 14, and 24 which require sampling additional data
portions between a strobe and terminate signal?
Hayes -Factual Findings
HI. Figure 2 from Hayes is depicted below:
FIG. 2
, UIPllAMI.TtON :
WEB {li£)j
r ..    
, IUS !lIJ<ITOO.. I
!
r--- ---1
1 I
 
i
:* :
I -----<
SYaTe! wmIQL
Figure 2 shows the slave (i.e., a memory board - see infi"a H5)
controlled, inter alia, by a write signal and a data strobe (DS) signal (see
infra H2) from the bus master via local data and address lines <31 :0>.
8
D
Case: 13-1623 Document: 10 Page: 44 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
The bus master depicted refers to either the processor 10 or chip 16.
(See Fig. 1 and col. 14, 11. 16-20.)
H2. In reference to Figure 2 supra, a general description of the master
(bus controller) and slave (memory) communication follows:
For a write cycle, "[t]he bus master ... drives data onto
DAL 31:0] and asserts DS [data strobe col. 7, 1. 56], indicating
that the data is valid on DAL [31:0]. Ifno error occurs, the
slave device reads the data, and the external logic asserts RDY.
If an error occurs, external logic asserts ERR, which aborts the
bus cycle. This causes the processor 10 to execute a machine
check. Finally, the bus master deasserts AS and DS to end the
cycle."
(Col. 9, 11. 58-65.)
More specifically, Hayes describes how the assertion and deassertion
of the DS (data strobe) provides timing for read and write operations as
follows:
The Data Strobe line (DS) provides timing information
for data transfers. During a read cycle or an interrupt
acknowledged cycle, the bus master asserts DS to indicate that
it is ready to receive incoming data. The bus master then
deasserts DS to indicate that it has received and latched the
incoming data. During a write cycle, the bus master asserts DS
to indicate that DAL [31 :0] contains valid write data. The bus
master then deasserts DS to indicate that it is about to remove
the write data from DAL [31 :0].
(Col. 7, 11. 56-65.)
H3. External logic asserts the ERR function "whenever a parity error
occurs on a read from a local RAM 13, provided that parity is enabled."
(Col. 11, 11. 33-35). The ERR function indicates "the abnormal termination
of a read, write or interrupt acknowledge cycle." (Col. 8, 11. 9-11.)
9
A9
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
The bus master depicted refers to either the processor 10 or chip 16.
(See Fig. 1 and col. 14,11. 16-20.)
H2. In reference to Figure 2 supra, a general description of the master
(bus controller) and slave (memory) communication follows:
For a write cycle, "[t]he bus master ... drives data onto
DAL 31:0] and asserts DS [data strobe col. 7, I. 56], indicating
that the data is valid on DAL [31 :0]. If no error occurs, the
slave device reads the data, and the external logic asserts RDY.
If an error occurs, external logic asserts ERR, which aborts the
bus cycle. This causes the processor 10 to execute a machine
check. Finally, the bus master deasserts AS and DS to end the
cycle."
(Col. 9, 11. 58-65.)
More specifically, Hayes describes how the assertion and deassertion
of the DS (data strobe) provides timing for read and write operations as
follows:
The Data Strobe line (DS) provides timing infommtlon
for data transfers. During a read cycle or an interrupt
acknowledged cycle, the bus master asserts DS to indicate that
it is ready to receive incoming data. The bus master then
deasserts DS to indicate that it has received and latched the
incoming data. During a write cycle, the bus master asserts DS
to indicate that DAL [31 :0] contains valid write data. The bus
master then deasserts DS to indicate that it is about to remove
the write data from DAL [31 :0].
(Col. 7, 11. 56-65.)
H3. External logic asserts the ERR function "whenever a parity error
occurs on a read from a local RAM 13, provided that parity is enabled."
(Col. 11, 11. 33-35). The ERR function indicates "the abnormal termination
of a read, write or interrupt acknowledge cycle." (Col. 8, II. 9-11.)
9
D
Case: 13-1623 Document: 10 Page: 45 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
H4. Bus master read and write cycles typically last at least eight clock
phases, with longer intervals possible in groups of four clock cycles.
During the write cycle, the bus master drives an address onto DAL (data and
address lines) and outputs data to the slave memory device at the end of the
write cycle. (Col. 7, 11. 3-6; col. 9, 11. 33-65.)
H5. In addition to the "slave device" as a memory board (see col. 7,
1. 36, 1. 44, HI), the" daisy chained memory array boards 15" (col. 5, 1. 5
(emphasis added)) are also described as "devices" as follows: "The term
'daisy chain' in the system of the present invention implies ... sequentially
connecting a series of devices such that the output connection of device one
is the input connection of device two ... and so on .... A 'memory node' ...
refers to the points at which a device may be connected." (Col. 2, 11. 33-43
(emphasis added).) Also, communication occurs "between any two devices
on the local bus 17 ... within a master/slave relationship." (Col. 6,11. 14-16
(emphasis added).) (The memory array boards 15 are on a bus 21 which "is
an off-board extension of the local bus 17." (Col. 5, 11. 3-5).)
H6. Communication between the master and slave devices is time
multiplexed. The time-multiplexed data and address lines (32 lines) on the
local bus (see Figs. 1 and 2 (copied supra HI)) carry address information
transmitted first to the slave device, followed by data, during a read or write
cycle. Data can be 8 bits ( one byte) 16 bits (one word), 32 bits (one
longword), or 64 bits (one quad word.) (Col. 6, 11. 9-63; col. 7, 11. 3-6.)
H7. Figure 7 depicts the components resident on the slave memory
board 15 (depicted in Fig. 2, HI supra). Figure 7 shows 32 "DAL 31:00"
(data and address lines) external to the slave memory board (see HI supra)
directly connected to an on-board transceiver (interface) 57, which directly
10
A10
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
H4. Bus master read and write cycles typically last at least eight clock
phases, with longer intervals possible in groups of four clock cycles.
During the write cycle, the bus master drives an address onto DAL (data and
address lines) and outputs data to the slave memory device at the end of the
write cycle. (Col. 7, 11. 3-6; col. 9, 11. 33-65.)
H5. In addition to the "slave device" as a memory board (see col. 7,
1. 36, 1. 44, HI), the "daisy chained memory array boards 15" (col. 5, 1. 5
(emphasis added)) are also described as "devices" as follows: "The term
'daisy chain' in the system of the present invention implies ... sequentially
connecting a series of devices such that the output connection of device one
is the input connection of device two ... and so on .... A 'memmy node' ...
refers to the points at which a device may be connected." (Col. 2, 11. 33-43
(emphasis added).) Also, communication occurs "between any two devices
on the local bus 17 ... within a master/slave relationship." (Col. 6,11. 14-16
(emphasis added).) (The memory array boards 15 are on a bus 21 which "is
an off-board extension of the local bus 17." (Col. 5,11. 3-5).)
H6. Communication between the master and slave devices is time
multiplexed. The time-multiplexed data and address lines (32 lines) on the
local bus (see Figs. 1 and 2 (copied supra H 1)) carry address in fonnati on
transmitted first to the slave device, followed by data, during a read or write
cycle. Data can be 8 bits ( one byte) 16 bits (one word), 32 bits (one
longword), or 64 bits (one quad word.) (Col. 6,11.9-63; col. 7, 11. 3-6.)
H7. Figure 7 depicts the components resident on the slave memory
board 15 (depicted in Fig. 2, HI supra). Figure 7 shows 32 "DAL 31:00"
(data and address lines) external to the slave memory board (see HI supra)
directly connected to an on-board transceiver (interface) 57, which directly
10
D
Case: 13-1623 Document: 10 Page: 46 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
connects to 32 on-board data and address lines "DATA <31:0>," which
directly connects to on-board RAM chips 64. The DS signal connects to
RAM control logic 62 on the slave memory board. (Fig. 7; col. 22, 11. 10-15;
col. 24, 11. 21-27.)
Hayes - Anticipation of Claims 1, 7, 11, and 19
Rambus argues independent claims 1, 11, and 19 together, asserting
that Hayes does not disclose a "memory device," because the memory
device in Hayes, a memory board, is not a single chip. (P.O. Cr. App. 12-
28.) However, claims 1 and 19 only recite a "memory device" in their
respective preambles. Claims typically are not limited by such preamble
recitations. Claim 1 does not refer back to the memory device in the body of
the claim. Thus, under one claim interpretation here, claim 1 does not
require a memory device. Similarly, claim 19 recites a memory device in
the preamble which comprises, according to the claim body, receiver circuits
having functional limitations. The body of claim 11 recites "the memory
device" and refers back to the preamble's "memory device." Consequently,
under the claim interpretation noted, Rambus' s arguments directed to the
asserted lack of a memory device as a single chip are deemed to apply only
to claim 11. The second claim interpretation assumes, for the sake of
argument, that all the claims require a memory device. That second
interpretation follows.
Requestor NVIDIA's contentions and the Examiner's findings
persuasively show that neither the plain and ordinary meaning of "memory
device," nor the '353 patent, requires a "memory device" to be limited to a
single chip so as to preclude reading the independent claims onto the
memory board of Hayes. The record also reveals no error in the finding that
11
A11
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
connects to 32 on-board data and address lines "DATA <31:0>," which
directly connects to on-board RAM chips 64. The DS signal connects to
RAM control logic 62 on the slave memory board. (Fig. 7; col. 22, 11. 10-15;
col. 24, 11. 21-27.)
Hayes - Anticipation (?fClaims I, 7, II, and 19
Rambus argues independent claims 1, 11, and 19 together, asserting
that Hayes does not disclose a "memory device," because the memory
device in Hayes, a memory board, is not a single chip. (P.O. Cr. App. 12-
28.) However, claims 1 and 19 only recite a "memory device" in their
respective preambles. Claims typically are not limited by such preamble
recitations. Claim 1 does not refer back to the memory device in the body of
the claim. Thus, under one claim interpretation here, claim 1 does not
require a memory device. Similarly, claim 19 recites a memory device in
the preamble which comprises, according to the claim body, receiver circuits
having functional limitations. The body of claim 11 recites "the memory
device" and refers back to the preamble's "memory device." Consequently,
under the claim interpretation noted, Rambus' s arguments directed to the
asserted lack of a memory device as a single chip are deemed to apply only
to claim 11. The second claim interpretation assumes, for the sake of
argument, that all the claims require a memory device. That second
interpretation follows.
Requestor NVIDIA's contentions and the Examiner's findings
persuasively show that neither the plain and ordinary meaning of "memory
device," nor the '353 patent, requires a "memory device" to be limited to a
single chip so as to preclude reading the independent claims onto the
memory board of Hayes. The record also reveals no error in the finding that
11
D
Case: 13-1623 Document: 10 Page: 47 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
Hayes's DS signal constitutes a strobe signal as recited in the disputed
claims.
Mr. Murphy, Rambus's expert, "read[s] the term 'memory device' in
the context of the specification and claims as a device that is implemented
on a single monolithic chip." (Murphy Decl. ,-r 33 (attached to Rambus
Cr. App. Br. at Ex. 9).) Mr. Murphy reasons that "the claims themselves are
directed to 'memory devices' and as such, their recited features define the
characteristics of a 'memory device. '" (Id. at,-r 34.) Mr. Murphy also
reasons that the claims require "an array of memory cells," and this feature
and others, "are typical of those specifically directed to a memory device on
a single monolithic chip." (Id.) Mr. Murphy also opines that skilled artisans
would have recognized that other portions of the '353 patent, such as the
specification and the abstract, indicate that memory devices are consistent
with a single chip. (Id. at ,-r,-r 35-37.) Mr. Murphy also points to a DRAM
with a unique device ID which "supports the understand [sic] that each
DRAM is a separate 'memory device'." (Id. at,-r 39.)
Mr. Murphy further opines that the Examiner's claim interpretation
(under which Hayes's memory board constitutes a memory device) is
"inconsistent with the specification and inconsistent with how that term
would have been understood by one of ordinary skill in the art." (Id. at
,-r 32.) Mr. Murphy makes a similar statement in his testimony about Hayes,
i.e., the Examiner's use "is also inconsistent with how the term is commonly
used in the DRAM field." (Id. at,-r 62.)
Mr. Murphy's bases his understanding on what someone "in the
DRAM field would understand the term 'memory device'" to be. (Murphy
Decl. ,-r62.) But the '353 patent is not limited to DRAM technology - just as
12
A12
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Hayes's DS signal constitutes a strobe signal as recited in the disputed
claims.
Mr. Murphy, Rambus's expert, "read[s] the term 'memory device' in
the context of the specification and claims as a device that is implemented
on a single monolithic chip." (Murphy Decl. ,-r 33 (attached to Rambus
Cr. App. Br. at Ex. 9).) Mr. Murphy reasons that "the claims themselves are
directed to 'memory devices' and as such, their recited features define the
characteristics of a 'memory device. ,,, (Id. at,-r 34.) Mr. Murphy also
reasons that the claims require "an array of memory cells," and this feature
and others, "are typical of those specifically directed to a memory device on
a single monolithic chip." (Id.) Mr. Murphy also opines that skilled artisans
would have recognized that other portions of the '353 patent, such as the
specification and the abstract, indicate that memory devices are consistent
with a single chip. (Id. at,-r,-r 35-37.) Mr. Murphy also points to a DRAM
with a unique device ID which "supports the understand [sic] that each
DRAM is a separate 'memory device'." (Id. at,-r 39.)
Mr. Murphy further opines that the Examiner's claim interpretation
(under which Hayes's memory board constitutes a memory device) is
"inconsistent with the specification and inconsistent with how that tenn
would have been understood by one of ordinary skill in the art." (Id. at
,-r 32.) Mr. Murphy makes a similar statement in his testimony about Hayes,
i.e., the Examiner's use "is also inconsistent with how the term is commonly
used in the DRAM field." (Id. at,-r 62.)
Mr. Murphy's bases his understanding on what someone "in the
DRAM field would understand the term 'memory device'" to be. (Murphy
Dec!. ,-r62.) But the '353 patent is not limited to DRAM technology - just as
12
D
Case: 13-1623 Document: 10 Page: 48 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
the memory device is not limited to a DRAM. For example, in other places,
Rambus implies that the relevant field is "memory systems, memory
controllers, and memory devices." (See Rambus Cr. App. Br. 21.) Similarly,
the '353 patent describes the invention even more broadly: "The present
invention provides a method and apparatus for performing data transfers
within a computer system." (PI) (emphasis added).) In other words, Mr.
Murphy's understanding is based on an overly narrow foundation.
Mr. Murphy's testimony may show that the term "memory device," as
used in the '353 patent, is consistent with a single DRAM chip, but it does
not show that the claims are limited to a single chip or that the Examiner's
interpretation of a memory device as a memory array board is inconsistent
with the '353 patent. NVIDIA relies, inter alia, upon an IEEE publication
defining "device" as including circuits on a board (D) to show that the
disputed claims read on Hayes's memory board pursuant to the ordinary and
plain meaning of the term. (Req. Resp. Br. 5; compare HI-H5 with D.)
Rambus's contentions notwithstanding, NVIDIA's contention has merit
because the IEEE definition coalesces with Hayes's memory board device;
and "does not contradict any definition found in" the '353 patent. See
Phillips, 415 F.3d at 1322-23 ("judges are free ... at any time ...
[to] ... rely on dictionary definitions when construing claim terms, so long
as the dictionary definition does not contradict any definition found in or
ascertained by a reading of the patent documents"). 1
1 Rambus argues that the Board should not consider the IEEE definition
because the proffer is "substantively improper" and "procedurally improper"
(P.O. App. Br. 21-22), but this argument runs counter to Phillips which
13
A13
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
the memory device is not limited to a DRAM. For example, in other places,
Rambus implies that the relevant field is "memory systems, memory
controllers, and memory devices." (See Rambus Cr. App. Br. 2l.) Similarly,
the '353 patent describes the invention even more broadly: "The present
invention provides a method and apparatus for performing data  
within a computer system." (PI) (emphasis added).) In other words, Mr.
Murphy's understanding is based on an overly narrow foundation.
Mr. Murphy's testimony may show that the term "memory device," as
used in the '353 patent, is consistent with a single DRAM chip, but it does
not show that the claims are limited to a single chip or that the Examiner's
interpretation of a memory device as a memory array board is inconsistent
with the '353 patent. NVIDIA relies, inter alia, upon an IEEE publication
defining "device" as including circuits on a board (D) to show that the
disputed claims read on Hayes's memory board pursuant to the ordinary and
plain meaning of the term. (Req. Resp. Br. 5; compare HI-H5 with D.)
Rambus's contentions notwithstanding, NVIDIA's contention has merit
because the IEEE definition coalesces with Hayes's memory board device;
and "does not contradict any definition found in" the '353 patent. See
Phillips, 415 F.3d at 1322-23 ("judges are free ... at any time ...
[to] ... rely on dictionary definitions when construing claim terms, so long
as the dictionary definition does not contradict any definition found in or
ascertained by a reading of the patent documents"). 1
1 Rambus argues that the Board should not consider the IEEE definition
because the proffer is "substantively improper" and "procedurally improper"
(P.O. App. Br. 21-22), but this argument runs counter to Phillips which
13
D
Case: 13-1623 Document: 10 Page: 49 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
Rambus also argues that the '353 patent describes connecting the bus
lines in Figure 4 to "each device" (P.O. Br. Cr. App. Br. 16) and that
Figure 4 depicts single chip devices such as DRAMs and CPUs (id. at 16-17
(also citing and quoting Murphy Decl. at,-r 38 and the '353 patent).) But
Figure 4 represents the prior art, not necessarily the invention, and also
shows interfaces, including RlT units, connected to the DRAMs and CPU s.
Figure 4 does not unequivocally limit a memory device as recited in the
claimed invention to a single chip memory device. Regardless of what
Figure 4 represents, claims typically are not limited to embodiments shown
in a figure. The '353 patent does not define a "memory device" as a chip as
NVIDIA maintains. (Req. Resp. Br. 6-9.)
The '353 patent broadly refers to "slave devices, such as memories."
(P2 (emphasis added).) In other words, even though the disclosure discusses
DRAMs, the disclosure is consistent with including as a slave device, a
typical slave memory, such as a slave memory board. Hayes supports this
general understanding in the art. (See HI, H2, H5.) Hayes describes "slave
invites judges at any time to consider such sources. Rambus relies upon, but
the Examiner apparently did not consider, Mr. Murphy's untimely second
supplemental declaration (countering the IEEE definition). (See P.O. Cr.
App. Br. 22-24 (citing Murphy 2
nd
SUpp. Decl. Ex. 15).) Rambus essentially
repeats Mr. Murphy's assertions in the noted declaration and argues that the
definition is relevant to electrical circuits but not relevant to the memory
arts, out of date, too general, too specific, too varied, untimely, and fails to
define a "memory device." (See P.O. App. Br. 21-25.) The definition,
published in 1988, corroborated by Hayes, and consistent with the '353
patent, is probative, even if it also applies to earlier systems as Mr. Murphy
maintains. (See Murphy 2
nd
SUpp. Decl. ,-r,-r 7-10.)
14
A14
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Rambus also argues that the '353 patent describes connecting the bus
lines in Figure 4 to "each device" (P.O. Br. Cr. App. Br. 16) and that
Figure 4 depicts single chip devices such as DRAMs and CPUs (id. at 16-17
(also citing and quoting Murphy Decl. at   38 and the '353 patent).) But
Figure 4 represents the prior art, not necessarily the invention, and also
shows interfaces, including RJT units, connected to the DRAMs and CPU s.
Figure 4 does not unequivocally limit a memory device as recited in the
claimed invention to a single chip memory device. Regardless of what
Figure 4 represents, claims typically are not limited to embodiments shown
in a figure. The '353 patent does not define a "memory device" as a chip as
NVIDIA maintains. (Req. Resp. Br. 6-9.)
The '353 patent broadly refers to "slave devices, such as memories."
(P2 (emphasis added).) In other words, even though the disclosure discusses
DRAMs, the disclosure is consistent with including as a slave device, a
typical slave memory, such as a slave memory board. Hayes supports this
general understanding in the art. (See HI, H2, H5.) Hayes describes "slave
invites judges at any time to consider such sources. Rambus relies upon, but
the Examiner apparently did not consider, My. Murphy's untimely second
supplemental declaration (countering the IEEE definition). (See P.O. Cr.
App. Br. 22-24 (citing Murphy 2
nd
Supp. Decl. Ex. 15).) Rambus essentially
repeats Mr. Murphy's assertions in the noted declaration and argues that the
definition is relevant to electrical circuits but not relevant to the memory
arts, out of date, too general, too specific, too varied, untimely, and fails to
define a "memory device." (See P.O. App. Br. 21-25.) The definition,
published in 1988, corroborated by Hayes, and consistent with the '353
patent, is probative, even if it also applies to earlier systems as Mr. Murphy
maintains. (See Murphy 2
nd
Supp. Decl.     7-10.)
14
D
Case: 13-1623 Document: 10 Page: 50 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
device[s]" as memory array boards (H5), thereby underscoring, in line with
Requestor's proposed definition (E), that the term "memory device,"
especially in reference to a slave device, carries a broad general
understanding in the art.
Requestor relies on this general understanding and refers to the Hayes
'''SLAVE' device" memory board in Figure 2 as a "memory device." (Req.
Resp. Br. 10-11; see HI, H5.) In the '353 patent and in Hayes, the slave
memory devices each have their own control logic and memory arrays, and
each slave device is tied to a bus node and responds to a master in a time
multiplexed fashion. (Compare H4-H7 with P2, P4.)
Moreover, the '353 patent unequivocally states that the disclosed
embodiments are to be construed as illustrative and not as limiting the
claims. (P3.) Rambus' s arguments here ignore that simple disclosure and
attempt to read the DRAM embodiment as limiting. Carrying such
arguments to their logical conclusion would require limiting the claims to
other disclosed features and lead to absurd results. For example, the
'353 patent describes four memory banks, two queues, control circuitry, and
an I/O unit (see Fig. 20A) in one memory device embodiment and a slew of
advantageous functional capabilities seemingly important to the invention.
(Accord Murphy Decl. ,-r,-r 19-20, 24, 35, 39 (describing interleave control,
control and data decoupling, control circuits for pre charging, internal
interface clocks, four memory banks, and a unique device ID, as part of the
disclosed memory device's functionality to provide various benefits and
improved ability).)
Interpreting analogous claim terms involving a related Rambus patent,
Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081,1094-95 (Fed.
15
A15
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
device[sJ" as memory array boards (H5), thereby underscoring, in line with
Requestor's proposed definition (E), that the term "memory device,"
especially in reference to a slave device, carries a broad general
understanding in the art.
Requestor relies on this general understanding and refers to the Hayes
"'SLA VE' device" memory board in Figure 2 as a "memory device." (Req.
Resp. Br. 10-11; see HI, H5.) In the '353 patent and in Hayes, the slave
memory devices each have their own control logic and memory arrays, and
each slave device is tied to a bus node and responds to a master in a time
multiplexed fashion. (Compare H4-H7 with P2, P4.)
Moreover, the '353 patent unequivocally states that the disclosed
embodiments are to be construed as illustrative and not as limiting the
claims. (P3.) Rambus's arguments here ignore that simple disclosure and
attempt to read the DRAM embodiment as limiting. Carrying such
arguments to their logical conclusion would require limiting the claims to
other disclosed features and lead to absurd results. For example, the
'353 patent describes four memory banks, two queues, control circuitry, and
an 1/0 unit (see Fig. 20A) in one memory device embodiment and a slew of
advantageous functional capabilities seemingly important to the invention.
(Accord Murphy Dec!. ,-r,-r 19-20, 24, 35, 39 (describing interleave control,
control and data decoupling, control circuits for precharging, internal
interface clocks, four memory banks, and a unique device ID, as part of the
disclosed memory device's functionality to provide various benefits and
improved ability).)
Interpreting analogous claim terms involving a related Rambus patent,
Rambus Inc. v.lnfineon Technologies AG, 318 F.3d 1081,1094-95 (Fed.
15
D
Case: 13-1623 Document: 10 Page: 51 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
Cir. 2003) refused to read the ordinary term "bus" restrictively as a
"multiplexed bus" even though the patentee described the "present
invention" in terms of a "multiplexed bus" in isolated portions of the
specification because "the remainder of the specification and the prosecution
history shows that Rambus did not clearly disclaim or disavow such claim
scope in this case.,,2 And in a related example, the '353 patent refers to
"[d]ynamic random access memory (DRAM) components . .. [as]
inexpensive solid-state storage technology for today's computer systems."
(Col. I,ll. 18-19.) Under Rambus's theory of limiting claims based on
preferred or sole disclosed embodiments, a memory component, which
includes a DRAM, would also be limited to a single chip.
Nowhere does the '353 patent unequivocally restrict a "memory
device" to a DRAM or a single chip. The '353 patent does not
"demonstrate[] a clear intention to limit the claim scope using 'words of
manifest exclusion or restriction'." See Leibel-Flarsheim Co., 358 F .3d at
906; accord In re Bigio, 381 F.3d 1320, 1325 (Fed. Cir. 2004) ("Absent
claim language carrying a narrow meaning, the PTO should only limit the
claim based on the specification or prosecution history when those sources
expressly disclaim the broader definition. "). There is no "clear disclaimer in
the specification," Am. Acad. Of Science Tech. Ctr., 367 F.3d at 1369, and
2 Also stating that '" [t]he present invention is designed to provide a high
speed, multiplexed bus "'(quoting Rambus's related '918 patent, col. 5,11.
36-46), but "the prosecution history shows that a multiplexing bus is only
one of many inventions disclosed in the '898 application." Id.
16
A16
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Cir. 2003) refused to read the ordinary term "bus" restrictively as a
"multiplexed bus" even though the patentee described the "present
invention" in terms of a "multiplexed bus" in isolated portions of the
specification because "the remainder of the specification and the prosecution
history shows that Rambus did not clearly disclaim or disavow such claim
scope in this case.,,2 And in a related example, the '353 patent refers to
"[d]ynamic random access memory (DRAM) components . .. [as]
inexpensive solid-state storage technology for today's computer systems."
(Col. I,ll. 18-19.) Under Rambus's theory oflimiting claims based on
preferred or sole disclosed embodiments, a memory component, which
includes a DRAM, would also be limited to a single chip.
Nowhere does the '353 patent unequivocally restrict a "memory
device" to a DRAM or a single chip. The '353 patent does not
"demonstrate[] a clear intention to limit the claim scope using 'words of
manifest exclusion or restriction'." See Leibel-Flarsheim Co., 358 F.3d at
906; accord In re Bigio, 381 F.3d 1320, 1325 (Fed. Cir. 2004) ("Absent
claim language carrying a narrow meaning, the PTO should only limit the
claim based on the specification or prosecution history when those sources
expressly disclaim the broader definition."). There is no "clear disclaimer in
the specification," Am. Acad. Of Science Tech. etr., 367 F.3d at l369, and
2 Also stating that "'[t]he present invention is designed to provide a high
speed, multiplexed bus '''(quoting Rambus's related '918 patent, col. 5, ll.
36-46), but "the prosecution history shows that a multiplexing bus is only
one of many inventions disclosed in the '898 application." Id.
16
D
Case: 13-1623 Document: 10 Page: 52 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
the claims do not "bear only one interpretation.,,3 The ultimate purpose of
the '353 patent is to maximize utilization of the channel over which
communications are to be performed- i.e., increase the computer speed by
interleaving the data packets over the bus to multiple devices thereon. (See
'353 patent Abstract; accord PI).) Limiting the open-ended claims to a
single memory chip is without support, as is limiting them to the disclosed
DRAM chip embodiment.
Claim 19 defines the memory device recited in the preamble as
comprising a plurality of receiving circuits to handle write and strobe
functions. NV1D1A contends (see Inter partes Request for Reexamination
18-19 "LP. Request"), and the Examiner finds (Action Closing Prosecution
1-16), that Hayes's memory board in Figure 7 comprises the recited
receiving circuits performing the recited functions, and Rambus does not
particularly dispute that finding (see P.O. Cr. App. Br. 18) other than to
assert that the Hayes's device is not a chip and does not receive a strobe
3 Johnson Worldwide Assocs., Inc. v. Zebco Corp., 175 F.3d 985, 991 (Fed.
Circ. 1999) (distinguishing Laitram Corp. v. Morehouse Industries, Inc., 143
F.3d 1456 (Fed. Cir. 1988) as involving a "written description that made
clear that 'the asserted claims will bear only one interpretation .... ' Here of
course, there is no such unambiguous language in the written description;
nothing suggests that 'heading' is required to be the heading of the trolling
motor."). See also Edwards Life Sciences LLC v. Cook Inc. , 582 F.3d 1322,
1329 (2009) (holding that the consistent interchanging of "interluminal graft
1 0" with "graft 1 0" in the patent and use of the phrase, "as defined above,"
created a narrowing definition of graft to mean an interluminal graft). "[1]f
the intrinsic evidence shows that the patentee distinguished that term from
prior art on the basis of a particular embodiment, expressly disclaimed
subject matter, or described a particular embodiment as important to the
invention." Id. at 1329. (citation omitted).
17
A17
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
the claims do not "bear only one interpretation.,,3 The ultimate purpose of
the '353 patent is to maximize utilization of the channel over which
communications are to be performed- i.e., increase the computer speed by
interleaving the data packets over the bus to multiple devices thereon. (See
'353 patent Abstract; accord PI).) Limiting the open-ended claims to a
single memory chip is without support, as is limiting them to the disclosed
D RAM chip embodiment.
Claim 19 defines the memory device recited in the preamble as
comprising a plurality of receiving circuits to handle write and strobe
functions. NVID1A contends (see Inter partes Request for Reexamination
18-19 "LP. Request"), and the Examiner finds (Action Closing Prosecution
1-16), that Hayes's memory board in Figure 7 comprises the recited
receiving circuits perfoffiling the recited functions, and Rambus does not
particularly dispute that finding (see P.O. Cr. App. Br. 18) other than to
assert that the Hayes's device is not a chip and does not receive a strobe
3 Johnson Worldwide Assocs., Inc. v. Zebco Corp., 175 F.3d 985,991 (Fed.
Circ. 1999) (distinguishing Laitram Corp. v. Morehouse Industries, Inc., 143
F.3d 1456 (Fed. Cir. 1988) as involving a "written description that made
clear that 'the asserted claims will bear only one interpretation .... ' Here of
course, there is no such unambiguous language in the written description;
nothing suggests that 'heading' is required to be the heading of the trolling
motor."). See also Edwards Life Sciences LLC v. Cook Inc. , 582 F.3d l322,
l329 (2009) (holding that the consistent interchanging of "interluminal graft
10" with "graft 10" in the patent and use of the phrase, "as defined above,"
created a narrowing definition of graft to mean an interluminal graft). "[1]f
the intrinsic evidence shows that the patentee distinguished that term from
prior art on the basis of a particular embodiment, expressly disclaimed
subject matter, or described a particular embodiment as important to the
invention." Id. at l329. (citation omitted).
17
D
Case: 13-1623 Document: 10 Page: 53 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
signal. Mr. Murphy agrees that the claims' "recited features define the
characteristics of a 'memory device'" (Murphy Decl. ,-r 34), contradicting his
opinion that the memory device is limited to a chip. Claim 11 recites related
functional limitations implicit in a memory device, while claim 1 at most
implies certain functions in a memory device. In any event, Hayes discloses
a memory device as recited in independent claims 1, 11, and 19.
As noted supra, Rambus objects to the dictionary definition provided
by NVIDIA, but Rambus and Mr. Murphy do not provide similar objective
corroborative and persuasive support by way of other patents, treatises, or
dictionaries, to show why the term "memory device" is generally considered
to be restricted to a chip. Cf Infineon 318 F.3d at 1091 (holding that the
term "integrated circuit device" as recited in claim 26 of Rambus's related
'804 patent takes its ordinary meaning of "chip") (internal quotation marks
and citations to trade dictionaries and other authority omitted); MangosoJt,
Inc. v. Oracle Corp., 525 F.3d 1327, 1331 (Fed. Cir. 2008) ("'the persistent
memory device will be understood to include a plurality of local persistent
memory devices"') (quoting U.S. Pat. No. 6,148,377). Mr. Murphy also
points to other Rambus patents (Murphy at,-r,-r 63-65), but in at least one
occasion in a related Rambus patent, the Board found that the term "memory
device" is not restricted to single chip.
4
NVIDIA notes that Rambus refers to the term "memory device" as a
generic term in over 400 of their patents. (Req. Resp. Br. 4-5.) In the
4 BPAI Appeal No. 2010-011178, Reexam. No. 901010420, now on appeal
to the Federal Circuit (Appeal No. 2011-1247). See also infra note 9 and
surrounding discussion.
18
A18
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
signal. Mr. Murphy agrees that the claims' "recited features define the
characteristics of a 'memory device'" (Murphy Decl. ,-r 34), contradicting his
opinion that the memory device is limited to a chip. Claim 11 recites related
functional limitations implicit in a memory device, while claim 1 at most
implies certain functions in a memory device. In any event, Hayes discloses
a memory device as recited in independent claims 1, 11, and 19.
As noted supra, Rambus objects to the dictionary definition provided
by NVIDIA, but Rambus and Mr. Murphy do not provide similar objective
corroborative and persuasive support by way of other patents, treatises, or
dictionaries, to show why the term "memory device" is generally considered
to be restricted to a chip. Cf Infineon 318 F.3d at 1091 (holding that the
term "integrated circuit device" as recited in claim 26 of Rambus's related
'804 patent takes its ordinary meaning of "chip") (internal quotation marks
and citations to trade dictionaries and other authority omitted); Mangosojt,
Inc. v. Oracle Corp., 525 F.3d 1327, 1331 (Fed. Cir. 2008) ("'the persistent
memory device will be understood to include a plurality of local persistent
memory devices"') (quoting U.S. Pat. No. 6,148,377). Mr. Murphy also
points to other Rambus patents (Murphy at,-r,-r 63-65), but in at least one
occasion in a related Rambus patent, the Board found that the term "memory
device" is not restricted to single chip.4
NVIDIA notes that Rambus refers to the term "memory device" as a
generic term in over 400 of their patents. (Req. Resp. Br. 4-5.) In the
4 BPAI Appeal No. 2010-011178, Reexam. No. 901010420, now on appeal
to the Federal Circuit (Appeal No. 2011-1247). See also infra note 9 and
surrounding discussion.
18
D
Case: 13-1623 Document: 10 Page: 54 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
related patent just noted (note 4), the Board found that Rambus refers to and
equates a memory stick, having a transceiver, multiple memory chips, and
optionally, other controllers thereon, to a memory device, showing that at
least some of Rambus's related patents indicate that the ordinary meaning of
a memory device includes a memory stick (i.e., a memory board).
NVIDIA also points out that Rambus recited claims in other patents to
a device "'formed on a single semiconductor substrate'" and to a "'single
chip memory device. ", (Req. Resp. Br. 5 (citation to Rambus patents
omitted).) While Rambus argues that "[eJach patent is a separate legal
instrument and should be interpreted separately with respect to its own
claims and specification," (P.O. Cr. App. Br. 21), NVIDIA's reliance on
these other Rambus patents to show the ordinary meaning of a memory
device as including a memory board, is persuasive. (See Req. Resp. Br. 4-
5.)
Mr. Murphy also cites to the iRAM handbook
5
and quotes a
discussion there of "semiconductor memories" and the announcement there
that "more than 3,000 different memory devices are now available." (See
Murphy Decl. ,-r 65 (quoting iRAM at 1-1 (emphasis by Mr. Murphy).) But
referring to memory devices as semiconductor memories indicates that other
forms of memory devices were known, such as the memory board devices of
Hayes. On the same page cited by Mr. Murphy, the authors issue a caveat
delimiting the scope of the article and supporting the notion that other
known memories would, absent the caveat, otherwise be included in the
5 Memory Components Handbook, Intel. Corp., Ch. 1,3 (1985) ("iRAM").
19
A19
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
related patent just noted (note 4), the Board found that Rambus refers to and
equates a memory stick, having a transceiver, multiple memory chips, and
optionally, other controllers thereon, to a memory device, showing that at
least some of Rambus's related patents indicate that the ordinary meaning of
a memory device includes a memory stick (i.e., a memory board).
NVIDIA also points out that Rambus recited claims in other patents to
a device "'formed on a single semiconductor substrate'" and to a "'single
chip memory device. '" (Req. Resp. Br. 5 (citation to Rambus patents
omitted).) While Rambus argues that "[eJach patent is a separate legal
instrument and should be interpreted separately with respect to its own
claims and specification," (P.O. Cr. App. Br. 21), NVIDIA's reliance on
these other Rambus patents to show the ordinary meaning of a memory
device as including a memory board, is persuasive. (See Req. Resp. Br. 4-
5.)
Mr. Murphy also cites to the iRAM handbook
5
and quotes a
discussion there of "semiconductor memories" and the announcement there
that "more than 3,000 different memory devices are now available." (See
Murphy Decl.   65 (quoting iRAM at 1-1 (emphasis by Mr. Murphy).) But
referring to memory devices as semiconductor memories indicates that other
fonns of memory devices were known, such as the memory board devices of
Hayes. On the same page cited by Mr. Murphy, the authors issue a caveat
delimiting the scope of the article and supporting the notion that other
known memories would, absent the caveat, otherwise be included in the
') Memory Components Handbook, Intel. Corp., Ch. 1,3 (1985) ("iRAM").
19
D
Case: 13-1623 Document: 10 Page: 55 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
term: "Tape and disk storage are also non-volatile memories but are not
included within the scope of this book which confines itself to solid-state
technologies in an Ie form factor." (iRAM 1-1 (emphasis added).) The
'353 patent not only fails to issue a similar caveat, it does the opposite and
proclaims that the claims are not to be limited by any disclosed embodiment.
(P3.) Moreover, "[a]bsent an express definition in their specification, the
fact that appellants can point to definitions or usages that conform to their
interpretation does not make the PTO's definition unreasonable when the
PTO can point to other sources that support their definition." In re Morris,
127 F.3d 1048, 1056 (Fed. Cir. 1997)
Rambus also asserts that Hayes's DS signal does not constitute the
claimed strobe signal. (P.O. Cr. App. Br. 26-28.) This contention is not
persuasive. The DS signal, a "data strobe" signal (HI, H2), reasonably
indicates that data is valid on the data lines as the Examiner finds. (ACP 13-
14 (quoting Hayes at col. 9, 11. 49-65 and citing col. 7, 11.41-43); accordH2.)
Figure 2 of Hayes depicts a slave memory board (the "memory device" in
claims 1, 11, and 19) receiving "INFORMATION TRANSFER"s on data
and address lines <31 :0> under direct "BUS CONTROL" by the "BUS
MASTER" which issues "DATA STROBE" (DS) and "WRITE" signals to
the "SLAVE" memory device to cause such a write transfer of data based on
the DS signal which indicates valid data on the bus. (HI, H2; see Req. Resp.
Br. 10-11.) In sum, the bus master asserts DS when data is valid on the bus,
the slave then reads the data (absent an abnormal abort as discussed below),
and then the bus master deasserts DS when data is about to be removed from
the bus. (H2.)
20
A20
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
term: "Tape and disk storage are also non-volatile memories but are not
included within the scope of this book which confines itself to solid-state
technologies in an Ie form factor." (iRAM 1-1 (emphasis added).) The
'353 patent not only fails to issue a similar caveat, it does the opposite and
proclaims that the claims are not to be limited by any disclosed embodiment.
(P3.) Moreover, "[a]bsent an express definition in their specification, the
fact that appellants can point to definitions or usages that conform to their
interpretation does not make the PTO's definition unreasonable when the
PTO can point to other sources that support their definition." In re Morris,
127 F.3d 1048, 1056 (Fed. Cir. 1997)
Rambus also asserts that Hayes's DS signal does not constitute the
claimed strobe signal. (P.O. Cr. App. Br. 26-28.) This contention is not
persuasive. The DS signal, a "data strobe" signal (HI, H2), reasonably
indicates that data is valid on the data lines as the Examiner finds. (ACP l3-
14 (quoting Hayes at col. 9, 11. 49-65 and citing col. 7, 11.41-43); accordH2.)
Figure 2 of Hayes depicts a slave memory board (the "memory device" in
claims 1, 11, and 19) receiving "INFORMATION TRANSFER"s on data
and address lines <31 :0> under direct "BUS CONTROL" by the "BUS
MASTER" which issues "DATA STROBE" CDS) and "WRITE" signals to
the "SLAVE" memory device to cause such a write transfer of data based on
the DS signal which indicates valid data on the bus. (HI, H2; see Req. Resp.
Br. 10-11.) In sum, the bus master asserts DS when data is valid on the bus,
the slave then reads the data (absent an abnormal abort as discussed below),
and then the bus master deasserts DS when data is about to be removed from
the bus. (H2.)
20
D
Case: 13-1623 Document: 10 Page: 56 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
Rambus's related assertion that data is not sampled until after an ERR
signal in Hayes does not disturb the finding about DS. (P.O. Cr. App. Br.
27.) Rambus agrees with the Examiner that "the claims do not exclude other
control signals" (P.O. Cr. App. Br. 27) but mischaracterizes another of the
Examiner's findings: "CRU [i.e., the Examiner at the Central Reexamination
Unit] agreed that the memory device does not sample data in response to
DS." (Jd.) To the contrary, the Examiner finds that "[t]he DS signal ...
functions to let the memory device known [sic] when to start to read/write
data." (RAN 10.)
As the Examiner explains, the ERR signal provides a parity check
which may override normal read/write functions, but the DS signal, the "data
strobe" signal, tells the slave memory device in Hayes that the data is valid
on the bus so that the slave memory device knows when to sample (read) it.
(See RAN 9-10.) The record supports the Examiner. (HI-H3.) During a
write cycle, the bus master asserts DS and the "slave device reads [samples]
the data." (H2, H6.) If there is no ERR signal after DS is asserted, the
memory device reads (i.e., "samples") the data from the bus. And any ERR
signal only occurs rarely, in "abnormal" situations. (H3.) Moreover, parity
must be, but need not be, enabled. (See H2.) In other words, in Hayes, the
ERR function is an option which need not be enabled, and, in any event,
occurs during an "abnormal" termination of a read, write, or interrupt. (H2,
H3.) Rambus agrees that the independent claims do not preclude additional
control as noted supra. It follows that the independent claims do not
preclude the abnormal ERR control, whether optional or not.
In a related argument, Rambus also contends that Hayes's slave
memory device does not sample data in response to Hayes's DS signal.
21
A21
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Rambus's related assertion that data is not sampled until after an ERR
signal in Hayes does not disturb the finding about DS. (P.O. Cr. App. Br.
27.) Rambus agrees with the Examiner that "the claims do not exclude other
control signals" (P.O. Cr. App. Br. 27) but mischaracterizes another of the
Examiner's findings: "CRU [i.e., the Examiner at the Central Reexamination
Unit] agreed that the memory device does not sample data in response to
DS." (Jd.) To the contrary, the Examiner finds that "[t]he DS signal ...
functions to let the memory device known [sic] when to start to read/write
data." (RAN 10.)
As the Examiner explains, the ERR signal provides a parity check
which may override normal read/write functions, but the DS signal, the "data
strobe" signal, tells the slave memory device in Hayes that the data is valid
on the bus so that the slave memory device knows when to sample (read) it.
(See RAN 9-10.) The record supports the Examiner. (Hl-H3.) During a
write cycle, the bus master asserts DS and the "slave device reads [samples]
the data." (H2, H6.) Ifthere is no ERR signal after DS is asserted, the
memory device reads (i.e., "samples") the data from the bus. And any ERR
signal only occurs rarely, in "abnormal" situations. (H3.) Moreover, parity
must be, but need not be, enabled. (See H2.) Tn other words, in Hayes, the
ERR function is an option which need not be enabled, and, in any event,
occurs during an "abnormal" termination of a read, write, or intemlpt. (H2,
H3.) Rambus agrees that the independent claims do not preclude additional
control as noted supra. It follows that the independent claims do not
preclude the abnormal ERR control, whether optional or not.
In a related argument, Rambus also contends that Hayes's slave
memory device does not sample data in response to Hayes's OS signal.
21
D
Case: 13-1623 Document: 10 Page: 57 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
(P.o. Cr. App. Br. 27-28.) This argument lacks merit. The DS "provides
timing for data control transfers" (H2), signifies to the the memory "slave"
(H5) that data is valid (H2), and thereby starts the data transfer response of
the "slave" memory to the "master" bus controller. (H2, H5.) Claim 1
"defer[ s] sampling ... until an external strobe signal is detected" and does
not require an immediate response based on the strobe signal. As NVIDIA
further points out, the '353 patent describes a delay between the strobe
signal and subsequent data sampling (with a data sample occurring
sometime after the strobe in further response to an external clock). (Req.
Resp. Br. 12.) Rambus corroborates NVIDIA's point and describes a similar
delay between the data and the strobe. (P.O. Cr. App. Br. 10.)
Since claim 1 neither requires an immediate response, nor precludes
an infrequent (abnormal) or optional interrupt (such as by Hayes's ERR
system), even if Hayes delays sampling after the DS, in light of the '353
patent, the DS constitutes a strobe signal as recited in the independent claims
because Hayes discloses that data is normally read by the slave memory
device after DS during a write cycle. (H2, H4.)
Rambus also argues that the doctrine of intervening rights forecloses
the practical ability to freely amend claims during reexamination so that
there is no valid policy reason for interpreting claims under a broadest
reasonable standard. (P.O. Cr. App. Br. 25-26; .P.O. Reb. Br. 13-14.) This
argument implies that Rambus seeks a substantive change to claim scope by
presenting arguments as opposed to amending the claims, see e.g., Marine
Polymer Technologies, Inc. v. HemCon, Inc., 659 F.3d 1084, 1092 (Fed. Cir.
2011) en banc rehearing granted, _Fed. Appx. _ (2012), contradicting
Rambus's other assertions addressed supra about the intrinsic meaning of
22
A22
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
(P.o. Cr. App. Br. 27-28.) This argument lacks merit. The DS "provides
timing for data control transfers" (H2), signifies to the the memory "slave"
(H5) that data is valid (H2), and thereby starts the data transfer response of
the "slave" memory to the "master" bus controller. (H2, H5.) Claim 1
"defer[ s] sampling ... until an external strobe signal is detected" and does
not require an immediate response based on the strobe signal. As NVIDIA
further points out, the '353 patent describes a delay between the strobe
signal and subsequent data sampling (with a data sample occurring
sometime after the strobe in further response to an external clock). (Req.
Resp. Br. 12.) Rambus corroborates NVIDIA's point and describes a similar
delay between the data and the strobe. (P.O. Cr. App. Br. 10.)
Since claim 1 neither requires an immediate response, nor precludes
an infrequent (abnormal) or optional intemlpt (such as by Hayes's ERR
system), even if Hayes delays sampling after the DS, in light of the '353
patent, the DS constitutes a strobe signal as recited in the independent claims
because Hayes discloses that data is normally read by the slave memory
device after DS during a write cycle. (H2, H4.)
Rambus also argues that the doctrine of intervening rights forecloses
the practical ability to freely amend claims during reexamination so that
there is no valid policy reason for interpreting claims under a broadest
reasonable standard. (P.O. Cr. App. Br. 25-26; .P.O. Reb. Br. l3-14.) This
argument implies that Rambus seeks a substantive change to claim scope by
presenting arguments as opposed to amending the claims, see e.g., Marine
Polymer Technologies, Inc. v. HemCon, Inc., 659 F.3d 1084, 1092 (Fed. Cir.
2011) en banc rehearing granted, _ Fed. Appx. _ (2012), contradicting
Rambus's other assertions addressed supra about the intrinsic meaning of
22
D
Case: 13-1623 Document: 10 Page: 58 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
the claim terms. But in any event, as NVIDIA maintains, Rambus's position
runs counter to In re Yamamoto, 740 F.2d 1569, 1571-72 (Fed. Cir. 1984)
( opportunity to amend during reexamination dictates same broadest
reasonable claim construction standard as applied during original
prosecution). (See Req. Res. Br. 9-10.) Also, Rambus does not show that a
different result necessarily would flow from a different standard under these
facts, and Rambus does not show that the interpretations by the Examiner
violate claim construction principles under Phillips, 415 F.3d 1303.
Based on the foregoing discussion, the Rambus did not show that the
Examiner erred in rejecting independent claims 1, 11, and 19 and dependent
claim 7 not argued separately as anticipated by Hayes.
Claims 5, 14, and 23
Dependent claims 5, 14, and 23 respectively depend from independent
claims 1, 11, and 19, and further recite a terminate signal: Claim 5 recites
"sampling additional portions of the data during a time interval between
detection of the external strobe signal and detection of the external terminate
signal." Claim 14 recites "issuing additional portions of the data to the
memory device; and issuing a terminate signal to the memory device to
signal to the memory device to stop sampling data." Claim 23 recites
"wherein the plurality of input receiver circuits receive additional portions of
the data before detection of a terminate signal."
The Examiner reasons that in Hayes, the deassertion of the DS signal
constitutes the terminate signal satisfying these dependent claims. The
Examiner also reasons that a 32 bit "longword," which Hayes transmits
between the assertion and deassertion of DS, comprises a first portion and
additional portions of data as recited in the claims. (RAN 11-12.)
23
A23
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
the claim terms. But in any event, as NVIDIA maintains, Rambus's position
runs counter to In re Yamamoto, 740 F.2d 1569, 1571-72 (Fed. Cir. 1984)
( opportunity to amend during reexamination dictates same broadest
reasonable claim construction standard as applied during original
prosecution). (See Req. Res. Br. 9-10.) Also, Rambus does not show that a
ditlerent result necessarily would flow from a ditlerent standard under these
facts, and Rambus does not show that the interpretations by the Examiner
violate claim construction principles under Phillips, 415 F.3d 1303.
Based on the foregoing discussion, the Rambus did not show that the
Examiner erred in rejecting independent claims 1, 11, and 19 and dependent
claim 7 not argued separately as anticipated by Hayes.
Claims 5, 14, and 23
Dependent claims 5, 14, and 23 respectively depend from independent
claims 1, 11, and 19, and further recite a terminate signal: Claim 5 recites
"sampling additional portions of the data during a time interval between
detection of the external strobe signal and detection of the external terminate
signal." Claim 14 recites "issuing additional portions of the data to the
memory device; and issuing a terminate signal to the memory device to
signal to the memory device to stop sampling data." Claim 23 recites
"wherein the plurality of input receiver circuits receive additional portions of
the data before detection of a terminate signal."
The Examiner reasons that in Hayes, the deassertion of the DS signal
constitutes the ternlinate signal satisfying these dependent claims. The
Examiner also reasons that a 32 bit "longword," which Hayes transmits
between the assertion and deassertion of DS, comprises a first portion and
additional portions of data as recited in the claims. (RAN 11-12.)
23
D
Case: 13-1623 Document: 10 Page: 59 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
Rambus treats the claims as a group and argues that "the CRU appears
to have construed the claims erroneously." (P.O. Cr. App. Br. 28.) Rambus
maintains that since Hayes only discloses that data is about to be removed
from the bus after the deassertion ofDS, Hayes does not satisfy the claims
because data sampling is still possible after the DS assertion and Hayes does
not signify exactly when the sampling stops. (P.O. Cr. App. Br. 29.t
Claim 14 requires the terminate signal "to signal to the memory
device to stop sampling data." Claims 5 and 11 are similar. Like the system
in Hayes, claims 5, 11, and 14 fail to define exactly when the sampling must
stop (or for how long it must stop). For example, the claim reasonably
allows for the memory device to complete the sampling of data already on
the data lines (e.g., within a predetermined number of clock cycles after the
terminate signal), and thereafter, to allow more sampling after the next
strobe or DS signal. As NVIDIA explains, the '353 patent supports this
claim interpretation: i.e., data transmission, and hence sampling thereof,
occurs for at least three clock cycles after the terminate signal. (Req. Resp.
Br. 13 (citing table and '353 patent, cols. 25-28).) NVIDA's explanation of
this delay coalesces with Rambus's. (See Rambus App. Br. 10 (showing
6 Rambus points to Hayes as removing data from DAL lines (connected
externally to the asserted memory device in Hayes (see HI, H7), and argues
that the data lines "DATA" are the only ones connected to "the alleged
memory device." (See P.O. Cr. App. Br. 29.) This argument is not clear. In
any case, during a write operation, the DAL lines (connected externally to
the memory board device (HI)) and the DATA lines (connected internally
on the memory board device (H7)) are connected together via the data
transceiver 57 of the memory device and the assertion ofDS indicates that
both buses contain valid write data. (See Parris Decl. ,-r,-r 15-16; Hayes, Fig.
2, H7.)
24
A24
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Rambus treats the claims as a group and argues that "the CRU appears
to have construed the claims erroneously." (P.O. Cr. App. Br. 28.) Rambus
maintains that since Hayes only discloses that data is about to be removed
from the bus after the de assertion of DS, Hayes does not satisfy the claims
because data sampling is still possible after the DS assertion and Hayes does
not signify exactly when the sampling stops. (P.O. Cr. App. Br. 29.)6
Claim 14 requires the terminate signal "to signal to the memory
device to stop sampling data." Claims 5 and 11 are similar. Like the system
in Hayes, claims 5, 11, and 14 fail to define exactly when the sampling must
stop (or for how long it must stop). For example, the claim reasonably
allows for the memory device to complete the sampling of data already on
the data lines (e.g., within a predeternlined number of clock cycles after the
terminate signal), and thereafter, to allow more sampling after the next
strobe or DS signal. As NVIDIA explains, the '353 patent supports this
claim interpretation: i.e., data transmission, and hence sampling thereof,
occurs for at least three clock cycles after the terminate signal. (Req. Resp.
Br. 13 (citing table and '353 patent, cols. 25-28).) NVIDA's explanation of
this delay coalesces with Rambus's. (See Rambus App. Br. 10 (showing
6 Rambus points to Hayes as removing data from DAL lines (connected
externally to the asserted memory device in Hayes (see HI, H7), and argues
that the data lines "DATA" are the only ones connected to "the alleged
memory device." (See P.O. Cr. App. Br. 29.) This argument is not clear. In
any case, during a write operation, the DAL lines (connected externally to
the memory board device (HI)) and the DATA lines (connected internally
on the memory board device (H7)) are connected together via the data
transceiver 57 of the memory device and the assertion of DS indicates that
both buses contain valid write data. (See Parris Decl. mJ 15-16; Hayes, Fig.
2, H7.)
24
D
Case: 13-1623 Document: 10 Page: 60 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
data transmission beginning between the strobe and terminate signal and
ending after the terminate signal).)
Rambus also maintains that Hayes does not disclose sampling
"additional portions" of the data before the deassertion of DS because
"quadwords are transferred over two write cycles." (Rambus App. Br. 29.)
But claim 14 does not even require the additional portions to be sampled
because it recites "stop sampling data" which may refer to the "first portion
of the data" introduced in independent claim 11. Claim 23, a product claim,
recites an intended use of the terminate signal, and requires the device to be
capable of receiving additional data before a terminate signal. Hayes's slave
device at least has that capability since it responds to the assertion of DS and
the data is removed after the deassertion ofDS, thereby signifying to the
slave device not to read data after the DS deassertion as the Examiner finds.
(See RAN 12, H2, H4.)
Claim 5 requires sampling additional portions between the strobe and
terminate signal, and to the extent claims 14 and 23 could be interpreted
similarly, the following discussion applies. The above-noted quadwords are
64 bits long, and represent two 32 bit longwords. (See H6.) According to
Rambus, each write transaction corresponds to one DS assertion followed by
its deassertion, so that for one quadword transaction, "the DS signal would
be asserted and deasserted twice" - once for each longword which occurs
over two write cycles. (P.O. Reb. Br. 17.)
Under Rambus's description, Hayes still satisfies the claims, because
the terminate signal in the claims is broad enough to read on the second
deassertion of DS in Hayes, since the claims simply do not define when the
terminate signal occurs. Therefore, under the quadword scenario described
25
A25
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
data transmission beginning between the strobe and terminate signal and
ending after the terminate signal).)
Rambus also maintains that Hayes does not disclose sampling
"additional portions" of the data before the deassertion of DS because
"quadwords are transferred over two write cycles." (Rambus App. Br. 29.)
But claim 14 does not even require the additional portions to be sampled
because it recites "stop sampling data" which may refer to the "first portion
of the data" introduced in independent claim 11. Claim 23, a product claim,
recites an intended use of the terminate signal, and requires the device to be
capable of receiving additional data before a terminate signal. Hayes's slave
device at least has that capability since it responds to the assertion of DS and
the data is removed after the de assertion of DS, thereby signifying to the
slave device not to read data after the DS deassertion as the Examiner finds.
(See RAN 12, H2, H4.)
Claim 5 requires sampling additional portions between the strobe and
terminate signal, and to the extent claims 14 and 23 could be interpreted
similarly, the following discussion applies. The above-noted quadwords are
64 bits long, and represent two 32 bit longwords. (See H6.) According to
Rambus, each write transaction corresponds to one DS assertion followed by
its deassertion, so that for one quadword transaction, "the DS signal would
be asserted and deasserted twice" - once for each longword which occurs
over two write cycles. (P.O. Reb. Br. 17.)
Under Rambus's description, Hayes still satisfies the claims, because
the tenninate signal in the claims is broad enough to read on the second
de assertion of DS in Hayes, since the claims simply do not define when the
terminate signal occurs. Therefore, under the quadword scenario described
25
D
Case: 13-1623 Document: 10 Page: 61 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
by Rambus, the first Hayes longword of the quadword constitutes a first
portion of the data and the second longword of the quadword corresponds to
the additional portion of data in the claims. (See Req. App. Br. 13-14
(asserting the second longword write corresponds to additional data
portions).)
Alternatively, as NVIDIA and the Examiner also maintain, a single
longword (32 bits) constitutes two portions of data - for example, one 16 bit
group in the word for the first portion and another 16 bit group for the
additional portion). (RAN 12; Req. Resp. Br.13-14.) Rambus asserts that
this is not "rational" because all 32 bits in Hayes are sampled at one time.
(P.O. Cr. App. Br. 18.) But the claims simply do not require sampling the
two different portions at different times and Rambus fails to direct attention
to any claim term which precludes simultaneous sampling of different data
portions on the 32 bit lines of Hayes.
Based on the foregoing discussion, Rambus fails to show error in the
rejection of claims 5, 14, and 23.
NVIDIA's APPEAL
The Examiner did not maintain the following proposed rejections by
Requestor:
Claims 11, 15-16, and 18 as invalid under 35 U.S.C. § 101 for
obviousness-type double patenting based on Farmwald et aI., U.S. 6,584,037
B2 (June 24, 2004)("Farmwald '037").
Claims 11, 15, 16, and 18 as anticipated under 35 U.S.C. § 102(e) by
Farmwald '037.
26
A26
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
by Rambus, the first Hayes longword of the quadword constitutes a first
portion of the data and the second longword of the quadword corresponds to
the additional portion of data in the claims. (See Req. App. Br. 13-14
(asserting the second longword write corresponds to additional data
portions).)
Alternatively, as NVIDIA and the Examiner also maintain, a single
longword (32 bits) constitutes two portions of data - for example, one 16 bit
group in the word for the first portion and another 16 bit group for the
additional portion). (RAN 12; Req. Resp. Br.l3-l4.) Rambus asserts that
this is not "rational" because all 32 bits in Hayes are sampled at one time.
(P.O. Cr. App. Br. 18.) But the claims simply do not require sampling the
two different portions at different times and Rambus fails to direct attention
to any claim term which precludes simultaneous sampling of different data
portions on the 32 bit lines of Hayes.
Based on the foregoing discussion, Rambus fails to show error in the
rejection of claims 5, 14, and 23.
NVIDIA's APPEAL
The Examiner did not maintain the following proposed rejections by
Requestor:
Claims 11, 15-16, and 18 as invalid under 35 U.S.C. § 101 for
obviousness-type double patenting based on Fannwald et al., U.S. 6,584,037
B2 (June 24, 2004)("Fannwald '037").
Claims 11, 15, 16, and 18 as anticipated under 35 U.S.C. § 102(e) by
Farmwald '037.
26
D
Case: 13-1623 Document: 10 Page: 62 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
Claims 3, 4, 12, 13,22, and 23 are obvious as obvious under
35 U.S.C. § 103(a) based on Barth et aI., U.S. 5,748,914 (May 5, 1998) and
Kushiyama et aI., A SOO-Megabytes Data-Rate 4.SM DRAM, IEEE 1. Sol.
State Circ., V. 28, No.4 (April 1994) ("Kushiyama").
Claims 2,6, 10, 17, and 25-26 as obvious under 35 U.S.C. § 103(a)
based on Hayes and Bennett et aI., U.S. Patent 4,734,909 (Mar. 29, 1988)
("Bennett").
Claims 3-4, 12-13, and 21-22 as obvious 35 U.S.C. § 103(a) based on
Hayes, Bennett and Inagaki, lP 57-210495 (Dec. 24, 1982).
Claims 12 and 13 as obvious under 35 U.S.C. § 103(a).
based on Hayes and Inagaki.
Claims 2-10, 12-14, 16-17, and 20-26 as obvious under 35 U.S.C.
§ 103(a) based on Hayes and Ohshima et aI., High Speed DRAMs with
Innovative Architectures IEICE Trans. Electron V. ECC-7, No.8, 1303-15
(Aug. 1994) ("Ohshima").
Claims 1-14, 16-17, and 19-26 as obvious under 35 U.S.C. § 103(a)
based on Kushiyama, Hayes, and Lu, The Future of DRAMs, 1988 IEEE
Inter. Solid-State Cir. Conf. (ISSCC), Digest Tech. Papers, 98-99 (Feb.
1988)("Lu").
Claims 1-4,6-9, 11-13, 15-16, 18-22, and 24-26 as obvious under
35 U.S.C. § 103(a) based on Farmwald et aI., U.S. 5,319,755 (June 7, 1994)
("Farmwald '755") and Lu.
Claims 1-4,6-9, 11-13, 15-16, 18-22, and 24-26 as obvious under
35 U.S.C. § 103(a) based on Farmwald '755 and iRAM (supra note 5).
(See Req. App. Br. 5-6.)
27
A27
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Claims 3, 4, 12, l3, 22, and 23 are obvious as obvious under
35 U.S.c. § 103(a) based on Barth et al., U.S. 5,748,914 (May 5, 1998) and
Kushiyama et al., A 500-Megabytes Data-Rate 4.5M DRAM, IEEE J. Sol.
State Cire., V. 28, No.4 (April 1994) ("Kushiyama").
Claims 2,6, 10, 17, and 25-26 as obvious under 35 U.S.C. § 103(a)
based on Hayes and Bennett et a1., U.S. Patent 4,734,909 (Mar. 29, 1988)
("Bennett").
Claims 3-4, 12-l3, and 21-22 as obvious 35 U.S.c. § 103(a) based on
Hayes, Bennett and Inagaki, JP 57-210495 (Dec. 24, 1982).
Claims 12 and 13 as obvious under 35 U.S.c. § 103(a).
based on Hayes and Inagaki.
Claims 2-10, 12-14, 16-17, and 20-26 as obvious under 35 U.S.c.
§ 103(a) based on Hayes and Ohshima et a1., High Speed DRAMs with
Innovative Architectures IEICE Trans. Electron V. ECC-7, No.8, l303-15
(Aug. 1994) ("Ohshima").
Claims 1-14, 16-17, and 19-26 as obvious under 35 U.S.C. § 103(a)
based on Kushiyama, Hayes, and Lu, The Future of DRAMs, 1988 IEEE
Inter. Solid-State Cir. Conf. (ISSCC), Digest Tech. Papers, 98-99 (Feb.
1988)("Lu").
Claims 1-4,6-9, ll-l3, 15-16, 18-22, and 24-26 as obvious under
35 U.S.c. § 103(a) based on Farmwald et al., U.S. 5,319,755 (June 7,1994)
("Famlwald '755") and Lu.
Claims 1-4,6-9, 11-l3, 15-16, 18-22, and 24-26 as obvious under
35 U.S.C. § 103(a) based on Fannwald '755 and iRAM (supra note 5).
(See Req. App. Br. 5-6.)
27
D
Case: 13-1623 Document: 10 Page: 63 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
Issues
As the discussion below indicates, the Briefs and Answer raise the
following issues of whether NVIDIA demonstrated that the Examiner erred
in failing to maintain the rejections listed supra. Based on the finding of
error with respect to claims 1-26, which are all of the claims on appeal, we
decline to reach the first three rejections listed supra.
Hayes with Bennett - Obviousness of
Claims 2, 6, 10, 17, 25, and 26
NVIDIA's contentions are persuasive to show that the Examiner erred
by not maintaining the obviousness rejections based on Hayes and Bennett.
7
(Req. App. Br. 6-9.) NVIDIA's Inter Partes Request for Reexamination
(attached to Req. App. Br. as Exhibit 1) and as supplemented by NVIDIA's
explanations of record, including the Briefs, are also incorporated here by
reference.
The Examiner agrees that Hayes discloses a memory device and
anticipates claim 1, but maintains that including all the RAM control logic
into each Hayes DRAM chip would not have been obvious. (See RAN 3,
33, 40-43.) But dependent claim 2 recites sampling data synchronously and
does not require all the RAM control logic to be integrated into each chip.
NVIDIA points out that the term "memory device" in these claims is not
limited to a single chip (Req. App. Br. 7 n. 3), but even if they are, NVIDIA
7 As discussed supra, the Examiner maintained NVIDIA's proposed
anticipation rejection of claims 1, 5, 7, 11, 14, 19, and 23 based on Hayes.
While NVIDIA also proposed alternative obviousness rejections based on
Hayes and Bennett with respect to those rejected claims, NVIDIA does not
appeal with respect to them.
28
A28
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Issues
As the discussion below indicates, the Briefs and Answer raise the
following issues of whether NVIDIA demonstrated that the Examiner erred
in failing to maintain the rejections listed supra. Based on the finding of
error with respect to claims 1-26, which are all of the claims on appeal, we
decline to reach the first three rejections listed supra.
Hayes with Bennett - Obviousness of
Claims 2, 6, 10, 17, 25, and 26
NVIDIA's contentions are persuasive to show that the Examiner erred
by not maintaining the obviousness rejections based on Hayes and Bennett.
7
(Req. App. Br. 6-9.) NVIDIA's Inter Partes Request for Reexamination
(attached to Req. App. Br. as Exhibit 1) and as supplemented by NVIDIA's
explanations of record, including the Briefs, are also incorporated here by
reference.
The Examiner agrees that Hayes discloses a memory device and
anticipates claim 1, but maintains that including all the RAM control logic
into each Hayes DRAM chip would not have been obvious. (See RAN 3,
33,40-43.) But dependent claim 2 recites sampling data synchronously and
does not require all the RAM controllogic to be integrated into each chip.
NVIDIA points out that the term "memory device" in these claims is not
limited to a single chip (Req. App. Br. 7 n. 3), but even if they are, NVIDIA
7 As discussed supra, the Examiner maintained NVIDIA's proposed
anticipation rejection of claims 1, 5, 7, 11, 14, 19, and 23 based on Hayes.
While NVIDIA also proposed alternative obviousness rejections based on
Hayes and Bennett with respect to those rejected claims, NVIDIA does not
appeal with respect to them.
28
D
Case: 13-1623 Document: 10 Page: 64 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
persuasively shows the obviousness of creating a single chip. (See Req.
Reb. Br. 4 n. 7(citing IP Request at 24); see also IP Request 19-24). The
claim 2 memory device, whether as a chip or a broader device, requires
strobe functionality which Hayes teaches and synchronization which Bennett
teaches according to this record. As NVIDIA persuasively explains, Hayes
describes time-multiplexed clock data transfers between a master and slave
during different clock cycles, and Bennett teaches benefits to providing a
synchronized interface in a memory device using an external clock. (See
Req. App. Br. 6-9; H6.) The Examiner does not appear to disagree with
these findings. (See RAN 41-43.)
NVIDIA also relies on Mr. Parris who testifies that ordinarily skilled
artisans were shifting from asynchronous to synchronous operations to
increase speed. (Req. App. Br. 8 n. 8 (citing Parris Decl. at,-r 17 attached to
Req. App. Br. at Ex. 30); see also Paris Decl. ,-r,-r 18-20).) Based on this
record, NVIDIA shows that it would have been obvious in view of Bennett
to implement certain control logic, including a synchronous logic interface,
into the memory device of Hayes. (See Req. App. Br. 6-9.)
Hayes. Bennett. and Inagaki - Obviousness of
Claims 3.4.12.13.21. and 22
Additional Findings of Fact
Inagaki8
II. Inagaki teaches a desire to increase data transfer rates in
computers, and discloses a method for increasing data rates in block access
8 Reference hereinafter is to an English translation attached to NVIDIA's
Appeal Brief as Exhibit 5.
29
A29
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
persuasively shows the obviousness of creating a single chip. (See Req.
Reb. Br. 4 n. 7(citing IP Request at 24); see also IP Request 19-24). The
claim 2 memory device, whether as a chip or a broader device, requires
strobe functionality which Hayes teaches and synchronization which Bennett
teaches according to this record. As NVIDIA persuasively explains, Hayes
describes time-multiplexed clock data transfers between a master and slave
during different clock cycles, and Bennett teaches benefits to providing a
synchronized interface in a memory device using an external clock. (See
Req. App. Br. 6-9; H6.) The Examiner does not appear to disagree with
these findings. (See RAN 41-43.)
NVIDIA also relies on Mr. Parris who testifies that ordinarily skilled
artisans were shifting from asynchronous to synchronous operations to
increase speed. (Req. App. Br. 8 n. 8 (citing Parris Decl. at   17 attached to
Req. App. Br. at Ex. 30); see also Paris Decl.     18-20).) Based on this
record, NVIDIA shows that it would have been obvious in view of Bennett
to implement certain control logic, including a synchronous logic interface,
into the memory device of Hayes. (See Req. App. Br. 6-9.)
Haves. Bennett. and Inagaki - Ohviousness or
Claims 3.4.12.13.21. and 22
Additional Findings of Fact
Inagaki8
n. Inagaki teaches a desire to increase data transfer rates in
computers, and discloses a method for increasing data rates in block access
8 Reference hereinafter is to an English translation attached to NVIDIA's
Appeal Brief as Exhibit 5.
29
D
Case: 13-1623 Document: 10 Page: 65 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
memory. As background, Inagaki teaches that conventional methods to
increase data transfer rates in RAMs were to increase the data bus width,
which adds cost of packaging and pin count, or to increase the clock rate.
(Inagaki 2.) Inagaki's solution involves using dual edges of an external
clock as the following quotations indicate.
12. "The rise and fall of external clock <P are detected, and clocks <PI
and <P2 are generated. Clocks <PI and <P2 drive shift pulses of the shift
register. ... In this way, since one bit is output on each half-cycle, the
operating speed is twice that of the conventional speed." (Id. at 4.)
13 "[T]he present invention presents block access memory that
transfers data with a speed that is twice the conventional speed, by
performing I/O [input/output] of data on every half-cycle of the external
clock that drives the I/O shift register." (Id. at 3.)
Discussion
NVIDIA's contentions are persuasive to show Examiner error in
failing to maintain the rejection. The Examiner relied on the above-
discussed reasons with respect to Hayes and Bennett. (See RAN 43.)
Inagaki's system improves memory access speed by providing data transfers
at odd and even (i.e., both) clock edges thereby doubling the overall speed.
(See Req. App. Br. 9-11; II-B.) Rambus's contention that Inagaki "uses the
word 'clock' in numerous locations" but does not disclose a clock because
the clock is pulsed and not periodic, lacks merit. (P.O. Resp. Br. 10.) The
clock is periodic while it runs, and in any event, skilled artisans would have
understood that using the dual clock edges in Bennett's external clock would
have doubled the system speed, provided for the same speed using a slower
30
A30
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
memory. As background, Inagaki teaches that conventional methods to
increase data transfer rates in RAMs were to increase the data bus width,
which adds cost of packaging and pin count, or to increase the clock rate.
(Inagaki 2.) Inagaki's solution involves using dual edges of an extemal
clock as the following quotations indicate.
12. "The rise and fall of extemal clock <p are detected, and clocks <P1
and <P2 are generated. Clocks <P1 and <P2 drive shift pulses ofthe shift
register. . .. In this way, since one bit is output on each half-cycle, the
operating speed is twice that of the conventional speed." (Id. at 4.)
13 "[T]he present invention presents block access memory that
transfers data with a speed that is twice the conventional speed, by
performing I/O [input/output] of data on every half-cycle of the extemal
clock that drives the 1/0 shift register." (ld. at 3.)
Discussion
NVIDIA's contentions are persuasive to show Examiner error in
failing to maintain the rejection. The Examiner relied on the above-
discussed reasons with respect to Hayes and Bennett. (See RAN 43.)
Inagaki's system improves memory access speed by providing data transfers
at odd and even (i.e., both) clock edges thereby doubling the overall speed.
(See Req. App. Br. 9-11; Il-13.) Rambus's contention that Inagaki "uses the
word 'clock' in numerous locations" but does not disclose a clock because
the clock is pulsed and not periodic, lacks merit. (P.O. Resp. Br. 10.) The
clock is periodic while it runs, and in any event, skilled artisans would have
understood that using the dual clock edges in Bennett's extemal clock would
have doubled the system speed, provided for the same speed using a slower
30
D
Case: 13-1623 Document: 10 Page: 66 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
clock, or provided a mechanism to minimize the number of data lines.
(See II-B.)
Inagaki discloses an "external clock <p" (I2) having odd and even
phases (i.e., on dual rising and falling edges of the external clock (Inagaki
Fig. 6; see II-B)) which in tum generate clock phases "to transfer data
with ... twice the conventional speed" (13). Rambus also contends that
Inagaki's clock signal is not external and that that motivation to combine the
references lacks because Hayes describes an asynchronous system. (P.O.
Resp. Br. 11.)
These arguments are not persuasive. Asynchronous to synchronous
migration was well-known and common. (See Paris Decl.) Hayes, Bennett,
and Inagaki disclose external clocks, and a "universal" desire for "faster"
operations creates an "implicit motivation," which is not isolated to
asynchronous devices. See Dystar Textilfarben GmBH & Co. Dutschland
KG v. C.H. Patrick Co., 464 F.3d 1356, 1368 (Fed. Cir. 2006) ("[A]n
implicit motivation to combine exists ... when the 'improvement' is
technology-independent and the combination of references results in a
product or process that is more desirable, for example because it is stronger,
cheaper, cleaner, faster, lighter, smaller, more durable, or more efficient.")
Also, Hayes employs a clock to drive time multiplexed signals between a
master and slave (H6), thereby suggesting a substitute clock operating at half
the speed, a fewer number of data lines based on using both clock edges, or a
faster clock, as Inagaki (II-B) suggests.
Based on the foregoing discussion, the Examiner erred by failing to
maintain Requestor's proposed rejection of claims 3, 4,12,13,21-23,33,
and 34.
31
A31
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
clock, or provided a mechanism to minimize the number of data lines.
(See II-B.)
Inagaki discloses an "external clock <p" (I2) having odd and even
phases (i.e., on dual rising and falling edges of the external clock (Inagaki
Fig. 6; see II-B» which in turn generate clock phases "to transfer data
with ... twice the conventional speed" (13). Rambus also contends that
Inagaki's clock signal is not external and that that motivation to combine the
references lacks because Hayes describes an asynchronous system. (P.O.
Resp. Br. 11.)
These arguments are not persuasive. Asynchronous to synchronous
migration was well-known and common. (See Paris Decl.) Hayes, Bennett,
and Inagaki disclose external clocks, and a "universal" desire for "faster"
operations creates an "implicit motivation," which is not isolated to
asynchronous devices. See Dystar Textilfarben GmBH & Co. Dutschland
KG v. Cg Patrick Co., 464 F.3d 1356, 1368 (Fed. Cir. 2006) ("[A]n
implicit motivation to combine exists ... when the 'improvement' is
technology-independent and the combination of references results in a
product or process that is more desirable, for example because it is stronger,
cheaper, cleaner, faster, lighter, smaller, more durable, or more efficient.")
Also, Hayes employs a clock to drive time multiplexed signals between a
master and slave (H6), thereby suggesting a substitute clock operating at half
the speed, a fewer number of data lines based on using both clock edges, or a
faster clock, as Inagaki (II-B) suggests.
Based on the foregoing discussion, the Examiner erred by failing to
maintain Requestor's proposed rejection of claims 3, 4,12,13,21-23,33,
and 34.
31
D
Case: 13-1623 Document: 10 Page: 67 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
Hayes with Inagaki - Claims 12 and 13
Based on the Rambus's explanation (P.O. Resp. Br. 11-12), NVIDIA
did not specifically propose the above-listed rejection, but instead also
included Bennett in the rejection heading and claim chart. (See Req. App.
Br. 11 (citing claim chart "Exhibit L" which is attached as Exhibit 13 to
Requestor's Appeal Brief).) But it is apparent that Bennett's teachings were
employed to suggest a single chip under the narrow definition of memory
device, and to suggest synchronization as necessary to reach claim 2, but
claims 12 and 13 do not require either. Therefore, this rejection is hereby
remanded for further consideration and under the broader interpretation of a
"memory device" which is not limited to a single chip.
Hayes with Ohshima - Claims 2-10, 12-14, 16, 17, and 20-26
Based on the NVIDIA's explanation, the Examiner erred by failing to
consider the above rejection. (See Req. App. Br. 12-13 n.16 (citing Exhibit
M and the IP Request at 30-35 which are attached respectively as Exhibits 1
and 14 to Requestor's Appeal Brief).) Taking claim 3 as an example,
NVIDIA discusses providing the relevant functionality ofOhshima's
clocking scheme in the system of Hayes. (See IP Request 30-31 and claim
chart at Ex. 14 of Requestor's Appeal Brief.) Requestor provides a similar
explanation in the Brief for claims 12 and 13.
The Examiner agrees that "Ohshima discloses the incorporation of
logic into a memory device" (RAN 44) but finds that it would not have been
obvious to incorporate all of the Hayes RAM control logic into the DRAMs
of Hayes since some of the logic must be kept separate from the DRAMs.
(See RAN 44-45.) However, the claim rejections here do not require
incorporating all the circuits and functionality into all the DRAMs, though a
32
A32
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Haves with Inagaki - Claims 12 and 13
Based on the Rambus's explanation (P.O. Resp. Br. 11-12), NVIDIA
did not specifically propose the above-listed rejection, but instead also
included Bennett in the rejection heading and claim chart. (See Req. App.
Br. 11 (citing claim chart "Exhibit L" which is attached as Exhibit 13 to
Requestor's Appeal Brief).) But it is apparent that Bennett's teachings were
employed to suggest a single chip under the narrow definition of memory
device, and to suggest synchronization as necessary to reach claim 2, but
claims 12 and 13 do not require either. Therefore, this rejection is hereby
remanded for further consideration and under the broader interpretation of a
"memory device" which is not limited to a single chip.
Haves with Ohshima - Claims 2-10, 12-14, 16, 17, and 20-26
Based on the NVIDIA's explanation, the Examiner erred by failing to
consider the above rejection. (See Req. App. Br. 12-13 n.16 (citing Exhibit
M and the IP Request at 30-35 which are attached respectively as Exhibits 1
and 14 to Requestor's Appeal Brief).) Taking claim 3 as an example,
NVIDIA discusses providing the relevant functionality ofOhshima's
clocking scheme in the system of Hayes. (See IP Request 30-31 and claim
chart at Ex. 14 of Requestor's Appeal Brief.) Requestor provides a similar
explanation in the Brief for claims 12 and 13.
The Examiner agrees that "Ohshima discloses the incorporation of
logic into a memory device" (RAN 44) but finds that it would not have been
obvious to incorporate all of the Hayes RAM control logic into the DRAMs
of Hayes since some of the logic must be kept separate from the DRAMs.
(See RAN 44-45.) However, the claim rejections here do not require
incorporating all the circuits and functionality into all the DRAMs, though a
32
D
Case: 13-1623 Document: 10 Page: 68 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
focus on remand as to which particular circuits and functions would have
been obvious and required by the claims may shed more light. Based on the
foregoing discussion, the Examiner erred by not maintaining the above
rejections of claims 2-10, 12-14, 16, 17, and 20-26.
Kushiyama with Hayes and Lu - Claims 1-14.16.17. and 19-26
Based on the NVIDIA's explanation, the Examiner erred by failing to
maintain the above rejection. (See Req. App. Br. 14-16.) Similar to the
above rejection, the Examiner agrees that Lu teaches incorporating logic
circuits into memory, but finds that it would not have been obvious to
incorporate the Hayes RAM control logic into DRAMs since some of the
logic must be kept separate from the DRAMs. (See RAN 44-45.) However,
the rejection here does not require incorporating all the RAM control logic
into DRAMs and the finding indicates the obviousness of keeping some
functions in a controller. NVIDIA reasons that integrating the DS logic of
Hayes into the Kushiyama chips would have been obvious where Lu teaches
incorporating on-chip logic to make DRAMs more intelligent and to
optimize performance at the system level. (Req. App. Br. 14-15.) Mr. Paris
corroborates this point and notes that chip designers were employing
asynchronous circuits on-chip, including some strobe signals, like RAS and
CAS, and that moving such circuits on-chip increase speed. (Parris Decl.
,-r,-r 9, 19.) Therefore, based on this record, the Examiner erred by failing to
maintain the obviousness rejection of claims 1-14, 16, 17, and 19-26.
Farmwald 755 with either ofLu or iRAM
Obviousness of Claims 1-4. 6-9. 11-13. 15. 16. 18-22. and 24-26
Primarily, the parties dispute whether or not Farmwald '755, in view
of either Lu or iRAM, renders obvious sending a strobe signal to a "memory
33
A33
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
focus on remand as to which particular circuits and functions would have
been obvious and required by the claims may shed more light. Based on the
foregoing discussion, the Examiner erred by not maintaining the above
rejections of claims 2-10, 12-14, 16, 17, and 20-26.
Kushivama with Haves and Tou - Claims 1-14,16, 17, and 19-26
Based on the NVIDIA's explanation, the Examiner erred by failing to
maintain the above rejection. (See Req. App. Br. 14-16.) Similar to the
above rejection, the Examiner agrees that Lu teaches incorporating logic
circuits into memory, but finds that it would not have been obvious to
incorporate the Hayes RAM control logic into DRAMs since some of the
logic must be kept separate from the DRAMs. (See RAN 44-45.) However,
the rejection here does not require incorporating all the RAM control logic
into DRAMs and the finding indicates the obviousness of keeping some
functions in a controller. NVIDIA reasons that integrating the DS logic of
Hayes into the Kushiyama chips would have been obvious where Lu teaches
incorporating on-chip logic to make DRAMs more intelligent and to
optimize performance at the system level. (Req. App. Br. 14-15.) Mr. Paris
corroborates this point and notes that chip designers were employing
asynchronous circuits on-chip, including some strobe signals, like RAS and
CAS, and that moving such circuits on-chip increase speed. (Parris Decl.
    9, 19.) Therefore, based on this record, the Examiner erred by failing to
maintain the obviousness rejection of claims 1-14, 16, 17, and 19-26.
Farmwald '755 with either orLu or iRAM
Obviousness orClaims 1-4,6-9,11-13,15,16,18-22, and 24-26
Primarily, the parties dispute whether or not Farmwald '755, in view
of either Lu or iRAM, renders obvious sending a strobe signal to a "memory
33
D
Case: 13-1623 Document: 10 Page: 69 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
device" as required by the independent claims at issue. (See Req. App.
Br. 18-21.) Rambus does not dispute that Farmwald '755 sends a strobe
signal called the TmcvrRW signal to a memory stick. (See P.O. Resp. Br.
21 (stating that the TmcvrRW signal "allegedly function[s] as the claimed
strobe signal" without arguing otherwise).)
Additional Findings of Fact
Farmwald '755
FWI. Farmwald employs a master/slave bus-based system. A
master gives "each device on the bus a unique device identifier (device ID)"
(col. 15, 11. 23-24) and uses the identifier to access a specific device.
"[E]ach device connected to the bus contains a special device-type register
which specifies the type of device, for instance CPU, 4 MBit memory, 64
MBit memory or disk controller." (Col. 15, 11. 33-36.) Masters also send
request packets and detect collisions for bus arbitration. (Col. 13,11.7-12;
col. 14, 11. 52-61.)
FW2. The disclosed invention saves power by performing a row
access on a "single RAM to supply all the bits for a block request (compared
to a row-access in each of multiple RAMs in conventional memory systems)
[and thus] the power per bit can be made very small." (Col. 18,11.9-12.)
Such reduced power allows RAMs to be stacked and/or placed closer
together than RAMs in the prior art. (Col. 18,11. 13-16,11.45-49.)
FW3. The invention also provides for a multiplexed time shared bus
on a small number of bus lines. Therefore, the number of pins per device,
even for an "arbitrarily large memory device[,] can be kept quite small- on
the order of20 pins .... [, and] kept constant from one generation of
DRAM density to the next." (Col. 18,11.20-23.)
34
A34
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
device" as required by the independent claims at issue. (See Req. App.
Br. l8-2l.) Rambus does not dispute that Farmwald '755 sends a strobe
signal called the TmcvrRW signal to a memory stick. (See P.O. Resp. Br.
21 (stating that the TmcvrRW signal "allegedly function[s] as the claimed
stro be signal" without arguing otherwise).)
Additional Findings of Fact
Farmwald '755
FWI. Farmwald employs a master/slave bus-based system. A
master gives "each device on the bus a unique device identifier (device ID)"
(col. 15,11.23-24) and uses the identifier to access a specific device.
"[E]ach device connected to the bus contains a special device-type register
which specifies the type of device, for instance CPU, 4 MBit memory, 64
MBit memory or disk controller." (Col. 15,11. 33-36.) Masters also send
request packets and detect collisions for bus arbitration. (Col. 13, 11. 7 -12;
col. 14,11. 52-6l.)
FW2. The disclosed invention saves power by performing a row
access on a "single RAM to supply all the bits for a block request (compared
to a row-access in each of multiple RAMs in conventional memory systems)
[and thus] the power per bit can be made very smal1." (Co1. 18,11. 9-12.)
Such reduced power allows RAMs to be stacked and/or placed closer
together than RAMs in the prior art. (Col. 18,11. 13-16,11.45-49.)
FW3. The invention also provides for a multiplexed time shared bus
on a small number of bus lines. Therefore, the number of pins per device,
even for an "arbitrarily large memory device[,] can be kept quite small - on
the order of 20 pins .... [, and] kept constant from one generation of
DRAM density to the next." (Col. 18,11.20-23.)
34
D
Case: 13-1623 Document: 10 Page: 70 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
FW4. An op code transmitted in a request packet to a slave DRAM
device specifies the time delay for writing a block of data to the data lines.
The code either directly specifies a register in the DRAM which holds the
delay value or the DRAM indirectly responds to the codes with preselected
access times (apparently via a table). (See col. 9,1. 27 to col. 10,1. 17.)
FW5. The DRAMs in Farmwald '755
differ from conventional DRAMs in a number of ways.
Registers are provided which may store control information,
device identification, device-type and other information
appropriate for the chip such as the address range for each
independent portion of the device. New bus interfaces circuits
must be added and the internals of prior art DRAM devices
need to be modified so they can provide and accept data to and
from the bus at the peak data rate of the bus. This requires
changes to the column access circuitry in the DRAM, with only
a minimal increase in die size. A circuit is provided to generate
a low skew internal device clock for devices on the bus, and
other circuits provide for demultiplexing input and multiplexing
output signals.
(Col. 4, 11. 21-35.)
FW6. Farmwald teaches that up to about 32 of the above-described
DRAMs can be used on the bus while maintaining speed. If more memory
is required, anther device can be used, a memory stick, also called a primary
bus unit (see Fig. 9), which itself can carry up to about 32 such DRAMs on
the stick (i.e., a circuit board), and the memory system can employ multiple
memory sticks. Each memory stick includes a transceiver in addition to one
or more DRAMs, all connected on a primary bus. Each memory stick, with
its primary bus of DRAMs, then connects via the transceiver device to a
larger system bus, called a transceiver bus. (Col. 20, 1. 48 to col. 21, 1. 17;
col. 22, 11. 1-31.)
35
A35
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
FW4. An op code transmitted in a request packet to a slave DRAM
device specifies the time delay for writing a block of data to the data lines.
The code either directly specifies a register in the DRAM which holds the
delay value or the DRAM indirectly responds to the codes with preselected
access times (apparently via a table). (See col. 9,1. 27 to col. 10,1. 17.)
FW5. The DRAMs in Farmwald '755
differ from conventional DRAMs in a number of ways.
Registers are provided which may store control information,
device identification, device-type and other information
appropriate for the chip such as the address range for each
independent portion of the device. New bus interfaces circuits
must be added and the internals of prior art DRAM devices
need to be modified so they can provide and accept data to and
from the bus at the peak data rate of the bus. This requires
changes to the colunm access circuitry in the DRAM, with only
a minimal increase in die size. A circuit is provided to generate
a low skew internal device clock for devices on the bus, and
other circuits provide for demultiplexing input and multiplexing
output signals.
(Col. 4, 11. 21-35.)
FW6. Fannwald teaches that up to about 32 of the above-described
DRAMs can be used on the bus while maintaining speed. If more memory
is required, anther device can be used, a memory stick, also called a primary
bus unit (see Fig. 9), which itself can carry up to about 32 such DRAMs on
the stick (i.e., a circuit board), and the memory system can employ multiple
memory sticks. Each memory stick includes a transceiver in addition to one
or more DRAMs, all connected on a primary bus. Each memory stick, with
its primary bus of DRAMs, then connects via the transceiver device to a
larger system bus, called a transceiver bus. (Col. 20, 1. 48 to col. 21, 1. 17;
col. 22, 11. 1-31.)
35
D
Case: 13-1623 Document: 10 Page: 71 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
"The transceivers are quite simple in function. They detect request
packets on the transceiver bus and transmit them to their primary bus unit."
(Col. 21, 11. 18-20.)
FW7. Farmwald '755 refers to a "memory device," a "transceiver
device" and "peripheral devices" as follows:
In a preferred implementation, all masters are situated on the
transceiver bus so there are no transceiver delays between
masters and all memory devices are on primary bus units so that
all memory accesses experience an equivalent transceiver delay,
but persons skilled in the art will recognize how to implement
systems which have masters on more than one bus unit and
memory devices on the transceiver bus as well as on primary
bus units. In general, each teaching of this invention which
refers to a memory device can be practiced using a transceiver
device and one or more memory devices on an attached
primary bus unit. Other devices, generically referred to as
peripheral devices, including disk controllers, video controllers
or I/O devices can also be attached to either the transceiver bus
or a primary bus unit as desired.
(Col. 20, 1. 67 to col. 21, 1. 14 (emphasis added).)
FW8. The system uses a TmcvrRW signal to control writing and
reading as follows:
Persons skilled in the art will recognize that a more
sophisticated transceiver can control transmissions to and from
primary bus units. An additional control line, TmcvrRW can
be bused to all devices on the transceiver bus, using that line in
conjunction with the Addr-Valid line to indicate to all devices
on the transceiver bus that the information on the data lines is
1) a request packet, 2) valid data to a slave, 3) valid data from a
slave, or 4) invalid data (or idle bus). Using this extra control
line obviates the need for the transceivers to keep track of when
data needs to be forwarded from its primary bus to the
transceiver bus - all transceivers send all data from their
36
A36
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
"The transceivers are quite simple in function. They detect request
packets on the transceiver bus and transmit them to their primary bus unit."
(Col. 21, 11. lS-20.)
FW7. Fannwald '755 refers to a "memory device," a "transceiver
device" and "peripheral devices" as follows:
In a preferred implementation, all masters are situated on the
transceiver bus so there are no transceiver delays between
masters and all memory devices are on primary bus units so that
all memory accesses experience an equivalent transceiver delay,
but persons skilled in the art will recognize how to implement
systems which have masters on more than one bus unit and
memOlY devices on the transceiver bus as well as on primmy
bus units. In general, each teaching of this invention which
refers to a memory device can be practiced using a transceiver
device and one or more memory devices on an attached
primary bus unit. Other devices, generically referred to as
peripheral devices, including disk controllers, video controllers
or 110 devices can also be attached to either the transceiver bus
or a primary bus unit as desired.
(Col. 20, 1. 67 to col. 21, 1. 14 (emphasis added).)
FWS. The system uses a TmcvrRW signal to control writing and
reading as follows:
Persons skilled in the art will recognize that a more
sophisticated transceiver can control transmissions to andfrom
primary bus units. An additional control line, TmcvrRW can
he hused to all devices on the transceiver hus, using that line in
conjunction with the Addr-Valid line to indicate to all devices
on the transceiver bus that the information on the data lines is
1) a request packet, 2) valid data to a slave, 3) valid data from a
slave, or 4) invalid data (or idle bus). Using this extra control
line obviates the need for the transceivers to keep track of when
data needs to be forwarded from its primary bus to the
transceiver bus - all transceivers send all data from their
36
D
Case: 13-1623 Document: 10 Page: 72 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
primary bus to the transceiver bus whenever the control signal
indicates the condition 2) above.
(Col. 21, 11. 35-49 (emphasis supplied).)
Farmwald' '755 discloses a "still more sophisticated transceiver"
(which only sends signals at requested times) in addition to the just-
described transceiver. (Col. 21, 11.65-68.)
FW9. Farmwald '755 describes device interfaces as follows:
The device interface to the high-speed bus can be divided into
three main parts. The first part is the electrical interface. This
part includes the input receivers, bus drivers, and clock
generation circuitry .... The final part, specifically for memory
devices such as DRAMs, is the DRAM column access path ....
Persons skilled in the art recognize how to modifY prior-art
address comparison circuitry and prior-art register circuitry in
order to practice the present invention.
(Col. 22, 11. 34-52 (emphasis supplied).)
FWI0. Circuitry which is "well-suited for use in DRAM devices ...
can be used or modified by one skilled in the art for use in other devices
connected to the bus of this invention." (Col. 22, 11.57-61.)
Lu
L 1. The Lu moderator predicts that "opportunities arise for
incorporating complex on-chip logic functions to make DRAMs more
intelligent." (Lu 98, ,-r 1.) One of the Lu article panelists explains that
adding logic functions on-chip with the memory, provide high
density and high performance in electronic systems. Data
processing executed within one chip eliminates interface loss in
speed and power consumption, which has been existing
inevitably in combinations of standard DRAMs with basic
common functions and logic parts.
(Lu 99, ,-r 1.)
37
A37
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
primary bus to the transceiver bus whenever the control signal
indicates the condition 2) above.
(Col. 21, ll. 35-49 (emphasis supplied).)
Farmwald' '755 discloses a "still more sophisticated transceiver"
(which only sends signals at requested times) in addition to the just-
described transceiver. (Col. 21, ll. 65-68.)
FW9. Farmwald '755 describes device interfaces as follows:
The device interface to the high-speed bus can be divided into
three main parts. The first part is the electrical interface. This
part includes the input receivers, bus drivers, and clock
generation circuitry .... The final part, specifically for memory
devices such as DRAMs, is the DRAM column access path ....
Persons skilled in the art recognize how to modifY prior-art
address comparison circuitry and prior-art register circuitry in
order to practice the present invention.
(Col. 22, ll. 34-52 (emphasis supplied).)
FW10. Circuitry which is "well-suited for use in DRAM devices ...
can be used or modified by one skilled in the art for use in other devices
connected to the bus of this invention." (Col. 22, 11. 57-6l.)
fu
L 1. The Lu moderator predicts that "opportunities arise for
incorporating complex on-chip logic functions to make DRAMs more
intelligent." (Lu 98,   l.) One of the Lu article panelists explains that
adding logic functions on-chip with the memory, provide high
density and high performance in electronic systems. Data
processing executed within one chip eliminates interface loss in
speed and power consumption, which has been existing
inevitably in combinations of standard DRAMs with basic
common functions and logic parts.
(Lu 99,   1.)
37
D
Case: 13-1623 Document: 10 Page: 73 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
Discussion
The Examiner and Rambus dispute NVIDIA's contention that it
would have been obvious to employ the '755 patent's TmcvrRW (i.e.,
strobe) signal as a signal to a memory device - as recited in the claims at
issue. (P.O Resp. Br. 21-29; RAN 12-24.) Contrary to Patent Owner's
arguments and the Examiner's findings, Farmwald '755, with or without
Lu's or iRAM's teachings, at least renders obvious employing the
TmcvrRW strobe signal to a "memory device" as recited in the claims at
issue here.
Requestor presents two theories for the obviousness rejection:
1) sending the TmcvrRW signal to a single chip device would have been
obvious, and 2) modifying the memory stick device to form a single chip
would have been obvious. (Req. App. Br. 18-22.)
Farmwald '755 states that "TmcvrRW can be bused to all devices on
the transceiver bus." (FW8 (emphasis added).) Requestor notes that the
Examiner acknowledges this teaching. (Req. App. Br. 19 n.25 (citing RAN
at 22).) But the Examiner finds that it is "unknown" whether chip memory
devices are on the transceiver bus. (RAN 22.) Rambus similarly maintains
that the TmcvrRW signal is only provided to the transceiver device (P.O.
Resp. Br. 23) and that Figure 9 depicts only transceiver devices, not memory
devices, on the transceiver bus (P.O. Resp. Br. 26). According to Rambus,
since only memory stick transceivers receive the TmcvrR W signal,
motivation for the proposed modification lacks and Farmwald '755 teaches
away from applying the TmcvrRW signal to a single memory device. (See
P.O. Resp. Br. 24-27). Rambus also maintains that NVIDIA failed to
38
A38
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Discussion
The Examiner and Rambus dispute NVIDIA's contention that it
would have been obvious to employ the '755 patent's TmcvrRW (i.e.,
strobe) signal as a signal to a memory device - as recited in the claims at
issue. (P.O Resp. Br. 21-29; RAN 12-24.) Contrary to Patent Owner's
arguments and the Examiner's findings, Farmwald '755, with or without
Lu's or iRAM's teachings, at least renders obvious employing the
TmcvrRW strobe signal to a "memory device" as recited in the claims at
issue here.
Requestor presents two theories for the obviousness rejection:
1) sending the TmcvrRW signal to a single chip device would have been
obvious, and 2) modifying the memory stick device to fomI a single chip
would have been obvious. (Req. App. Br. 18-22.)
Farmwald '755 states that "TmcvrRW can be bused to all devices on
the transceiver bus." (FW8 (emphasis added).) Requestor notes that the
Examiner acknowledges this teaching. (Req. App. Br. 19 n.25 (citing RAN
at 22).) But the Examiner finds that it is "unknown" whether chip memory
devices are on the transceiver bus. (RAN 22.) Rambus similarly maintains
that the TmcvrRW signal is only provided to the transceiver device (P.O.
Resp. Br. 23) and that Figure 9 depicts only transceiver devices, not memory
devices, on the transceiver bus (P.O. Resp. Br. 26). According to Rambus,
since only memory stick transceivers receive the TmcvrRW signal,
motivation for the proposed modification lacks and Farmwald '755 teaches
away from applying the TmcvrR W signal to a single memory device. (See
P.O. Resp. Br. 24-27). Rambus also maintains that NVIDIA failed to
38
D
Case: 13-1623 Document: 10 Page: 74 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
respond to the Examiner's teaching away finding, thereby waiving the issue.
(P.O. Resp. Br. 21.)
There is no dispute that Farmwald '755 discloses at least two
embodiments, a single-chip DRAM device (Fig. 2), and a primary bus unit -
also described as a memory stick device (Fig. 9). (See FW6.) This memory
stick includes at least one DRAM and a transceiver. (FW6; FW7.)
By arguing that only transceiver (i.e., memory stick) devices are on
the transceiver bus, and that the phrase "all devices on the transceiver bus"
(FW8) refers only to such memory stick devices and not to memory chip
devices, Rambus ignores the phrase "all devices" and another passage in the
'755 patent which describes "memory devices on the transceiver bus as well
as on primary bus units" (FW7 (emphasis added)). (Similar to arguments
presented supra that a memory device is limited to a single chip, Rambus
asserts that a memory stick can replace, but is not, a memory device in a
related reexamination now on appeal to the Federal Circuit (BPAI App.
No. 2010-0011178, Reexam. No. 901010420.)9
As such, NVIDIA's argument is persuasive and supported by the
record: The TmcvrRW signal indicates that "'valid data to a slave'" is
available on the data bus, and that "[ c ]learly, a slave (e.g., a memory device
should not begin sampling data from the bus if the data is not valid.
Also ... all devices on the bus receive the TmcvrRW signal", including the
9 See supra note 4. The Board held in Appeal No. '1178 that the memory
stick embodiment disclosed in the related '918 patent there under
reexamination is a memory device. The '918 patent claims continuity to the
'755 patent which both claim continuity back to the same underlying
application.
39
A39
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
respond to the Examiner's teaching away finding, thereby waiving the issue.
(P.O. Resp. Br. 2l.)
There is no dispute that Farmwald '755 discloses at least two
embodiments, a single-chip DRAM device (Fig. 2), and a primary bus unit -
also described as a memory stick device (Fig. 9). (See FW6.) This memory
stick includes at least one DRAM and a transceiver. (FW6; FW7.)
By arguing that only transceiver (i.e., memory stick) devices are on
the transceiver bus, and that the phrase "all devices on the transceiver bus"
(FW8) refers only to such memory stick devices and not to memory chip
devices, Rambus ignores the phrase "all devices" and another passage in the
'755 patent which describes "memory devices on the transceiver bus as well
as on primary bus units" (FW7 (emphasis added)). (Similar to arguments
presented supra that a memory device is limited to a single chip, Rambus
asserts that a memory stick can replace, but is not, a memory device in a
related reexamination now on appeal to the Federal Circuit (BPAI App.
No. 2010-0011178, Reexam. No. 901010420.)9
As such, NVIDIA's argument is persuasive and supported by the
record: The TrncvrRW signal indicates that "'valid data to a slave'" is
available on the data bus, and that "[ c Jlearly, a slave (e.g., a memory device
should not begin sampling data from the bus if the data is not valid.
Also ... all devices on the bus receive the TrncvrRW signal", including the
9 See supra note 4. The Board held in Appeal No. '1178 that the memory
stick embodiment disclosed in the related '918 patent there under
reexamination is a memory device. The '918 patent claims continuity to the
'755 patent which both claim continuity back to the same underlying
application.
39
D
Case: 13-1623 Document: 10 Page: 75 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
single-chip DRAM memory devices and the primary bus units. (Req. App.
Br. 19.)
Farmwald '755 also specifically teaches that "each teaching of this
invention which refers to a memory device can be practiced using a
transceiver device and one or more memory devices," i.e., can be
practiced using a memory stick. (FW7 (emphasis added).) Thus, even if
Farmwald '755 does not anticipate the claims at issue here, skilled artisans
would have recognized that teachings involving a single-chip (DRAM)
memory device apply to transceiver devices and vice versa as Farmwald
'755 indicates. (FW7; see also FWI0 (showing that skilled artisans would
have recognized that other devices on the bus can be modified similarly to
DRAMs).)
The Examiner's findings do not rebut persuasively NVIDIA's
contentions for obviousness. The Examiner points to arguments by Rambus
and Respondent's expert Mr. Murphy and concludes that Farmwald '755
teaches away from the claimed invention because the memory stick
embodiment provides for chip expansion - i.e., allowing the number of chips
on the stick to increase. (RAN 23 (citing Murphy Supp. Decl. ,-r 34).)
According to the Examiner, integrating the memory stick into a single chip
removes the benefit of chip expansion, thereby teaching away from such
integration. (RAN 23.)
Based on the discussion above, the Examiner's rationale, like
Rambus's, fails to address the fact found supra that all memory devices in
Farmwald '755 receive the strobe signal, TmcvrRW. Thus, Farmwald' 755
cannot teach away as asserted. And the finding of teaching away contradicts
the Examiner's finding that it is unknown whether the signal goes to both
40
A40
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
single-chip DRAM memory devices and the primary bus units. (Req. App.
Br. 19.)
Farmwald '755 also specifically teaches that "each teaching of this
invention which refers to a memOfY device can be practiced using a
transceiver device and one or more memory devices," i.e., can be
practiced using a memory stick. (FW7 (emphasis added).) Thus, even if
Farmwald '755 does not anticipate the claims at issue here, skilled artisans
would have recognized that teachings involving a single-chip (DRAM)
memory device apply to transceiver devices and vice versa as Fannwald
'755 indicates. (FW7; see also FWlO (showing that skilled artisans would
have recognized that other devices on the bus can be modified similarly to
DRAMs).)
The Examiner's findings do not rebut persuasively NVIDIA's
contentions for obviousness. The Examiner points to arguments by Rambus
and Respondent's expert Mr. Murphy and concludes that Farmwald '755
teaches away from the claimed invention because the memory stick
embodiment provides for chip expansion - i.e., allowing the number of chips
on the stick to increase. (RAN 23 (citing Murphy Supp. Decl. ,-r 34).)
According to the Examiner, integrating the memory stick into a single chip
removes the benefit of chip expansion, thereby teaching away from such
integration. (RAN 23.)
Based on the discussion above, the Examiner's rationale, like
Rambus's, fails to address the fact found supra that all memory devices in
Fannwald '755 receive the strobe signal, TmcvrRW. Thus, Fannwald' 755
cannot teach away as asserted. And the finding of teaching away contradicts
the Examiner's finding that it is unknown whether the signal goes to both
40
D
Case: 13-1623 Document: 10 Page: 76 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 B1
devices and Rambus' s assertion that the chip and stick embodiments act as
(slave) replacements for one another. The '353 patent at least suggests that
each device can receive a TmcvrRW signal to indicate valid data to that
slave.
Also, contrary to the Examiner's and Patent Owner's rationales, even
if memory sticks allow for chip expansion, this does not relate to NVIDIA's
first listed rationale for combining Farmwald '755 and Lu (or iRAM) - i.e.,
whether or not applying the TmcvrRW signal to a single chip would have
been obvious. In other words, Farmwald '755's memory sticks could have
been expanded regardless of whether or not it would have been obvious to
send the TmcvrRW signal directly to the single-chip devices disclosed in
Farmwald '755.
As NVIDIA similarly points out, one major benefit of the
Farmwald '755 system is to allow different types of devices, including
peripheral devices, DRAMs, and memory sticks, to attach to the bus. (Req.
Reb. Br. 6-7 n.12; accord FW1; FW7.) Farmwald '755 also indicates other
goals, such as decreasing the power per pin while allowing for natural
DRAM expansion in "an arbitrarily large memory device" (FW3). (Accord
FW2.) Modifying a DRAM so that it accepts the TmcvrRW signal in the
manner proposed does not deter from the goal of also providing an
expandable memory stick and other devices attached to the bus, and such
DRAM modifications were well within the skill in the art. (See e.g. FW7,
FW9, FW10, L1, Paris Decl. ,-r,-r 9, 14).)
Farmwald '755 teaches modifying existing DRAMs (FW4, FW9,
FW10) and teaches "sophisticated" and "still more sophisticated" devices
(FW8.) And Farmwald '755 does not clearly define a transceiver (on a
41
A41
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
devices and Rambus' s assertion that the chip and stick embodiments act as
(slave) replacements for one another. The '353 patent at least suggests that
each device can receive a TrncvrRW signal to indicate valid data to that
slave.
Also, contrary to the Examiner's and Patent Owner's rationales, even
if memory sticks allow for chip expansion, this does not relate to NVIDIA's
first listed rationale for combining Farmwald '755 and Lu (or iRAM) - i.e.,
whether or not applying the TrncvrRW signal to a single chip would have
been obvious. In other words, Farmwald '755's memory sticks could have
been expanded regardless of whether or not it would have been obvious to
send the TrncvrRW signal directly to the single-chip devices disclosed in
Farmwald '755.
As NVIDIA similarly points out, one major benefit of the
Farmwald '755 system is to allow different types of devices, including
peripheral devices, DRAMs, and memory sticks, to attach to the bus. (Req.
Reb. Br. 6-7 n.12; accord FW1; FW7.) Farmwald '755 also indicates other
goals, such as decreasing the power per pin while allowing for natural
DRAM expansion in "an arbitrarily large memory device" (FW3). (Accord
FW2.) Modifying a DRAM so that it accepts the TmcvrRW signal in the
manner proposed does not deter from the goal of also providing an
expandable memory stick and other devices attached to the bus, and such
DRAM modifications were well within the skill in the art. (See e.g. FW7,
FW9, FW10, Ll, Paris Decl. ,-r,-r 9, 14).)
Farmwald '755 teaches modifying existing DRAMs (FW4, FW9,
FW 10) and teaches "sophisticated" and "still more sophisticated" devices
(FWS.) And Farmwald '755 does not clearly define a transceiver (on a
41
D
Case: 13-1623 Document: 10 Page: 77 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
memory stick) as a master (see FW7), as masters have relatively
complicated functions (FW1), and the transceiver devices are described as
bus interfaces with relatively simple functions (FW6). Accordingly,
Rambus's contention that one of the Farmwald '755 goals is to keep slaves
as simple as possible (P.O. Resp. Br. 27) ignores the fact that a memory
stick typically functions as a slave (with some embodiments having masters
thereon) but can become more sophisticated to obtain other goals (i.e., a
tradeoff). Most if not all of the goals (e.g., low power per pin, DRAM
memory expansion, attachment of multiple devices to a small bus, high
speed, etc., see FW2, FW3) would not have been compromised by sending a
TmcvrRW strobe signal to a DRAM.
NVIDIA further relies on Lu to show that it would have been obvious
to employ known memory stick functions in a single integrated DRAM
package to increase speed and decrease power consumption. (Req. App.
Br. 20 (quoting Lu at 99); accord Ll.) Farmwald '755 buttresses Lu and
shows that skilled artisans knew how to modify existing DRAM logic
circuits (FW9), and Farmwald '755 specifically teaches modifying such
DRAMs (FWI-3, FW5, FWI0).
Rambus's counter arguments that Lu is equivocal and teaches away
from moving logic on-chip are not persuasive. (P.O. Resp. Br. 27-30.)
Rambus's arguments show that Lu teaches tradeoffs in terms of
"economics" versus "generic[ ]. .. benefits." (P.O. Resp. Br. 27.) But the
benefits of speed, reduced power (i.e., efficiency), and compactness
constitute universal motivators "even absent any hint of suggestion in the
references themselves." Dystar, 464 F.3d at 1368 ("[A]n implicit
motivation to combine exists ... when the 'improvement' is technology-
42
A42
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
memory stick) as a master (see FW7), as masters have relatively
complicated functions (FW1), and the transceiver devices are described as
bus interfaces with relatively simple functions (FW6). Accordingly,
Rambus's contention that one of the Farmwald '755 goals is to keep slaves
as simple as possible (P.O. Resp. Br. 27) ignores the fact that a memory
stick typically functions as a slave (with some embodiments having masters
thereon) but can become more sophisticated to obtain other goals (i.e., a
tradeoff). Most ifnot all of the goals (e.g., low power per pin, DRAM
memory expansion, attachment of multiple devices to a small bus, high
speed, etc., see FW2, FW3) would not have been compromised by sending a
TrncvrRW strobe signal to a DRAM.
NVIDIA further relies on Lu to show that it would have been obvious
to employ known memory stick fimctions in a single integrated DRAM
package to increase speed and decrease power consumption. (Req. App.
Br. 20 (quoting Lu at 99); accordLl.) Farmwald '755 buttresses Lu and
shows that skilled artisans knew how to modify existing DRAM logic
circuits (FW9), and Fannwald '755 specifically teaches modifying such
DRAMs (FWl-3, FW5, FW10).
Rambus's counter arguments that Lu is equivocal and teaches away
from moving logic on-chip are not persuasive. (P.O. Resp. Br. 27-30.)
Rambus's arguments show that Lu teaches tradeoffs in terms of
"economics" versus "generic[ ]. .. benefits." (P.O. Resp. Br. 27.) But the
benefits of speed, reduced power (i.e., efficiency), and compactness
constitute universal motivators "even absent any hint of suggestion in the
references themselves." Dystar, 464 F .3d at 13 68 ("[A]n implicit
motivation to combine exists ... when the 'improvement' is technology-
42
D
Case: 13-1623 Document: 10 Page: 78 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
independent and the combination of references results in a product or
process that is more desirable, for example because it is stronger, cheaper,
cleaner, faster, lighter, smaller, more durable, or more efficient.")
"In such situations, the proper question is whether the ordinary
artisan possesses knowledge and skills rendering him capable of combining
the prior art references." Id. Rambus does not direct attention to sufficient
evidence showing that skilled artisans were incapable of combining memory
stick functions into a DRAM (which would have rendered the DRAM faster,
smaller, and more durable than the memory stick).
Under another, but similar, rationale involving the proposed rejection
based on Farmwald '755 and Lu or iRAM, NVIDIA contends that it would
have been obvious to integrate the transceiver and DRAMs of Farmwald's
memory stick into a single chip. (Req. App. Br. 20-22 (id. at 22 citing LP.
Request at 58-59.) Here, the Examiner's and Respondent's teaching away
rationale based on defeating chip expansion on the memory stick may be
more applicable, but it is not persuasive. Even if a manufacturer would have
produced memory sticks for the purpose of providing a customer the option
of adding more DRAM chips to the memory stick as the Examiner and
Rambus maintain, it does not follow that other customers would not have
desired a large amount of memory in a single integrated chip, based on the
reasons discussed supra. For example, such a chip would have offered
speed, compactness, efficiency, and durability based on the integration,
universal desires carrying implicit motivation according to Dystar, 464 F.3d
at 1368.
Farmwald '755, like iRAM, (II-B) describes a natural growth in the
industry toward enhanced memory DRAMs (FW3), and indicates that
43
A43
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
independent and the combination of references results in a product or
process that is more desirable, for example because it is stronger, cheaper,
cleaner, faster, lighter, smaller, more durable, or more efficient.")
"In such situations, the proper question is whether the ordinary
artisan possesses knowledge and skills rendering him capahle of combining
the prior art references." ld. Rambus does not direct attention to sutlicient
evidence showing that skilled artisans were incapable of combining memory
stick functions into a DRAM (which would have rendered the DRAM faster,
smaller, and more durable than the memory stick).
Under another, but similar, rationale involving the proposed rejection
based on Farmwald '755 and Lu or iRAM, NVIDIA contends that it would
have been obvious to integrate the transceiver and DRAMs of Farmwald's
memory stick into a single chip. (Req. App. Br. 20-22 (id. at 22 citing l.P.
Request at 58-59.) Here, the Examiner's and Respondent's teaching away
rationale based on defeating chip expansion on the memory stick may be
more applicable, but it is not persuasive. Even if a manufacturer would have
produced memory sticks for the purpose of providing a customer the option
of adding more DRAM chips to the memory stick as the Examiner and
Rambus maintain, it does not follow that other customers would not have
desired a large amount of memory in a single integrated chip, based on the
reasons discussed supra. For example, such a chip would have offered
speed, compactness, efficiency, and durability based on the integration,
universal desires carrying implicit motivation according to Dystar, 464 F.3d
at 1368.
Farmwald '755, like iRAM, (11-13) describes a natural growth in the
industry toward enhanced memory DRAMs (FW3), and indicates that
43
D
Case: 13-1623 Document: 10 Page: 79 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
integrating new circuits and logic into existing single-chip DRAMs was
routine (FW 5, FW9, FWI0). Moreover, iRAM assumes an integrated
memory device (i.e., iRAM means integrated RAM) and teaches shifting
some of the CPU tasks to this integrated RAM, relieving the CPU of
hardware and transceiver functions. (iRAM 1-1; 3-432-433.)10 In other
words, iRAM teaches integrating more functions into a single device, an
integrated memory, to relieve the CPU.
Rambus's arguments fail to show with persuasive evidence that a
memory stick device would have been as fast (or as compact or durable) as
an integrated DRAM. And iRAM points skilled artisans towards an
integrated memory - based, for example, on the noted universal desires.
Mr. Murphy relies on Farmwald '755 (Murphy Supp. Decl. at ~ 5   (citing
col. 21, 11. 27-34) to show speed reduction, but Mr. Murphy does not explain
why this occurs. 11
The evidence and common sense indicates that an integrated
transceiver and DRAM would have been faster than a non-integrated
transceiver and DRAM merely based on the distance (propagation delay)
between the two. (See Parris Decl. ~ 19; Ll; iRAM 4-433 ("optimized
timing")). Rambus and the Examiner do not contend, much less show, that
skilled artisans, motivated by the universal desire for speed, durability, and
10 These latter pages, i.e., 3-432, etc., appear under headings of "AP-132" on
each page, which appear to signify an attached application note by John J.
Fallin and William H. Righter (Intel. Corp. 1982). (See iRAM at 3-431.)
11 Mr. Parris states that Mr. Murphy fails to provide a reason why "moving
logic on-chip" would decrease speed, and explains that physically closer
devices increase speed. (Parris Decl. ~ 19.)
44
A44
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
integrating new circuits and logic into existing single-chip DRAMs was
routine (FW 5, FW9, FWlO). Moreover, iRAM assumes an integrated
memory device (Le., iRAM means integrated RAM) and teaches shifting
some of the CPU tasks to this integrated RAM, relieving the CPU of
hardware and transceiver functions. (iRAM 1-1; 3-432-433./° In other
words, iRAM teaches integrating more functions into a single device, an
integrated memory, to relieve the CPU.
Rambus's arguments fail to show with persuasive evidence that a
memory stick device would have been as fast (or as compact or durable) as
an integrated DRAM. And iRAM points skilled artisans towards an
integrated memory - based, for example, on the noted universal desires.
Mr. Murphy relies on Farmwald '755 (Murphy Supp. Decl. at ~ 5   (citing
col. 21, 11. 27-34) to show speed reduction, but Mr. Murphy does not explain
why this occurs. 11
The evidence and common sense indicates that an integrated
transceiver and DRAM would have been faster than a non-integrated
transceiver and DRAM merely based on the distance (propagation delay)
between the two. (See Parris Decl. ~ 19; Ll; iRAM 4-433 ("optimized
timing")). Rambus and the Examiner do not contend, much less show, that
skilled artisans, motivated by the universal desire for speed, durability, and
10 These latter pages, i.e., 3-432, etc., appear under headings of"AP-132" on
each page, which appear to signify an attached application note by John 1.
Fallin and William H. Righter (Intel. Corp. 1982). (See iRAM at 3-431.)
11 Mr. Parris states that Mr. Murphy fails to provide a reason why "moving
logic on-chip" would decrease speed, and explains that physically closer
devices increase speed. (Parris Decl. ~ 19.)
44
D
Case: 13-1623 Document: 10 Page: 80 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Control 95/001, 169
Patent 6,591,353 Bl
compactness, would have lacked the capability to integrate the memory stick
components into a single chip.
Pursuant to the foregoing discussion, the Examiner erred by not
maintaining NVIDIA's proposed rejection of claim 1, based on Farmwald
'755 and Lu or iRAM, and also, the proposed rejection of claims 2-13,15,
16, 18-22, and 24-35, because the Examiner focuses on the alleged
deficiencies of the rejection of claim 1.
Remaining Proposed Rejections
Reversal of the failure to maintain the proposed rejections of claims 1-
26 makes it unnecessary to reach the remaining rejections for anticipation
and double patenting based on Farmwald '037, and for obviousness based,
inter alia, on Barth. Cf In re Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009)
(not reaching obviousness after finding anticipation).
DECISION
The Examiner's decision to reject claims 1, 5, 7, 11, 14, 19, and 23 as
anticipated based on Hayes is affirmed. The Examiner's decision not to
reject appealed claims 1-26 for obviousness based on the listed references
. d 12
supra IS reverse .
AFFIRMED-IN-PART
ak
12 See Bd.R. 41.77 (b ) (reversal of determination not to rej ect is denominated
a new ground of rejection).
45
A45
Appeal 2011-010623
Reexamination Control 95/001,169
Patent 6,591,353 Bl
compactness, would have lacked the capability to integrate the memory stick
components into a single chip.
Pursuant to the foregoing discussion, the Examiner erred by not
maintaining NVIDIA's proposed rejection of claim 1, based on Farmwald
'755 and Lu or iRAM, and also, the proposed rejection of claims 2-13, 15,
16, 18-22, and 24-35, because the Examiner focuses on the alleged
deficiencies of the rej ection of claim 1.
Remaining Proposed Rejections
Reversal of the failure to maintain the proposed rejections of claims 1-
26 makes it unnecessary to reach the remaining rejections for anticipation
and double patenting based on Farmwald '037, and for obviousness based,
inter alia, on Barth. Gf In re Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009)
(not reaching obviousness after finding anticipation).
DECISION
The Examiner's decision to reject claims 1, 5, 7, 11, 14, 19, and 23 as
anticipated based on Hayes is affinned. The Examiner's decision not to
reject appealed claims 1-26 for obviousness based on the listed references
. d
P
supra 1S reverse . -
AFFIRMED-IN-PART
ak
12 See Bd.R. 41.77(b) (reversal of detennination not to reject is denominated
a new ground of rejection).
45
D
Case: 13-1623 Document: 10 Page: 81 Filed: 11/04/2013
Appeal 2011-010623
Reexamination Contro195/001, 169
Patent 6,591,353 Bl
Finnegan Henderson Farabow
Garrett & Dunner, LLP
901 New York Avenue, NW
Washingon, DC 20001
Third Party Requester:
Haynes and Boone, LLP
IP Section
2323 Victory Avenue
Suite 700
Dallas, TX 75219
46
A46
Appeal 2011-010623
Reexamination Contro195/001,169
Patent 6,591,353 B1
Finnegan Henderson Farabow
Garrett & Dunner, LLP
901 New York Avenue, NW
Washingon, DC 20001
Third Party Requester:
Haynes and Boone, LLP
IP Section
2323 Victory Avenue
Suite 700
Dallas, TX 75219
46
D
Case: 13-1623 Document: 10 Page: 82 Filed: 11/04/2013
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Inter Partes
RAMBUS, INC.
Patent Owner, Appellant
v.
NVIDIA, CORP.
Requester (Withdrawn)
Appea12013-000562
Reexamination Control No. 95/001,169
United States Patent 6,591,353 B1
Technology Center 3900
Before ALLEN R. MacDONALD, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.
EASTHOM, Administrative Patent Judge.
DECISION ON APPEAL
A131
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Inter Panes
RAMBUS, INC.
Patent Owner, Appellant
v.
NVIDIA, CORP.
Requester (Withdrawn)
Appeal 2013-000562
Reexamination Control No. 95/001,169
United States Patent 6,591,353 B1
Technology Center 3900
Before ALLEN R. MacDONALD, KARL D. EASTHOM, and
STEPHEN C. SID, Administrative Patent Judges.
EASTHOM, Administrative Patent Judge.
DECISION ON APPEAL
Case: 13-1623 Document: 10 Page: 83 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
This reexamination proceeding (95/001,169) returns to the Board after
the Examiner's Determination Under 37 CF.R. 41.77(d) (April 19, 2012)
which responds to the Board's rejections designated as new grounds in its
previous Decision on Appeal, Inter Partes NVIDIA, Corp. v. Rambus, Inc.,
BPAI 2011-010623 (Jan. 24, 2012) involving Patent Owner Rambus's '353
patent at issue here.
1
We have jurisdiction under 35 U.S.C. §§ 134(b) and
306.
The previous Board Decision, BP AI 2011-010623, is sustained and is
part of this decision.
STATEMENT OF THE CASE
In the above-described '623 Board Decision, the Board, in a
bifurcated decision, affirmed the Examiner's decision to maintain the
rejection of claims 1,5,7, 11, 14, 19, and 23 cross-appealed by Rambus, and
reversed the Examiner's decision not to reject claims 1-26 appealed by
Third-Party Requester NVIDIA. (See '623 Bd. Dec. 45.) As to the
reversal, pursuant to 37 C.F.R. § 41.77(b), the '623 Board Decision
reversed the portion of the Examiner's Answer (which incorporates by
reference the Examiner's Right of Appeal Notice) in which the Examiner
decided not to maintain NVIDIA's proposed rejections, and the Board
designated the reversal "a new ground of rejection." (See '623 Bd. Dec. 45
n.12.f
1 U.S. 6,591,353 Bl to Barth et aI., Protocol For Communication with
Dynamic Memory (July 8, 22, 2003).
2 The rejections are designated as "new ground[s]" under 37 CFR § 41.77(b)
because the Examiner decided not to adopt or maintain them and the Board
reversed the Examiner. Notwithstanding the "new ground" designation,
2
A132
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
This reexamination proceeding (95/001,169) returns to the Board after
the Examiner's Determination Under 37 C.P.R. 41.77(d) (April 19, 2012)
which responds to the Board's rejections designated as new grounds in its
previous Decision on Appeal, Inter Partes NVIDIA, Corp. v. Rambus, Inc.,
BPAT 2011-010623 (Jan. 24, 2012) involving Patent Owner Rambus's '353
patent at issue here.) We have jurisdiction under 35 US.c. §§ 134(b) and
306.
The previous Board Decision, BP AI 2011-010623, is sustained and is
part of this decision.
STATEMENT OF THE CASE
In the above-described '623 Board Decision, the Board, in a
bifurcated decision, affirmed the Examiner's decision to maintain the
rejection of claims 1,5,7, 11, 14, 19, and 23 cross-appealed by Rambus, and
reversed the Examiner's decision not to reject claims 1-26 appealed by
Third-Party Requester NVIDIA. (See '623 Bd. Dec. 45.) As to the
reversal, pursuant to 37 C.F.R. § 41. 77 (b), the '623 Board Decision
reversed the portion of the Examiner's Answer (which incorporates by
reference the Examiner's Right of Appeal Notice) in which the Examiner
decided not to maintain NVlDLA's proposed rejections, and the Board
designated the reversal "a new ground ofrejection." (See '623 Bd. Dec. 45
n. 12,i
) U.S. 6,591,353 Bl to Barth et al., Protocol For Communication with
Dynamic Memory (July 8, 22, 2003).
2 The rejections are designated as "new ground[s]" under 37 CFR § 41.77(b)
because the Examiner decided not to adopt or maintain them and the Board
reversed the Examiner. Notwithstanding the "new ground" designation,
2
Case: 13-1623 Document: 10 Page: 84 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
In response to the '623 Board Decision, Rambus elected the 37 C.F .R.
§ 41.77(b) (1) option of reopening prosecution before the Examiner to
address the new grounds of rej ections (originally proposed by NVID A, see
note 2 supra) and presented new evidence to rebut the "new ground [ s] of
rejection" by the Board as required under 37 C.F.R. § 41.77 (b) (1) & (d).
(See Rambus's Request to Reopen Prosecution (Feb. 24,2012).) Prior to
Rambus's Request to Reopen and after the '623 Board Decision, NVIDIA,
citing a settlement with Rambus, withdrew from the reexamination
proceeding. (See Notice o/Withdrawal o/Third-Party Requester's Appeal
and Other Papers (Feb. 17, 2012); Notice 0/ Non-Participation in Inter
Partes Reexamination (Feb. 8,2012).)
Under 37 C.F.R. § 41.77(d), the prior '623 Board Decision is
"binding upon the examiner unless an amendment or new evidence not
previously of record is made which, in the opinion of the examiner,
overcomes the new ground ofrejection stated in the [Board's '623]
decision." Further pursuant to 3 7 C.F .R. § 41. 77 (d), the Examiner must
consider Rambus' s Request to Reopen and "issue a determination that the
rejection is maintained or has been overcome."
Pursuant to 37 C.F.R. § 41.77(d), the Examiner determined that
Rambus's Request to Reopen did not overcome the "new ground [ s]" of
rejections. In the Examiner's Determination, the Examiner considered
Rambus's newly submitted evidence as discussed further below (which
third-party Requester NVIDIA originally proposed the rejections in its inter
partes request, though some grounds thereof ultimately were remanded with
modification to the rationale and/or findings. (See Bd. Dec. 26-27 (listing
NVIDIA's originally proposed rejections).)
3
A133
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
In response to the '623 Board Decision, Rambus elected the 37 C.F.R.
§ 41.77(b) (1) option of reopening prosecution before the Examiner to
address the new grounds of rejections (originally proposed by NVIDA, see
note 2 supra) and presented new evidence to rebut the "new ground [ s] of
rejection" by the Board as required under 37 C.F.R. § 41.77 (b) (1) & (d).
(See Rambus's Request to Reopen Prosecution (Feb. 24,2012).) Prior to
Rambus's Request to Reopen and after the '623 Board Decision, NVIDIA,
citing a settlement with Rambus, withdrew from the reexamination
proceeding. (See Notice o/Withdrawal o/Third-Party Requester's Appeal
and Other Papers (Feb. 17,2012); Notice o/Non-Participation in Inter
Partes Reexamination (Feb. 8,2012).)
Under 37 C.F.R. § 41.77(d), the prior '623 Board Decision is
"binding upon the examiner unless an amendment or new evidence not
previously of record is made which, in the opinion of the examiner,
overcomes the new ground ofrejection stated in the [Board's '623]
decision." Further pursuant to 37 C.F.R. § 41.77(d), the Examiner must
consider Rambus's Request to Reopen and "issue a determination that the
rejection is maintained or has been overcome."
Pursuant to 37 C.P.R. § 41.77(d), the Examiner determined that
Rambus's Request to Reopen did not overcome the "new ground[s]" of
rejections. In the Examiner's Determination, the Examiner considered
Rambus's newly submitted evidence as discussed further below (which
third-party Requester NVTDTA originally proposed the rejections in its inter
partes request, though some grounds thereof ultimately were remanded with
modification to the rationale and/or findings. (See Bd. Dec. 26-27 (listing
NVIDIA's originally proposed rejections).)
3
Case: 13-1623 Document: 10 Page: 85 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
includes a Third Supplemental Declaration by Rambus's expert Robert J.
Murphy and other extrinsic evidence including publications by one of
NVIDIA's experts). (See Reopen Req. 2.)
The following "new ground [ s] of rejection" listed in the '623 Board
Decision are addressed in the Examiner's Determination and are at issue
here:
Claims 2,6, 10, 17,25, and 26 as obvious under 35 U.S.C. § 103(a)
based on Hayes and Bennett et aI., U.S. Patent 4,734,909 (Mar. 29, 1988)
("Bennett").
Claims 3, 4,12,13,21, and 22 as obvious under 35 U.S.C. § 103(a)
based on Hayes, Bennett and Inagaki, JP 57-210495 (Dec. 24,1982).
Claims 12 and 13 as obvious under 35 U.S.C. § 103(a) based on
Hayes and Inagaki.
Claims 2-10, 12-14, 16, 17, and 20-26 as obvious under 35 U.S.C.
§ 103(a) based on Hayes and Ohshima et aI., High Speed DRAMs with
Innovative Architectures IEICE Trans. Electron V. ECC-7, No.8, 1303-15
(Aug. 1994) ("Ohshima").
Claims 1-14, 16, 17, and 19-26 as obvious under 35 U.S.C. § 103(a)
based on Kushiyama, Hayes, and Lu, The Future of DRAMs, 1988 IEEE
Inter. Solid-State Cir. Conf. (ISSCC), Digest Tech. Papers, 98-99 (Feb.
1988)("Lu").
Claims 1-4,6-9, 11-13, 15, 16, 18-22, and 24-26 as obvious under
35 U.S.C. § 103(a) based on Farmwald et aI., U.S. 5,319,755 (June 7, 1994)
("Farmwald '755") and Lu.
4
A134
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
includes a Third Supplemental Declaration by Rambus's expert Robert 1.
Murphy and other extrinsic evidence including publications by one of
NVIDIA's experts). (See Reopen Req. 2.)
The following "new ground[s] of rejection" listed in the '623 Board
Decision are addressed in the Examiner's Determination and are at issue
here:
Claims 2,6, 10, 17,25, and 26 as obvious under 35 U.S.C. § 103(a)
based on Hayes and Bennett et al., U.S. Patent 4,734,909 (Mar. 29, 1988)
("Bennett").
Claims 3, 4, 12, 13,21, and 22 as obvious under 35 U.S.c. § 103(a)
based on Hayes, Bennett and Inagaki, JP 57-210495 (Dec. 24, 1982).
Claims 12 and 13 as obvious under 35 U.S.C. § 1 03(a) based on
Hayes and lnagaki.
Claims 2-10, 12-14, 16, 17, and 20-26 as obvious under 35 U.S.c.
§ 103(a) based on Hayes and Ohshima et al., High Speed DRAMs with
Innovative Architectures IEICE Trans. Electron V. ECC-7, No.8, 1303-15
(Aug. 1994) ("Ohshima").
Claims 1-14, 16, 17, and 19-26asobviousunder35U.S.C.§ 103(a)
based on Kushiyama, Hayes, and Lu, The Future of DRAMs, 1988lEEE
Inter. Solid-State Cir. Conf. (ISSCC), Digest Tech. Papers, 98-99 (Feb.
1988)("Lu").
Claims 1-4,6-9, 11-13, 15, 16, 18-22, and 24-26 as obvious under
35 U.S.c. § 103(a) based on Fannwald et al., U.S. 5,319,755 (June 7, 1994)
("Fannwald '755") and Lu.
4
Case: 13-1623 Document: 10 Page: 86 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
Claims 1-4,6-9, 11-13, 15, 16, 18-22, and 24-26 as obvious under
35 U.S.C. § 103(a) based on Farmwald '755 and iRAM, Memory
Components Handbook, Intel. Corp., Ch. 1, 3 (1985).
(See '623 Bd. Dec. 27.)
Exemplary claims of the '353 patent under reexamination follow:
1. A method of operation in a memory device that includes a plurality
of memory cells, the method comprising:
receiving a command to sample data;
deferring sampling a first portion of the data until an external strobe
signal is detected; and
sampling the first portion of the data from an external signal line in
response to detecting the external strobe signal.
2. The method of claim 1, wherein the first portion of the data is
sampled synchronously with respect to an external clock signal.
5. The method of claim 1, further comprising:
detecting an external terminate signal; and
sampling additional portions of the data during a time interval
between detection of the external strobe signal and detection of the external
terminate signal.
11. A method of controlling a memory device that includes a plurality
of memory cells, the method comprising:
issuing a first write command to the memory device, the memory
device being configured to defer sampling data that corresponds to the first
write command until a strobe signal is detected;
delaying for a first time period after issuing the write command; and
after delaying for the first time period, issuing the strobe signal to the
memory device to initiate sampling of a first portion of the data by the
memory device.
5
A135
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Claims 1-4,6-9, 11-13, 15, 16, 18-22, and 24-26 as obvious under
35 U.S.C. § 103(a) based on Farmwald '755 and iRAM, MemOlY
Components Handbook, Intel. Corp., Ch. 1,3 (1985).
(See '623 Bd. Dec. 27.)
Exemplary claims of the '353 patent under reexamination follow:
1. A method of operation in a memory device that includes a plurality
of memory cells, the method comprising:
receiving a command to sample data;
deferring sampling a first portion of the data until an external strobe
signal is detected; and
sampling the first portion of the data from an external signal line in
response to detecting the external strobe signal.
2. The method of claim 1, wherein the first portion of the data is
sampled synchronously with respect to an external clock signal.
5. The method of claim 1, further comprising:
detecting an external terminate signal; and
sampling additional portions of the data during a time interval
between detection of the external strobe signal and detection of the external
terminate signal.
11. A method of controlling a memory device that includes a plurality
of memory cells, the method comprising:
issuing a first write command to the memory device, the memory
device being configured to defer sampling data that corresponds to the first
write command until a strobe signal is detected;
delaying for a first time period after issuing the write command; and
after delaying for the first time period, issuing the strobe signal to the
memory device to initiate sampling of a first portion of the data by the
memory device.
5
Case: 13-1623 Document: 10 Page: 87 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
19. A memory device having a plurality of memory cells, the memory
device comprising:
a plurality of input receiver circuits to receive a write command and
sample data that corresponds to the write command in response to detecting
a strobe signal that is delayed relative to the write command by a first time
period.
DICUSSION
Pursuant to 37 CPR § 41.77(t) and the new grounds ofrejection
issued in the '623 Board Decision, the Board hereby "reconsiders the matter
and issue[ s] a new decision. The new decision ... incorporate [ s] the earlier
['623Board D]ecision, except for those portions specifically withdrawn." No
such portions are withdrawn.
The Examiner's Determination is also hereby adopted and
incorporated by reference. Rambus did not file "comments in response to
the [E]xaminer's [D]etermination" as allowed under 37 CPR § 41.77(e) to
rebut or show error in the Examiner's Determination with respect to the new
grounds.
Preliminary Remarks - Bifurcated Proceeding
Aside from the new grounds ofrejection, as the Examiner reasons,
Rambus improperly also seeks review before the Examiner in the bifurcated
portion of the requested review which involves the Examiner's anticipation
rejection of claims 1,5,7,11,14,19, and 23 based on Hayes which Rambus
cross-appealed and which the Board affirmed in the '623 Board Decision.
(See Ex. Det. 4-5; Reopen Req. 3-14; Bd. Dec. 7-16.) Reopening
prosecution under 37 CPR § 41.77(b) is only "one of the ... two [possible]
options ... with respect to the new ground of rejection." Id. (emphasis
added). The affirmed rejection was not part of any "new ground of
6
A136
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
19. A memory device having a plurality of memory cells, the memory
device comprising:
a plurality of input receiver circuits to receive a write command and
sample data that corresponds to the write command in response to detecting
a strobe signal that is delayed relative to the write command by a first time
period.
DICUSSION
Pursuant to 37 CPR § 41.77(f) and the new grounds of rejection
issued in the '623 Board Decision, the Board hereby "reconsiders the matter
and issue[ s] a new decision. The new decision ... incorporate [ s] the earlier
['623Board D]ecision, except for those portions specifically withdrawn." No
such portions are withdrawn.
The Examiner's Determination is also hereby adopted and
incorporated by reference. Rambus did not file "comments in response to
the [E]xaminer's [D]etermination" as allowed under 37 CPR § 41.77(e) to
rebut or show error in the Examiner's Determination with respect to the new
grounds.
Preliminary Remarks - Bifurcated Proceeding
Aside from the new grounds ofrejection, as the Examiner reasons,
Rambus improperly also seeks review before the   in the bifurcated
portion of the requested review which involves the Examiner's anticipation
rejection of claims 1,5,7, 11, 14, 19, and 23 based on Hayes which Rambus
cross-appealed and which the Board affirmed in the '623 Board Decision.
(See Ex. Det. 4-5; Reopen Req. 3-14; Bd. Dec. 7-16.) Reopening
prosecution under 37 CPR § 41.77(b) is only "one of the ... two [possible]
options ... with respect to the new ground 0.[ rejection." Id. (emphasis
added). The atlirmed rejection was not part of any "new ground of
6
Case: 13-1623 Document: 10 Page: 88 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
rejection" under the rule and the Examiner properly refused to consider
Rambus's request for review of the affirmed rejection. (See Ex. Det. 4-5.)
Subsequent to the underlying '623 Board Decision, the Board began
issuing clarifying information for situations such as this which involve new
grounds ofrejection. (See, e.g., PTAB 2012-001976 at 43-45 (clarifying
information related to new grounds).) Under the circumstances involved
here, the portion of Rambus' s Response with respect to the affirmed
rejection appealed by Rambus is not responsive to the new grounds but is
deemed to be in the nature of a request for rehearing under 37 CFR § 47
(Rehearing).
With further respect to the affirmed rejection based on anticipation by
Hayes, a primary point of contention involves the "strobe signal" element
recited in the independent claims. The "strobe signal" is also an element in
the dependent claims which are involved in the new grounds ofrejection
based on obviousness over Hayes. Accordingly, some substantive issues
overlap between the two portions of the bifurcated proceeding. As such, the
Board exercises its discretion and addresses all of Rambus' s arguments and
new evidence to expedite the proceeding with special dispatch as 35 U.S.C.
§ 314 (c) mandates, to avoid further unnecessary procedural issues, to afford
Rambus a fair hearing, and to provide a record summary.
Hayes -Anticipation - Rehearing
NVID IA argued, and the Examiner and the Board found, that the
Hayes memory device as represented in the figure below anticipates claims
1,5,7, 11, 14, 19 and 23 of the '353 patent. (See '623 Bd. Dec.5-26.)
Rambus's arguments focus on claim 1 which is hereby selected to be
representative of claims 1, 7, 11, and 19. For the most part, notwithstanding
7
A137
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
rejection" under the rule and the Examiner properly refused to consider
Rambus's request for review of the affirmed rejection. (See Ex. Det. 4-5.)
Subsequent to the underlying '623 Board Decision, the Board began
issuing clarifying information for situations such as this which involve new
grounds of rejection. (See, e.g., PTAB 2012-001976 at 43-45 (clarifying
information related to new grounds).) Under the circumstances involved
here, the portion of Rambus' s Response with respect to the affirmed
rejection appealed by Rambus is not responsive to the new grounds but is
deemed to be in the nature of a request for rehearing under 37 CFR § 47
(Rehearing).
With further respect to the affirmed rejection based on anticipation by
Hayes, a primary point of contention involves the "strobe signal" element
recited in the independent claims. The "strobe signal" is also an element in
the dependent claims which are involved in the new grounds ofrejection
based on obviousness over Hayes. Accordingly, some substantive issues
overlap between the two portions of the bifurcated proceeding. As such, the
Board exercises its discretion and addresses all of Ram bus's arguments and
new evidence to expedite the proceeding with special dispatch as 35 U.S.c.
§ 314 (c) mandates, to avoid further unnecessary procedural issues, to afford
Rambus a fair hearing, and to provide a record summary.
Hayes -Anticipation - Rehearing
NVID IA argued, and the Examiner and the Board found, that the
Hayes memory device as represented in the figure below anticipates claims
1,5,7, 11, 14, 19 and 23 of the '353 patent. (See '623 Bd. Dec.5-26.)
Rambus's arguments focus on claim 1 which is hereby selected to be
representati ve of claims 1, 7, 11, and 19. For the most part, notwithstanding
7
Case: 13-1623 Document: 10 Page: 89 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
the new evidence proffered, the arguments restate or repackage similar
arguments made in the original appeal without adding sufficient or probative
evidence which shows that the '623 Board Decision overlooks or
misapprehends the teachings of Hayes as applied to the claims at issue.
Hayes's Figure 2, as annotated by NVIDIA, appears next:
Annotated Figure 2 shows Hayes's slave memory device. (See
NVIDA App. Br. 7 (addressed further in the underlying '623 Board
Decision).)
Rambus argues, relying on its expert declarant Murphy, that the Hayes
"Data Strobe" (see Fig. 2 above) ("DS") signal is not an external strobe
signal as recited in claim 1. (See Reopen Req. 6-8 (citing Murphy 3
rd
Supp.
Dec!. ,-r,-r 5-9).) The '623 Board Decision addresses this repackaged
argument: "Claim 1 'defer[ s] sampling ... until an external strobe signal is
8
A138
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
the new evidence proffered, the arguments restate or repackage similar
arguments made in the original appeal without adding sufficient or probative
evidence which shows that the '623 Board Decision overlooks or
misapprehends the teachings of Hayes as applied to the claims at issue.
Hayes's Figure 2, as annotated by NVTDTA, appears next:
Annotated Figure 2 shows Hayes's slave memory device. (See
NVIDA App. Br. 7 (addressed further in the underlying '623 Board
Decision).)
Rambus argues, relying on its expert declarant Murphy, that the Hayes
"Data Strobe" (see Fig. 2 above) ("DS") signal is not an external strobe
signal as recited in claim 1. (See Reopen Req. 6-8 (citing Murphy 3
rd
Supp.
Dec!. ,-r,-r 5-9).) The '623 Board Decision addresses this repackaged
argument: "Claim 1 'defer[ s] sampling ... until an external strobe signal is
8
Case: 13-1623 Document: 10 Page: 90 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
detected' and does not require an immediate response to the strobe signal."
('623 Bd. Dec. 22.) The '623 Board Decision explains that the DS signal, a
"data strobe" signal, constitutes a strobe signal which "tells the slave
memory device in Hayes that the data is valid on the bus so that the slave
memory device knows when to sample (read) it." ('623 Bd. Dec. 21.)3
Murphy's new testimony and Rambus's arguments do not rebut these
facts or other facts or rationale in the '623 Board Decision with a necessary
evidentiary underpinning. Similar to Rambus, as an example, Murphy
testifies that "multiple signals. . . are asserted when sampling is alleged to
occur in Hayes" and this shows that none of those signals "initiate
sampling." (Murphy 3
rd
Supp. Decl. ,-r 8.t
But nowhere does Murphy even assert, much less show, that the
Hayes memory device does not defer sampling until the after the DS is
detected as claim 1 requires. Murphy also does not show that the memory
device does not sample data in response to the DS as called for in claim 1.
As the '623 Board Decision finds, Hayes states that '" [d]uring a write cycle,
the bus master asserts DS to indicate that DAL [31 :0] contains valid write
data. The bus master then deasserts DS to indicate that it is about to remove
the write data from the DAL [31 :0]. '" ('623 Bd. Dec. 9 -listing fact H2
(i.e., quoting Hayes).) The Decision also relies on Hayes which states that
3 As used here, a read by the memory device in Hayes also constitutes a
write to the device - in both cases, a "sample" by the memory device.
4 Such arguments and new evidence technically are not proper in a request
for rehearing since the Board could not have overlooked such evidence, but
the evidence is similar to previous evidence submitted and addressed to
expedite this bifurcated proceeding on the merits as indicated at the outset.
9
A139
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
detected' and does not require an immediate response to the strobe signa1."
('623 Bd. Dec. 22.) The '623 Board Decision explains that the DS signal, a
"data strobe" signal, constitutes a strobe signal which "tells the slave
memory device in Hayes that the data is valid on the bus so that the slave
memory device knows when to sample (read) it." ('623 Bd. Dec. 21.l
Murphy's new testimony and Rambus's arguments do not rebut these
facts or other facts or rationale in the '623 Board Decision with a necessary
evidentiary underpinning. Similar to Rambus, as an example, Murphy
testifies that "multiple signals. . . are asserted when sampling is alleged to
occur in Hayes" and this shows that none of those signals "initiate
sampling." (Murphy 3
rd
Supp. Decl.   S.t
But nowhere does Murphy even assert, much less show, that the
Hayes memory device does not defer sampling until the after the DS is
detected as claim 1 requires. Murphy also does not show that the memory
device does not sample data in response to the DS as called for in claim 1.
As the '623 Board Decision finds, Hayes states that '" [d]uring a write cycle,
the bus master asserts DS to indicate that DAL [31 :0] contains valid write
data. The bus master then deasserts DS to indicate that it is about to remove
the write data from the DAL [31 :0]. '" ('623 Bd. Dec. 9 -listing fact H2
(i.e., quoting Hayes).) The Decision also relies on Hayes which states that
3 As used here, a read by the memory device in Hayes also constitutes a
write to the device - in both cases, a "sample" by the memory device.
4 Such arguments and new evidence technically are not proper in a request
for rehearing since the Board could not have overlooked such evidence, but
the evidence is similar to previous evidence submitted and addressed to
expedite this bifurcated proceeding on the merits as indicated at the outset.
9
Case: 13-1623 Document: 10 Page: 91 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
for a write cycle, "'[t]he bus master ... drives data onto DAL 31 :0] and
asserts DS [data strobe col. 7, 1. 56], indicating that the data is valid on DAL
[31 :0]. If no error occurs, the slave device reads the data. '" ('623 Bd. Dec.
9, H2 (quoting Hayes).)
The Decision also explains that claim 1 and the '353 patent disclosure
include a delay after the DS (e.g., waiting until several cycles of an external
clock signal) and do not preclude other subsequent control, and Rambus
"corroborates" this understanding and "describes a similar delay between the
data and the strobe." (See '623 Bd. Dec. 22 (citing P.O. Cr. App. Br. 10;
Req. Resp. Br. 12).)
In response to the '623 Board Decision, Murphy also avers that other
signals in Hayes enable the data transceivers 57 and that the RAM control
logic 62 receives the DS signals but the "'memory devices' represented by
the 256Kbit DRAM chips 64" do not receive the DS signal. (See Murphy 3
rd
S. Decl. ,-r,-r 9-10.) The Board accepts that testimony as it appears to be
supported by Hayes, but that testimony does not upset the '623 Board
Decision. For example, as to the latter point, the '623 Board Decision does
not rely on one DRAM chip as the recited memory device. Rather, as
indicated in the annotated Figure 2 supra, the Board relies on the whole
memory/slave board in Hayes which includes the RAM control logic 62 and
which therefore receives the DS as claim 1 requires.
Murphy also explains that "RAM control logic 62 is not connected to
any other device that receives data on DAL [31 :0]" and also opines that the
error signal which might occur after the DS in Hayes shows that DS does not
satisfy the strobe signal recited in the claims. (See Murphy 3
rd
S. Decl. ,-r 9-
10
A140
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
for a write cycle, '" [t]he bus master ... drives data onto DAL 31 :0] and
asserts DS [data strobe col. 7, 1. 56], indicating that the data is valid on DAL
[31 :0]. If no error occurs, the slave device reads the data. '" ('623 Bd. Dec.
9, H2 (quoting Hayes).)
The Decision also explains that claim 1 and the '353 patent disclosure
include a delay after the DS (e.g., waiting until several cycles of an external
clock signal) and do not preclude other subsequent control, and Rambus
"corroborates" this understanding and "describes a similar delay between the
data and the strobe." (See '623 Bd. Dec. 22 (citing P.O. Cr. App. Br. 10;
Req. Resp. Br. 12).)
In response to the '623 Board Decision, Murphy also avers that other
signals in Hayes enable the data transceivers 57 and that the RAM control
logic 62 receives the DS signals but the '''memory devices' represented by
the 256Kbit DRAM chips 64" do not receive the DS signal. (See Murphy 3
rd
S. Decl. ,-r,-r 9-10.) The Board accepts that testimony as it appears to be
supported by Hayes, but that testimony does not upset the '623 Board
Decision. For example, as to the latter point, the '623 Board Decision does
not rely on one DRAM chip as the recited memory device. Rather, as
indicated in the annotated Figure 2 supra, the Board relies on the whole
memory/slave board in Hayes which includes the RAM control logic 62 and
which therefore receives the DS as claim 1 requires.
Murphy also explains that "RAM control logic 62 is not connected to
any other device that receives data on DAL [31 :0]" and also opines that the
error signal which might occur after the DS in Hayes shows that DS does not
satisfy the strobe signal recited in the claims. (See Murphy 3
rd
S. Decl. ,-r 9-
10
Case: 13-1623 Document: 10 Page: 92 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
10.) Rambus makes similar arguments, relying on Murphy. (See Reopen
Req.6-10.)
The Board was cognizant of how the Hayes system operates based on
related arguments and findings, including details about the error signal and
the transceivers. As Rambus's expert Murphy points out, the transceivers
become enabled during the data transfer process, but this simply agrees with
the Board's finding that the external data lines DAL[31 :0] and DATA <31
:0> lines on the memory board become connected directly together through
the enabled transceivers 57 on the memory board in Figure 7. (See '623 Bd.
Dec. 24, n. 6 (citing Parris Declaration).) As NVIDIA's expert Parris
testifies, "[t]owards the end of a write cycle, when data is being transmitted
to the slave device, the DATA TRANSCEIVER 57 connects DAL[31 :0]
directly to DATA <31 :0>." (Parris Dec!. 15.) Murphy's new testimony and
Parris's testimony coalesce on that point.
Rambus's assertion that "the RAM control logic 62, which receives
the DS signal, is not connected to the data and address and [control] lines
DAL[31 :0] or even to the device [transceiver 57] that is connected to
DAL[31 :0]" (see Reopen Req. 9), is not material given the finding that the
data lines external to and on the bus are connected via the transceiver prior
to a data transfer. The enabled transceiver 57 directly connects the DRAM
chips to the external DAL[31 :0], and therefore, the DS signal does
"necessarily indicate[] whether valid data is on the separate data
lines<31 :00>," contrary to Rambus' s argument (see id.), because the same
data is on both connected lines - according to the un-rebutted findings based
on the Parris, Murphy, and Hayes, and as outlined in in the '623 Decision as
mentioned supra.
11
A141
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
10.) Rambus makes similar arguments, relying on Murphy. (See Reopen
Req.6-10.)
The Board was cognizant of how the Hayes system operates based on
related arguments and findings, including details about the error signal and
the transceivers. As Rambus's expert Murphy points out, the transceivers
become enabled during the data transfer process, but this simply agrees with
the Board's finding that the external data lines DAL[31 :OJ and DATA <31
:0> lines on the memory board become connected directly together through
the enabled transceivers 57 on the memory board in Figure 7. (See '623 Bd.
Dec. 24, n. 6 (citing Parris Declaration).) As NVIDIA's expert Parris
testifies, "[ t J owards the end of a write cycle, when data is being transmitted
to the slave device, the OAT A TRANSCEIVER 57 connects OAL[31 :OJ
directly to DATA <31 :0>." (Parris Dec!. 15.) Murphy's new testimony and
Parris's testimony coalesce on that point.
Rambus's assertion that "the RAM control logic 62, which receives
the DS signal, is not connected to the data and address and [controlJ lines
DAL[31 :OJ or even to the device [transceiver 57J that is connected to
OAL[31 :0]" (see Reopen Req. 9), is not material given the finding that the
data lines external to and on the bus are connected via the transceiver prior
to a data transfer. The enabled transceiver 57 directly connects the DRAM
chips to the external DAL[31 :OJ, and therefore, the DS signal does
"necessarily indicate[J whether valid data is on the separate data
lines<31 :00>," contrary to Rambus's argument (see id.), because the same
data is on both connected lines - according to the un-rebutted findings based
on the Parris, Murphy, and Hayes, and as outlined in in the '623 Decision as
mentioned supra.
11
Case: 13-1623 Document: 10 Page: 93 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
In other words, the DRAM chips sample the same data from DAL[31
:0] and data lines<31 :00> through the enabled transceivers 57. The assertion
of DS at the RAM control logic 62 input 62 which controls the DRAM chips
initiates sampling by the DRAM chips of the data lines DAL[31 :0] and
connected data lines<31 :00>. Rambus' s arguments and evidence do not
rebut or even address with particularity the Board's summary finding: "In
sum, the bus master asserts DS when data is valid on the bus, the slave then
reads the data (absent an abnormal abort as discussed below), and then the
bus master deasserts DS when data is about to be removed from the bus.
(H2.)" ('623 Bd. Dec. 20 (emphasis added, citing "H2" facts found from
Hayes).)
Rambus also does not rebut the underlying related finding that the
slave memory device 15 responds to DS as the one-way DS (DATA
STROBE) signal in Figure 2 shows, and as the noted passages show, the
slave memory device reads the data after the DS in normal circumstances
(i.e., when no abnormal error signal aborts the process as the '623 Board
Decision explains). Rambus also does not point to any normal external
signal to the memory device which occurs after the DS control signal and
before sampling in Hayes.
Rambus's arguments reduce to its following statement by Rambus:
"Merely because DS happens to be asserted when valid data is present and
the alleged sampling in Hayes also happens to occur when valid data is
present does not mean that DS causes the alleged sampling." (Reopen Req.
7.) To the contrary, without the DS which occurs before the sampling,
sampling would not occur - as indicated, Rambus does not challenge the
Board's finding that "'the bus master asserts DS when data is valid on the
12
A142
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
In other words, the DRAM chips sample the same data from DAL[31
:0] and data lines<31 :00> through the enabled transceivers 57. The assertion
ofDS at the RAM control logic 62 input 62 which controls the DRAM chips
initiates sampling by the DRAM chips ofthe data lines DAL[31 :0] and
connected data lines<31 :00>. Rambus's arguments and evidence do not
rebut or even address with particularity the Board's summary fInding: "In
sum, the bus master asserts DS when data is valid on the bus, the slave then
reads the data (absent an abnormal abort as discussed below), and then the
bus master deasserts DS when data is about to be removed from the bus.
(H2.)" ('623 Bd. Dec. 20 (emphasis added, citing "H2" facts found from
Hayes).)
Rambus also does not rebut the underlying related finding that the
slave memory device 15 responds to DS as the one-way DS (DATA
STROBE) signal in Figure 2 shows, and as the noted passages show, the
slave memory device reads the data after the DS in normal circumstances
(i.e., when no abnormal error signal aborts the process as the '623 Board
Decision explains). Rambus also does not point to any normal external
signal to the memory device which occurs after the DS control signal and
before sampling in Hayes.
Rambus's arguments reduce to its following statement by Rambus:
"Merely because DS happens to be asserted when valid data is present and
the alleged sampling in Hayes also happens to occur when valid data is
present does not mean that DS causes the alleged sampling." (Reopen Req.
7.) To the contrary, without the DS which occurs before the sampling,
sampling would not occur - as indicated, Rambus does not challenge the
Board's finding that "'the bus master asserts DS when data is valid on the
12
Case: 13-1623 Document: 10 Page: 94 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
bus, the slave then reads the data. '" (See Reopen Req. 7 (quoting' 623 Bd.
Dec. at 20, emphasis here).) As such, the Board shows a causal relationship,
contrary to Rambus's argument that the Board "confuses coincidence with
causation." (Reopen Req. 7; accord Parris Decl. ,-r 11 (discussing an
analogous or similar TrncvrR W signal and explaining why indicating valid
data to a slave indicates when to sample the data).)
Rambus also states that the memory device excludes an external bus
controller. (See Reopen Req. 10-11.) But as Rambus also notes, the
disclosed memory device is a slave device and has "some internal 'control
logic.'" (Id. at 11 (citing Figs. 6 and 20 of the '353 patent).) Similarly, in
Hayes, the memory controller 12 and other masters 10, 11 (Hayes Fig. 1) are
external to the slave memory device 15, but the slave memory board
includes some RAM "control logic" on the board. (See Hayes, Fig. 7.) In a
related Rambus appeal, the Federal Circuit recently held that contrary to
Rambus's similar arguments, the term "memory device" is not limited to a
single chip and includes a memory board and some control logic. 5
Rambus also asserts that the '353 patent specification exhibits an
"explicit definition" which the Board overlooks. Rambus states that a
"strobe signal" in the '353 patent means "'data transfer start information.'"
(See Reopen Req. 8 (quoting '353 patent at col. 8,11.60-63).) The Board
could not have overlooked this new evidence submitted by Rambus as part
of this rehearing request.
5 See In re Rambus Inc., 694 F.3d 42 (Fed. Cir. 2012) (holding that the
claim term "memory device" in a related Rambus patent includes a memory
board and is not limited to a single chip contrary to Rambus' s similar
arguments otherwise).
13
A143
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
bus, the slave then reads the data.'" (See Reopen Req. 7 (quoting '623 Bd.
Dec. at 20, emphasis here).) As such, the Board shows a causal relationship,
contrary to Rambus's argument that the Board "confuses coincidence with
causation." (Reopen Req. 7; accord Parris Decl.,-r 11 (discussing an
analogous or similar TrncvrRW signal and explaining why indicating valid
data to a slave indicates when to sample the data).)
Rambus also states that the memory device excludes an external bus
controller. (See Reopen Req. 10-11.) But as Rambus also notes, the
disclosed memory device is a slave device and has "some internal 'control
logic.'" (Id. at 11 (citing Figs. 6 and 20 of the '353 patent).) Similarly, in
Hayes, the memory controller 12 and other masters 10, 11 (Hayes Fig. 1) are
external to the slave memory device 15, but the slave memory board
includes some RAM "control logic" on the board. (See Hayes, Fig. 7.) In a
related Rambus appeal, the Federal Circuit recently held that contrary to
Rambus's similar arguments, the term "memory device" is not limited to a
single chip and includes a memory board and some control logic. 5
Rambus also asserts that the '353 patent specification exhibits an
"explicit definition" which the Board overlooks. Rambus states that a
"strobe signal" in the '353 patent means '''data transfer start infonnation. '"
(See Reopen Req. 8 (quoting '353 patent at col. 8, 11. 60-63).) The Board
could not have overlooked this new evidence submitted by Rambus as part
of this rehearing request.
5 See In re Rambus Inc., 694 F.3d 42 (Fed. Cir. 2012) (holding that the
claim term "memory device" in a related Rambus patent includes a memory
board and is not limited to a single chip contrary to Rambus' s similar
arguments otherwise).
13
Case: 13-1623 Document: 10 Page: 95 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
In any event, it is not clear how that disclosure distinguishes over
Hayes. The Hayes DS includes "start information" by indicating valid data
right before the data starts transferring. Moreover, the passage in the '353
patent relied upon by Rambus specifically describes "indicat[ing] when the
DRAM is to begin sending data" (id. at 11. 63-64 (emphasis added)) but does
not refer to when the DRAM begins sampling data. Rambus's Cross-Appeal
Brief points to other passages which generically refer to transferring data in
relation to the strobe signal, but the '623 Board Decision addresses
variations of Ram bus's argument and relies on NVIDIA's and Rambus's
briefs which essentially agree that "the '353 patent describes a delay
between the strobe signal and sampling" as noted supra. (See '623 Bd. Dec.
at 22; P.O. Cr. App. Br. 10; Req. Resp. Br. 12.) Rambus fails to rebut these
findings and explain how this limited disclosure of "start information"
associated with the strobe signal and data transfers shows that the Board's
interpretation of the Hayes DS signal which starts the sampling process is
inconsistent with the '353 Patent Specification.
Also, Rambus does not explain clearly how the '353 patent "defines"
a strobe signal or even when the DRAM begins sending data after the strobe
signal, let alone when the DRAM samples data. According to the '353
patent, the DRAM begins to send data in what amounts to two different
phases over several clock cycles after the strobe signal: the DRAM first
accesses a column in the DRAM and then it sends the accessed data from the
column onto an external bus. (See '353 patent, col. 21,11. 13-21.) These
unclear time distinctions for sending data upon which Rambus relies, and the
seemingly related above-discussed time delays between the strobe signal and
data transfer, do not define any clear distinction over Hayes which similarly
14
A144
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
In any event, it is not clear how that disclosure distinguishes over
Hayes. The Hayes DS includes "start information" by indicating valid data
right before the data starts transferring. Moreover, the passage in the '353
patent relied upon by Rambus specifically describes "indicat[ing] when the
DRAM is to begin sending data" (id. at II. 63-64 (emphasis added)) but does
not refer to when the DRAM begins sampling data. Rambus's Cross-Appeal
Brief points to other passages which generically refer to transferring data in
relation to the strobe signal, but the '623 Board Decision addresses
variations of Ram bus's argument and relies on NVIDIA's and Rambus's
briefs which essentially agree that "the '353 patent describes a delay
between the strobe signal and sampling" as noted supra. (See '623 Bd. Dec.
at 22; P.o. Cr. App. Br. 10; Req. Resp. Br. 12.) Rambus fails to rebut these
findings and explain how this limited disclosure of "start information"
associated with the strobe signal and data transfers shows that the Board's
interpretation of the Hayes DS signal which starts the sampling process is
inconsistent with the '353 Patent Specification.
Also, Rambus does not explain clearly how the '353 patent "defines"
a strobe signal or even when the DRAM begins sending data after the strobe
signal, let alone when the DRAM samples data. According to the '353
patent, the DRAM begins to send data in what amounts to two different
phases over several clock cycles after the strobe signal: the DRAM first
accesses a column in the DRAM and then it sends the accessed data from the
column onto an external bus. (See '353 patent, col. 21, 11. 13-21.) These
unclear time distinctions for sending data upon which Rambus relies, and the
seemingly related above-discussed time delays between the strobe signal and
data transfer, do not define any clear distinction over Hayes which similarly
14
Case: 13-1623 Document: 10 Page: 96 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
samples data in response to the DS signal. Moreover, though not required
necessarily to support the Board's claim interpretation, these time delays
between data transmission and the strobe signal as disclosed in the '353
patent indicate that something other than, or, in addition to, the disclosed
strobe signal (i.e., perhaps stored or pre-programmed clock delay times)
govern the actual timing of any data transmission after the data strobe.
Rambus's repackaged arguments that Hayes does not anticipate
claims 5, 14, and 23 based on the recited "terminate signal" in those claims
lack a citation to new evidence and also fail to show that the '623 Board
Decision overlooks or misapprehends a material consideration. (See '623
Bd. Dec. 23-26; Reopen Req. 13-14.)
Based on the foregoing discussion, Rambus' s new evidence and
arguments fail to show that the' 623 Board Decision overlooks or
misapprehends a material consideration warranting a modification of the
anticipation rejection of claims 1,5,7,11,14,19, and 23 based on Hayes.
Remanded Proceeding
Hayes and Bennett - Claims 2, 6, 10, 17,25, and 26
Rambus does not direct attention to a specific claim. Claim 2, taken
to be representative, depends from claim 1 and further requires the "data [to
be] sampled synchronously with respect to an external clock." On remand,
"[t]he [E]xaminer does not find patent owner's evidence sufficient to
overcome the Board's decision." (Ex. Det. 5.) The Examiner's findings and
rationale are adopted and incorporated by reference and supported by the
record.
As explained in the Decision and under In re Rambus (supra note 5),
the Hayes memory device satisfies the claim 1 memory device. (See '623
15
A145
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
samples data in response to the DS signal. Moreover, though not required
necessarily to support the Board's claim interpretation, these time delays
between data transmission and the strobe signal as disclosed in the '353
patent indicate that something other than, or, in addition to, the disclosed
strobe signal (i.e., perhaps stored or pre-programmed clock delay times)
govern the actual timing of any data transmission after the data strobe.
Rambus's repackaged arguments that Hayes does not anticipate
claims 5, 14, and 23 based on the recited "terminate signal" in those claims
lack a citation to new evidence and also fail to show that the '623 Board
Decision overlooks or misapprehends a material consideration. (See '623
Bd. Dec. 23-26; Reopen Req. 13-14.)
Based on the foregoing discussion, Rambus's new evidence and
arguments fail to show that the '623 Board Decision overlooks or
misapprehends a material consideration warranting a modification of the
anticipation rejection of claims 1,5,7,11,14,19, and 23 based on Hayes.
Remanded Proceeding
Hayes and Bennett - Claims 2, 6, 10, 17, 25, and 26
Rambus does not direct attention to a specific claim. Claim 2, taken
to be representative, depends from claim 1 and further requires the "data [to
be] sampled synchronously with respect to an external clock." On remand,
"[t]he [E]xaminer does not find patent owner's evidence sufficient to
overcome the Board's decision." (Ex. Det. 5.) The Examiner's findings and
rationale are adopted and incorporated by reference and supported by the
record.
As explained in the Decision and under In re Ramhus (supra note 5),
the Hayes memory device satisfIes the claim 1 memory device. (See '623
15
Case: 13-1623 Document: 10 Page: 97 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
Bd. Dec. 28-29.) The combination of Bennett and Hayes renders obvious
claim 2 even if it requires a single chip memory device as discussed further
below. Bennett teaches a memory device receiving data synchronously with
an external clock from a master, and Hayes teaches sending signals from a
bus master to a slave memory device as depicted supra in Figure 2.
Rambus contests the Board's and the Examiner's finding that Bennett
discloses a synchronous single chip memory device and that the combination
with Hayes would have been obvious. (See Reopen Req. 14-21.) The
contentions are addressed below after a summary of Bennett's teachings.
Bennett's Teachings
B1. Bennett's "paramount object" is to provide communication
between "very large scale integrated VLSI (circuit) elements" (col. 12,
11. 14-18) - i.e., "VLSIC chips" (col. 9,11. 35-40). Bennett discloses
combining Versatile Bus Interfaces (VB!) and VLSIC "upon the same chip
substrate as the VLSI User Device" (col. 12,11.29-32 (emphasis added))
with such a user device including "interfaces intended to be built with a
CPU, IOC or Memory, or similar User device for signal or data exchange"
(col. 35, 11. 59-62 (emphasis added)). (See also col. 14,11. 19-24 (describing
"interface to the user devices (usually upon the same chip substrate)".)
Bennett's Figure 1 represents a single chip User Device, which
includes memory, as noted supra: "Each Versatile Bus Interface Logics, for
example Versatile Bus Interface Logics 102a, interfaces a User module, for
example VLSI Circuit User Device 1 06a which is pictorially represented in
shadow line within FIG. 1 as existing on the same VLSIC chip substrate as
Versatile Bus Interface Logics 102a." (Col. 36, 11. 19-24 (emphasis added).)
16
A146
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Bd. Dec. 28-29.) The combination of Bennett and Hayes renders obvious
claim 2 even if it requires a single chip memory device as discussed further
below. Bennett teaches a memory device receiving data synchronously with
an external clock from a master, and Hayes teaches sending signals from a
bus master to a slave memory device as depicted supra in Figure 2.
Rambus contests the Board's and the Examiner's finding that Bennett
discloses a synchronous single chip memory device and that the combination
with Hayes would have been obvious. (See Reopen Req. 14-21.) The
contentions are addressed below after a summary of Bennett's teachings.
Bennett's Teachings
Bl. Bennett's "paramount object" is to provide communication
between "very large scale integrated VLST (circuit) elements" (col. 12,
11. 14-18)-i.e., "VLSIC chips" (col. 9,11.35-40). Bennett discloses
combining Versatile Bus Interfaces (VBT) and VLSIC "upon the same chip
substrate as the VLSI User Device" (col. 12,11.29-32 (emphasis added))
with such a user device including "interfaces intended to be built with a
CPU, IOC or Memory, or similar User device for signal or data exchange"
(col. 35, 11. 59-62 (emphasis added)). (See also col. 14,11. 19-24 (describing
"interface to the user devices (usually upon the same chip substrate)".)
Bennett's Figure 1 represents a single chip User Device, which
includes memory, as noted supra: "Each Versatile Bus Interface Logics, for
example Versatile Bus Interface Logics 102a, interfaces a User module, for
example VLSI Circuit User Device 1 06a which is pictorially represented in
shadow line within FIG. 1 as existing on the same VLSIC chip substrate as
Versatile Bus Interface Logics 102a." (Col. 36, 11. 19-24 (emphasis added).)
16
Case: 13-1623 Document: 10 Page: 98 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
Bennett's chips have up to 120 pins as a practical limit. (Col. 9,
11. 60-61.) Bennett also discloses different memory types as "Fast Memory"
or "Large Memory" with the memory having address widths of 16, 24, or
32, and one fast memory embodiment having 37 pins (col. 92, 11. 15-56;
Fig. 32). One large memory has at least 16 pins to access 2
32
addresses by
employing two 16-bit address words over successive clock cycles. (See col.
95, 11. 59-60; Fig. 36.)
B2. Figure 38 shows "memories device" 3802c and 3802d connected
to a "Versatile Bus." (Col. 97, 11. 8-10.) In the next paragraph, Bennett
refers to "VSLI chips hav[ ing] access to all Versatile Bus lines and
therefore, the Versatile Bus protocols." (Id. at 11. 20-22.)
Bennett elsewhere refers to "memory devices" including, but not
limited to, a ROM: "Not all memory devices can perform all operations; for
example, read only memory (ROM) cannot execute the write operations."
(Col. 90, 1. 66 to col. 91, 1. 2.) Bennett then refers to "[s]ample memory
operations ... defined in the following paragraphs" (col. 91, 11. 4-5) and
thereafter describes "relatively small fast memories, and ... larger and
relatively slower memories" (col. 92,11. 13-14).
Bennett also refers to "VLSIC chip devices" (col. 90, 11. 38-41) and in
the next section, Section "4.1, Sample Memory Operations," states that
"[m]any, ifnot most, applications ofVLSIC technology are likely to include
memory devices." (Col. 90, 11. 42-44.) Bennett generally discusses these
chip devices as employing the interconnection protocol standards outlined
generally in Section 3 and more specifically discusses memory devices in
Section 4, including embodiments or configurations involved in Figures 31-
36. (See id. at 11.36-41.) For example, as discussed in Section 4 of Bennett,
17
A147
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Bennett's chips have up to 120 pins as a practical limit. (Col. 9,
11.60-61.) Bennett also discloses different memory types as "Fast Memory"
or "Large Memory" with the memory having address widths of 16, 24, or
32, and one fast memory embodiment having 37 pins (col. 92, II. 15-56;
Fig. 32). One large memory has at least 16 pins to access 2
32
addresses by
employing two 16-bit address words over successive clock cycles. (See col.
95, 11. 59-60; Fig. 36.)
B2. Figure 38 shows "memories device" 3802c and 3802d connected
to a "Versatile Bus." (Col. 97,11. 8-10.) In the next paragraph, Bennett
refers to "VSLI chips hav[ ing] access to all Versatile Bus lines and
therefore, the Versatile Bus protocols." (Id. at 11.20-22.)
Bennett elsewhere refers to "memory devices" including, but not
limited to, a ROM: "Not all memory devices can perform all operations; for
example, read only memory (ROM) cannot execute the write operations."
(Col. 90, 1. 66 to col. 91, 1. 2.) Bennett then refers to "[s]ample memory
operations ... defined in the following paragraphs" (col. 91, 11. 4-5) and
thereafter describes "relatively small fast memories, and ... larger and
relatively slower memories" (col. 92, 11. 13-14).
Bennett also refers to "VLSIC chip devices" (col. 90, 11. 38-41) and in
the next section, Section "4.1, Sample Memory Operations," states that
"[m]any, ifnot most, applications ofVLSIC technology are likely to include
memory devices." (Col. 90, 11. 42-44.) Bennett generally discusses these
chip devices as employing the interconnection protocol standards outlined
generally in Section 3 and more specifically discusses memory devices in
Section 4, including embodiments or configurations involved in Figures 31-
36. (See id. at 11. 36-41.) For example, as discussed in Section 4 of Bennett,
17
Case: 13-1623 Document: 10 Page: 99 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
Figures 32 and 33 represent fast memory read or write operations, with
Figures 32 and 33 respectively signifying "DATA" transmission on 16 and 8
pins. Other pins are used for arbitration and slave ID. (See col. 93, 1.12 -
col. 94, 1. 56.)
Figures 25a-h, represent more generic slave device configurations as
discussed in Section 3 of Bennett. (Col. 25, 1. 57 to col. 26,1. 11; see
generally columns 81-88). Bennett also refers to the Section 3 figures as
representing chips: "Section 3 provided for the electrical connection of many
chips on one bus .... Each chip recognizes the existence of the transactions
.... " (Col. 90, 11. 27 -30.)
B3. In addition to chips, Bennett also discusses memory cards in
Section 2, "Description of the Prior Art" (see col. 5, 1.52 et seq.), and states
that "the functionality ofVLSIC chips is often similar to that of cards today"
but that "VLSIC technology promises much higher performance than that of
cards," even though cards hold more memory and chips have higher
development costs. (Col. 9, 11. 43-56.) In the next passage, Bennett
discusses creating larger chips to accommodate a greater numbers of pins.
(Col. 9, 1. 66 to col. 10,1. 29.)
B4. Bennett describes a "third physical objective" - the VBI
(versatile bus interface) "should occupy a reasonable VLSI circuit substrate
area" using fast and efficient CMOS technology as the preferred
embodiment. (Col. 13,11.18-23.) Typically, only about 20 VLSIC devices
will be interconnected. As a "first logical object," the VBI logics "should
offer a fixed format, simply controlled, powerfully featured interface to the
user devices (usually upon the same chip substrate)" yet with certain options
for use. (Col. 14, 11. 20-30.)
18
A148
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Figures 32 and 33 represent fast memory read or write operations, with
Figures 32 and 33 respectively signifying "DATA" transmission on 16 and 8
pins. Other pins are used for arbitration and slave ID. (See col. 93, L 12 -
col. 94,1. 56.)
Figures 25a-h, represent more generic slave device configurations as
discussed in Section 3 of Bennett. (Col. 25, 1. 57 to col. 26,1. 11; see
generally columns 81-88). Bennett also refers to the Section 3 figures as
representing chips: "Section 3 provided for the electrical connection of many
chips on one bus .... Each chip recognizes the existence of the transactions
.... " (Col. 90, 11. 27-30.)
B3. In addition to chips, Bennett also discusses memory cards in
Section 2, "Description of the Prior Art" (see col. 5,1.52 etseq.), and states
that "the functionality of V LSIC chips is often similar to that of cards today"
but that "VLSIC technology promises much higher performance than that of
cards," even though cards hold more memory and chips have higher
development costs. (Col. 9, 11. 43-56.) In the next passage, Bennett
discusses creating larger chips to accommodate a greater numbers of pins.
(Col. 9, 1. 66 to col. 10, 1. 29.)
B4. Bennett describes a "third physical objective" - the VBI
(versatile bus interface) "should occupy a reasonable VLSI circuit substrate
area" using fast and efficient CMOS technology as the preferred
embodiment. (CoL 13,11.18-23.) Typically, only about 20 VLSIC devices
will be interconnected. As a "first logical object," the VBI logics "should
offer a fixed format, simply controlled, powerfully featured interface to the
user devices (usually upon the same chip substrate)" yet with certain options
for use. (Col. 14,11.20-30.)
18
Case: 13-1623 Document: 10 Page: 100 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
Bennett contemplates simple devices with "as few as three pins"
(Bennett, col. 12, 1. 61), or "pass[ing] but a single bit of data from a single
master device to a single slave device ... [or more bits and devices]. The
versatility is from the trivial to the profound." (Col. 15, 11. 26, 42-50.)
Figure 32, a "sample fast memory," has "an address field arbitrarily sized at
four bits." (Col. 93, 11. 12, 23.) Generally, large memories are slower than,
and have more address pins, than fast memories. (Co. 94, 11. 26-33.)
Bennett mentions that for large memories, "[a]ddress width may be
configured to 16,24, or 32 bits to match requirements." (Col. 94, 11. 35-36.)
In another section, Bennett describes a fast memory which may have 16 bit
words, and if so, "at a 40 nanosecond pace may either have to be very wide
or very fast or both." (Col. 89, 11. 30-32.) "The technology is projected to
drive signals form chip to chip in 20 to 40 nanoseconds with internal gate
delays of 1 to 2 nanoseconds." (Col. 9, 11. 57 -60.)
B5. Bennett discloses synchronous clocked communication between
bused VLSIC chips over 16 data lines at 25MHz, and notes that synchronous
communication is more efficient than asynchronous communication.
(Col. 13,11.3-17; col. 66, 1. 9 - col 67, 1. 18; col. 101,11.50-54 ("all
communication ... is synchronously referenced"); col. 101, 11. 51-54.)
Bennett also states that the clock signals "are normally synchronous."
(Col. 274, 1. 62.)
B6. As noted supra, Bennett contemplates simple systems having "a
single slave memory." (Col. 57, 1. 57.) Bennett explains that "the number of
[ device] locations strongly affects complexity." (Col. 8, 11. 30-31.) Bennett
distinguishes between slaves and masters: slaves "only respond to
19
A149
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Bennett contemplates simple devices with "as few as three pins"
(Bennett, col. 12, I. 61), or "pass[ing] but a single bit of data from a single
master device to a single slave device ... [or more bits and devices]. The
versatility is from the trivial to the profound." (Col. 15,11.26,42-50.)
Figure 32, a "sample fast memory," has "an address field arbitrarily sized at
four bits." (Col. 93,11. 12,23.) Generally, large memories are slower than,
and have more address pins, than fast memories. (Co. 94, 11.26-33.)
Bennett mentions that for large memories, "[a ]ddress width may be
configured to 16,24, or 32 bits to match requirements." (Col. 94, 11. 35-36.)
In another section, Bennett describes a fast memory which may have 16 bit
words, and if so, "at a 40 nanosecond pace may either have to be very wide
or very fast or both." (Col. 89, II. 30-32.) "The technology is projected to
drive signals form chip to chip in 20 to 40 nanoseconds with internal gate
delays of 1 to 2 nanoseconds." (Col. 9, 11. 57-60.)
B5. Bennett discloses synchronous clocked communication between
bused VLSIC chips over 16 data lines at 25MHz, and notes that synchronous
communication is more efficient than asynchronous communication.
(Col. 13, II. 3-17; col. 66, 1. 9-coI67, 1. 18; col. 101, II. 50-54 ("all
communication ... is synchronously referenced"); col. 101, 11. 51-54.)
Bennett also states that the clock signals "are normally synchronous."
(Col. 274, I. 62.)
B6. As noted supra, Bennett contemplates simple systems having "a
single slave memory." (Col. 57, I. 57.) Bennett explains that "the number of
[ device] locations strongly affects complexity." (Col. 8, 11. 30-31.) Bennett
distinguishes between slaves and masters: slaves "only respond to
19
Case: 13-1623 Document: 10 Page: 101 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
information on the interconnect," masters "control the interconnect"; thus,
slaves are subordinate to masters. (Col. 8, 11. 30-41.)
Analysis
Rambus's arguments do not focus on any particular claim. Claim 2 is
selected to be representative. The '623 Decision reasons as follows:
As NVIDIA persuasively explains, Hayes describes time-
multiplexed clock data transfers between a master and slave
during different clock cycles [see Hayes col. 19,11.45-46], and
Bennett teaches benefits to providing a synchronized interface
in a memory device using an external clock. (See Req. App. Br.
6-9; H6.)
('623 Bd. Dec. 29; see also id. at 6 - facts found in Hayes designated as
"H6".)
Rambus's new evidence does not rebut these findings or rationale.
Bennett, like Hayes, teaches transmitting time multiplexed signals to slave
memory devices, and Bennett teaches slave memory devices ranging from
the trivial to the complex. (See Bennett, col. 93, 1. 64 to col. 94, 1. 5; B4;
B7.)
Rambus asserts that Bennett does not teach a single chip memory
device. Claim 2 does not require a single chip. Assuming arguendo that it
does, Rambus asserts that Bennett only teaches "that the VBI can be placed
on the same VLSIC chip under certain circumstances, [but] it teaches away
from doing so when the chip is relatively simple, like a memory device."
(See Reopen Req. 15.)
Contrary to Rambus's single chip argument based on an asserted
tendency toward complexity in Bennett, as quoted supra, Bennett
20
A150
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
information on the interconnect," masters "control the interconnect"; thus,
slaves are subordinate to masters. (Col. 8, n. 30-41.)
Analysis
Rambus's arguments do not focus on any particular claim. Claim 2 is
selected to be representative. The '623 Decision reasons as follows:
As NVIDIA persuasively explains, Hayes describes time-
multiplexed clock data transfers between a master and slave
during different clock cycles [see Hayes col. 19,11. 45-46], and
Bennett teaches benefits to providing a synchronized interface
in a memory device using an external clock. (See Req. App. Br.
6-9; H6.)
('623 Bd. Dec. 29; see also id. at 6 - facts found in Hayes designated as
"H6".)
Rambus's new evidence does not rebut these findings or rationale.
Bennett, like Hayes, teaches transmitting time multiplexed signals to slave
memory devices, and Bennett teaches slave memory devices ranging from
the trivial to the complex. (See Bennett, col. 93, 1. 64 to col. 94,1. 5; B4;
B7.)
Rambus asserts that Bennett does not teach a single chip memory
device. Claim 2 does not require a single chip. Assuming arguendo that it
does, Rambus asserts that Bennett only teaches "that the VBT can be placed
on the same VLSIC chip under certain circumstances, [but] it teaches away
from doing so when the chip is relatively simple, like a memory device."
(See Reopen Req. 15.)
Contrary to Rambus's single chip argument based on an asserted
tendency toward complexity in Bennett, as quoted supra, Bennett
20
Case: 13-1623 Document: 10 Page: 102 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
specifically contemplates "the pass[ing ofJ but a single bit of data from a
single master device to a single slave device. . . . The versatility is from the
trivial to the profound." (B4 (emphasis added).)
Rambus's position that Bennett teaches only simple memory devices
and teaches away from memory devices with an integrated interface (a VB!)
(see Reopen Req. 20) also relies on Murphy's testimony that "[t]he same
circuitry supports everything form 3 7 -path embodiments to 3 -path
embodiments, the only difference being that portions of the interface may be
disabled." (3
rd
Supp. Murphy Decl. ,-r 18.) This testimony and Rambus's
position do not account for common sense possessed by skilled artisans and
the breadth of claim 2. If circuitry on a memory device can be "disabled,"
skilled artisans would have figured out that only some of it would need to be
put on a simple or trivial 3-pin memory devices to save the cost of putting it
on that device and then disabling it. Claim 2 also does not preclude complex
circuitry whether disabled or not.
Even though Bennett does discuss memory cards (see B3) as Rambus
also maintains, Bennett points toward single chip memory devices (B I-B3).
In any event, even Bennett's slave memory card, like Hayes's slave memory
board, satisfies the broadly recited memory device in the claims as noted
supra.
As indicated supra, the Board (see PTAB 2012-9762; PTAB 2012-
2081, BPAI 2012-000168, and BPAI 2012-000169 decisions) and a District
Court ("Hynix IF't have addressed the single chip argument and similar
6 Rambus, Inc. v. Hynix Semiconductor, Inc. 628 F.Supp.2d 1114, 1132-38
(N.D. Cal. 2008) (Judge R. H. Whyte ruling on summary judgment and
21
A151
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
specifically contemplates "the pass[ing of] but a single bit of data from a
single master device to a single slave device. . .. The versatility is from the
trivial to the profound." (B4 (emphasis added).)
Rambus's position that Bennett teaches only simple memory devices
and teaches away from memory devices with an integrated interface (a VBT)
(see Reopen Req. 20) also relies on Murphy's testimony that "[tJhe same
circuitry supports everything form 37-path embodiments to 3-path
embodiments, the only difference being that portions of the interface may be
disabled." (3
rd
Supp. Murphy Decl.   18.) This testimony and Rambus's
position do not account for common sense possessed by skilled artisans and
the breadth of claim 2. If circuitry on a memory device can be "disabled,"
skilled artisans would have figured out that only some of it would need to be
put on a simple or trivial 3-pin memory devices to save the cost of putting it
on that device and then disabling it. Claim 2 also does not preclude complex
circuitry whether disabled or not.
Even though Bennett does discuss memory cards (see B3) as Rambus
also maintains, Bennett points toward single chip memory devices (BI-B3).
Tn any event, even Bennett's slave memory card, like Hayes's slave memory
board, satisfies the broadly recited memory device in the claims as noted
supra.
As indicated supra, the Board (see PTAB 2012-9762; PTAB 2012-
2081, BPAI 2012-000168, and BPAI 2012-000169 decisions) and a District
Court ("Hynix IF')6 have addressed the single chip argument and similar
6 Ramhus, Inc. v. Hynix Semiconductor, Inc. 628 F.Supp.2d 1114, 1132-38
(N.D. Cal. 2008) (Judge R. H. Whyte ruling on summary judgment and
21
Case: 13-1623 Document: 10 Page: 103 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
arguments by Rambus in related proceedings. To the extent Rambus
maintains the Board overlooks arguments made here, Hynix II and the
above-listed decisions are adopted and incorporated herein by reference in
response.
In Hynix II, Judge Whyte in made extensive factual findings and
"concludes that the Manufacturers have carried their burden of producing
evidence that Bennett discloses a memory device, and that Rambus failed to
rebut this showing." Hynix II at 1131. Judge Whyte found that the Bennett
inventors "were aware of memory cards and referred to them as such when
they chose" and "disparaged the ... 'many cards [that] can be placed on the
bus.'" (Id. (quoting Bennett at col. 37,11. 26-28).) Judge Whyte also found
that the Bennett inventors turned away from such memory cards and toward
"VSLIC devices, including memory devices" which the court referred to as
"such memory chips." Hynix II at 1131.
As indicated in the description of Bennett supra, Bennett refers to
"VLSIC chip devices" and states that "[m]any, ifnot most, applications of
VLSIC technology are likely to include memory devices." (Bennett, col. 90,
11. 42-44; B2.) Bennett's "paramount object" is to provide flexible, versatile,
and configurable communication between "very large scale integrated VLSI
(circuit) elements" (col. 12,11. 14-25) - i.e., "VLSIC chips" (col. 9, 11. 35-
40). (See Bl.) The term VLSIC (very large scale integrated circuit) in
Bennett and conventionally signifies a single chip device. See Rambus Inc.
anticipation by Bennett of similar claims 27 and 43 in the 6,314,051 patent
which was also involved in the Board's BPAI 2012-000169 original and
rehearing decisions).
22
A152
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
arguments by Rambus in related proceedings. To the extent Rambus
maintains the Board overlooks arguments made here, Hynix II and the
above-listed decisions are adopted and incorporated herein by reference in
response.
Tn Hynix Il, Judge Whyte in made extensive factual findings and
"concludes that the Manufacturers have carried their burden of producing
evidence that Bennett discloses a memory device, and that Rambus failed to
rebut this showing." Hynix II at 1131. Judge Whyte found that the Bennett
inventors "were aware of memory cards and referred to them as such when
they chose" and "disparaged the ... 'many cards [that] can be placed on the
bus.'" (Id. (quoting Bennett at col. 37,11.26-28).) Judge Whyte also found
that the Bennett inventors turned away from such memory cards and toward
"VSLIC devices, including memory devices" which the court referred to as
"such memory chips." Hynix II at 1131.
As indicated in the description of Bennett supra, Bennett refers to
"VLSIC chip devices" and states that "[m]any, ifnot most, applications of
VLSIC technology are likely to include memory devices." (Bennett, col. 90,
11. 42-44; B2.) Bennett's "paramount object" is to provide flexible, versatile,
and configurable communication between "very large scale integrated VLSI
(circuit) elements" (col. 12,11. 14-25) - i.e., "VLSIC chips" (col. 9, 11. 35-
40). (See B1.) The term VLSIC (very large scale integrated circuit) in
Bennett and conventionally signifies a single chip device. See Rambus Inc.
anticipation by Bennett of similar claims 27 and 43 in the 6,314,051 patent
which was also involved in the Board's BPAI2012-000169 original and
rehearing decisions).
22
Case: 13-1623 Document: 10 Page: 104 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
v. Infineon Tech. AG, 318 F.3d 1081,1085-86,1091 (Fed. Cir. 2003)
(defining Rambus's claim term, "integrated circuit device," as a "circuit
constructed on a single monolithic substrate, commonly called a 'chip"')
(relying on trade dictionaries, citations omitted). Bennett states that a
VLSIC chip "cannot currently provide for as much memory as can be placed
on a card" (col. 9,11.47-48), but "VLSIC technology promises much higher
performance than that of cards," (col. 9, 11. 45-47), and "[t]he [VLSIC]
technology is projected to drive signals from chip to chip in 20 to 40
nanoseconds" (col. 9,11.58-60; B4). (Accord AA 3.)
Rambus also contradicts itself by arguing that "extrinsic evidence also
demonstrates that 'memory device' is a single chip that does not include a
memory controller." (Reopen Req. 11.) If that extrinsic evidence is correct,
then Bennett's "memory device" also signifies a single chip.
7
In other
words, Bennett's disclosure of the same term, "memory device[J" (B2),
references to "VLSIC upon the same chip substrate," "interfaces intended to
be built with ... Memory," (B 1) and other similar references to VLSIC,
chips or "same" substrates (BI-B4), combined with a limited and
disparaging discussion of memory cards as prior art (B3), all show that
Bennett's memory device includes a single chip embodiment (even if the
term also signifies other memory forms of memory as Rambus argues).
Bennett's Figures 1 and 38 also represent single chip memory devices. (See
Bl, B2.)
7 See note 5 supra, In re Rambus Inc., 694 F.3d at 42 (holding that the claim
term "memory device" in a related Rambus patent can signify but is not
limited to a single memory chip and includes a memory board).
23
A153
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
v. Injineon Tech. AG, 318 FJd 1081,1085-86,1091 (Fed. Cir. 2003)
(defining Rambus's claim term, "integrated circuit device," as a "circuit
constructed on a single monolithic substrate, commonly called a 'chip"')
(relying on trade dictionaries, citations omitted). Bennett states that a
VLSTC chip "cannot currently provide for as much memory as can be placed
on a card" (col. 9,11.47-48), but "VLSIC technology promises much higher
performance than that of cards," (col. 9,11.45-47), and "[t]he [VLSIC]
technology is projected to drive signals from chip to chip in 20 to 40
nanoseconds" (col. 9,11.58-60; B4). (Accord AA 3.)
Rambus also contradicts itself by arguing that "extrinsic evidence also
demonstrates that 'memory device' is a single chip that does not include a
memory controller." (Reopen Req. 11.) Tfthat extrinsic evidence is correct,
then Bennett's "memory device" also signifies a single chip.7 In other
words, Bennett's disclosure of the same term, "memory device[J" (B2),
references to "VLSIC upon the same chip substrate," "interfaces intended to
be built with. . . Memory," (B 1) and other similar references to VLSIC,
chips or "same" substrates (BI-B4), combined with a limited and
disparaging discussion of memory cards as prior art (B3), all show that
Bennett's memory device includes a single chip embodiment (even if the
term also signifies other memory forms of memory as Rambus argues).
Bennett's Figures 1 and 38 also represent single chip memory devices. (See
Bl, B2.)
7 See note 5 supra, In re Rambus Inc., 694 F.3d at 42 (holding that the claim
term "memory device" in a related Rambus patent can signify but is not
limited to a single memory chip and includes a memory board).
23
Case: 13-1623 Document: 10 Page: 105 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
As discussed above, Bennett discloses ROM chips and implies other
chips for reading and writing data, at least suggesting the popular DRAMs
for reading and writing. Judge Whyte makes a similar finding:
Bennett discusses ROMs while explaining the limited number
of operations that can be done with a memory device, and it
does so to point out that memories like ROMs cannot receive
write operations ... . Bennett's discussion thus impliedly
discloses some type of memory device that can receive write
operations. The jury will have to determine at trial whether
that implied disclosure encompasses a dynamic ran do m access
memory.
Hynix II at 1137 (emphasis added).
Rambus also alleges that asynchronous RAS and CAS signals
"perform completely different functions" in asynchronous systems like that
of Hayes as compared to synchronous systems like those from Bennett, and
thus, this shows the unobviousness of modifying Hayes's memory slave
devices into either a synchronous memory board device or a synchronous
memory single chip device. (See Reopen Req. 17 (discussing NVIDIA's
expert Parris's Declaration).) But in Hayes, the CAS and RAS signals
transfer within Hayes's slave memory device - a memory board device.
(See Hayes Fig. 7 (showing internal portions of slave/memory board with
RAS and CAS lines connecting RAM control logic 62 to the DRAM chips).)
Moreover, to the processor chip in the Hayes external bus master, the
memory board looks just like a single slave RAM chip. "An important
feature of the present invention is that to local bus 17 master [i.e., processer
10 or chip 16, Hayes, col. 14,11.3-4)] there is no distinction between on-
board RAM and off-board RAM." (Hayes, col. 14, 11. 29-31.) Therefore,
24
A154
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
As discussed above, Bennett discloses ROM chips and implies other
chips for reading and writing data, at least suggesting the popular DRAMs
for reading and writing. Judge Whyte makes a similar finding:
Bennett discusses ROMs while explaining the limited number
of operations that can be done with a memory device, and it
does so to point out that memories like ROMs cannot receive
write operations ... . Bennett's discussion thus impliedly
discloses some type of memOlY device that can receive write
operations. The jury will have to determine at trial whether
that implied disclosure encompasses a dynamic random access
memory.
Hynix II at 1137 (emphasis added).
Rambus also alleges that asynchronous RAS and CAS signals
"perform completely different functions" in asynchronous systems like that
of Hayes as compared to synchronous systems like those from Bennett, and
thus, this shows the unobviousness of modifying Hayes's memory slave
devices into either a synchronous memory board device or a synchronous
memory single chip device. (See Reopen Req. 17 (discussing NVlDlA's
expert Parris's Declaration).) But in Hayes, the CAS and RAS signals
transfer within Hayes's slave memory device - a memory board device.
(See Hayes Fig. 7 (showing internal portions of slave/memory board with
RAS and CAS lines connecting RAM control logic 62 to the DRAM chips).)
Moreover, to the processor chip in the Hayes external bus master, the
memory board looks just like a single slave RAM chip. "An important
feature of the present invention is that to local bus 17 master [i.e., processer
10 or chip 16, Hayes, col. 14,11. 3-4)J there is no distinction between on-
board RAM and off-board RAM." (Hayes, col. 14,11. 29-31.) Therefore,
24
Case: 13-1623 Document: 10 Page: 106 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
contrary to Rambus' s arguments, the RAS and CAS signals on the memory
board slave device do not overly complicate rendering such a device into a
single slave chip device or render unobvious sending a synchronous signal to
either one - especially since, as noted supra, Hayes's system sends time
multiplexed signals from a master to a slave (which look the same to the bus
master whether the slave is a board or a chip) as similarly occurs in Bennett.
Further, since Bennett similarly discloses memory boards and
memory chips according to the record and Rambus, Bennett suggests the
obviousness of synchronizing either one of these memory devices, including
a memory device such as Hayes's memory board - i.e., regardless of the
functionality of the RAS or CAS signals thereon. (See also Ex. Det. 7, 8
(addressing Rambus' s arguments about RAS and CAS signals and relying
on the Parris testimony showing the "shift in the art from asynchronous to
synchronous systems" to increase speed).)
In sum, Rambus' s contentions which rely on Murphy's new testimony
add little or nothing to Murphy's prior testimony as the Examiner finds.
(See Ex. Det. 5-6, 9 (finding that Murphy's Third Supplemental Declaration
to be cumulative to prior testimony).) Rambus's further reliance on Dr.
Jacob and Betty Prince also fails to show unobviousness.
Rambus asserts that Dr. Jacob and others such as Betty Prince show
distinctions between asynchronous and synchronous devices and logic.
Rambus's assertions do not overcome the Board's finding that skilled
artisans were modifying asynchronous systems and transforming them into
synchronous systems while keeping some of, or modifying, the logic in
asynchronous systems, as the expert Parris testifies and as the Examiner
finds in reliance thereon. (See Reopen Req. 18-19; Ex. Det. 6-14.)
25
A155
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
contrary to Rambus' s arguments, the RAS and CAS signals on the memory
board slave device do not overly complicate rendering such a device into a
single slave chip device or render unobvious sending a synchronous signal to
either one - especially since, as noted supra, Hayes's system sends time
multiplexed signals from a master to a slave (which look the same to the bus
master whether the slave is a board or a chip) as similarly occurs in Bennett.
Further, since Bennett similarly discloses memory boards and
memory chips according to the record and Rambus, Bennett suggests the
obviousness of synchronizing either one of these memory devices, including
a memory device such as Hayes's memory board - i.e., regardless of the
functionality of the RAS or CAS signals thereon. (See also Ex. Det. 7, 8
(addressing Rambus's arguments about RAS and CAS signals and relying
on the Parris testimony showing the "shift in the art from asynchronous to
synchronous systems" to increase speed).)
In sum, Rambus's contentions which rely on Murphy's new testimony
add little or nothing to Murphy's prior testimony as the Examiner finds.
(See Ex. Det. 5-6, 9 (finding that Murphy's Third Supplemental Declaration
to be cumulative to prior testimony).) Rambus's further reliance on Dr.
Jacob and Betty Prince also fails to show unobviousness.
Rambus asserts that Dr. Jacob and others such as Betty Prince show
distinctions between asynchronous and synchronous devices and logic.
Rambus's assertions do not overcome the Board's finding that skilled
artisans were modifying asynchronous systems and transforming them into
synchronous systems while keeping some of, or modifying, the logic in
asynchronous systems, as the expert Parris testifies and as the Examiner
finds in reliance thereon. (See Reopen Req. 18-19; Ex. Det. 6-14.)
25
Case: 13-1623 Document: 10 Page: 107 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
Rambus cites to Dr. Jacob's textbook which describes a history of
DRAMs. In the mid-1970's, "[o]ther early DRAMs were sometimes
clocked ... by a periodic clock signal" (i.e., apparently, synchronously) and
then the technology moved toward asynchronous devices. (See Ch. 12,461,
§ 12.2.2.) Dr. Jacob explains that asynchronous DRAM devices were "more
of a hindrance than an asset" and that "computer manufacturers pushed to
place a synchronous interface on the DRAM device." (See id. at 466.) (It is
not clear when this "push" occurred or who the manufactures were, but
Rambus relies on the textbook to support its position.)
In any event, Dr. Jacob states that a central difference between RAS
and CAS in synchronous and asynchronous DRAMs is that the latter
involves controlling "latches that are internal to the DRAM device" while
the former involves
(Id.)
signals [which] deliver ... commands ... acted upon by the
control logic of the SDRAM device at the falling edge of the
clock signal. In this manner, the operation of the state machine
in the DRAM device moved from the memory controller into
the DRAM device, enabling features such as programmability
and multi -bank operation.
Rambus's assertions fail to show how Dr. Jacob's textbook reveals an
insurmountable, if any, challenge, in accommodating any functional
difference between synchronous and asynchronous RAS and CAS signals.
Rambus also does not show that synchronously operated logic circuits
including any "truth table [ s]" discussed by Betty Prince would have
presented any technical challenge to skilled artisans attempting to modify
internal DRAM circuits to handle RAS and CAS logic. (See Reopen Req.
18 (discussing Betty Prince).)
26
A156
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Rambus cites to Dr. Jacob's textbook which describes a history of
DRAMs. In the mid-1970's, "[o]ther early DRAMs were sometimes
clocked ... by a periodic clock signal" (i.e., apparently, synchronously) and
then the teclmology moved toward asynchronous devices. (See Ch. 12,461,
§ 12.2.2.) Dr. Jacob explains that asynchronous DRAM devices were "more
of a hindrance than an asset" and that "computer manufacturers pushed to
place a synchronous interface on the DRAM device." (See id. at 466.) (It is
not clear when this "push" occurred or who the manufactures were, but
Rambus relies on the textbook to support its position.)
In any event, Dr. Jacob states that a central difference between RAS
and CAS in synchronous and asynchronous DRAMs is that the latter
involves controlling "latches that are internal to the DRAM device" while
the former involves
([d.)
signals [which] deliver ... commands ... acted upon by the
control logic of the SDRAM device at the falling edge of the
clock signal. In this manner, the operation of the state machine
in the DRAM device moved from the memory controller into
the DRAM device, enabling features such as programmability
and multi-bank operation.
Rambus's assertions fail to show how Dr. Jacob's textbook reveals an
insurmountable, if any, challenge, in accommodating any functional
difference between synchronous and asynchronous RAS and CAS signals.
Rambus also does not show that synchronously operated logic circuits
including any "truth table[ s]" discussed by Betty Prince would have
presented any technical challenge to skilled artisans attempting to modify
internal DRAM circuits to handle RAS and CAS logic. (See Reopen Req.
18 (discussing Betty Prince).)
26
Case: 13-1623 Document: 10 Page: 108 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
Parris also contradicts Rambus' s assertions and describes modifying,
in a "straight forward" manner, i.e., "well within the ability of one of
ordinary skill in the art," such "previously asynchronous DRAM ['RAS'
and 'CAS'] signals" to be "on-chip," generally describes "incorporat[ing]
asynchronous functionality on previous asynchronous memory systems into
synchronous memory systems," and further notes that the "logic circuitry
[including latches, registers, and counters] was typically [modified to be] ...
synchronous with the [external] clock". (Parris Decl. ,-r 9.)
Rambus also argues that the Board does not identify a reason for
modifying Hayes's traditional asynchronous CAS and RAS signals to
include Bennett's clocking scheme. But as the Examiner recognizes, the
Board did identify reasons, including the industry push toward integration
and synchronization to create smaller and faster memory devices. (See Ex.
Det. 7 (citing '623 Bd. Dec. 29 which cites Parris Decl. ,-r,-r 18-20).) Dr.
Jacob's textbook and Rambus's other cited evidence fail to rebut Parris who
also testifies as follows: "To the contrary [of Murphy's testimony and
Rambus's arguments], adding logic on-chip with the memory device
increases processing speed for multiple reasons, including reducing
propagation delays and allowing the memory device to by physically closer
to other devices driving the bus." (Parris Decl. ,-r 19.)
In addition, Hayes also discloses at least partial synchronization -
bank select strobes on the memory board device are "synchronized with the
processor timing by ARR RASIN (Array Row Address Strobe In)" during a
memory board transaction. (Hayes, col. 23, 11. 38-41.) The evidence shows
that synchronizing signals with an external clock would not have required an
unobvious or insurmountable modification of the traditional RAS, CAS, or
27
A157
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Parris also contradicts Rambus' s assertions and describes modifying,
in a "straight forward" manner, i.e., "well within the ability of one of
ordinary skill in the art," such "previously asynchronous DRAM ['RAS'
and 'CAS'] signals" to be "on-chip," generally describes "incorporat[ing]
asynchronous functionality on previous asynchronous memory systems into
synchronous memory systems," and further notes that the "logic circuitry
[including latches, registers, and counters] was typically [modified to be] ...
synchronous with the [external] clock". (Parris Decl.   9.)
Rambus also argues that the Board does not identify a reason for
modifying Hayes's traditional asynchronous CAS and RAS signals to
include Bennett's clocking scheme. But as the Examiner recognizes, the
Board did identify reasons, including the industry push toward integration
and synchronization to create smaller and faster memory devices. (See Ex.
Det. 7 (citing '623 Bd. Dec. 29 which cites Parris Decl.     18-20).) Dr.
Jacob's textbook and Rambus's other cited evidence fail to rebut Parris who
also testifies as follows: "To the contrary [of Murphy's testimony and
Rambus's arguments], adding logic on-chip with the memory device
increases processing speed for multiple reasons, including reducing
propagation delays and allowing the memory device to by physically closer
to other devices driving the bus." (Parris Decl.   19.)
In addition, Hayes also discloses at least partial synchronization -
bank select strobes on the memory board device are "synchronized with the
processor timing by ARR RASIN (Array Row Address Strobe In)" during a
memory board transaction. (Hayes, col. 23, 11. 38-41.) The evidence shows
that synchronizing signals with an external clock would not have required an
unobvious or insurmountable modifIcation of the traditional RAS, CAS, or
27
Case: 13-1623 Document: 10 Page: 109 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
DS signals in Hayes, contrary to Rambus' s arguments - arguments which
lack sufficient factual supporting evidence. (See Reopen Req. 16-18.)
Other alleged structural features in SDRAMs (synchronous DRAMs)
supposedly showing unobvious according to Rambus, such as programmable
registers and multiple internal banks, fail to support Rambus, because these
added SDRAM features are neither needed to modify Hayes nor to satisfy
the claims. (See Reopen Req. 19-20.) Rambus does not assert that it
invented these SDRAM features, that synchronous memory devices require
them, or that the claims require them, so it is not clear how the features show
unobviousness. Bennett discloses synchronous memory chips that either
have or do not have these specific SDRAM features - showing the
obviousness of using generic synchronous memory chips encompassed by
the claims.
Based on the foregoing discussion, Rambus' s new evidence and
arguments do not show unobviousness or error in the '623 Board Decision
as the Examiner finds and reasons.
Hayes with Bennett and Inagaki - Claims 3,4,12,13,21, and 22
Rambus does not direct attention to a specific claim. Claim 3 is
selected as representative. Claim 3 depends from claim 2 and additionally
requires sampling first and second data portions on odd and even phases of
the external clock signal. The record supports the Examiner's findings and
rationale which are hereby adopted and incorporated by reference. (See Ex.
Det. 10-14.) Rambus's new evidence does not undermine the '623 Board
Decision. (See Bd. Dec. 29-31.) As the Decision explains and as noted
supra, Hayes uses a clock to drive time multiplexed signals to a memory
device. Bennett also uses a clock to drive time multiplexed signals and to
28
A158
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
DS signals in Hayes, contrary to Rambus's arguments - arguments which
lack sufficient factual supporting evidence. (See Reopen Req. 16-18.)
Other alleged structural features in SDRAMs (synchronous DRAMs)
supposedly showing unobvious according to Rambus, such as programmable
registers and multiple internal banks, fail to support Rambus, because these
added SDRAM features are neither needed to modify Hayes nor to satisfy
the claims. (See Reopen Req. 19-20.) Rambus does not assert that it
invented these SDRAM features, that synchronous memory devices require
them, or that the claims require them, so it is not clear how the features show
unobviousness. Bennett discloses synchronous memory chips that either
have or do not have these specific SDRAM features - showing the
obviousness of using generic synchronous memory chips encompassed by
the claims.
Based on the foregoing discussion, Rambus' s new evidence and
arguments do not show unobviousness or error in the '623 Board Decision
as the Examiner finds and reasons.
Hayes with Bennett and Inagaki - Claims 3,4,12,13,21, and 22
Rambus does not direct attention to a specific claim. Claim 3 is
selected as representative. Claim 3 depends from claim 2 and additionally
requires sampling first and second data portions on odd and even phases of
the external clock signal. The record supports the Examiner's findings and
rationale which are hereby adopted and incorporated by reference. (See Ex.
Det. 10-14.) Rambus's new evidence does not undermine the '623 Board
Decision. (See Bd. Dec. 29-31.) As the Decision explains and as noted
supra, Hayes uses a clock to drive time multiplexed signals to a memory
device. Bennett also uses a clock to drive time multiplexed signals and to
28
Case: 13-1623 Document: 10 Page: 110 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
synchronize memory devices. Inagaki merely teaches using both clock
phases, i.e., the rising and falling edges of an external clock, to double the
clock speed in memory devices. (See id.)
As the Examiner recognizes, contrary to Rambus' s characterization,
Bennett's system is not being modified by the proposed combination, but
rather, Bennett is employed to suggest using an external clock to
synchronize memory devices. As such, as the Examiner recognizes,
Rambus's argument and Murphy's testimony that Bennett's system would
have been rendered inoperable or that Bennett's principle of operation would
have been destroyed via the proposed prior art combination are not germane
to the proposed rejection. (See Ex. Det. 12-13; Reopen Req. 24-25.)8
Contrary to related arguments by Rambus that Bennett's system
would not have employed a faster clock (see Reopen Req. 24-25), Bennett's
system is not being modified as noted, and in any event, contemplates faster
speeds including doubled speeds: "The technology is projected to drive
signals form chip to chip in 20 to 40 nanoseconds with internal gate delays
of 1 to 2 nanoseconds." (B4; Ex. Det. 12 (also quoting this Bennett
sentence).) This fact and related facts, including a universal desire for speed
and industry drives toward integration, all suggest the obviousness of using a
8 The Board addressed arguments about Bennett's alleged inoperability in a
related decision involving Rambus. (See e.g., PTAB 2012-001976 at 19-
30).) The' 1976 decision, adopted and incorporated herein by reference,
finds that Bennett's principle of operation would not have been destroyed or
that Bennett's system would not have required appreciable alteration to use
falling and rising clock edges. In the alternative, the' 1976 decision finds
that Bennett's system would not require two clocks for simple single device
systems.
29
A159
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
synchronize memory devices. Inagaki merely teaches using both clock
phases, i.e., the rising and falling edges of an external clock, to double the
clock speed in memory devices. (See id.)
As the Examiner recognizes, contrary to Rambus's characterization,
Bennett's system is not being modified by the proposed combination, but
rather, Bennett is employed to suggest using an external clock to
synchronize memory devices. As such, as the Examiner recognizes,
Rambus's argument and Murphy's testimony that Bennett's system would
have been rendered inoperable or that Bennett's principle of operation would
have been destroyed via the proposed prior art combination are not germane
to the proposed rejection. (See Ex. Det. 12-13; Reopen Req. 24-25f
Contrary to related arguments by Rambus that Bennett's system
would not have employed a faster clock (see Reopen Req. 24-25), Bennett's
system is not being modified as noted, and in any event, contemplates faster
speeds including doubled speeds: "The technology is projected to drive
signals form chip to chip in 20 to 40 nanoseconds with internal gate delays
of 1 to 2 nanoseconds." (B4; Ex. Det. 12 (also quoting this Bennett
sentence).) This fact and related facts, including a universal desire for speed
and industry drives toward integration, all suggest the obviousness of using a
8 The Board addressed arguments about Bennett's alleged inoperability in a
related decision involving Rambus. (See e.g., PTAB 2012-001976 at 19-
30).) The '1976 decision, adopted and incorporated herein by reference,
finds that Bennett's principle of operation would not have been destroyed or
that Bennett's system would not have required appreciable alteration to use
falling and rising clock edges. In the alternative, the '1976 decision finds
that Bennett's system would not require two clocks for simple single device
systems.
29
Case: 13-1623 Document: 10 Page: 111 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
both edges of a clock to gain clock speed in Hayes as modified by Bennett,
according to Inagaki's teachings. As the '623 Board Decision also explains,
in addition to increasing speed using both the rising and falling clock edges,
Inagaki also suggests using a relatively slower clock's dual edges as a mere
substitute for a faster clock which uses only the rising edges. U sing dual
edges can also allow for a decreased number of signal lines since twice the
data can be pushed over half the lines using both clock edges as Inagaki
teaches. (See Bd. Dec. 29-31.)
Based on the foregoing discussion, Rambus' s new evidence does not
show unobviousness and does not upset the '623 Board Decision as the
Examiner finds and reasons.
Hayes with Inagaki - Claims 12 and 13
Claim 12, like claim 3 discussed supra, requires sampling data on
both clock edges. Rambus does not direct attention to either claim 12 or 13.
Claim 12 is selected as representative.
The Examiner's findings and rationale are supported and adopted and
incorporated herein by reference. (See Ex. Det. 10.) Rambus maintains that
the prior art combination does not render obvious a synchronous memory
device using a data strobe and a periodic clock. (See Reopen Req. 26.)
Hayes's DS satisfies the data strobe signal as discussed supra, and
Hayes and Inagaki each disclose a clock, contrary to Rambus' s arguments.
As the Decision explains - which Rambus does not address - claims 12 and
13 depend from claim 1, and unlike claim 2, do not recite synchronous
operation. Inagaki' s clock samples data during odd and even phases of a
clock, as claim 12 requires: "'[S]ince one bit is output on each half-cycle,
the operating speed is twice that of the conventional speed. '" (See '623 Bd.
30
A160
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
both edges of a clock to gain clock speed in Hayes as modified by Bennett,
according to Jnagaki's teachings. As the '623 Board Decision also explains,
in addition to increasing speed using both the rising and falling clock edges,
Jnagaki also suggests using a relatively slower clock's dual edges as a mere
substitute for a faster clock which uses only the rising edges. Using dual
edges can also allow for a decreased number of signal lines since twice the
data can be pushed over half the lines using both clock edges as Inagaki
teaches. (See Bd. Dec. 29-31.)
Based on the foregoing discussion, Rambus's new evidence does not
show unobviousness and does not upset the '623 Board Decision as the
Examiner finds and reasons.
Hayes with lnagaki - Claims 12 and 13
Claim 12, like claim 3 discussed supra, requires sampling data on
both clock edges. Rambus does not direct attention to either claim 12 or 13.
Claim 12 is selected as representative.
The Examiner's findings and rationale are supported and adopted and
incorporated herein by reference. (See Ex. Det. lO.) Rambus maintains that
the prior art combination does not render obvious a synchronous memory
device using a data strobe and a periodic clock. (See Reopen Req. 26.)
Hayes's DS satisfies the data strobe signal as discussed supra, and
Hayes and Jnagaki each disclose a clock, contrary to Rambus's arguments.
As the Decision explains - which Rambus does not address - claims 12 and
13 depend from claim 1, and unlike claim 2, do not recite synchronous
operation. Jnagaki' s clock samples data during odd and even phases of a
clock, as claim 12 requires: '" [S]ince one bit is output on each half-cycle,
the operating speed is twice that of the conventional speed.'" (See '623 Bd.
30
Case: 13-1623 Document: 10 Page: 112 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
Dec. 30 (quoting Inagaki at 4).) Rambus also does not provide new
evidence to upset the '623 Board Decision. (See Reopen Req. 26.)
Assuming arguendo that the claims implicitly require synchronous
operation, Inagaki characterizes the clock operation as synchronous: For
example, "clock <pI is generated synchronously with the external clock <p."
(Inagaki at 5 (discussing Figurel0).) As the Examiner also notes, the Parris
declaration and other references of record show that such synchronous
operation was known and the industry was moving towards it. (See Ex. Det.
14-15. ) Using dual edges of a clock (synchronously or not) would have
been obvious to increase speed as Inagaki teaches.
Based on the foregoing discussion, Rambus's arguments, lacking in
new evidence, do not show unobviousness and do not upset the '623 Board
Decision as the Examiner finds and reasons.
Hayes with Ohshima - Claims 2-10,12-14,16,17, and 20-26
Rambus does not direct its arguments to any single claim. Claim 2 is
selected to be representative of the above-listed group based on Rambus's
arguments. The Decision largely relies on and refers to NVIDIA's inter
partes request and Brief for the rejection of these claims. (See '623 Bd. Dec.
32-33.) As an example, NVIDIA relies on Ohshima to teach that
intervening circuits should be added on -chip in a simple chip-to-chip
interface. NVIDIA also relies on Ohshima's synchronous chip teachings
and other features to increase speed in a DRAM. (See e.g. NVIDIA App.
Br. Exhibit 14 (claim chart at 1.2,2.0); App. Br. 13; I.P. Request at 30-35.)
NVIDIA's inter partes request reasons that Ohshima teaches that combining
logic on chip reduces the number of chips and complexity. (See I.P. Request
at 30.) Rambus does not challenge these relied upon findings or rationale.
31
A161
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Dec. 30 (quoting Jnagaki at 4).) Rambus also does not provide new
evidence to upset the '623 Board Decision. (See Reopen Req. 26.)
Assuming arguendo that the claims implicitly require synchronous
operation, Jnagaki characterizes the clock operation as synchronous: For
example, "clock <p 1 is generated synchronously with the external clock <p."
(Jnagaki at 5 (discussing Figurel0).) As the Examiner also notes, the Parris
declaration and other references of record show that such synchronous
operation was known and the industry was moving towards it. (See Ex. Det.
14-15.) Using dual edges of a clock (synchronously or not) would have
been obvious to increase speed as Jnagaki teaches.
Based on the foregoing discussion, Rambus's arguments, lacking in
new evidence, do not show unobviousness and do not upset the '623 Board
Decision as the Examiner finds and reasons.
Hayes with Ohshima - Claims 2-10,12-14,16,17, and 20-26
Rambus does not direct its arguments to any single claim. Claim 2 is
selected to be representative of the above-listed group based on Rambus's
arguments. The Decision largely relies on and refers to NVID IA' sinter
partes request and Brief for the rejection of these claims. (See '623 Bd. Dec.
32-33.) As an example, NVlDIA relies on Ohshima to teach that
intervening circuits should be added on -chip in a simple chip-to-chip
interface. NVIDIA also relies on Ohshima's synchronous chip teachings
and other features to increase speed in a DRAM. (See e.g. NVIDIA App.
Br. Exhibit 14 (claim chart at 1.2,2.0); App. Br. 13; I.P. Request at 30-35.)
NVIDIA's inter partes request reasons that Ohshima teaches that combining
logic on chip reduces the number of chips and complexity. (See I.P. Request
at 30.) Rambus does not challenge these relied upon findings or rationale.
31
Case: 13-1623 Document: 10 Page: 113 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
The Examiner reasons that incorporating the Hayes RAM control DS
circuitry into a single chip memory device according to Ohshima's teachings
would have been obvious and that the claims do not require incorporating all
the RAM logic into a single chip as Rambus's arguments imply. (See Ex.
Det. 15-16; Reopen Req. 27-28 (citing Murphy 3
rd
Supp. Dec!. at,-r,-r 28-29).)
Murphy's Third Supplemental Declaration addresses the obviousness of
incorporating all the Hayes DS RAM logic into a single chip and thus fails
to address the Board's Decision. (See '623 Bd. Dec. 32-33.) The thrust of
Rambus's position reduces skilled artisans to automatons who would blindly
incorporate all of Hayes's RAM control logic which controls multiple chips
into a single chip. To the contrary, as a matter of routine skill, skilled
artisans would have eliminated any unnecessary circuitry to create a single,
simple DRAM chip having the necessary interface control to control that
DRAM to transfer data as Ohshima shows.
Such a combination involving integration would have been obvious
for creating faster and smaller components as Parris declares as noted supra.
See also Dystar Textilfarben GmBH & Co. Dutschland KG v. CN Patrick
Co., 464 F.3d 1356,1368 (Fed. Cir. 2006) ("[A]n implicit motivation to
combine exists ... when the 'improvement' is technology-independent and the
combination of references results in a product or process that is more
desirable, for example because it is stronger, cheaper, cleaner, faster, lighter,
smaller, more durable, or more efficient.") Contrary to Rambus' s arguments
(Reopen Req. 23), Dystar's motivation is not limited to "technology-
independent" improvements. Rambus's arguments illogically would mean
that the memory device industry or any single industry would not desire
speed increases.
32
A162
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
The Examiner reasons that incorporating the Hayes RAM control DS
circuitry into a single chip memory device according to Ohshima's teachings
would have been obvious and that the claims do not require incorporating all
the RAM logic into a single chip as Rambus's arguments imply. (See Ex.
Det. 15-16; Reopen Req. 27-28 (citing Murphy 3
rd
Supp. Decl. at     28-29).)
Murphy's Third Supplemental Declaration addresses the obviousness of
incorporating all the Hayes DS RAM logic into a single chip and thus fails
to address the Board's Decision. (See '623 Bd. Dec. 32-33.) The thrust of
Rambus's position reduces skilled artisans to automatons who would blindly
incorporate all of Hayes's RAM control logic which controls multiple chips
into a single chip. To the contrary, as a matter of routine skill, skilled
artisans would have el1minated any unnecessary circuitry to create a single,
simple DRAM chip having the necessary interface control to control that
DRAM to transfer data as Ohshima shows.
Such a combination involving integration would have been obvious
for creating faster and smaller components as Parris declares as noted supra.
See also Dystar Textilfarben GmBH & Co. Dutschland KG v. C.H Patrick
Co., 464 F.3d 1356,1368 (Fed. Cir. 2006) ("[AJn implicit motivation to
combine exists ... when the 'improvement' is technology-independent and the
combination of references results in a product or process that is more
desirable, for example because it is stronger, cheaper, cleaner, faster, lighter,
smaller, more durable, or more efficient.") Contrary to Rambus's arguments
(Reopen Req. 23), Dystar's motivation is not limited to "technology-
independent" improvements. Rambus's arguments illogically would mean
that the memory device industry or any single industry would not desire
speed increases.
32
Case: 13-1623 Document: 10 Page: 114 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
Ohshima teaches using "newly developed high speed DRAMs
and their innovative circuit techniques" to solve memory bottleneck
problems. (See Ohshima 1303 ("Summary").) Ohshima also discusses
using the "Rambus DRAM" for the same or similar purpose of increasing
speed. (See id.) Rambus does not assert that Ohshima is not prior art in this
reexamination proceeding. In several other proceedings before the Board,
Rambus has asserted that their claimed devices have been highly successful
to solve speed and memory bottleneck problems. Using these synchronous
DRAMs and similar DRAMs to modify a single DRAM of Hayes while
incorporating the Hayes DS logic to tell the DRAM that data is valid would
have been obvious. As noted, Parris bolsters the obviousness of such
integration and testifies that asynchronous systems were migrating to
synchronous memory devices and designers were incorporating memory
logic into such integrated devices to increase speed.
Based on the foregoing discussion, Rambus' s new evidence and
arguments do not disturb the '623 Board Decision as the Examiner
determined.
Kushiyama with Hayes and Lu - Claims 1-14, 16, 17, and 19-26
Rambus does not direct its arguments to any single claim. Claim 1 is
selected to be representative of the above-listed claims based on Rambus's
arguments. As Rambus notes, the Examiner finds that Lu teaches
incorporating logic circuits into memory, and finds that it would have been
obvious to incorporate some of the Hayes RAM control logic, such as the
DS signal circuitry, into a DRAM ofKushiyama. (See Reopen Req. 28.) As
the '623 Board Decision explains:
33
A163
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Ohshima teaches using "newly developed high speed DRAMs
and their innovative circuit techniques" to solve memory bottleneck
problems. (See Ohshima 1303 ("Summary").) Ohshima also discusses
using the "Rambus DRAM" for the same or similar purpose of increasing
speed. (See id.) Rambus does not assert that Ohshima is not prior art in this
reexamination proceeding. In several other proceedings before the Board,
Rambus has asserted that their claimed devices have been highly successful
to solve speed and memory bottleneck problems. Using these synchronous
DRAMs and similar DRAMs to modify a single DRAM of Hayes while
incorporating the Hayes DS logic to tell the DRAM that data is valid would
have been obvious. As noted, Parris bolsters the obviousness of such
integration and testifies that asynchronous systems were migrating to
synchronous memory devices and designers were incorporating memory
logic into such integrated devices to increase speed.
Based on the foregoing discussion, Rambus's new evidence and
arguments do not disturb the '623 Board Decision as the Examiner
determined.
Kushiyama with Hayes and Lu - Claims 1-/4,16, 17, and 19-26
Rambus does not direct its arguments to any single claim. Claim 1 is
selected to be representative of the above-listed claims based on Rambus's
arguments. As Rambus notes, the Examiner finds that Lu teaches
incorporating logic circuits into memory, and finds that it would have been
obvious to incorporate some of the Hayes RAM control logic, such as the
DS signal circuitry, into a DRAM ofKushiyama. (See Reopen Req. 28.) As
the '623 Board Decision explains:
33
Case: 13-1623 Document: 10 Page: 115 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
NVIDIA reasons that integrating the DS logic of Hayes into the
Kushiyama chips would have been obvious where Lu teaches
incorporating on-chip logic to make DRAMs more intelligent
and to optimize performance at the system level. (Req. App.
Br. 14-15.) Mr. Par[rJis corroborates this point and notes that
chip designers were employing asynchronous circuits on-chip,
including some strobe signals, like RAS and CAS, and that
moving such circuits on-chip increase speed.
('623 Bd. Dec. 33 (citing Parris Decl. ,-r,-r 9, 19.)
In response to the Board's finding, Rambus maintains that the Board
"provides no indication of how the DS signal from Hayes's asynchronous
system would have been incorporated into Kushiyama's synchronous system
or why such incorporation would have been beneficial." (Reopen Req. 28-
29.) But Rambus does not show that skilled artisans would have been
unable to make such a change, and the DS signal serves the stated purpose in
Hayes of telling the memory device that data is valid and thereby ready to be
sampled, rendering its use in other memory devices to signal sampling
obvious. (See Ex. Det. 17; accord Parris Decl. ,-r 11 (discussing a similar
TmcvrRW signal and explaining why indicating valid data to a slave
indicates when to sample); ,-r 24 (discussing Kushiyama).)
The record reflects that the skill level here in memory systems was
advanced at the time of the invention. Hence, while Murphy testifies that
such integration would be "non-trivial" and "the disadvantage of cost and
establishing a common architecture may outweigh the advantages of new
features" (see 3
rd
Supp. Murphy Decl. ,-r31), this testimony falls short of
showing that skilled artisans could or would not have seized the known
34
A164
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
NVIDIA reasons that integrating the DS logic of Hayes into the
Kushiyama chips would have been obvious where Lu teaches
incorporating on-chip logic to make DRAMs more intelligent
and to optimize performance at the system level. (Req. App.
Br. 14-15.) Mr. Par[rJis corroborates this point and notes that
chip designers were employing asynchronous circuits on-chip,
including some strobe signals, like RAS and CAS, and that
moving such circuits on-chip increase speed.
('623 Bd. Dec. 33 (citing Parris Decl. ~ ~ 9, 19.)
In response to the Board's finding, Rambus maintains that the Board
"provides no indication of how the DS signal from Hayes's asynchronous
system would have been incorporated into Kushiyama's synchronous system
or why such incorporation would have been beneficiaL" (Reopen Req. 28-
29.) But Rambus does not show that skilled artisans would have been
unable to make such a change, and the DS signal serves the stated purpose in
Hayes of telling the memory device that data is valid and thereby ready to be
sampled, rendering its use in other memory devices to signal sampling
obvious. (See Ex. Det. 17; accord Parris Decl. ~ 11 (discussing a similar
TrncvrRW signal and explaining why indicating valid data to a slave
indicates when to sample); ~ 24 (discussing Kushiyama).)
The record reflects that the skill level here in memory systems was
advanced at the time of the invention. Hence, while Murphy testifies that
such integration would be "non-trivial" and "the disadvantage of cost and
establishing a common architecture may outweigh the advantages of new
features" (see 3
rd
Supp. Murphy Decl. ~ 3 1   , this testimony falls short of
showing that skilled artisans could or would not have seized the known
34
Case: 13-1623 Document: 10 Page: 116 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
advantages. Rambus similarly reasons that artisans would not have
incorporated asynchronous features into synchronous systems and that Lu
does not "unequivocally teach integration of logic into DRAMs." (Reopen
Req. 29 (citing 3
rd
Supp. Murphy Dec!. at,-r,-r 31-32).)
Lu discusses trade-offs and implicit in trade-offs is a weighing process
by skilled artisans. Rambus' s evidence and arguments fail to show how
weighing the Lu factors redounds to unobviousness. Lu explicitly states that
"for some systems new functions, better performance, and size reduction can
be achieved by integrating more logic circuits on DRAM chips." (Lu at 98.)
Lu indicates that "high bandwidth[,J capacity" and "cost, reliability and
packaging" must all be considered. (Id. at 99.) Higher cost does not
mandate unobviousness. Faster, smaller, and more durable packages
constitute universal motivators under Dystar. Integrating logic on-chip
creates fewer chips and faster chips based on propagation distance and
simplifies external wiring (reliability) and packaging. As Lu states, "ASIC
DRAMs, adding logic functions on-chip with the memory, provide high
density and high performance .... [since J [dJata processing executed within
one chip eliminates interface loss in speed and power consumption, which
has been existing inevitably in combination of standard DRAMs with basic
common functions and logic parts." (Id.)
Based on the foregoing discussion, Rambus' s new evidence and
arguments do not upset the '623 Board Decision as the Examiner finds.
35
A165
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
advantages. Rambus similarly reasons that artisans would not have
incorporated asynchronous features into synchronous systems and that Lu
does not "unequivocally teach integration oflogic into DRAMs." (Reopen
Req. 29 (citing 3
rd
Supp. Murphy Decl. at     31-32).)
Lu discusses trade-offs and implicit in trade-offs is a weighing process
by skilled artisans. Rambus' s evidence and arguments fail to show how
weighing the Lu factors redounds to unobviousness. Lu explicitly states that
"for some systems new functions, better performance, and size reduction can
be achieved by integrating more logic circuits on DRAM chips." (Lu at 98.)
Lu indicates that "high bandwidth[,J capacity" and "cost, reliability and
packaging" must all be considered. (Id. at 99.) Higher cost does not
mandate unobviousness. Faster, smaller, and more durable packages
constitute universal motivators under Dystar. lntegrating logic on-chip
creates fewer chips and faster chips based on propagation distance and
simplifies external wiring (reliability) and packaging. As Lu states, "ASIC
DRAMs, adding logic functions on-chip with the memory, provide high
density and high performance .... [since J [dJata processing executed within
one chip eliminates interface loss in speed and power consumption, which
has been existing inevitably in combination of standard DRAMs with basic
common functions and logic parts." (Id.)
Based on the foregoing discussion, Rambus' s new evidence and
arguments do not upset the '623 Board Decision as the Examiner finds.
35
Case: 13-1623 Document: 10 Page: 117 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
Farmwald '755 with either ofLu or iRAM
Claims 1-4,6-9,11-13,15,16,18-22, and 24-26
Rambus primarily focuses on independent claim 11, selected to be
representati ve based on the arguments presented, even though independent
claims 1 and 19 are broader than claim 11. Rambus maintains that the
rejection is deficient because the TmcvrRW signal disclosed in Farmwald
'755 does not "cause the memory devices to sample data" as required by the
"strobe signal" recited in the independent claims. (Reopen Req. 31.) As the
'623 Board Decision and the Examiner explain, the TmcvrR W signal
indicates there is valid data on the bus, thereby indicating it is time to sample
the valid data. (See '623 Bd. Dec. 34; Ex. Det. 20.)
The '623 Decision quotes Farmwald '755 as follows:
Persons skilled in the art will recognize that a more
sophisticated transceiver can control transmissions to and from
primary bus units. An additional control line, TrncvrRW can be
bused to all devices on the transceiver bus, using that line in
conjunction with the Addr-Valid line to indicate to all devices
on the transceiver bus that the information on the data lines is:
1) a request packet, 2) valid data to a slave, 3) valid data from a
slave, or 4) invalid data (or idle bus). Using this extra control
line obviates the need for the transceivers to keep track of when
data needs to be forwarded from its primary bus to the
transceiver bus - all transceivers send all data from their
primary bus to the transceiver bus whenever the control signal
indicates the condition 2) above.
(Bd. Dec. 36-37 (quoting Farmwald '755 at col. 21, 11. 35-49) (emphasis
supplied). )
The TmcvrRW signal, as quoted supra, indicates "to all [slave]
devices" that there is "valid data to a slave" and thereby signals the slave
36
A166
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Farmwald '755 with either ofLu or iRAM
Claims 1-4,6-9,11-13,15,16,18-22, and 24-26
Rambus primarily focuses on independent claim 11, selected to be
representati ve based on the arguments presented, even though independent
claims I and 19 are broader than claim II. Rambus maintains that the
rejection is deficient because the TmcvrRW signal disclosed in Farmwald
'755 does not "cause the memory devices to sample data" as required by the
"strobe signal" recited in the independent claims. (Reopen Req. 31.) As the
'623 Board Decision and the Examiner explain, the TmcvrR W signal
indicates there is valid data on the bus, thereby indicating it is time to sample
the valid data. (See '623 Bd. Dec. 34; Ex. Det. 20.)
The '623 Decision quotes Farmwald '755 as follows:
Persons skilled in the art will recognize that a more
sophisticated transceiver can control transmissions to and from
primary bus units. An additional control line, TrncvrRW can be
bused to all devices on the transceiver bus, using that line in
conjunction with the Addr-Valid line to indicate to all devices
on the transceiver bus that the information on the data lines is:
1) a request packet, 2) valid data to a slave, 3) valid data from a
slave, or 4) invalid data (or idle bus). Using this extra control
line obviates the need for the transceivers to keep track of when
data needs to befbrwarded from its primary bus to the
transceiver bus - all transceivers send all data from their
primary bus to the transceiver bus whenever the control signal
indicates the condition 2) above.
(Bd. Dec. 36-37 (quoting Farmwald '755 at col. 21, II. 35-49) (emphasis
supplied).)
The TmcvrRW signal, as quoted supra, indicates "to all [slave]
devices" that there is "valid data to a slave" and thereby signals the slave
36
Case: 13-1623 Document: 10 Page: 118 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
device to sample the data - because the data is valid and ready. As the
passage supra reveals, the TmcvrRW "extra control line obviates the need
for the transceivers to keep track of when data needs to be forwarded."
Tellingly, Rambus's new argument that the TmcvrRW signal in
Rambus's '755 patent does not function as a "strobe signal" as recited in the
independent claims constitutes a pronounced shift from the thrust of
Rambus's original position as presented in its Respondent Brief. Rambus's
arguments originally did not focus on the new allegation here that the
TmcvrRW fails to function as the strobe signal recited in the claims.
Rather, Rambus's central contention addressed in the '623 Board
Decision was that "NVIDIA ... mischaracterizes Farmwald '755 by
claiming' all devices on the bus receive the TmcvrR W signal" (Rambus
Resp. Br. 26) and similarly that "there is no reason one would have modified
a memory device to receive a signal that is specific to a transceiver."
(Rambus Resp. Br. 24.)
In essence, Rambus originally maintained that Farmwald '755 did not
disclose or render obvious sending a TmcvrRW strobe signal to a single chip
memory device or integrating a memory stick which receives that strobe
signal into a single chip. Based on NVIDIA's proposed rejection, Rambus's
contentions, and the Examiner's findings, the Board concentrated the bulk of
the Farmwald' 755 analyses on those paramount issues before it. (See Bd.
Dec. 38-44.)
Rambus's Request to Reopen quotes only the highlighted sentence
below from Rambus' s Respondent Brief, but Rambus relies on that sentence
and maintains that the Respondent Brief shows that Rambus did not concede
that the TmcvrRW signal functions as the claimed strobe signal:
37
A167
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
device to sample the data - because the data is valid and ready. As the
passage supra reveals, the TrncvrRW "extra control line obviates the need
for the transceivers to keep track of when data needs to be forwarded."
Tellingly, Rambus's new argument that the TrncvrRW signal in
Rambus's '755 patent does not function as a "strobe signal" as recited in the
independent claims constitutes a pronounced shift from the thrust of
Rambus's original position as presented in its Respondent Brief. Rambus's
arguments originally did not focus on the new allegation here that the
TrncvrRW fails to function as the strobe signal recited in the claims.
Rather, Rambus's central contention addressed in the '623 Board
Decision was that "NVIDIA ... mischaracterizes Farmwald '755 by
claiming 'all devices on the bus receive the TrncvrRW signal" (Rambus
Resp. Br. 26) and similarly that "there is no reason one would have modified
a memory device to receive a signal that is specific to a transceiver."
(Rambus Resp. Br. 24.)
In essence, Rambus originally maintained that Farmwald '755 did not
disclose or render obvious sending a TrncvrRW strobe signal to a single chip
memory device or integrating a memory stick which receives that strobe
signal into a single chip. Based on NVLDLA's proposed rejection, Rambus's
contentions, and the Examiner's findings, the Board concentrated the bulk of
the Farmwald' 755 analyses on those paramount issues before it. (See Bd.
Dec. 38-44.)
Rambus's Request to Reopen quotes only the highlighted sentence
below from Rambus's Respondent Brief, but Rambus relies on that sentence
and maintains that the Respondent Brief shows that Rambus did not concede
that the TrncvrRW signal functions as the claimed strobe signal:
37
Case: 13-1623 Document: 10 Page: 119 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
Even if the Board considers NVIDIA's argument, it
should affirm the CRU panel on the merits. NVIDIA cites
iRAM for motivating the same combination-moving the
Farmwald transceiver on-chip--argued in issue 8. Here again,
NVIDIA does not rebut the substantial evidence presented to
the CRU showing how Farmwald '755 teaches away from this
combination and how the TrncvrRW does not/unction as the
claimed strobe signal.
(See Response 31 (quoting only the emphasized portion from Rambus Resp.
Br. at 29) (emphasis added by Board).)
Rambus did not explain to the Board in its Respondent Brief why the
TmcvrRW does not function as a strobe signal and did not point the Board
to any rationale or evidence supporting the reason behind the denial. Such a
"naked assertion" amounting to a denial that the Farmwald '755 does not
function as a strobe signal, without explaining why, generally constitutes a
waiver of the argument in typical appeals before the Board. See In re Lovin,
652 F.3d 1349, 1357 (2011).
As opposed to only truncated arguments as involved in In re Lovin,
the thrust of Rambus's position essentially buried the naked assertion and
pointed the Examiner, NVIDIA and the Board in a totally different direction
which required some effort to analyze.
9
As a procedural matter, Rambus's
9 Rambus also refers to its "12/22/09 Response to ACP at 16-19" in an effort
to show that it earlier raised this argument about the function of the
TmcvrRW signal, but that response was not cited in its Respondent Brief
(see Reopen Req. 31), and even if it were, it too concentrates on the same
argument addressed in the '623 Board Decision - i.e., that a single memory
chip in Farmwald '755 would not receive such a TmcvrRW signal.
For example, the "Response to ACP" summary arguments follow:
38
A168
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Even if the Board considers NVIDIA's argument, it
should affirm the CRU panel on the merits. NVIDIA cites
iRAM for motivating the same combination-moving the
Farmwald transceiver on-chip--argued in issue 8. Here again,
NVIDIA does not rebut the substantial evidence presented to
the CRU showing how Farmwald '755 teaches away from this
combination and how the TrncvrRW does not/unction as the
claimed strobe signal.
(See Response 31 (quoting only the emphasized portion from Rambus Resp.
Br. at 29) (emphasis added by Board).)
Rambus did not explain to the Board in its Respondent Brief why the
TrncvrRW does not function as a strobe signal and did not point the Board
to any rationale or evidence supporting the reason behind the denial. Such a
"naked assertion" amounting to a denial that the Fannwald '755 does not
function as a strobe signal, without explaining why, generally constitutes a
waiver of the argument in typical appeals before the Board. See In re Lovin,
652 F.3d 1349, 1357 (2011).
As opposed to only truncated arguments as involved in In re Lovin,
the thrust of Rambus's position essentially buried the naked assertion and
pointed the Examiner, NVTDTA and the Board in a totally different direction
which required some effort to analyze.
9
As a procedural matter, Rambus's
9 Rambus also refers to its" 12/22/09 Response to ACP at 16-19" in an effort
to show that it earlier raised this argument about the function of the
TrncvrRW signal, but that response was not cited in its Respondent Brief
(see Reopen Req. 31), and even if it were, it too concentrates on the same
argument addressed in the '623 Board Decision - i.e., that a single memory
chip in Farmwald '755 would not receive such a TrncvrRW signal.
For example, the "Response to ACP" summary arguments follow:
38
Case: 13-1623 Document: 10 Page: 120 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
new evidence and arguments about the function of the TmcvrR W function
fail to respond to the thrust of the new ground ofrejection which
concentrated on the use of the TmcvrR W signal in a single chip device. As
such, Rambus's new position does not appear to be proper procedurally
because it is not responsive to the thrust of the new grounds ofrejection. But
Rambus's new argument is made on remand before the Examiner and
involves the same claim element in dispute prior to remand, the TmcvrRW
signal, a situation not involved in In re Lovin. To avoid procedural pitfalls,
the Board considers Rambus's new argument. See Rexnord Industries, LLC
v. Kappas and Habasit Belting, Inc. No. 2011-1434 (Fed. Circ. Jan. 23,
2013) (holding that prior consistent positions in the record by an appellee in
a reexamination proceeding are not waived and must be considered),
http://www.ipo.org/AM/Template.cfm?Section=Federal_Circuit_Opinions
&ContentID=3 5 527 &template=ICM/ContentDisplay.cfm.
Rambus's new evidence and arguments do not support this shifted
argument. For example, Rambus argues that the '353 patent disclosure
implies a "'data transfer start information'" requirement in claim 11, but
Rambus does not explain how that disclosure limits further the recited
requirement in claim 11 for the "strobe signal to initiate sampling" and why
In teaching these non-transceiver device [i.e., single chip]
systems, the TmcvrRW or any equivalent signal is never used.
Therefore, a person of skill in the art would understand that the
'755 patent teaches away from using such a signal, except in
combination with a transceiver device that connects to a
transceiver bus on one end and a primary bus on the other end.
(Response to ACP at 19 (Dec. 22,2009).)
39
A169
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
new evidence and arguments about thejimctian of the TmcvrRW function
fail to respond to the thrust of the new ground of rejection which
concentrated on the use of the T mcvrR W signal in a single chip device. As
such, Rambus's new position does not appear to be proper procedurally
because it is not responsive to the thrust of the new grounds of rejection. But
Rambus's new argument is made on remand before the Examiner and
involves the same claim element in dispute prior to remand, the TmcvrRW
signal, a situation not involved in In re Lavin. To avoid procedural pitfalls,
the Board considers Rambus's new argument. See Rexnard Industries, LLC
v. Kappas and Habasit Belting, Inc. No. 2011-1434 (Fed. Circ. Jan. 23,
2013) (holding that prior consistent positions in the record by an appellee in
a reexamination proceeding are not waived and must be considered),
http://www.ipo.org/AM/Template.cfm?Section=FederaLCircuiCOpinions
&ContentID=3 5527 &template=ICM/ContentDisplay. cfm.
Rambus's new evidence and arguments do not support this shifted
argument. For example, Rambus argues that the '353 patent disclosure
implies a '" data transfer start information '" requirement in claim 11, but
Rambus does not explain how that disclosure limits further the recited
requirement in claim 11 for the "strobe signal to initiate sampling" and why
In teaching these non-transceiver device [i.e., single chip]
systems, the TmcvrRW or any equivalent signal is never used.
Therefore, a person of skill in the art would understand that the
'755 patent teaches away from using such a signal, except in
combination with a transceiver device that connects to a
transceiver bus on one end and a primary bus on the other end.
(Response to ACP at 19 (Dec. 22,2009).)
39
Case: 13-1623 Document: 10 Page: 121 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
that type of information, if it is imputed to be a claim limitation,
distinguishes over the '755 Farmwald TrncvrRW signal. (See Reopen Req.
31 (quoting '353 patent, col. 8,1. 61).) A similar argument is addressed
supra in the section discussing anticipation by Hayes. As discussed, column
8 does not describe sampling which claim 11 requires. Rather, it describes
transmitting data from a memory device at two different delay times after
the strobe signal and indicates that transmitting times relative to the strobe
are governed by something other than the disclosed data strobe. Hence, it is
not clear how the passage even applies to sampling or how it limits it even if
it does apply. The TrncvrRW signal logically contains "data transfer start
information" since it indicates valid data to a slave after which the memory
device begins to sample the data.
In a related finding, the '623 Board Decision finds that "the '353
patent describes a delay between the strobe signal and sampling" and that
"Rambus corroborates NVIDIA's point and describes a similar delay
between the data and the strobe." (See '623 Bd. Dec. at 22; P.O. Cr. App.
Br. 10; Req. Resp. Br. 12.) Rambus does not challenge this finding or
explain how the disclosed start information at column 8 upsets it. As
discussed, some delay in clock cycles not defined by the strobe signal occurs
between sampling and the strobe signal as disclosed and claimed in the '353
patent. In light of this unchallenged delay between the strobe signal and
sampling, Rambus fails to demonstrate how the TrncvrRW signal (like the
Hayes DS), as construed here, is inconsistent with the '353 Patent
Specification's strobe signal.
Also, Parris's testimony supports the Board and directly contradicts
Rambus: "[T]he TrncvrRW signal does indeed indicate when the memory
40
A170
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
that type of information, if it is imputed to be a claim limitation,
distinguishes over the '755 Farmwald TrncvrRW signal. (See Reopen Req.
31 (quoting '353 patent, col. 8,1. 61).) A similar argument is addressed
supra in the section discussing anticipation by Hayes. As discussed, column
8 does not describe sampling which claim 11 requires. Rather, it describes
transmitting data from a memory device at two different delay times after
the strobe signal and indicates that transmitting times relative to the strobe
are governed by something other than the disclosed data strobe. Hence, it is
not clear how the passage even applies to sampling or how it limits it even if
it does apply. The TrncvrRW signal logically contains "data transfer start
information" since it indicates valid data to a slave after which the memory
device begins to sample the data.
In a related finding, the '623 Board Decision finds that "the '353
patent describes a delay between the strobe signal and sampling" and that
"Rambus corroborates NVIDIA's point and describes a similar delay
between the data and the strobe." (See '623 Bd. Dec. at 22; P.O. Cr. App.
Br. 10; Req. Resp. Br. 12.) Rambus does not challenge this finding or
explain how the disclosed start information at column 8 upsets it. As
discussed, some delay in clock cycles not defined by the strobe signal occurs
between sampling and the strobe signal as disclosed and claimed in the '353
patent. In light of this unchallenged delay between the strobe signal and
sampling, Rambus fails to demonstrate how the TrncvrR W signal (like the
Hayes DS), as construed here, is inconsistent with the '353 Patent
Specification's strobe signal.
Also, Parris's testimony supports the Board and directly contradicts
Rambus: "[T]he TrncvrRW signal does indeed indicate when the memory
40
Case: 13-1623 Document: 10 Page: 122 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
device is to begin sampling write data." (Parris Decl. ,-r 11 (explaining, inter
alia, that "[t]he slave should not, and will not, begin sampling write data
until the data is valid.").) Rambus fails to present persuasive evidence
rebutting Parris's testimony or the evidence in Farmwald '755 relied upon
by the Board and the Examiner. Murphy testifies that because the
"TrncvrRW signal indicates whether a transceiver should forward data," the
signal would not be sent to a memory device "since the memory device does
not make the forwarding decisions that are made by a transceiver." (3
rd
Supp. Murphy Decl. at,-r 35.io Murphy's testimony focuses on whether the
TrncvrRW signal is sent to a single chip and does not squarely address the
function of the signal. It also seemingly contradicts, without a supporting
explanation, the un-rebutted fact, discussed further below, that "all devices"
(including memory devices) on the transceiver bus receive the TrncvrRW
signal (i.e., not just memory stick devices with transceivers thereon) to
indicate valid data to a slave device. 11
10 Rambus also argues that "the purpose of the TrncvrRW signal is to allow
the transceiver to decide whether to forward data from the transceiver bus to
the primary bus." (Reopen Req. 31.) An interface on a DRAM chip
obviously can serve the same function. Rambus also notes that the signal
indicates forwarding data the other way - from the primary bus to the
transceiver bus. (See id.) The Board agrees with Rambus that the TrncvrRW
signal logically indicates to a slave to send or receive data both ways - i.e.,
depending on if a read or write is being performed.
11 The memory stick, or primary bus unit, includes a transceiver device 19
and one or more memory chip devices. (See Reopen Req. 30 (annotating
Fig. 9 of the '755 patent and showing the memory stick and external
transceiver bus); '623 Bd. Dec. 35 (FW6), 40.)
41
A171
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
device is to begin sampling write data." (Parris Dec!.   11 (explaining, inter
alia, that "[t]he slave should not, and will not, begin sampling write data
until the data is valid.").) Rambus fails to present persuasive evidence
rebutting Parris's testimony or the evidence in Fannwald '755 relied upon
by the Board and the Examiner. Murphy testifies that because the
"TrncvrRW signal indicates whether a transceiver should forward data," the
signal would not be sent to a memory device "since the memory device does
not make the forwarding decisions that are made by a transceiver." (3
n1
Supp. Murphy Decl. at   35.io Murphy's testimony focuses on whether the
TrncvrRW signal is sent to a single chip and does not squarely address the
function of the signal. It also seemingly contradicts, without a supporting
explanation, the un-rebutted fact, discussed further below, that "all devices"
(including memory devices) on the transceiver bus receive the TrncvrR W
signal (i.e., not just memory stick devices with transceivers thereon) to
indicate valid data to a slave device. 11
10 Rambus also argues that "the purpose of the TrncvrRW signal is to allow
the transceiver to decide whether to forward data from the transceiver bus to
the primary bus." (Reopen Req. 3 1.) An interface on a DRAM chip
obviously can serve the same function. Rambus also notes that the signal
indicates forwarding data the other way - from the primary bus to the
transceiver bus. (See id.) The Board agrees with Rambus that the TrncvrRW
signal logically indicates to a slave to send or receive data both ways - i.e.,
depending on if a read or write is being performed.
11 The memory stick, or primary bus unit, includes a transceiver device 19
and one or more memory chip devices. (See Reopen Req. 30 (annotating
Fig. 9 of the '755 patent and showing the memory stick and external
transceiver bus); '623 Bd. Dec. 35 (FW6), 40.)
41
Case: 13-1623 Document: 10 Page: 123 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
Rambus does not direct attention to another signal in its '755
Farmwald patent which would cause data sampling and which occurs after
the TmcvrRW signal. Rambus does not maintain that data sampling does
not occur after the TmcvrRW signal as Parris's testimony shows. (Parris
Decl. ,-r 11.) As such, Rambus fails to define to a patentable distinction
between the two signals. Even if the TmcvrR W signal somehow does not
constitute a strobe signal, using it as such a signal to tell the memory device
to start sampling because the data is valid would have been obvious for the
reasons noted- i.e., the data is ready to be sampled.
Rambus's new thrust about the TmcvrRW functionality may have
been in anticipation of the later-decided controlling precedent, In re Rambus
(supra note 5), holding that the term "memory device" in the family of
Rambus's patents is a generic term that embraces memory board devices and
memory chip devices. However, this rejection was not proposed in
NVIDIA's original inter partes request and the Board did not propose it as a
new ground. 12
12 Also, In re Rambus indicates that a portion of the Board's underlying
analysis in that case was "incorrect" for" equating the multichip 'memory
stick' with a' memory device, '" but the court held that "this does not mean
that a memory device must contain only one chip." 694 F.3d at 47
(emphasis added). The court held that a "'memory device' is a broad term
which has been used consistently in the '918 patent and in the family of
patents related to it to encompass a device having one or more chips." Id. at
48 (emphasis added). Hence, while the court found that "a memory device
and a memory stick are [not equated or not] the same," see id. at 47, since a
memory device includes multiple chips and includes the prior art "iAPX
Manual's memory module, which contains several chips and a controller that
provides the logic for those chips to function," id. at 50, it appears that the
42
A172
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
Rambus does not direct attention to another signal in its '755
Farmwald patent which would cause data sampling and which occurs after
the TmcvrRW signal. Rambus does not maintain that data sampling does
not occur after the TmcvrRW signal as Parris's testimony shows. (Parris
Dec!.   11.) As such, Rambus fails to define to a patentable distinction
between the two signals. Even if the TmcvrRW signal somehow does not
constitute a strobe signal, using it as such a signal to tell the memory device
to start sampling because the data is valid would have been obvious for the
reasons noted- i.e., the data is ready to be sampled.
Rambus's new thrust about the TmcvrRW functionality may have
been in anticipation of the later-decided controlling precedent, In re Rambus
(supra note 5), holding that the tenn "memory device" in the family of
Rambus's patents is a generic term that embraces memory board devices and
memory chip devices. However, this rejection was not proposed in
NVIDIA's original inter partes request and the Board did not propose it as a
new ground. 12
12 Also, In re Rambus indicates that a portion of the Board's underlying
analysis in that case was "incorrect" for "equating the multi chip 'memory
stick' with a' memory device, ,,, but the court held that "this does not mean
that a memory device must contain only one chip." 694 F.3d at 47
(emphasis added). The court held that a "'memory device' is a broad term
which has been used consistently in the '918 patent and in the family of
patents related to it to encompass a device having one or more chips." Id. at
48 (emphasis added). Hence, while the court found that "a memory device
and a memory stick are [not equated or not] the same," see id. at 47, since a
memory device includes multiple chips and includes the prior art "iAPX
Manual's memory module, which contains several chips and a controller that
provides the logic for those chips to function," id. at 50, it appears that the
42
Case: 13-1623 Document: 10 Page: 124 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
The TrncvrRW signal in Farmwald '755 is sent to all memory devices
(i.e., including single chip memory devices) on the external (i.e., transceiver)
bus as the Board finds. ('623 Bd. Dec. 39-40.) For example, as the '755
patent states, "'[a]n additional control line, TrncvrRW can be bussed to all
devices on the transceiver bus.'" ('623 Bd. Dec. 36 (quoting Farmwald '755
at col. 21, 11. 37-39).) The '755 patent also describes "'memory devices on
the transceiver bus as well as on primary bus units.'" (See '623 Bd. Dec. 36,
39 (quoting '755 Farmwald at col. 21, 11. 6-7 (emphasis added).)
Rambus now virtually concedes this point, contrary to its earlier
Respondent Briefposition. For example, Rambus now states that the
TrncvrRW signal "can be bused to all devices on the transceiver bus.
Nothing in the specification suggests that the TrncvrRW signal is also sent
to devices on the primary bus." (Reopen Req. 33 n.l 0 quoting Farmwald
'755 at col. 21, 11.37-39 (first emphasis by Board).) Rambus's second
quoted sentence sets up a straw man. The primary bus on the memory stick
generic term "memory device" also includes the two disclosed species - i.e.,
the memory stick device and a memory chip device - even though they are
not "the same" species. Alternatively, perhaps the court carved out an
exception from the broad reach of the term "memory device" so that it
somehow includes everything from a broad prior art memory board to a
narrow single chip memory device except the intermediate memory stick.
See id. at 48 ("the specification could not be clearer that the disclosed
invention can be practiced with either a memory device or with a memory
stick.") If so, the court did not have benefit of the explicit finding by the
Board in the '623 Board Decision and concession by Rambus here that the
TrncvrRW signal is bussed to all memory devices on the transceiver bus
(i.e., to memory stick devices and memory chip devices on that bus). (See
'623 Bd.Dec. 39.)
43
A173
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
The TrncvrRW signal in Farmwald '755 is sent to all mem01Y devices
(i.e., including single chip memory devices) on the external (i.e., transceiver)
bus as the Board finds. ('623 Bd. Dec. 39-40.) For example, as the '755
patent states, "'[a]n additional control line, TrncvrRW can be bussed to all
devices on the transceiver bus. '" ('623 Bd. Dec. 36 (quoting Farmwald '755
at col. 21, 11. 37-39).) The '755 patent also describes "'memory devices on
the transceiver bus as well as on primary bus units.'" (See '623 Bd. Dec. 36,
39 (quoting '755 Farmwald at col. 21, 11. 6-7 (emphasis added).)
Rambus now virtually concedes this point, contrary to its earlier
Respondent Brief position. For example, Rambus now states that the
TrncvrRW signal "can be bused to all devices on the transceiver bus.
Nothing in the specification suggests that the TmcvrRW signal is also sent
to devices on the primary bus." (Reopen Req. 33 n.l 0 quoting Farmwald
'755 at col. 21, 11.37-39 (first emphasis by Board).) Rambus's second
quoted sentence sets up a straw man. The primalY bus on the memory stick
generic term "memory device" also includes the two disclosed species - i.e.,
the memory stick device and a memory chip device - even though they are
not "the same" species. Alternatively, perhaps the court carved out an
exception from the broad reach of the term "memory device" so that it
somehow includes everything from a broad prior art memory board to a
narrow single chip memory device except the intermediate memory stick.
See id. at 48 ("the specification could not be clearer that the disclosed
invention can be practiced with either a memory device or with a memory
stick.") If so, the court did not have benefIt of the explicit fInding by the
Board in the '623 Board Decision and concession by Rambus here that the
TmcvrRW signal is bussed to all memory devices on the transceiver bus
(i.e., to memory stick devices and memory chip devices on that bus). (See
'623 Bd.Dec. 39.)
43
Case: 13-1623 Document: 10 Page: 125 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
has nothing to do with the Board's rejection or Rambus's concession. All
devices, including single chip memory devices, disclosed in the '755 patent
as residing on the external transceiver bus, receive the TrncvrR W signal. As
the '623 Board Decision explains, and as Rambus depicts (see Reopen Req.
30), the transceiver bus is the bus external to the memory stick and that bus
has memory sticks and other memory devices attached to it. (See note 11.)
Rambus similarly concedes the point that the TrncvrRW signal goes
to all memory devices in another argument. "Because it [the TrncvrRW
signal] does not indicate to which memory device data being transmitted is
intended to be written and is provided to all devices on the transceiver bus,
TrncvrRW cannot be considered to indicate to a memory device to initiate
sampling." (Reopen Req. 31 (emphasis supplied).)
Rambus concession quoted supra imbeds an unclear argument which
is difficult to address, but Rambus appears to be taking the untenable and
immaterial position that each "memory device" disclosed in its '755
Farmwald patent cannot determine from the TrncvrRW signal that it is being
addressed by a controller for a data transfer. This argument is a red herring
because the Board does not assert that the TrncvrRW signal includes address
information and the claims do not require it. Perhaps Rambus implies that
the TrncvrRW signal goes to all slave memory devices on the transceiver
bus as a broadcast signal. (See e.g. '353 patent, col. 16, 1. 49 et seq.
(discussing broadcast data).) If so, claims 1, 11, and 19 do not preclude all
the memory devices on the '755 Farmwald transceiver bus from sampling
the data on the bus in response to the TrncvrR W strobe signal.
Assuming for the sake of argument that Farmwald' 755 only discloses
that the TrncvrRW goes to a transceiver chip on a memory stick to indicate
44
A174
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
has nothing to do with the Board's rejection or Rambus's concession. All
devices, including single chip memory devices, disclosed in the '755 patent
as residing on the external transceiver bus, receive the TrncvrR W signal. As
the '623 Board Decision explains, and as Rambus depicts (see Reopen Req.
30), the transceiver bus is the bus external to the memory stick and that bus
has memory sticks and other memory devices attached to it. (See note 11.)
Rambus similarly concedes the point that the TmcvrRW signal goes
to all memory devices in another argument. "Because it [the TmcvrRW
signal] does not indicate to which mem01Y device data being transmitted is
intended to be written and is provided to all devices on the transceiver bus,
TmcvrRW cannot be considered to indicate to a memory device to initiate
sampling." (Reopen Req. 31 (emphasis supplied).)
Rambus concession quoted supra imbeds an unclear argument which
is difficult to address, but Rambus appears to be taking the untenable and
immaterial position that each "memory device" disclosed in its '755
Farmwald patent cannot determine from the TmcvrRW signal that it is being
addressed by a controller for a data transfer. This argument is a red herring
because the Board does not assert that the TrncvrRW signal includes address
information and the claims do not require it. Perhaps Rambus implies that
the TmcvrRW signal goes to all slave memory devices on the transceiver
bus as a broadcast signal. (See e.g. '353 patent, col. 16,1. 49 et seq.
(discussing broadcast data).) If so, claims 1, 11, and 19 do not preclude all
the memory devices on the '755 Fannwald transceiver bus from sampling
the data on the bus in response to the TmcvrRW strobe signal.
Assuming for the sake of argument that Farmwald' 755 only discloses
that the TmcvrR W goes to a transceiver chip on a memory stick to indicate
44
Case: 13-1623 Document: 10 Page: 126 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
valid data to that slave memory stick device, as the Decision and the
Examiner explain at length, the prior art combination, which includes
Farmwald '755 with either ofLu or iRAM, renders obvious modifying the
stick by integrating its simple functionality into a single chip memory device
having a transceiver interface. An obvious purpose would have been that
receiving a TmcvrRW signal or a similar strobe signal (assuming arguendo
that the TmcvrR W signal does not satisfy the strobe signal limitation for
some reason) in a smaller and faster device such as a single chip would have
informed the fast chip when to sample data since the TmcvrRW signal tells
all slave memory devices that there is "2) valid data to a slave" (quoted
supra from '755 Farmwald). (See Ex. Det. 22-24; Bd. Dec. 38-45.) As an
example of further rationale for creating a single chip out of two chips, aside
from the beneficial reduction in chip number, the Board reasons that
Farmwald '755 specifically teaches that "'each teaching of this invention
which refers to a memory device can be practiced using a [memory stick -
i.e., a] transceiver device and one or more memory devices. '" (Bd. Dec. 36,
40 (FW7 quoting '755 Farmwald at col. 21, 11. 7-10).)
The Examiner's responses to Rambus, which rely on the '623 Board
Decision, persuasively rebut Rambus's remaining arguments, add additional
supporting facts and rationale, and are adopted and incorporated by
reference as indicated at the outset. (See Ex. Det. 18-24.) For example,
Murphy opines that combining a DRAM with a transceiver would make the
DRAM chip bigger and hence slower than a normal DRAM chip, thereby
defeating one rationale for obviousness. (See 3
rd
Supp. Murphy Decl. at ,-r
36.) However, that rebuttal compares the wrong devices, two chips, instead
of a chip and a memory stick. A single chip memory integrated with a
45
A175
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
valid data to that slave memory stick device, as the Decision and the
Examiner explain at length, the prior art combination, which includes
Fannwald '755 with either ofLu or iRAM, renders obvious modifying the
stick by integrating its simple functionality into a single chip memory device
having a transceiver interface. An obvious purpose would have been that
receiving a TmcvrRW signal or a similar strobe signal (assuming arguendo
that the TmcvrR W signal does not satisfy the strobe signal limitation for
some reason) in a smaller and faster device such as a single chip would have
informed the fast chip when to sample data since the TmcvrRW signal tells
all slave memory devices that there is "2) valid data to a slave" (quoted
supra from '755 Farmwald). (See Ex. Det. 22-24; Bd. Dec. 38-45.) As an
example of further rationale for creating a single chip out of two chips, aside
from the beneficial reduction in chip number, the Board reasons that
Fannwald '755 specifically teaches that '''each teaching of this invention
which refers to a memory device can be practiced using a [memory stick -
i.e., a] transceiver device and one or more memory devices. '" (Bd. Dec. 36,
40 (FW7 quoting '755 Fannwald at col. 21, 11. 7-10).)
The Examiner's responses to Rambus, which rely on the '623 Board
Decision, persuasively rebut Rambus's remaining arguments, add additional
supporting facts and rationale, and are adopted and incorporated by
reference as indicated at the outset. (See Ex. Det. 18-24.) For example,
Murphy opines that combining a DRAM with a transceiver would make the
DRAM chip bigger and hence slower than a nonnal DRAM chip, thereby
defeating one rationale for obviousness. (See 3
rd
Supp. Murphy Decl. at  
36.) However, that rebuttal compares the wrong devices, two chips, instead
of a chip and a memory stick. A single chip memory integrated with a
45
Case: 13-1623 Document: 10 Page: 127 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
beneficial transceiver interface would be smaller and faster than the
Farmwald '755 multi-chip memory stick. A memory stick is "quite simple
in function" ('755 Farmwald, col. 21, 1. 18) and encompasses as few as two
chips, a memory chip, and a transceiver chip which functions as a simple
interface to the bus for the memory chip, further suggesting integration
thereof. (See '755 patent col. 211. 18-24; Ex. Det. 23-24; '623 Bd. Dec. 41-
45.)
Pursuant to the foregoing discussion, Rambus' s evidence and
arguments do not support altering the '623 Decision and the Examiner's
Determination that claims 1-4, 6-9, 11-13, 15, 16, 18-22, and 24-26 based
on Farmwald '755 and Lu or iRAM would have been obvious.
DECISION
Rambus has not shown that the Board's Decision, BPAI2011-
010623, requires a modification with respect to the affirmance of claims 1,
5,7, 11, 14, 19, and 23 as anticipated based on Hayes.
Rambus also has not shown that Board's Decision, BPAI2011-
010623, requires a modification with respect to altering the underlying
holding that the new grounds of rejection listed supra render claims 1-26
obvious.
Requests for extensions of time, if available in this inter partes
reexamination proceeding, are governed by 37 C.F.R. § 1.956. See 37
C.F.R. §§ 41.77 and 41.79.
REHEARING RELIEF DENIED and DECISION UNMODIFIED
46
A176
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 Bl
beneficial transceiver interface would be smaller and faster than the
Farmwald '755 multi-chip memory stick. A memory stick is "quite simple
in function" ('755 Fannwald, col. 21, 1. 18) and encompasses as few as two
chips, a memory chip, and a transceiver chip which functions as a simple
interface to the bus for the memory chip, further suggesting integration
thereof (See '755 patent col. 211. 18-24; Ex. Det. 23-24; '623 Bd. Dec. 41-
45.)
Pursuant to the foregoing discussion, Rambus' s evidence and
arguments do not support altering the '623 Decision and the Examiner's
Determination that claims 1-4, 6-9, 11-13, 15, 16, 18-22, and 24-26 based
on Farmwald '755 and Lu or iRAM would have been obvious.
DECISION
Rambus has not shown that the Board's Decision, BP Al 20 11-
010623, requires a modification with respect to the affirmance of claims 1,
5,7, 11, 14, 19, and 23 as anticipated based on Hayes.
Rambus also has not shown that Board's Decision, BP AI 2011-
010623, requires a modification with respect to altering the underlying
holding that the new grounds of rejection llsted supra render claims 1-26
obvious.
Requests for extensions of time, if available in this inter partes
reexamination proceeding, are governed by 37 C.F.R. § 1.956. See 37
C.F.R. §§ 41.77 and 41.79.
REHEARING RELIEF DENIED and DECISION UNMODIFIED
46
Case: 13-1623 Document: 10 Page: 128 Filed: 11/04/2013
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 B 1
PATENT OWNER:
FINNEGAN, HENDERSON, FARABOW,
GARRETT & DUNNER LLP
901 New York Avenue, NW
Washington, DC 20001-4413
Ib
47
A177
Appeal 2013-000562
Reexamination Control 95/001,169
Patent 6,591,353 BI
PATENT OWNER:
FINNEGAN, HENDERSON, FARABOW,
GARRETT & DUNNER LLP
901 New Y ork Avenue, NW
Washington, DC 20001-4413
Ib
47
Case: 13-1623 Document: 10 Page: 129 Filed: 11/04/2013
A186
(12) United States Patent
Harth et al.
(54) PROTOCOL FOR COMMUNICATION WITH
DYNAMIC MEMORY
(75) Inventors: Richard Maurice Barth, Palo Alto, CA
(US); Frederick Abbot Ware, Los
Altos Hills, CA (US); John Bradly
Dillon, Palo Alto, CA (US); Donald
Charles Stark, Woodside, CA (US);
Craig Edward Hampel, San Jose, CA
(US); Matthew Murdy Griffin,
Mountain View, CA (US)
(73) Assignee: Rambus Inc" Los Altos, CA (US)
(*) Notice: Subject to any disclaimer, the term of this
patent is extended or adjusted under 35
U.S.c. 154(b) by 0 days.
This patent is subject to a terminal dis-
claimer.
(21) App!. No.: 09/561,868
(22) Filed: May 1, 2000
Related U.S. Application Data
(60) Continuation of application No. 09/480,767, filed on Jan. 10.
2000, which is a continuation of application No. 08/979,402,
filed on Nov. 26, 1997, which i, 3 divi,ion of application No.
08/545,292, filed on Oct. 19, 1995, now Pat. No. 5,748,914.
(51) Int. CI.7 ................................................ G06F 12/00
(52) U.S. CI. ........................ 711/167; 710/100; 710/107
(58) Field of Search ................................. 710/100-107;
711/167
(56) References Cited
U.S. PATENT DOCUMENTS
3,950,735 A 4/1976 Patel
4,183,095 A 1/1980 Ward
4,315,308 A 2/1982 Jackson
4,330,852 A 5/1982 Redwine et a1.
4,337,523 A 6/1982 Hotta et a1.
4,445.204 A 4/1984 Nishiguchi
111111111111111111111111111111111111111111111111111111111111111111111111111
EP
EP
USUU6591353B 1
(10) Patent No.: US 6,591,353 Bl
* J ul. 8, 2003 (45) Date of Patent:
4,499,536 A
4,037,01il A
4,040,270 A
4,712,190 A
2/1985 Gemma et a1.
1/19il7 Flora et a1.
2/19il7 Voss
12/1987 Gllgliemi et 31.
(List continued on next page.)
FOREIGN PATENT DOCUMENTS
0339224
o 561 370
11/1989
3/1993
(List continued on next page.)
OTHER PUBLICATIONS
Mosys, "MD904 to MD920, Multibank DRAM (MDRAM)
128Kx32 to 656Kx32" Datasheet, Document DS01-2.1,
MoSys Inc. California, Dec. 18, 1995, pp. 1-14.
(List continued on next page.)
{'rimary h;xaminer--David Wiley
Assistant Examiner---George Neurauter
(57) ABSTRACT
A system and method for performing data transfers within a
computer system is provided. The system includes a con-
troller configured to dynamically acljust the interleave of the
communications required to perform a series of data transfer
operations to maximize utilization of the channel over which
the communications are to be performed. The controller is
able to vary the time interval between the transmission of
control iniormation that requests a data transfer and the
performance of the data transfer by signaling the beginning
of the data transfer with a strobe signal sent separate from
the control information. TIle controller is able to defer the
determination of how much data will be transferred in the
operation by initiating the termination of a data transfer with
a termination signa!. The method provides a technique for
distinguishing between identical control signals that are
carried on the same line. The system includes a memory
device with control circuitry that allows no more than one
memory bank powered by any given power supply line to
perform sense or precharge operations.
26 Claims, 21 Drawing Sheets
E
FA\SM,T I
CCNTROL.lNE
I::::
I.RANSMIT CONTROL
I INr')H/ATION eN TII= DU:; CONTRJL
L  
,------_ _
__ __
Case: 13-1623 Document: 10 Page: 130 Filed: 11/04/2013
A187
EP
FR
JP
JP
JP
U.S. PATENT DOCUMENTS
1/1988
7/1988
8/1988
12/1988
12/1988
1/1989
1/1989
4/1989
4/1989
7/1989
7/1989
7/1989
9/1989
10/1989
11/1989
111990
4/1990
4/1990
5/1990
6/1990
7/1990
8/1990
3/1991
12/1991
1/1992
5/1992
6/1992
8/1992
1/1993
Hag et al.
Glier
Bomba et al.
Roberts
Redwine et al.
Scales, III et al.
Hoh et al.
Christopher et al.
Hamano
Aichelmann, Jr. et al.
Chappell et al.
Yoshimoto
Kawashima
Matsumoto
Ohno ct al.
Iijima
Suzuki et al.
Pogue et al.
IIiguchi et al.
Bechtolsheim
Kashiyama
Kawai et al.
Ebbers et a1.
Hardee et al.
Hara et a1.
Fujishima et al.
Shiomi et al.
White el al.
Hidaka el al.
Mori
US 6,591,353 HI
Page 2
JP
JP
JP
JP
JP
JP
SIlO 62-16289
SIlO 63-217452
SHO 1-236494
SHO 63-34795
SHO 63-91766
SHO 63-239676
1/1987
3/1987
9/191l7
2/191l1l
4/1988
10/1988
OTHER PUBLICATIONS
Minutes of meeting and presentations made at JC-42.3
Committee on RAM Memories, Meeting No. 59 Sep. 18,
1991 Philadelphia.
Minutes of meeting and presentations made at JC-42.3
Committee on RAM Memories, Meeting No. 58 May 9,
1991 Anchorage AK.
Minutes of meeting and presentations made at JC-42.3
Committee on RAM Memories, Meeting No. Ii') Dec. 9-10,
1992 Ft Lauderdale, FL.
Minutes of meeting and presentations made at JC-42.3
Committee on RAM Memories, Meeting No. 64 Sep.16-17,
1992 Crystal City, VA
Minutes of meeting and presentations made at JC-42.3
Committee on RAM Memories, Meeting No. 66 Mar. 3-4,
1993 Scottsdale AZ.
Minutes of meeting and presentations made at JC-42.3
Committee on RAM Memories, Meeting No. 72 Sep. 13,
1994 Alhuquerque NM.
4,719,602 A
4,755,937 A
4,763,249 A
4,792,926 A
4,792,929 A
4,799,199 A
4,800,530 A
4,821,226 A
4,825,411 A
4,845,664 A
4,845,677 A
4,849.937 A
4,866.675 A
4,875,192 A
4,882,712 A
4,891,791 A
4,916,670 A
4,920,483 A
4,928,265 A
4,937,734 A
4,945,516 A
4,953,128 A
5,001,672 A
5,077,693 A
5,OIl3,296 A
5,111,386 A
5,124,589 A
5,140,688 A
5,179,687 A
5,260,905 A
5,276,858 A *
5,301,278 A
5,305,278 A
5,311,483 A
5,319,755 A
5,323,358 A
5,327,390 A
5,339,276 A
5,341,341 A
5,345,573 A
5,365,489 A
5,381.376 A
5,381,538 A
5,384.745 A
5,386385 A
5,390,149 A
5,392,239 A
5,404,338 A
5,404,463 A
5,444,667 A
5,455,803 A
5,504,874 A
5,533,204 A
5,548,786 A
5,553,248 A
5,611,058 A
5,(,31l,531 A
5,M9,1()1 A
5,655,113 A
5,748,914 A *
5,778,419 A
6,065,092 A
11/1993
1/1994
4/1994
4/1994
5/1994
6/1994
6/1994
7/1994
8/1994
8/1994
9/1994
Oak et al. .................. 711/167
Minutes of meeting and presentations made at JC-42.3
Committee on RAM Memories, Meeting No. 75 May 24,
1995 New Orleans.
11/1994
1/1995
1/1995
1/1995
1/1995
2/1995
2/1995
4/1995
4/1995
8/1995
10/1995
4/1996
7/1996
8/1996
9/1996
3/1997
()/1997
7/1997
8/1997
5/1998
7/1998
5/2000
Bowater et al.
Inoue
Takasugi
Farmwald et al.
Toda et al.
Takasugi
Takasugi
Fukuzo
Bowden, III et al.
Jeong
Kim et al.
Amini et al.
Konishi et al.
Stephens, Jr.
Vogley et al.
Margulis ct al.
Murai ct al.
McGarvey
Obara
Kodama
Galles et al.
Tipley
Amini et al.
Melo et al.
Moore et al.
Crump et a1.
Andrade et a1.
Leung el al.
Barth et al.
Hansen el al.
Roy
FOREJ('N PArENT DOCUMENTS
0535670
2695227
SHO 58-192154
SHO 61-107453
SHO 61-160556
4/1993
3/1994
11/1983
5/1986
10/1986
710/105
Minutes of meeting and presentations made at JC-42.3
Committee on RAM Memories, Meeting No. 76 Sep. 11,
1995 Crystal City, VA
Minutes of meeting and presentations made at JC-42.3
Committee on RAM Memories, Jan. 17, 1995, San Jose CA
Knut Alnes, "Scalable Coherent Interface",
SCI-Feb89-doc52, (To appear in Eurobus Conference Pro-
ceedings May 1989) pp. 1-8.
Hansen et aI., "A RISC Microprocessor with Integral MMU
and Cache Interface", MIPS Computer Systems, Sunnyvale,
CA, IEEE 1986 pp 145-148.
Moussouris et aI., "A CMOS Processor with Integrated
Systems runctions", MIPS Computer Systems, Sunnyvale,
CA, IEEE 1986 pp 126-130.
"1989 GaAs IC Data Book & Designer's Guide", Aug. 1989,
Gigabit Logic Inc.
"ICs for Entertainment Electronics Picture-in-Picture Sys-
tem Edition 8.89", Siemens AG, 1989.
"High Speed CMOS Databook", Integrated Device Tech-
nology Inc. Santa Clara, CA, 1988 pp 9-1 to 9-14.
"LR2000 High Performance RISC Microprocessor Prelimi-
nary" LSI Logic Corp. 1988, pp. 1-15.
'"LR2010 Floating Point Accelerator Preliminary" LSI Logic
Corp. 1988, pp 1-20.
B. Ramakrishna et aI., "The Cydra 5 Departmental Super-
computer Design Philosophies, Decisions, and Trade-offs"
Computer IEEE, Jan. 1989 pp. 12-35.
"LR2000 High Performance RISC Microprocessor Prelimi-
nary" LSI Logic Corp. 1988, pp. 1-15.
"Motorola MCHH200 Cache/Memory Management Unit
User's Manual", Molorola Inc., 1988.
Case: 13-1623 Document: 10 Page: 131 Filed: 11/04/2013
A188
US 6,591,353 HI
Page 3
Moussouris, J. "TIle Advanced Systems Outlook-Life
Beyond RISe: The next 30 years in high-performance
computing", Computer Letter, Jul. 31, 1989 (an edited
excerpl from an address al the fourlh annual conference on
the Advanced Systems Outlook, in San Francisco, CA (Jun.
5».
F. Anceau, "A Synchronous Approach for Clocking VLSI
Systems", IEEE Journal of Solid-State Circuits, vol. SC-17,
No.1, pp. 51-56 (Feb. 1982).
Knut A1nes, "SCI: A Proposal for SCI Operation",
SCI-6Jan89-doc31, Norsk Data, Oslo, Norway, pp. 1-24,
Jan. 6, 1989.
Bakka et aI., "SCI: Logical Level Proposals"
SCI-(iJanH9-doc32, Norsk Data, Oslo, Norway, pp. 1-20,
Jan. 6, 1989.
Gustavson et aI., "The Scalable Interface Project (Super-
hus)" (Dratl), SO-22 Aug 88-docl pp 1-16, Aug. 22, 1988.
Knut A1nes, "SCI: A Proposal for SCI Operation",
SCI-lONov88-doc23, Norsk Data, Oslo, Norway, pp. 1-12,
Nov. 10, 1988.
E. H. Frank, "The SBUS: Sun's High Performance System
Bus for RISC Workstations," IEEE pp. 189-194, Sun Micro-
systems Inc. 1990.
H. L. Kalter et al. "A50-ns 16Mb DRAM with a 10--ns Data
Rate and On-Chip DCC' IEEE Journal of Solid State
Circuils, vol. 25 No.5, pp. 1118-1128 (Ocl. 1990).
T. L. Jeremiah, "Synchronous LSSD Packet Switching
Memory and 110 Channel", IBM Technical Bulletin vol. 24
No. 10, pp. 4986-4987 (Mar. 1982).
T. Williams et. aI., "An Experimental1-Mbit CMOS SRAM
with Configurable Organization and Operation", IEEE Jour-
nal of Solid State Circuits, vol. 23 No.5, pp. 1085-1094
(Oct. 1988).
K. Ohta, "A 1-Mbil DRAM with 33-MHz Serial I/O Porls",
IEEE Journal of Solid State Circuits, vol. 21 No.5, pp.
649-654 (Oct. 1986).
K. Numata et. a1. " New Nibbled-Page Architecture for High
Density DRAM's", IEEE Journal of Solid State Circuits,
vol. 24 No.4, pp. 900-904 (Aug. 1989).
D.Y. James, "Scalable I/O Architecture for Buses", IEEE, pp
539-544, Apple Computer 19H9.
S. Watanabe et. aI., "An Experimental 16-Mbit CMOS
DRAM Chip with a 100--MHz Serial Read/Write Mode",
IEEE Journal of Solid State Circuits, vol. 24 No.3, pp.
763-770 (Jun. 1982).
A. Fielder et aI., "A 3 NS lK x 4 Static Self-Timed GaAs
RAM", IEEE Gallium Arsenide Integrated Circuit Sympo-
sium Technical Digest, pp. 67-70, (Nov. 1988).
H. Kuriyama et aI., "A 4-Mbit CMOS SRAM with 8-NS
Serial Access Time", IEEE Symposium On VLSI Circuils
Digest Of Technical Papers, pp. 51-52, (Jun. 1990).
PCT Invitation to Pay Additional Fees with Communication
Relating to the Results of the Partial International search,
mailed Apr. 21, 1997, for counterpart PCT Application No.
PCT/US 96/16835.
Steven A. Przybylski, "New DRAM Tecnologies, A Com-
prehensive Analysis of the New Architectures," pp. iii-iv,
119-121, 13H-15H, 177-203 (Micro Design Resource 1994).
TMS626402, "2097 152-Word By 2-Bank Synchronous
Dynamic Random-Access Memory", Texas Instf1lments,
1994, (pp. 5-3 to 5-23).
"Architectural Overview", Rambus, Inc., 1992, pp. 1-24.
"MT4LC4M4E9 (S) 4 Meg x 4 DRAM", Micron Semicon-
ductor, Inc., 1994, (pp. 1-183 to 1-196).
"M5M4V16807 ATP-lO, -12, -15, Target Spec. (Rev. 0.3)",
Milsubishi Electric, May 7, 1993, (pp. 1-36).
* cited hy examiner
Case: 13-1623 Document: 10 Page: 132 Filed: 11/04/2013
A189
u.s. Patent Jul. 8,2003 Sheet 1 of 21 US 6,591,353 Bl
--_., Column
Column Decode
Address
Columr;l

t
va
Figure 1A
  Art)
wordline
tra1SiSDr
ca cita
T
Storage Cell
Figure 1 B
(Prior Art)
Case: 13-1623 Document: 10 Page: 133 Filed: 11/04/2013
A190
u.s. Patent
Processor
or
,
Memory
Controller
,
Jul. 8,2003 Sheet 2 of 21 US 6,591,353 Bl
"
" ,

"".
,
""
DRAM
Row Address ]
1
Memory Core
SenselRestore ....
:....
" Column Column Amplifiers
 
RAS CAS
TransmiVReceive
Control
Address
Data
Figure 2
(Prior Art)
,
....
\
\'
\'
'\
Case: 13-1623 Document: 10 Page: 134 Filed: 11/04/2013
A191
D

A
d
d
r
e
s
s

R
o
w
r
a
l

I

C
o
n
H

I

C
o
U
2
1

l

I

C
o
U
n
l

r

R
o
w
r
b
l

I

-
-
,
-
-
,

-
-
.
.
.
.
J

,
-
-
.

-
-
I
D
a
t
a

I

W
D
a
t
a
[
a
,
1
]

I

W
D
a
t
a
[
a
,
2
]

i
·
·
·

I

W
D
a
t
a
[
a
,
n
]

I

I

C
o
n
t
r
o
l

I

 

I

I

W
r
i
t
E
(
C
A
S
)

I

W
r
i
t
E
(
C
A
S
)

I

I

W
r
i
t
t
(
C
A
S
)

I

S
e
n
s
e
(
R
A
S
)

I

4



t
R
C
D

F
i
g
u
r
e

3
A

(
P
r
i
o
r

A
r
t
)

d

.

r
J
J
.

.

'
"
'
C

f
"
'
I
"

=

f
"
'
I
"

!
=
-

N

§

r
.
F
l

=
-

:
l

o

.
.
.
.

N

.
.
.
.
.
.

c
:
:

r
:
I
J

0
"
1

0
.

\
0

W

U
t

c
=

Case: 13-1623 Document: 10 Page: 135 Filed: 11/04/2013
A192
D

A
d
d
r
e
s
s

R
o
w
[
a
]

C
o
l
[
l
]

C
o
l
f
i
]
-
C

C
o
l
[
3
]

C
o
l
[
4
]

C
o
l
[
S
]

D
a
t
a

I

R
D
a
t
a
[
a
,
l
]

I

R
D
a
t
a
[
a
,
2
]

I

C
o
n
t
r
o
l

I

S
e
n
s
e
{
R
A
S
)

I

I

R
e
a
d
(
C
A
S
)

I

R
e
a
d
(
C
A
S
)

I

R
e
a
d
(
C
A
S
)

I

R
e
a
d
(
C
A
S
)

I

R
e
a
d
(
C
A
S
)

I

t
R
C
D

i
C
A
A

F
i
g
u
r
e

3
8

(
P
r
i
o
r

A
r
t
)

d

.

r
J
J
.

.

'
"
'
C

 

f
"
'
I
"

 

=

f
"
'
I
"

 

!
=
-
5
'
0

N

§

r
.
F
l

=
-
 

:
l

"
"

o

.
.
.
.

N

.
.
.
.
.
.

c
:
:

r
:
I
J

0
"
1

0
.

\
0

 

W

U
t

 

c
=

 

Case: 13-1623 Document: 10 Page: 136 Filed: 11/04/2013
A193
C
P
U

R
E
S
E
T

O
U
T

D

D
R
A
M

D
R
A
M

F
i
g
u
r
e

4

(
P
r
i
o
r

A
r
t
)

D
R
A
M

R
E
S
E
T
i
N

8
U
S
D
A
T
A

[
8
]







B
U
S
D
A
T
A

[
1
]

B
U
S
D
A
T
A

[
0
]

B
U
S
C
T
L

B
U
S
E
N
A
B
L
E

C
L
O
C
K
l

C
L
O
C
K
2

V
R
E
F

G
N
D

V
O
D

d

.

r
J
J
.

.

'
"
'
C

~

f
"
'
I
"

~

=

f
"
'
I
"

~

!
=
-
~
 
I
O

N

=

=

~

r
.
F
l

=
-
~

~

.
.
.
.

U
l

0

.
.
.
.

N

.
.
.
.
.
.

c
:
:

r
:
I
J

0
"
1

0
.

\
0

~

W

U
t

~

c
=

~

Case: 13-1623 Document: 10 Page: 137 Filed: 11/04/2013
A194
u.s. Patent Jul. 8,2003
Clock Bus- Bus-
Cycle Enable Ctrl
OE
00
1E
10
2E
20
'-----
Sheet 6 of 21 US 6,591,353 Bl
BusData
[8] [7] [6] [5] [4] [3] [2] [1] [0]
Op
510
Adr
502
[0]
[9:2J
Adr
[17:10] 504
Adr
[26:18]
Adr
[35:27]
Count
[Ei,4,2]
Count
[7',5,3]
524
500
Figure 5
(Prior Art)
 
 
Case: 13-1623 Document: 10 Page: 138 Filed: 11/04/2013
A195
D

F
i
g
u
r
e

6

1
:
1

I

C
P
U

I

I

I

I
t
-
.

r

2
Q
1

M
E
M
O
R
Y

C
O
N
T
R
O
L
L
E
R

h

R
2
2

6
2
4



7

\
J

\

6
2
6

I
:

,
1
-
-

-
-

-
I

B
A
N
K

0

B
A
N
K

1

.
.
.

J

,
.

T

 

6
2
8

6
3
0

T

I

I

L

T

/

t

T

\
6
5
0

u

.
.
.

.
.
.

d

.

r
J
J
.

.

'
"
'
C

f
"
'
I
"

=

f
"
'
I
"

!
=
-
5
'
0

N

§

r
.
F
l

=
-

:
l

-
-
l

o

.
.
.
.

N

.
.
.
.
.
.

c
:
:

r
:
I
J

0
"
1

0
.

\
0

w

U
t

c
=

Case: 13-1623 Document: 10 Page: 139 Filed: 11/04/2013
A196
u.s. Patent Jul. 8,2003 Sheet 8 of 21 US 6,591,353 Bl
•. -
702A ..
1+
IQ;2B
BANKO
..
71.6
f-+-
BANKO
..
COLUMN
f-+-
704
DECODER
Zilli
I+-
~ ROW DECODER
..
f-+-
ROW DECODER
..
1+
lQM
...
~
ZQaa
BANK1
..
BANK1
722 f--
.-
VO AND CONTROL CIRCUITRY I
-
-
r{
724
.. -
710A ...
~
7   O f ~
BANK2
.....
ill!
f+.
BANK2
.....
COLUMN
f+
712
DECODER 714
4
ROW DECODER
..
1+
ROW DECODER
~
..
f-+-
716A
::
~
ill:6
BANK3
BANK3
Figure 7
Case: 13-1623 Document: 10 Page: 140 Filed: 11/04/2013
A197
u.s. Patent Jul. 8,2003 Sheet 9 of 21
I TRANSMIT WAKEUP G N A L ON THE BUS I
CONTROL LINE
r---,-I
~
TRANSMIT COMMAND CONTROL
INFORMATION ON THE BUS CONTROL
LINE AND DATA BUS
.----__ ,_I,
~
r                                 ~
ID.Q
US 6,591,353 Bl
ro3
TRANSMIT ADDRESSES
SERIALLY ON THE BUS
ENABLE LINE
TFtANSMIT STROBE SIGNAL
ON THE BUS CONTROL LINE
....--____ L __ -------.
814
TRANSMIT DATA ON THE
DATA BUS
ID2
TRANSMIT TERMINATE
SIGNAL ON THE BUS
CONTROL LINE
Figure 8
Case: 13-1623 Document: 10 Page: 141 Filed: 11/04/2013
A198
u.s. Patent Jul. 8,2003 Sheet 10 of 21 US 6,591,353 Bl
Clock Bus- Bus- BusData
Cycle Enable Clrl
[8] [7] [6] [5] [4] [3] [   ~ ] [1] [OJ:
Op[O]
906
Adr
'Write'
[9:2]
OE
Op[3]
912:
Adr
'Besl' [17:101
00
Adr
904
1E
[26:181
10
2E
20
Figure 9
Case: 13-1623 Document: 10 Page: 142 Filed: 11/04/2013
A199
D

A
d
d
r
e
s
s

D
a
t
a

C
o
n
t
r
o
l

4

C
o
l
[
1
]

C
o
l
[
2
]

r

C
a
l
[
3
]

I

C
a
!
[
4
]

I

-
-
c
o
H
s
]
-
-
-
r
-
c
o
!
[
s
T
u
-
,

C
a
l
m

I

R
D
a
t
a
[
a
,
1
]

I

W
D
a
t
a
[
a
,
2
]

I

R
D
a
t
a
[
a
,
3
]

I

W
D
a
t
a
[
S
,
4
]

I

R
e
a
d
(
C
A
S
)

I

W
r
i
t
e
(
C
A
S
)

I

R
e
a
d
(
C
A
S
)

I

W
r
i
t
e
(
C
A
S
)

I

R
e
a
d
(
C
A
S
)

I

W
r
i
t
e
(
C
A
S
)

I

R
e
a
d
(
C
A
S
)

I

t
C
A
A

.

~
~
 
 
 
 
 
 
-
-
-
-
-
-
-
.

F
i
g
u
r
e

1
0

P
r
i
o
r

A
r
t

t
C
l
o
c
k
C
y
c
l
e

d

.

r
J
J
.

.

'
"
'
C

~

f
"
'
I
"

~

=

f
"
'
I
"

~

!
=
-
~
C
I
O

N

§

r
.
F
l

=
-
~

:
l

.
.
.
.
.
.

.
.
.
.
.
.

o

.
.
.
.
.

N

.
.
.
.
.
.

c
:
:

r
:
I
J

0
"
1

0
.

\
0

~

W

U
t

~

c
=

~

Case: 13-1623 Document: 10 Page: 143 Filed: 11/04/2013
A200
D

C
o
l
u
m
n

A
d
d
r
e
s
s

C
o
l
A
d
d
r

C
o
l
A
d
d
r

C
o
l
A
d
d
r

C
o
l
A
d
d
r

C
o
l
A
d
d
r

C
o
l
A
d
d
r

C
o
l
A
d
d
r

D
a
t
a
/
R
o
w
A
d
d
r
e
s
s
l
C
o
n
t
r
o
l

R
e
a
d
(
C
A
S
)

R
O
a
t
a

R
O
a
t
a

R
O
a
t
a

R
O
a
t
a

R
e
a
d
(
C
A
S
)

R
D
a
t
a

R
D
a
t
a

D
a
t
a
/
C
o
n
t
r
o
l

S
e
l
e
c
t

C
o
n
t
r
o
l

O
a
t
a
-
-
·

I

D
a
t
a

n
T
-
D
a
t
a

,
-
O
a
t
a
-
,
-
-
C
o
n
t
r
o
l

O
a
t
s

D
a
t
a





t
C
A
A

F
i
g
u
r
e

1
1

P
r
i
o
r

A
r
t

d

.

r
J
J
.

.

'
"
'
C

~

f
"
'
I
"

~

=

f
"
'
I
"

~

!
=
-
~
 
I
O

N

§

r
.
F
l

=
-
~

:
l

.
.
.
.
.
.

N

o

.
.
.
.

N

.
.
.
.
.
.

c
:
:

r
:
I
J

0
"
1

0
.

\
0

~

W

U
t

~

c
=

~

Case: 13-1623 Document: 10 Page: 144 Filed: 11/04/2013
A201
D

c
e
l

(

I

I

S
T
R
O
B
E

C
O
L
U
M
N

A
D
D
R
E
S
S

{

f


I

T
E
R
M
I
N
A
T
E

F
i
g
u
r
e

1
2

O
P
E
R
A
T
I
O
N

0

(

O
P
E
R
A
T
I
O
N

1

t

O
P
E
R
A
T
I
O
N

2

f

\

O
P
E
R
A
T
I
O
N

3

{

O
P
E
R
A
T
I
O
N

4

{

o

H

"
H

H
.
¥

D
A
T
A

I

I
.
-
J

I

C
C
I

C
O
L
U
M
N

A
D
D
R
E
S
S

I

.
.

H

T
E
R
M
!
N
A
T
E

.
.
.
.

H
H
.
H

H
k
"
"
D
A
T
A

W
A
K
E
U
P

I

I

I

I

.
-
J

S
T
R
O
B
E

I

C
C
I

C
O
L
U
M
N

A
D
D
R
E
S
S

+
.

T
E
R
M
I
N
A
T
E

.
.
.
.

 

W
A
K
E
U
P

I

1
/

I

I

.
.
.
.
.
.
.
.

I

S
T
R
O
B
E

S
T
R
O
B
E

C
O
L
U
M
N

A
D
D
R
E
S
S

C
C
I

f
"
l

I

T
E
R
M
I
N
A
T
E

.
.
.
.

H

H

H

H
.
¥

D
A
T
A

W
A
K
E
U
P

I

.

.

I

I

.
.
-
J

I

S
T
R
O
B
E

C
O
L
U
M
N

A
D
D
R
E
S
S

c
q

t

I

T
E
R
M
I
N
A
T
E

W
A
K
E
U
P

-
+
-
H

I
I

"
H

H
.
¥

D
A
T
A

I

I
.
.
-
J

3
5

6
7

9
9

1
3
4

1
7
6

T
I
M
E

d

.

r
J
J
.

.

'
"
'
C

f
"
'
I
"

=

f
"
'
I
"

!
=
-

N

§

r
.
F
l

=
-

:
l

.
.
.
.
.
.

o

.
.
.
.

N

.
.
.
.
.
.

c
:
:

r
:
I
J

0
"
1

0
.

\
0

W

U
t

c
=

Case: 13-1623 Document: 10 Page: 145 Filed: 11/04/2013
A202
d

.

r
J
J
.

.

e
e
l

F
i
g
u
r
e

1
3

'
"
'
C

S
T
R
O
B
E

e
O
L
U
M
N

A
D
D
R
E
S
S

T
E
R
M
I
N
A
T
E

f
"
'
I
"

=

O
P
E
R
A
T
I
O
N

0

H

H

H
k
'

D
A
T
A

f
"
'
I
"

I

I
.
-
J

e
C
I

C
O
L
U
M
N

A
D
D
R
E
S
S

{
'

T
E
R
M
I
N
A
T
E

!
=
-
O
P
E
R
A
T
I
O
N

1

t

H
¥
O
A
T
A

N

=

I

=

D

S

R
O
B
E

O
P
E
R
A
T
I
O
N

2

[

I

e
C
I

I

C
O
L
U
M
N

A
D
D
R
E
S
S

I

T
E
R
M
I
N
A
T
E

r
.
F
l

I
H

t
H

I

H
k
'
D
A
T
A

=
-

l

I

)
t
1

.
.

I
I

I
I

I
.
-
J

.
.
.
.

W
A
K
E
U
P

.
.
.
.
.
.

S
T
R
O
B
E

I

"
'
"

0

O
P
E
R
A
T
I
O
N

3

{

I

I

S
T
R
O
B
E

I

C
O
L
U
M
N

A
D
D
R
E
S
S



.
.
.
.

e
e
l
,

I

N

 

T
E
R
M
I
N
A
T
E

.
.
.
.
.
.

.
.
,
.
H

H
I

H

.

H
k
'

D
A
T
A

W
A
K
E
U
P

I

.
-
J

{

I

I

S
T
R
O
B
E

C
O
L
U
M
N

A
D
D
R
E
S
S

O
P
E
R
A
T
I
O
N

4

I

e
C
I
,

 

I

T
E
R
M
I
N
A
T
E

c
:
:

r
:
I
J

.
.
.
.
H
H

H

H

D
A
T
A

0
"
1

I

0
.

\
0

0

6
7


3
5

9
9

1
3
4

W

T
I
M
E

U
t

c
=

Case: 13-1623 Document: 10 Page: 146 Filed: 11/04/2013
A203
u.s. Patent
1508
1502
1 5     ~
Jul. 8,2003 Sheet 15 of 21 US 6,591,353 Bl
·1406
~ 1 4 C 2
Figure 14
PRIOR ART
----"'..., 1520
----''-'1518
----r--........ 1516
1506
Figure 15
Case: 13-1623 Document: 10 Page: 147 Filed: 11/04/2013
A204
u.s. Patent Jul. 8,2003 Sheet 16 of 21 US 6,591,353 Bl
Op[2] - NoByte M WriteOp WriteRegOp
Op[O]- WMte
ReadRegOp
T
Op[31· BC+t
OP[1 1•   W;g
ACTION
ILLEGAL 0 0 0 0 X
MEMORY WRITE DIRECTED BYTE MASK 0 0 0 1
ILLEGAL 0 0 1 0
ILLEGAL 0 0 1 1
MEMORY READ DIRECTED 0 1 0 0 X
MEMORY WRITE DIRECTED 0 1 0 1 X
REGISTER READ DIRECTED 0 1 1 0 X X X X
REGISTER WRITE DIRECTED 0 1 1 1 X X X X
ILLEGAL 1 0 0 0
MEMORY WRITE BROADCAST BYTE MASK 1 0 0 1 X
ILLEGAL 1 0 1 0
ILLEGAL 1 0 1 1
ILLEGAL 1
,
0 0
MEMORY WRITE BROADCAST 1 1 0 1 X
ILLEGAL 1 1 1 0
REGISTER WHITE BROADCAST 1 1
,
1 X X X X
Figure 16A
Case: 13-1623 Document: 10 Page: 148 Filed: 11/04/2013
A205
u.s. Patent Jul. 8,2003 Sheet 17 of 21 US 6,591,353 Bl
BroadcastOp
RsrvOp
WrlteMemByteMaskBroadcaslOp
 
WriteMemByteMaskOp
WriteMemNoByteMaskBradcastOp
WrileMemNoByteMaskDirectedOp
WrrteMemNoByteMaskOp
WriteMemOp
ReadMemDirec1edOp
ReadMemOp
Mem+
r r
, , ,
r
ACTION
ILLEGAL X
MEMORY WRITE DIRECTED BYTE MASK X X X X
ILLEGAL X
ILLEGAL X
MEMORY READ DIRECTED X X X
MEMORY WRITE DIRECTED X X X X
REGISTER READ DIRECTED
REGISTER WRITE DIRECTED
ILLEGAL X
MEMORY WRITE BROADCAST BYTE MASK X X X X X
ILLEGAL X
ILLEGAL X
ILLEGAL X
MEMORY WRITE BROADCAST X ! X X X X
ILLEGAL X
REGISTER WRITE BROADCAST
I
X
Figure 168
Case: 13-1623 Document: 10 Page: 149 Filed: 11/04/2013
A206
u.s. Patent Jul. 8,2003 Sheet 18 of 21
DEVICE 10
REQUEST
ADDRESS
DEVICE BITS
1..-1 ___ '--.
OP CODE 17().d
1 702
r
-
=?
OTHER 1708
COMMANDS -,
US 6,591,353 Bl
1706
1712
  PERFORM
    COMMAND
1-1 ___ ,-::]
DECODE            
---17110
REQUEST
ADDRESS
DEVICE BITS
1
BROADCAST -.J
COMMAND
Figure 17
..

1802
,.      
=?        
OP BROADCAST BIT .,'-----
Figure 18
PERFORM
COMMAND
Case: 13-1623 Document: 10 Page: 150 Filed: 11/04/2013
A207
u.s. Patent
OPEN CLOSE
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
Jul. 8,2003
Current
NEW
BANK BANK
STATE STATE
CLOSED CLOSED
CLOSED I CLOSED
CLOSED OPEN
CLOSED CLOSED
OPEN OPEN
OPEN CLOSED
OPEN OPEN
OPEN CLOSED
Sheet 19 of 21 US 6,591,353 Bl
AC TIO N
Ill.EGA
NO ACT
L
ION
CAF
cm
NO
NO-
SENSE-
SENSE-
COMM,A,
COMM,A,
PRECH
PRECH
ARG
ARG
m
 
PRECHARGE
E-SENSE-COMMAND
E-SENSE-COMMAND-PRECHARGE
Figure 19
Case: 13-1623 Document: 10 Page: 151 Filed: 11/04/2013
A208
u.s. Patent Jul. 8,2003 Sheet 20 of 21 US 6,591,353 Bl
--
-
2010

BANKO
--
--
I- 2012
-
BANK1
2016
.-
I QUEU0-

--
2008
X
2020
CONTROL

 
CIRCUITRY I/O
-
I QUEUE r-
--
"
UNIT
-.-
2004
.--. CONTROLLER

y
r-
BANK2 r-
--

]-
Figure 20A
Case: 13-1623 Document: 10 Page: 152 Filed: 11/04/2013
A209
u.s. Patent Jul. 8,2003 Sheet 21 of 21 US 6,591,353 Bl
-
f.Q1Q ]
BANKO
-
2012 ]
BANK1
.......... 2014 20S0
,I
,
-'--
2008
illQ
r'"
2004
I/O ""'"
,
CONTROLLER
INIT
I QUEuE} r----2QQ2
X 2020 CONTROL
CIRCUITRY
:---
 
V
BANK2
]
-C_BAN_K3 _],
Figure 208
Case: 13-1623 Document: 10 Page: 153 Filed: 11/04/2013
A210
US 6,591,353 B1
1
PROTOCOL FOR COMMUNICATION WITH
DYNAMIC MEMORY
This application is a continuation of application Ser. No.
09/480,767, filed on Jan. 10,2000; which is a continuation
of application Ser. No. 08/979,402, filed on Nov. 26, 1997;
which is a division of application Ser. No. 08/545,292 filed
on Oct. llJ, llJlJ5 (now U.S. Pat. No.  
FIELD OF THE INVENTION
The present invention relates to dynamic random access
memory (DRAM), and more specifically, to a method and
apparatus for controlling data transfers to and from a
dynamic random access memory.
BACKGROUND OF THE INVENTION
2
alternative DRAM architectures are described in detail in
NEW DRAM TECHNOLOGIES, by Steven A. Przybylski,
published by MicroDesign Resources, Sebastopol, Calif.
(1994). Some of those architectures are generally described
below.
Extended Data-Out DRAMS
The prior art includes Extended Data-Out (EDO) memory
systems. In EDO DRAMs, the output buffer is controlled by
10 signals applied to output enable (OE) and column address
stobe (CAS) control lines. In general, data remains valid at
the output of an EDO DRAM longer than it does for
conventional DRAMs. Because the data remains valid
longer, the transfer of the data to the latch in the memory
15 controller can be overlapped with the next column pre-
charge. As a result, burst transfers can be performed in fewer
clock cycles. Dynamic random access memory (DRAM) components,
such as those illustrated in FIG. lA, provide an inexpensive
solid-state storage technology for today's computer systems. 20
Digital information is maintained in the form of a charge
stored on a two-dimensional array of capacitors. One such
capacitor is illustrated in FIG. lB.
Synchronous DRAMS
The prior art also includes Synchronous DRAM
(SDRAM) memory systems. The interface of an SDRAM
includes a multiplexed address bus and a high-speed clock.
The high speed clock is used to synchronize the flow of FIG. 2 illustrates a prior art memory system including
DRAM with the corresponding control, address and data
wires which connect the DRAM to the processor or memory
controller component. In synchronous DRAMs, a write
access is initiated by transmitting a row address on the
address wires and hy transmitting row address strohe (RAS)
signal. This causes the desired row to be sensed and loaded
by the column amplifiers. The column address is transmitted
on the address wires and the column address strobe (CAS)
signal is transmitted along with the first word of the write
data WData(a,l). The data word is then received by the
DRAM and written into the column amplifiers at the speci-
fied column address. This step can be repeated "n" times in
the currently loaded row before a new row is sensed and
loaded. Before a new row is sensed, the old row must be
restored back to the memory core and the bit lines of the
DRAM precharged.
FIG. 3A illustrates synchronous write timing. In the
figure, a, b ... represent a row address; 1, 2 ... n represent
25 addresses, data, and control on and off the DRAM, and to
facilitate pipelining of operations. All address, data and
control inputs are latched on the rising edge of the clock.
Outputs change after the rising edge of the clock. SDRAMs
typically contain a mode register. The mode register may he
30 loaded with values which control certain operational param-
eters. For example, the mode register may contain a burst
length value, a bmst type value, and a latency mode value.
The burst length value determines the length of the data
bursts that the DRAM will perform. The burst type value
35 determines the ordering of the data sent in the bursts. Typical
burst orders include sequential and subblock ordered. The
latency mode value determines the number of clock cycles
between a column address and the data appearing on the data
bus. The appropriate value for this time interval depends
40 largely on the operating frequency of the SDRAM. Since the
SDRAM cannot detect the operating frequency, the latency
mode value is programmable by a user.
a column address, WData [row, col] represents the DRAM
address of data words, the row address strohe (RAS) is a
control signal for initiating a sense operation, and WRITE 45
(CAS) initiates the write operation on the column amplifiers.
Request Oriented DRAM Systems
The prior art also includes memory systems in which data
transfer operations are performed by DRAMs in response to
transfer requests issued to the DRAMs by a controller.
Referring to FIG. 4, it illustrates a memory system in which
data transfers are made in response to transfer requests. The
request packet format is designed for use on a high speed
multiplexed bus for communicating between master devices,
In the present example, the row column address delay timing
parameter is equal to two clock cycles. After the row address
is asserted at the first clock cycle, column addresses and
write data are asserted after the delay to write the data into 50
the DRAM array.
such as processors, and slave devices, such as memories.
The bus carries substantially all address, data, and control
information needed hy the master devices for communica-
FIG. 3B illustrates synchronous read timing. A processor
initiates a read access by transmitting a row address on the
address wires and by transmitting the row address strobe
(RAS) signal. This causes the desired row to be sensed by
the column amplifiers. The column address is then trans-
milled on the address wire and the column address strobe
(CAS) signal is transmitted. The first word of the read data
RData (a,l) is then transmitted hy the DRAM and received
55 tion with the slave devices coupled to the bus. The bus
architecture includes the following signal transmission lines:
by the processor. This step can be repeated "n" times in the 60
currently loaded row before a new row is sensed and loaded.
Before a new row is sensed, the old row must be restored
back to the memory array.
Various attempts have been made to improve the perfor-
mance of conventional DRAMs. Such attempts have 65
resulted in DRAM architectures that deviate in varying
degrees from conventional DRAM architectures. Various
BusCtl, BusData [8:0], BusEnable, as well as clock signal
lines and power and ground lines. These lines are connected
in parallel to each device.
The processors communicate with the DRAMs to read
and write data to the memory. The processors form request
packets which are communicated to the DRAMs by trans-
mitting the bits on predetermined transmission lines at a
predetermined time sequence (i.e. at predetermined clock
cycles). The bus interface of the DRAM receiver processes
the information received to determine the type of memory
request and the number of bytes of the operation. The
Case: 13-1623 Document: 10 Page: 154 Filed: 11/04/2013
A211
US 6,591,353 B1
3
DRAMs then perform the memory operation indicated by
the request packet.
FIG. 5 illustrates command control information 500 that
4
transferred. The controller determines, after transmitting the
control information on the bus, a desired amount of data to
be transferred in the data transfer operation. The controller
transmits over the bus a terminate indication at a time that
is based on the desired amount of data and a beginning time
of the data transfer operation. A memory device reads the
control information on the bus. The memory device per-
forms the specified data transfer operation on data stored at
the heginning location. The memory device continues to
10 perform the specified data transfer operation until detecting
the terminate indication on the bus. The memory device
is sent in a data transfer request according to a prior art
protocol. In the illustrated example, the command control
information 500 is sent over a BusCt11ine and a nine-bit data
hus (nusData[!!:OJ) in six clock cycles. The command con-
trol information 500 includes groups of bits 501, 502, 504,
506 and 508 that constitute an address, an operation code
consisting of six hits 5111, 512, 514, 516, 51!! and 520, and
groups of bits 522, 524 and 528 that specify a count. The
address identified in the command control information 500
specifies the target DRAM and the beginning location within
the DRAM of the data on which the operation is to be
performed. The count identified in the command control 15
information 500 specifies the amount of information on
which the operation is to be performed.
SUMMARY AND OBJECTS OF THE
INVENTION
One object of the present invention is to provide a
mechanism to decouple control timing from data timing.
20
Another object of the present invention is to provide
mechanisms that use minimal bandwidth to determine data 25
timing while minimizing the latency from signaling that the
data transfer should terminate to the transmission of the final
data packet.
ceases to perform the data transfer operation at a time that
is based on the time at which the terminate indication is
detected.
Other objects, features, and advantages of the present
invention will be apparent from the accompanying drawings
and from the detailed description that follows below.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention is illustrated by way of example,
and not by way of limitation, in the figures of the accom-
panying drawings and in which like reference numerals refer
to similar elements and in which:
FIG. 1A is a block diagram of prior art dynamic random
access memory (DRAM) component;
FIG. 1B illustrates a storage cell of the DRAM shown in
FIG.1A;
Another object of the present invention is to provide
mechanisms for arhitrarily long data transfers following a
command. This may include simultaneous provision of a
new column address for each data packet transferred.
FIG. 2 is a hlock diagram illustrating a DRAM system and
30 input/output pins and signal lines for accessing the DRAM;
FIG. 3A is a timing diagram illustrating synchronous
write timing;
Another object of the present invention is to provide a
means to signal simultaneously with termination of the data
transfer that a precharge operation should be performed. 35
FIG. 3B is a prior art timing diagram illustrating synchro-
nous read timing;
FIG. 4 is a prior art memory system in which a memory
controller issues request packets to DRAM over a channel;
lilU. 5 illustrates command control information that is
Another object of the present invention is to provide
mechanisms and methods for interleaving control and data
information in such a fashion that pin utilization is maxi-
mized without placing latency requirements upon the
DRAM core that are difficult or expensive to satisfy.
sent from a controller to a DRAM according to a prior art
40 protocol;
Another object of the present invention is to provide a
mechanism for interleaving control and data information
that minimizes bandwidth consumed for signaling the begin-
ning and ending of data transfers.
Another object of the present invention is to provide for 45
devices that do not always interpret the information pre-
sented at their pins. Each command provides sufficient
information that all further control information related to the
command can be easily determined even in the presence of 50
control information related to previous command transfers.
FIG. 6 is a block diagram of a computing system that
includes the present invention;
FIG. 7 is a block diagram the illustrates the control and
decode circuitry of a DRAM according to one embodiment
of the invention;
FIG. 8 is a flow chart illustrating the protocol employed
by a controller to initiate data transfers according to an
embodiment of the present invention;
FIG. 9 illustrates a request packet according to one
embodiment of the present invention;
FIG. 10 is a timing diagram illustrating interleaved read/
write transaction timing when the read latency equals the
write latency according to a prior art protocol;
Another object of the present invention is to provide a
mechanism for optionally sequencing a series of core opera-
tions prior to data transmission and, optionally, a final core
operation after data transmission is terminated.
55 FIG. 11 is a timing diagram which illustrates synchronous
interleaved read timing with multiplexed data/row/control
information according to an alternative prior art protocol;
FIG. 12 illustrates the timing of five transactions per-
formed in a non-interleaved embodiment of the present
Another object of the present invention is to provide a
DRAM core which allows a single high current RAS opera-
tion at anyone time in order to minimize the cost and
complexity of the DRAM.
Another object of the present invention is to provide an
encoding of the command such that decoding space and time
is minimized and functionality is maximized.
60 invention;
The present invention provides a method and apparatus
for performing data transfers within a computer system. The
method includes causing a controller to transmit control 65
information on a bus. The control information specifics a
data transfer operation and a beginning location of data to be
FIG. 13 illustrates the timing of five transactions per-
formed in an interleaved embodiment of the present inven-
tion;
FIG. 14 illustrates circuitry for decoding operation codes
according to the prior art;
FLU. 15 illustrates circuitry for decoding operation codes
according to one embodiment of the present invention;
Case: 13-1623 Document: 10 Page: 155 Filed: 11/04/2013
A212
US 6,591,353 B1
5
FIG. 16A illustrates an operation code encoding scheme
according to an embodiment of the invention;
FIG. 16B is a continuation of the table illustrated in FIG.
16A;
FIG. 17 illustrates a prior art circuit for determining
whether a particular DRAM should respond to an operation
request; and
FIG. 18 illustrates a circuit for determining whether a
particular DRAM should respond to an operation request
according to an embodiment of the present invention;
FIG. 19 illustrates a mapping between Open and Close
bits and the operations that are performed by a DRAM in
response to the bits according to an embodiment of the
invention;
FIG. 20A is a block diagram illustrating a DRAM con-
figured to allow no more than one high current operation to
be performed over each internal power supply line according
to an embodiment of the invention; and
FIG. 20B is a block diagram illustrating a DRAM con-
figmed to allow no more than one high cmrent operation to
be performed within the DRAM at any given time according
to an embodiment of the invention.
DETAILED DESCRIPTION
FIG. 6 is a block diagram of a computing system that
includes the present invention. The data transport system
includes a central processing unit 600, a memory controller
601 and a DRAM 603. The memory controller 601 connecls
the CPU 600 to a channel 622 to which DRAM 603 is
connected. For the pmposes of explanation, a single DRAM
is shown on channel 622. However, the present invention is
not limited to any particular number of DRAMs on the
channel 622.
The CPU 600 may be, for example, a microprocessor.
When the CPU 600 executes instructions that require a data
transfer operation, the CPU 600 transmits control signals
specifying the desired transfer operations to memory con-
troller 601. Memory controller 601 may be, for example, an
application specific integrated circuit (ASIC) memory con-
troller configmed to transmit request packets to DRAM 6U3
over channel 622 to specify the desired transfer operation.
6
Each of the memory banks 602 and 606 has a latching
sense amplifier cache 604 and 608. The caches 604 and 608
hold the cmrently sensed row of their respective memory
banks. The control section 634 includes control logic 610
and control registers 614. Control logic 610 performs ini-
tialization operations in response to control signals on line
624. Control registers 614 are read and wrillen to using
special register space commands. The contents of the control
registers 614 determine how DRAM 603 operates. I'or
10 example, the control registers 614 may store values that
determine the output drive current used by DRAM 603, the
base address of DRAM 603 and the configmation and size
of DRAM 603.
The I/O section 636 includes a clock generator 618, a
15 receiver 620, and a transmitter 616. The clock generator 618
uses the external-clock signals to create clock signals used
internally by DRAM 603. The receiver 620 and transmitter
616 contain multiplexing and storage hardware to permit
internal data paths to operate at a slower clock rate, but
20 equivalent bandwidth, to lines 626.
FIG. 7 is a block diagram of a DRAM in which the present
invention may be implemented according to one embodi-
ment of the invention. Referring to FIG. 7, a DRAM 700
25 generally includes I/O and control circuitry 722, four banks
of memory, a plurality of column decoders 718 and 720, and
a plurality of row decoders 704, 706, 712 and 714. Each of
the four banks are split into two memory blocks.
Specifically, BANKO is distributed over blocks 702A and
702B, BANKI is distributed over blocks 708A and 708B,
30 BANK2 is distributed over block5 71UA and 71UB and
BANK3 is distributed over blocks 716A and 716B.
I/O and control circuitry 722 receives request packets
from a controller over a channel 724. The request packets
35 include an address that corresponds to a storage location and
an operation code that specifies the operation to be per-
formed on the data stored in the specified storage location.
To perform a read operation, I/O and control circuitry 722
transmits control signals to the row decoders 704, 706, 712
40 and 714 to cause the row that contains the specified data to
be moved into a cache. Then the I/O and control circuitrv
722 transmits control signals to the column decoders 718
and 720 to cause the data from a column of the row in the
row cache to be transmitted out onto the channel 724. The
According to one embodiment, channel 622 includes a
line 624 for initializing daisy chain input, a "clock to end"
line 650, a "clock from master" line 628; a "clock to master"
line 630, and a plurality of lines 626 that includes a
BusEnable line, a BusCtl line and a nine-bit data bus
(BusData[H:O]). The "clock to end" line 650 carries a clock
signal from memory controller 601 to the end of line 630.
The "'clock to master" line 630 routes the clock signal to the 50
various devices on channel 622 and back to memory con-
troller 601. The "clock from master" line 628 routes the
clock signal from the "clock to master" line 630 back to the
various devices on channel 622. The clock signal on the
"clock from master" line 628 is aligned with request and 55
write data packets transmitted by controller 601. The clock
signal on the "clock to master" line 630 is aligned with read
data packets transmitted by DRAM 603. The information
communicated over lines 626 includes request packets, data
transfer control signals, and data packets.
45 column that is transmitted is the column that corresponds to
the address contained in the request packet.
Controller Operation
Referring to FIG. 8, it is a flow chart that illustrates the
protocol employed by a controller to initiate data transfers
according to one embodiment of the invention. At step 802,
the controller transmits a wakeup signal to the DRAM that
will be involved in the data transfer operation (the "target
DRAM"). At step 804, the controller transmits command
control information to the target DRAM. The contents of the
command control information according to one embodiment
of the invention are illustrated in FIG. 9.
Referring to FIG. 9, the command control information is
transmitted over the BusCt1line and BusData[H:O] lines over
60 three clock cycles, where each clock cycle has even and odd
phases. A start bit 902 is sent over the BusCtl line on the
even phase of the first clock cycle. As shall be described in
greater detail below, the start bit serves as a flag which
DRAM 603 is divided into three sections: an storage
section 632, a control section 634, and a I/O section 636. The
storage section 632 includes a DRAM core consisting of two
independent memory banks 602 and 606. It should be noted
that a two-bank DRAM shall be described simply for the 65
purposes of explanation. The present invention is not limited
to DRAMs with any particular number of memory banks.
allows the DRAM to identify the signals as command
control information.
rhe command control information includes an address
904 that identifies the beginning memory location in the
Case: 13-1623 Document: 10 Page: 156 Filed: 11/04/2013
A213
US 6,591,353 B1
7
target DRAM that will be involved in the specified data
transfer operation. The command control information fur-
ther includes an operation code, open and close bits, and a
Pend value.
As shall be explained below, certain bits in the operation
code directly correspond to control lines within the target
DRAM. Specifically, the operation code includes a Write hit
906, a Reg bit 90S and a NoByteM bit 910 that correspond
to control lines in the target DRAM. Upon receipt of the
command control information, the DRAM simply places the 10
value stored in these bits on the respective control line. The
operation code also contains a broadcast bit 912 to indicate
whether the specified operation is a broadcast operation.
              15
Close bits specify whether prechargc and/or scnse opera-
tions are to be performed before and/or after the operation
specified in the operation code. The Pend value indicates
how many odd phase bits will appear on the BusCtlline after 20
the command control information and before the strobe
signal that corresponds to the operation specified in the
command control information (other than any odd phase bits
in request packets for other transactions). The command
control information also contains other values "EvaICC" and
,. Mask" that do not relate to the present invention. 25
Referring again to FIG. S, control passes from step S04 to
step S06. During step S06, the controller transmits the strobe
signal over the BusCtl line (step SI0). If the transaction
involves more than one data packet, then the column address 30
for data packets that are to be sent subsequent to the first data
packet are transmitted serially over the 13uslmable line (step
SOS). Steps SOS and S10 are combined in step S06 to indicate
that step S10 is performed concurrently with step SOS. In one
embodiment, the transmission of the address for subsequent 35
data packets begins at a sufficient interval prior to the time
at which those data packets are to be sent to allow the second
and subsequent data packets to be sent after the first data
packet without interruption.
At step S14, the data is transmitted over the data bus 40
(BusData[S:O]). During this step, the data may be transmit-
ted to or from the target DRAM, depending on whether the
data transfer operation is write or read operation. At some
fixed period of time prior to the transmission of the last data
packet, the controller transmits the terminate signal on the 45
BusCt1line,(step SI6). Steps S16 and S14 are shown as a
single step R12 to indicate that step R16 is performed during
the performance of step S14.
As shall be explained below, one embodiment of the
memory controller dynamically adjusts the interleave of data 50
and control information to more fully utilize the channel.
Interleave refers to the relative ordering of data, requests and
control signals that are associated multiple transactions. To
allow dynamic interleave adjustment, there is no fixed time
period between the execution of steps S04 and S06. Rather, 55
the controller is free to adjust the timing of step S06 relative
to the timing of step S04 as needed to provide the desired
interleave (e.g., to provide time to transmit the command
control information for othcr transactions bctwecn cxccution
8
command queue within the DRAM may be reduced,
decreasing the complexity of the DRAM.
In one embodiment, the number of outstanding requests
on the channel may he larger than the numher of rests heing
processed by any single DRAM. Preferably, the number of
outstanding requests is limited only by the size of the field
which indicates the number of outstanding requests, and the
aggregate number of requests which can be handled by all of
the DRAMs on the channel.
Deferred Transfer Size Determination
In typical EDO and SDRAM components, only a finite
number of data transfer sizes are supported. For each data
transfer size, there is a fixed ratio betwecn the amount of
control information that must be sent to a DRAM and the
amount of data to be transferred in the operation. Thus, the
larger the amount of data to he transferred, the larger the
amount of control information that must be sent to the
DRAM. For example, with an SDRAM that only supports
transfers of one or four data words, two four-word transfers
must be performed to transfer eight data words. Thus, all of
the control information that a controller must send to the
DRAM for a four data word transfer, including an operation
code and an address, must be sent twice.
In prior art request-oriented systems, a data transfer count
is part of the command control information that a controller
sends to a DRAM to initiate a data transfer operation. The
amount of bits allocated in the control information for
sending the data transfer count is fixed. Consequently, the
size of data transfers that a system may perform in response
to a single transfer request is limited to the number of data
packets that can be specified in the available number of bits.
The size limit thus placed on data transfers makes it neces-
sary for transfers of large amounts of data to be performed
using numerous rcquests for smaller data transfer opera-
tions. For example, if the data transfer count is only five bits
long and data packets are eight bytes, then the maximum
size of a data transfer is 256 hytes (32 data packets). I'or
transfers larger than 256 bytes, more than one request packet
must be used.
In one prior art request-oriented system, the controller is
allowed to prematurely terminate a data transfer operation
by transmitting a terminate control signal to the DRAM.
Upon receipt of the terminate control signal during a par-
ticular data transfer operation, the DRAM ccases to process
data for the operation, even if the amount of data that has
been transferred is less than the amount of data that was
specified in the data transfer count of the operation. This
technique allows the controller to shorten data transfers after
a particular transfer size has been specified, but does not
overcome the limitations associated with having a maximum
size limit per requested transaction.
According to one aspect of the present invention, the
command control information within a request packet no
longer contains size information. Rather, the DRAM is
configured to start and end the transmission of data based on
data transfer control information sent by the controller to the
DRAM separate from and suhsequent to the transmission of
the command control information. According to one
of steps S04 and S06).
60 embodiment, the data transfer control information includes
data transfer start information (a "strobe signal") sent from
the controller to indicate when the DRAM is to begin
sending data, and data transfer end information (a "terminate
In one embodiment, the controller is configllfed to limit
the number of requests that are targeted to any given DRAM.
For example, if two data transfer operations have been
requested for a given DRAM, the controller will refrain from
issuing a third request until one of the outstanding requests 65
has becn serviced. By limiting the number of requcsts any
DRAM must handle at any given time, the size of the
signal") to indicate when the DRAM is to stop sending data.
The number of clock cycles that elapse between the trans-
mission of the strobe signal and the terminate signal indi-
cates the size of the data transfer.
Case: 13-1623 Document: 10 Page: 157 Filed: 11/04/2013
A214
US 6,591,353 B1
9
If a data transfer operation involves more than one data
packet, then the controller serially transmits column address
information on the BusEnable line to specify the columns
that contain the data to be sent in the second and subsequent
data packets. Preferably, the controller begins to transmit the
column address information at a time that allows the DRAM
10
The exact timing of the terminate signal may be used to
indicate whether a transfer operation should be terminated or
merely suspended. For example, if the terminate signal is
sent at one modulus relative to the strobe signal, the DRAM
is configured to terminate the data transfer operation. A
modulus is the remainder obtained after dividing one integer
by another integer. If the terminate signal is sent at a
different modulus relative to the strobe signal, the DRAM is
configured to suspend the transfer operation. The I) RAM
to have sufficient time to reconstruct the column addresses
and pre fetch the data from the specified columns in the
DRAM core before the data packets that correspond to the
column addresses are to be transmitted over the channel.
Because the DRAM continuously receives column
addresses over the BusEnable line during multi-packet
transfers, the DRAM itself does not have to maintain a
counter to determine from where to retrieve data for the next
data packet.
10 may be configured to continue transfer operations that have
been suspended upon receipt of a continue control signal.
By transmitting data transfer control information separate 15
from the command control information, it is possible to
specify a transfer operation for any amount of data. Thus,
large transfers do not have to he hroken up into multiple
requests for smaller amounts of data. In one embodiment,
the control circuitry within the DRAM is configured to begin 20
retrieving requested data from the DRAM core as soon as
possible after receipt of a request packet. The DRAM does
not wait for the strobe signal to begin retrieving the data
from the DRAM core. However, the DRAM does not
transmit any data on the channel until the strobe signal is 25
received. Because the initial data packet to be transmitted by
the DRAM has been prefetched from the core, the data
packet can he transmitted over the channel with minimal
delay from when the strobe signal ultimately arrives.
There are numerous benefits to reducing the delay 30
between the transmission of (1) a strobe signal for a transfer
operation and (2) the first packet in the transfer operation.
For example, the minimum latency between a transfer
request and the beginning of the transfer can never be less
than the strobe-to-data delay. Therefore, the strobe-to-data 35
delay may determine the critical path for DRAMs that
support fast core operations. In addition, the longer the
strobe-to-data delay, the more complex the controller must
Decoupled Data Transfer Control Information
In prior art systems, the timing of a data transfer is
dictated hy the timing of the request for the data transfer.
Thus, given that a transfer request arrived on a particular
clock cycle, it was known that the data specified in the
request would begin to appear on BusData[8:0] a predeter-
mined number of clock cycles from the particular clock
cycle. For example, the number of clock cycles that elapse
between a request packet and the transfer of data specifred
in the request packet may be determined by a value stored
in a register within the DRAM. This fact renders prior art
systems inllexible with respect to how control and data
signals may be interleaved to maximize the use of the
channel.
As mentioned above, the data transfer control information
which controls the timing of the data transfer associated with
a request packet is sent separately from the command
control information to which it corresponds. According to
another aspect of the invention, the timing of the data
transfer control information is variable relative to the timing
of the corresponding request packet. That is, the number of
clock cycles between the transmission of a request packet
and the transmission of the strobe signal to begin the transfer
specified in the request packet may vary from transaction to
transaction.
According to an alternate embodiment of the invention, he to accurately and efficiently pipeline the command con-
trol information and strobe signals. 40 the amount of time that elapses between the transmission of
a request packet and the transmission of the data specified in
a request packet is varied without the use of strohe and
terminate signals. In this embodiment, the request packet
The bandwidth required to indicate the start and end of a
data transfer operation with single bit strobe and terminate
signals is minimal. In one embodiment, a single line (the
BusCtl line) is used to carry a variety of control signals,
including the strobe and terminate signals. Further, the 45
channel utilization employed to start and terminate a transfer
operation does not vary with the size of the data to be
transferred.
Due to intrinsic circuit delays, the DRAM does not
instantly terminate data transmission upon the receipt of the
terminate signal. Rather, the terminate signal causes the
DRAM to initiate termination of the data transfer. Trans-
mission of the last data packet in a transfer actually occurs
contains a delay value that indicates to the DRAM when the
data specified in the request packet will begin to be sent
relative to the time at which the request packet is sent. The
DRAM would include a counter to count the clock cycles
that elapse from the arrival of the request packet in order to
send or receive the data specified in the request on the
50 appropriate clock cycle. Because the controller may vary the
latency between request packet and data transmission, the
controller is able to dynamically adjust the operative inter-
leave on the channel, as shall he descrihed in greater detail
below.
on some clock cycle after the receipt of the terminate signal.
When a terminate signal is used to specify the end of a 55
transfer operation, it is important to minimize the latency
between the transmission of the terminate signal for the
transaction and the transmission of the last data packet of the
transaction. By reducing the latency hetween the terminate
signal for a transaction and the time at which the channel 60
ceases to be used to send data for the transaction, the amount
Dynamic Interleave Adjustment
As mentioned above, the fixed timing between requests
and data transmissions renders prior art systems inflexible
with respect to how control and data signals may be inter-
leaved. For example, FIGS. 10 and 11 illustrate the timing
of transactions for particular prior art protocol systems.
of time required for the controller to use the channel for
another transaction is reduced. This is particularly important
when there arc multiple requesters that arc contending for
use of the same channel.
According to one embodiment, the terminate signal may
be used to either end a transaction or suspend a transaction.
Referring to FIG. 10, it illustrates interleaved timing of
read and write accesses. The interleave structure permits
read accesses to a DRAM to be interleaved with write
65 accesses to another DRAM. FIG. 11 illustrates synchronous
interleaved read timing with multiplexed data/row/control
information according to an alternative prior art protocol.
Case: 13-1623 Document: 10 Page: 158 Filed: 11/04/2013
A215
US 6,591,353 B1
11
Both of these prior art interleave patterns increase utilization
of the channel and the internal resources of the DRAM
relative to non-interleaved protocols. However, the timing
between requests and data transfers is fixed, so the interleave
patterns are fixed. Consequently, controllers cannot make
interleave adjustments to maximize usage of the channel and
DRAM resources in response 10 changing condilions in lhe
system.
12
requests. After start, the controller adjusts the interleave to
shift from minimizing latency to maximizing utilization of
the channel and internal resources of the DRAM. Therefore,
after a steady state has been achieved, the controller avoids
having too many back-to-back requests. Rather, the control-
ler switches to a smoother interleave pattern, such as the
pallern illuslrated in Appendix B. An exemplary series of
transactions that illustrate how a controller that employs the
protocol of the present invention is ahle to dynamically
The ability to vary the timing between the transmission of
a request packet and the transmission of the data specified in
the command control information makes it possible to
interleave the information on BusData[8:0] in variations that
were not previously possible. According to one embodiment
10 change the interleave of transactions shall be discussed in
greater detail below with reference to Appendix C.
of the invention, controllers dynamically adjust the inter-
leave to maximize the use of the channcl in the face of 15
internal DRAM lalencies lhal are long wilh respecl 10 lhe
transmission of control information or data.
Signal Overload
To help maximize utilization of the channel, the same
control line may be used to carry numerous control signals.
For example, in the protocol illustrated in Appendixes A and
B, the BusCt1line is used to carry wakeup signals, strobe
signals, portions of the command control information, and
terminate signals. According to one embodiment of the
Referring to Appendix A and FIG. 12, they illustrate the
timing of five non-interleaved data transfer operations. At
clock cycle 0, a wakeup signal associated with transaction 0
is transmitted from the controller to the DRAM on the
BusCt1line "BC". At clock cycles 4 through 6 the command
control information for transaction 0 is sent from the con-
troller to the DRAM over the BusCtlline and nine bus data
lines "BD8:0". At clock cycle 10 the DRAM begins sensing
the row specified in the command control information of the
bank specified in the command control information. At clock
cycle 17 the controller sends the strobe signal associated
with transaction 0 to the DRAM. At clock cycle 23 the
DRAM begins transferring data beginning at the address
specified in the command control information. At clock
cycle 30 the controller sends a terminate signal associated
with transaction 0 to the DRAM. At clock cycle 38, the
DRAM sends the last data associated with transaction O.
20 invention, clock cycles are divided into even and odd
phases. The command control information is preceded by a
non-zero value "start bit" on the BusCtlline at an even phase
of the dock cycle. Upon deteclion of a slart bil, a DRAM
knows that any signals on the BusCtlline during the three
25 subsequent odd phases of the clock cycle are part of the
command control information, and not strobe, wakeup or
terminate signals. The strobe signals, wakeup signals and
terminate signals are all indicated by non-zero values on the
BusCtlline at an odd phase of the clock cycle. Consequently,
30 the DRAM must have some mechanism for distinguishing
belween lhe signals.
In an embodiment of the invention that uses fixed
interleaves, an operation begins at a fixed interval relative to
35 the command control information that specifies the opera-
tion. Therefore, DRAMs simply use the arrival time of the
command control information and the known interval to
determine when to perform the operation. The terminate
The wakeup signal for transaction 1 is transmitted at clock
cycle 35. At clock cycles 39 through 41 the command
conlrol informalion for lransaclion 1 is lransmilled. The
timing for transactions 1 through 4 proceeds as illustrated.
This example clearly illustrates that there is mining timing 40
overlap between transactions when signals for different
transactions are not interleaved. Consequently, bandwidth
that may be used to begin subsequent transactions goes
unused.
Referring to Appendix B and FIG. 13, they illustrate the 45
timing of interleaved data transfer operations. In the illus-
lrated example, lhe wakeup signal for lransaction 1 is
transmitted at clock cycle 20, even before data has started to
he sent for transaction O. By the time the terminate signal has
been sent for transaction 0, the wakeup signal and command 50
control information have been sent to the DRAM for trans-
signal associated with a transaction is always the next
odd-phased signal on the BusCtlline aftcr its corresponding
command control information. Therefore, if the command
control information can be identified, the terminate signal
can also he identified. Any signal on the ilusCtl line during
an odd phase of a clock cycle is a wakeup signal.
The method described above for distinguishing between
identical control signals (i.e. control signals that use the
same line and have the same characteristics) works well in
an embodimenl that employs fixed interleaves. However,
where the timing interval between a request packet and its
corresponding strobe signal is variable, a mechanism must
be provided to indicate to the DRAMs when to look for the
strobe signal that corresponds to a request packet that has
been received.
action 1. TIle transmission of this information during the
execution of transaction 0 does not result in any perfor-
mance penalty because the bandwidth used to transfer the
informalion was olherwise unused. Significantly, five lrans-
actions are completed by clock cycle 131 using the inter-
leaved example shown in Appendix n, while completion of
five lransactions requires 172 clock cycles in lhe non-
interleaved system shown in Appendix A.
In the example illustrated in Appendix B, the period
55 between the transmission of the command control informa-
tion for a transaction and the strobe signal for the transaction
is not fixed. Consequently, the DRAM must have some other
mechanism for determining that, of all the signals that arrive
on the BusCtlline, the signal at clock cycle 47 is the strobe
The ability to dynamically adjust the interleave of control
and data information allows controllers to increase the
utilization of the channel. In addition, the controller can
adapt the interleave to the changing demands being placed
60 signal associated with the command control information for
transaction 1.
on the bus to minimize latency. For example, the controller
can transition from a cold start, where the bus is idle, to an 65
active state by issuing a series of requests back-to-back and
then waiting for the data that will be sent in response 10 the
According to one embodiment of the present invention,
the DRAM is able to distinguish between identical signals
on the BusCtlline based on knowledge of what information
has previously appeared on the channel. To obtain informa-
tion about data on the channel, the DRAM constantly
monitors the channel. Because the DRAM conslanlly moni-
Case: 13-1623 Document: 10 Page: 159 Filed: 11/04/2013
A216
US 6,591,353 B1
13
tors the channel, the controller does not have to transmit
wakeup signals to the DRAM. Therefore, the only identical
signals on the BusCtl line are the strobe signal and the
terminate signal.
According to this emhodiment, the order in which the
controller sends strobe and terminate signals must match the
order in which the controller sends request packets. For
example, if the controller transmits request packets for
transactions 0, 1, and 2, in that order, then the controller
must send strobe and terminate signals for transactions 0, 1, 10
and 2, in that order.
Under the constraints described above, the DRAM has the
information it requires to correctly identify the strobe and
terminate signals on the channel. Specifically, the first
control signal on the BusCtl line will always be a strobe 15
signal associated with the first transaction. The control
signal that follows any strobe signal is always the terminate
signal for the transaction that corresponds to the preceding
strobe signal. The control signal that follows any terminate
signal will always be a strobe signal for the transaction that 20
immediately follows the transaction associated with the
previous strobe signal.
While the approach described above allows a DRAM to
accllfately identify strobe and terminate signals, it has two 25
obvious disadvantages. First, it requires that all DRAMs
monitor the channel at all times. If any DRAM fails to
monitor the line for any period, the DRAM will not be able
to accurately identify the identical control signals. Because
the DRAM has to constantly monitor the channel, the
DRAM will not be able to conserve energy by entering a 30
power-down mode. The expense associated with keeping all
DRAMs powered up at all times is significant.
The second disadvantage is that the controller must send
the control signals in exactly the same order as the command 35
control information. As a result, the controller is limited with
respect to the type of interleave patterns it may select.
Specifically, the controller may not select any interleave
patterns that retire a transaction out of order.
According to an alternate embodiment of the present 40
invention, the controller is configured to transmit, as part of
the command control information in a request packet, data
which allows the DRAM to identify the strobe signal that
corresponds to the command control information. for
example, in one embodiment, the controller includes a 45
"Pend" value in the command control information. The Pend
14
Pend value, the DRAM is made aware that two strobe-like
signals will appear on the Busetl line prior to the actual
strobe signal for transaction 1. The DRAM monitors the
channel after the receipt of the command control informa-
tion for transaction 1. Based on the Pend information in the
command control information for transaction 1 and the
signals that occur on the channel after receipt of the com-
mand control information for transaction 1, the DRAM can
identify the strohe for transaction 1.
The Pend approach overcomes the disadvantages of the
constant channel monitoring approach because the DRAM
involved in a transaction does not need to know what
transpired on the channel prior to the arrival of the command
control information for the transaction. Consequently, a
DRAM may assume a powered down mode until the arrival
of a wakeup signal just prior to the transmission of a request
packet. In addition, the Pend approach does not require
transactions to he retired in the same order as the order in
which they are requested. Therefore, a controller may
specify interleave patterns in which some transactions are
retired out of order.
Deferred Precharge Notification
At the time that a request packet is transmitted by a
controller, the controller may not have enough information
to determine whether a precharge operation should be per-
formed after the completion of the transaction. Therefore,
according to one embodiment of the invention, the com-
mand control information sent in request packets does not
contain an indication of whether or not a precharge is to be
performed after the transaction. Rather, the controller com-
municates to the DRAM whether a precharge is to be
performed when the terminate signal that initiates the ter-
mination of a transfer operation is sent to the DRAM.
Because the transmission of the terminate signal is deferred,
the determination of whether or not a precharge operation is
appropriate may be made by the controller based on infor-
mation obtained between the transmission of the request
packet and the transmission of the terminate signal.
For example, at the time that the request packet is sent,
additional requests for data from different rows in the same
DRAM may not have arrived. Therefore, it would appear
that no post-operation precharge is required. However, prior
to the transmission of the terminate signal, a request may
arrive for an operation to be performed on a different row of
the same bank within a DRAM. When the controller sends
the terminate signal for the Cllfrent operation, the controller
can comnllUlicate to the DRAM that a precharge operation
value in a request packet indicates how many control signals
that are identical to the strobe signal will occur between the
end of the command control information for a transaction
and the actual strobe signal for the transaction. Based on the
Pend value, a DRAM is able to identify control signals
without having to know what has transpired on the channel
prior to the arrival of the command control information.
50 is to be performed. The DRAM can therefore begin a
precharge operation for the bank containing the appropriate
row while the current data transfer operation is being
completed.
The technique used by the controller to communicate
whether a precharge is to be performed after an operation
preferably takes advantage of the fact that data is typically
transferred as a series of one or more fixed-sized packets,
where each packet contains more data than can he transmit-
ted dllfing a single clock cycle. Because the transmission of
In the example illustrated in Appendix B, the command
control information for transaction 1 is sent at clock cycle 55
24, and the strobe signal for transaction 1 is sent at clock
cycle 47. Between the transmission of the command control
information for transaction 1 and the transmission of the
strohe signal for transaction 1, a terminate signal for trans-
action 0, a wakeup signal for transaction 2 and a request
packet for transaction 2 are sent. (The DRAM knows to
ignore the command control information for transaction 1 by
detecting its start bit on an even phase of the clock cycle.).
60 a single packet is performed over multiple clock cycles, the
terminate signal may be sent dllfing anyone of a plllfality of
clock cycles to specify that a particular packet is the last
packet. For example, assume that it takes four clock cycles
to send a single packet of data, and that the DRAM is The terminate signal for transaction 0 and the wakenp
signal for transaction 2 both have identical characteristics to
strobe signals. Therefore, the Pcnd value sent in the com-
mand control information for transaction 1 is two. By this
65 configured to send exactly one data packet after receipt of
the terminate signal. As long as the terminate signal is sent
at anyone of the four clock cycles during which the
Case: 13-1623 Document: 10 Page: 160 Filed: 11/04/2013
A217
US 6,591,353 B1
15
penultimate data packet is sent, the data transmission will
terminate at the appropriate time.
16
1512 corresponds to one of the control lines 1516, 1518 and
1520. Unlike the prior art decode circuit 1400, each of
decode units 1508, 1510 and 1512 receives only the signal
from one pin. Based on the signal from the pin and state
information stored in the decode unit, the decode unit
applies the appropriate signal to the control line to which it
corresponds.
The advantages of decode circuit 1500 over the prior art
circuit shown in FIG. 14 include decreased wiring
According to one embodiment of the invention, the con-
troller uses the exact timing of the terminate signal to
indicate to the DRAM whether the DRAM is to perform a
precharge operation. For example, assume that the controller
can terminate a transfer at the appropriate time hy sending
the terminate signal during anyone of four dock cycles, as
described above. The controller can indicate to the DRAM
that precharge is to he performed hy transmitting the termi-
nate signal in the first of the four possible clock cycles, and
indicate that precharge is not to be performed by transmit-
ting the terminate signal on the second of the four possible
clock cycles. The DRAM decodes the precharge information
by determining on which of the four possible clock cycles
the terminate signal appeared. The DRAM may make this
determination, for example, by determining the modulus of
the clock cycle on which the terminate signal was received
relative to the dock cycle on which the corresponding strobe
was received.
10 requirements, decreased power consumption and decreased
circuit complexity. Specifically, only one line per pin is
required to route the signals from pins 1502, 1504 and 1506
to decode units 1508, 1510 and 1512, respectively. Further,
the complexity of decoders 1508, 1510 and 1512 is signifi-
15 cantly reduccd.
For decode circuit 1500 to work correctly, the operation
codes transmitted by the controller must include bits that
directly correspond to the signals carried on lines 1516, 1518
20 and 1520. Typically, the global control lines include a
NoByteM line, a Reg line, and a Write line. The NoByteM
line indicates whether a byte mask should be used on the
data specified in the operation. The Reg line indicates
According to an alternate embodiment, a particular pre-
charge operation is associated with each of the four available
clock cycles. For example, the DRAM may contain four
banks of memory. The technique described above may be 25
extended so that a terminate signal in the first possible clock
cycle causes the DRAM to precharge the first memory bank,
a terminate signal in the second possible clock cycle causes
the DRAM to precharge the second memory bank, a termi-
nate signal in the third possible clock cycle causes the
DRAM to precharge the third memory bank, and a terminate 30
signal in the fourth possible clock cycle causes the DRAM
to pre charge the fourth memory bank. Significantly, this
embodiment allows the position of the terminate signal for
an operation on one memory bank to indicate that a pre-
charge operation is to be performed on a different memory 35
bank. In this embodiment, the command control information
may contain a bit for specifying that no precharge is to be
performed, regardless of the timing of the terminate signal.
whether the operation relates to a register or to memory. The
Write line indicates whether the operation is a read operation
or a write operation.
FIGS. 16A and 16B illustrates an operation code encoding
scheme according to an embodiment of the invention. Refer-
ring to PIGS. 16A and 16n, they illustrate an operation-to-
operation-code mapping in which bits in the operation code
directly dictate the signals to be placed on each of the global
control lines to perform the corresponding operation.
Specifically, each operation code has a bit "OP[2]" that
specifies whether a signal should be placed on the NoByteM
control line, a bit "OP[l]" that specifies whether a signal
should be placed on the Reg control line, and a bit "OP[O]"
that specifies whether a signal should be placed on the Write
control line. The operation code that corresponds to each
possible type of operation has the various operation code
Optimized Operation Encoding
Typically, a controller indicates to a DRAM the operation
40 bits set so as to cause the appropriate signals to be generated
on the global control lines. For example, to perform a
register read directed operation, a signal must be generated
on the NoByteM and Reg control lines, but not on the Write
control line. Therefore, in the operation code that corre-
it desires the DRAM to perform by transmitting to the
DRAM a request packet that includes an operation code that
corresponds to the desired operation. To determine how to
respond to a request packet, each of the bits of the operation
code must he wired from its point of reception on the I)RAM
and to a decoder prior to being globally transmilled through
the interface in order to control functionality. The wiring and
decoding process consumes space and power. A typical 50
circuit for performing operation code decoding is illustrated
45 sponds to the register read directed operation, the bits that
correspond to the NoByteM, Reg and Write control lines are
respectively "1", "1" and "0".
in FIG. 14.
Broadcast Operations
DRAMs respond to request packets if the operations
specified in the request packets are specifically directed to
the DRAM, or if the request packets specify broadcast
operations. FIG. 17 illustrates a prior art circuit for deter-
mining whether a particular DRAM should respond to an
Referring to FIG. 14, a decoding circuit 1400 includes a
plurality of pins 1402, a plurality of glohal control lines
1404, and a plurality of decode units 1406. Each decode unit
1406 corresponds to a particular global control line 1404.
When a multiple-bit operation code is received at pins 1402,
the entire operation code is routed to each of decode units
1406. Each of decode units 1406 decodes the operation code
55 operation request.
to determine the appropriate signal to apply to the control 60
line 1404 to which it. corresponds.
Referring to FIG. 15, it illustrates a decode circuit 1500
according to an embodiment of the invention. Similar to
decode circuit 1400, decode circuit 1500 includes a plurality
of pins 1502, 1504 and 1506, a plurality of decode units 65
1508, 1510 and 1512, and a plurality of global control lines
1516, 1518 and 1520. Each of decode units 1508, 1510 and
Referring to FIG. 17, a comparator 1702 compares the
address bits in an request packet with the device ID of the
DRAM. If the address hits in the request packet do not match
the device ID, then a logical LOW is transmitted to one input
of AND gate 1706. Consequently, the output of AND gate
1706 will be LOW. The operation code contained in the
request is decoded by decode unit 1704. Decode unit 1704
decodes the operation code in the request packet and trans-
mits signals over lines 1708 and 1710 based on the operation
specified by the operation code. If the operation code
represents a broadcast operation, then the decode unit 1704
applies a logical HIGH to line 1710. If the operation code
Case: 13-1623 Document: 10 Page: 161 Filed: 11/04/2013
A218
US 6,591,353 B1
17
represents a non-broadcast operation, then the decode unit
1704 transmits a signal on line 1708 indicative of the
command, and a logical LOW on line 1710. Line 1710 and
the output of AND gate 1706 are applied to an OR gate 1712.
The signal at output of OR gate 1712 determines whether the
DRAM should process the specified operation. When the
specified opera lion is a broadcasl operation, lhe oulpul of
OR gate 1712 will be HIGH regardless of the output of AND
gate 1706.
Referring to FIG. II!, it illustrates a circuit for determining
whether a DRAM should respond to request packet, accord-
ing to an embodiment of the present invention. Similar to the
circuit shown in FIG. 17, circuit 1800 includes a comparator
1802 for comparing the address bits in a request packet wit
the device ID of the DRAM. However, circuit 1800 is
configured for a prolocol in which one bil in lhe operalion
code of a request indicates whether the request is for a
hroadcast operation. Referring again to rIGS. 16A and 16TI,
lhe opera lion codes employed in one embodimenl include a
18
and performance penalty. Consequently, the present inven-
tion provides a controller that determines whether precharge
and/or sense operations are required prior to making data
transfer requests. Because the controller makes the
determination, the complexity of the DRAM is reduced
while the performance of the overall data transfer system is
improved. The conlroller makes lhe delerminalion of
whether precharge and/or sense operations are required
based on the address of the data in the operation, the current
10 state of the hank that corresponds to the address and the
address of the data that is currently stored in the bank.
Typically, this information is already maintained by the
controller for other purposes. 111erefore, little additional
overhead is required for the controller to make the determi-
15 nation.
Once the controller has made the determination for a
particular data transfer operation, the controller must com-
municale lhe decision 10 lhe DRAM. Preferably, lhe con-
troller communicates the determination to the DRAM
bit "Op[3]" that indicates whether the operation specified by 20
the operation code is a broadcast operation.
through data sent with the command control information for
the transaction. According to one embodiment of the
invention, the command control information includes two
bits ("Open" and "Close") that indicate to the DRAM what
action to take with respect to the sensing and precharging the
Because the operation code contains a bit which indicates
whether the operation is a broadcast operation, it is not
necessary to decode the operation code to determine whether
the operation is a broadcast operation. Rather, the value of
the broadcast bit is fed directly into one input of an OR gate
1804. The other input of the OR gate 1804 receives a signal
that indicates whether the address in the request matched the
device ID of the DRAM. The output of the OR gate 1804
indicates whether the DRAM should respond to the request.
Because the operation code for every type of operation
contains a bit that specifies whether the operation is a
broadcast operation, the need to decode the operation codes
to identify broadcast operations is avoided. Consequently,
circuit 1800 is clearly simpler and more efficient that the
circuit shown in l'lU. 17.
Controller-Specified State Changes
25 memory cells that correspond to the operation. Based on the
currenl bank slate and lhe value of lhe Open and Close bils,
the DRAM determines what action to perform.
In general, lhe Close bil indicales whelher 10 precharge
the memory bank after performing the operation specified in
30 the command control information, and the Open hit indi-
cates whether some type of sense or precharge/sense opera-
tion must be performed before the operation. The actions
performed in response to the Open and Close bits depends
on the previous state of the bank in question. FIG. 19
35 illustrates how the combinations of values for the Open bit,
Close bit, and previous bank slale are mapped 10 actions 10
be performed according to one embodiment of the invention.
Referring to FIG. 19, if lhe currenl bank slale is closed
and the Open and Close bits are "0" and "I", respectively,
40 then the DRAM performs no action in response to the data
transfer request. Since no action is performed, the state of
the bank remains closed. If the current bank state is closed
and the Open and Close bits are "1" and "0", respectively,
In typical DRAMs, data is not directly transmitted from
the storage cells. Rather, data is temporarily copied to sense
amplifiers prior 10 lransmission. Typically, lhe sense ampli-
fiers only store one row of data. If an operation is to be
performed on a row of data other than the currently stored
row, two operations must be performed. The first operation 45
is referred to as a precharge operation, where pairs of bit
lines within the memory are equalized to a midpoint voltage
level. The second operation is referred to as a sense
operation, where the row on which the operation is to be
performed is copied onto lhe sense amplifiers. Belween lhe 50
precharge operation and the subsequent sense operation, the
then the DRAM senses the bank and then performs the
operation specified in the command control information.
Afler lhe operalion is performed, lhe bank will be in lhe open
state. If the current bank state is closed and the Open and
Close hits are hoth "1 ", then the DRAM senses the hank,
performs the specified operation, and precharges the bank.
After these actions have been performed, the bank will be in
the closed state. If the current bank state is closed, then both
I) RAM in question is said to he in a closed state. At all other
limes, lhe DRAM is said 10 be in an open slale.
In the prior art, DRAMs are configured to determine
whether pre charge and sense operations have to be per-
formed prior to servicing a data transfer request from a
conlroller. Typically, lhe DRAM performs lhis delermina-
tion by comparing the address contained in the request
packet to the current address in the hank. If the addresses
match, then the data is transmitted from the sense amplifiers
and no precharge or sense operations are required. If the
addresses do not match, then the DRAM performs a pre-
charge and sense operation to load the sense amplifiers with
data from the appropriate row, but docs not service the data
transfer request.
'lhe overhead and complexity required for the DRAM to
perform lhe address comparison results in a signifIcanl cosl
Open and Close bits cannot be "0".
If the current bank state is open and the Open and Close
bits are both "0", then the DRAM simply performs the
55 operation specified in the command control information.
After the operation, the bank will still be in the open state.
If the current bank state is open and the Open and Close bits
are "0" and "1 ", respectively, then the DRAM performs the
command and then precharges the memory bank. After the
60 bank is precharged, it will be in the Closed state. If the
current bank state is open and the Open and Close bits are
"1" and "0", respectively, then the DRAM precharges the
bank, senses the bank, and performs the specified operation.
After the operation is performed, the bank will be in the open
65 state. If the current bank state is open and the Open and
Close bits arc both "1", then the DRAM precharges the
bank, senses the bank, performs lhe specifred operalion, lhen
Case: 13-1623 Document: 10 Page: 162 Filed: 11/04/2013
A219
US 6,591,353 B1
19
precharges the bank. After these actions have been
performed, the bank will be in the closed state.
In addition to giving the controller significantly more
control over internal DRAM operation, the present invention
establishes a one-to-many correspondence between request
packets and specified operations. Specifically, a single
request packet can cause a DRAM to perform (1) a plurality
of DRAM core operations, (2) a DRAM core operation and
a data transfer operation, or (3) a data transfer operation and
a plurality of DRAM core operations. By increasing the
number of operations performed by the DRAM in response
to a request packet, the ratio of control information per
operations performed is significantly reduced.
Line Noise Reduction
In typical DRAMs, multiple banks of memory receive
power over the same power supply line. Every precharge or
sense operation performed on a bank of memory generates
some noise on the power supply line to which the bank is
connected. In general, memory banks are not aware of
operations that are concurrently being performed by other
memory hanks. Consequently, two or more memory hanks
that are powered over the same power supply line may
concurrently perform precharge and/or sense operations.
The increased noise that the power supply line experiences
due to the concurrent execution of multiple noise-producing
operations impairs the reliability of the DRAM in question
or forces the power supply line to be larger, consuming
precious die area.
To prevent these reliability problems, those prior art
DRAMs must be exhaustively tested to ensure that all
possible sense and precharge patterns can be performed
without error. In the present invention, the DRAM includes
a control circuit that is configured to allow no more than one
bank on any given power supply line from performing
precharge or sense operations at any given time. Because the
DRAM does not allow more than one bank on a power
supply line to be charged or sensed at a time, the DRAM is
not susceptible to the noise problems that concurrent sense
and precharge operations create. Further, the DRAM does
not need to be tested for patterns that will never occur. In
addition, the die size of the DRAM may he reduced hecause
the power supply lines do not have to be able to handle
current for more than one operation. The control circuit
within the DRAM may enforce this restriction in a variety of
ways.
In one embodiment, the control circuit includes a queue
20
power supply line 2014. Therefore, control circuitry 2002
will place both operations in the queue 2016 associated with
power supply line 2014.
rhe control circuit 2002 services the operations in any
given queue one at a time. Thus, in the example given above,
the control circuitrv 2002 may cause the operation on bank
2010 to be perfori'ned, then 'cause the operation on bank
2012 to be performed. Because the operations are serviced
sequentially, no more than one sense or precharge operation
10 will be performed concurrently on banks connected to the
same power supply line. Because the control circuitry 2002
maintains separate queues for each power supply line,
precharge and sense operation may be perform concurrently
on hanks that are powered hy different power supply lines
within the same DRAM 2000. In this embodiment, the
15 controller 2004 is preferably configured to set the Open and
Close bits in each request packet to prevent the queues
associated with the power supply lines from overflowing.
In an alternate embodiment, control circuitry 2002 is
configured to ignore request packets for operations that
20 require a sense or precharge operation to be performed on a
hank that is connected to the same power supply line as
another bank on which a sense or precharge operation is
currently being performed. In yet another embodiment,
control circuitry 2002 does not process request packets that
25 would violate the restriction, but transmits a message back
to the controller 2004 to indicate that the request packet will
not be serviced.
While a prohibition against concurrent sense and pre-
charge operations by banks on the same power supply line
30 limits the amount of concurrency that can take place
between the memory banks, the overall architecture of the
present invention is designed to maximize channelutiliza-
tion without violating this restriction. Specifically, the con-
troller adjusts the interleave of transactions in such a way as
to maximize usage of the channel. No amount of concllf-
35 rency within a DRAM will increase the throughput of a
chan'ne1 that is already fully utilized. Therefore, the enforce-
ment of a prohibition against concurrent sense and precharge
operations by banks on the same power supply line docs not
detrimentally affect the performance of the data transport
40 system.
In an alternate embodiment illustrated in FIG. 20B, the
DRAM 2000 contains a single queue 2050. All operations
that require the DRAM 2000 of FIG. 20B to perform a
precharge or sense operation on any memory bank within
45 DRAM 2000 of FIG. 20B are placed in the queue 2050 by
control circuitrv 2002. The control circuitry 2002 processes
the operations "stored in the queue 2050 sequentially, pre-
venting more than one precharge or sense operation from
being performed at the same time. While this embodiment
for each power supply line. Such an embodiment is illus-
trated in FIG. 20A. Referring to FIG. 20A, a DRAM 2000
includes control circuitry 2002 and four memory banks
powered over two power supply lines that extend from a
bond site 2020. The control circuit 2002 receives request
packets from the controller 2004 over the channel 2008
through an lJO unit 2030. 'lbe request packets specify data
transfer operations and the memory banks on which the
operations are to be performed. The control circuit 2002 is
configured to detect when the specified operations require
precharge or sense operations. When a requested operation
requires a precharge or a sense operation, the operation is
placed on the queue associated with the power supply line to
which the memory bank specified in the request packet is
connected. For example, assume that control circuit 2002
receives a request packet that specifies an operation that
requires bank 2010 to be precharged, and a request packet 65
that specifics an operation that requires bank 2012 to be
sensed, Banks 2010 and 2012 are powered by the same
50 does not allow the concurrency that is possible with the
one-queue-per-power supply line embodiment, it requires
less complex control circuitry.
In yet another emhodiment, the control circuitry on the
DRAM does not enforce the one core operation per power
55 supply line restriction. Rather, control circuitry within the
controller is configured to transmit request packets by select-
ing an order and timing that will not cause more than one
core operation to be performed at the same time on banks
connected to the same power supply line. In this
60 embodiment, the DRAM may be manufactured with power
supply lines designed to only support one core operation at
a time, even though the DRAM itself does not enforce the
restriction.
Example of Dynamically Adjusting Interleave
Referring to Appendix C, it illustrates a series of trans-
actions in which a controller has dynamically adjusted the
Case: 13-1623 Document: 10 Page: 163 Filed: 11/04/2013
A220
US 6,591,353 B1
21 22
ing and sending data for transaction 2. In response to the
strobe signal, the DRAM begins to retrieve data from the
specified columns at clock cycle 51, and begins sending the
data over BusData[8:0J lines at clock cycle 56. The control-
ler transmits the terminate signal for transaction 2 over the
BusCtrlline at clock cycle 51. The timing of the terminate
signal indicates to the DRAM when to stop sending data [or
transaction 2. In response to the terminate signal, the DRAM
ceases to retrieve data after clock cycle 54, and ceases to
10 transfer data after clock cycle 59. A single octhyte data
packet is transmitted for transaction 2.
interleave. The controller transmits the wakeup signal for the
first transaction (transaction 0) over the BusCtr1line at clock
cycle O. The controller transmits the request packet for
transaction 0 over the BusCtr! line and the BusData[8:0J
lines from clock cycle 4 to clock cycle 6. The controller
transmits column address information over the BusEnable
line from clock cycle 8 to clock cycle 10. This col1lIlln
address information indicates the column address ofthe data
[or the second and subsequent data packets that will be
involved in the transaction. The column address of the data
for the first packet is included in the request packet. At clock
cycle 10, the controller transmits the strobe signal for
transaction O. The timing of the strobe signal indicates to the
DRAM when the DRAM is to begin retrieving and sending
data for transaction O. In response to the strobe signal, the
DRAM begins to retrieve data from the specified columns at
clock cycle 10, and begins sending the data over BusData
[8:0J lines at clock cycle 16. The DRAM first retrieves data
from the column specified in the request packet, and then
from the columns specified in the column address informa-
tion that is sent over the BusEnable line. The controller
transmits the terminate signal for transaction 0 over the
BusCtr!line at clock cycle 15. The timing of the terminate
signal indicates to the DRAM when to stop sending data for
tansaction O. In response to the terminate signal, the DRAM 25
ceases to retrieve data after clock cycle 18, and ceases to
transfer data after clock cycle 23. A total of two octbyte data
packets are transmilled [or transaction O.
The controller transmits the wakeup signal for the trans-
action 3 over the BusOr! line at clock cycle 40. The
controller transmits the request packet for transaction 3 over
15 the BusCtr!line and the BusData[8:0J lines from clock cycle
44 to clock cycle 46. The "open, no-close" parameters
contained within the request packet indicates to the DRAM
that the DRAM must perform a precharge and sense opera-
tion prior to performing the requested data transfer. Without
waiting for the strobe signal for transaction 3, the DRAM
20 performs the precharge operation from clock cycle 50 to
clock cycle 57, and the sense operation from clock cycle 58
to clock cycle 65. After the sense operation, a RAS operation
is performed from clock cycle 66 to clock cycle 73. The
controller does not transmit column address information
over the EusEnable line because transaction 3 involves only
one octbyte data packet, the column address for which is
included in the request packet. At clock cycle 66, the
controller transmits the strobe signal for transaction 3. The
timing of the strobe signal indicates to the DRAM when the The controller transmits the wakeup signal for the trans-
actionl over the BusCtr!line at clock cycle 8. The controller
transmits the request packet for transaction 1 over the
BusCtrlline and the BusData[8:0J lines from clock cycle 12
to clock cycle 14. The controller transmits column address
information over the BusEnablc line from clock cycle 20 to
clock cycle 31. This column address information indicates
the column address of the data for the second and subsequent
data packets that will be involved in the transaction. The
column address o[ the data [or the first packet is included in
the request packet. At clock cycle 22, the controller trans-
mits the strobe signal for transaction 1. The timing of the
strobe signal indicates to the DRAM when the DRAM is to
begin retrieving and sending data for transaction 1. In
response to the strobe signal, the DRAM begins to retrieve
data from the specified columns at clock cycle 23, and
begins sending the data over BusData[8:0J lines at clock
cycle 28. The DRAM first retrieves data [rom the column
specified in the request packet, and then from the columns
specified in the column address information that is sent over
the BusEnable line. The controller transmits the terminate
signal for transaction lover the BusCtr!line at clock cycle
35. The timing of the terminate signal indicates to the
DRAM when to stop sending data for transaction 1. In
response to the terminate signal, the DRAM ceases to
retrieve data after clock cycle 38, and ceases to transfer data
after clock cycle 43. A total of four octbyte data packets are
transmitted for transaction 1.
The controller transmits the wakeup signal for the trans-
action 2 over the RusCtrl line at clock cycle 211. The
controller transmits the request packet for transaction 2 over
the BusCtrlline and the BusData[8:0J lines from clock cycle
24 to clock cycle 26. The controller does not transmit
column address information over the BusEnable line
because transaction 1 involves only one octbyte data packet,
the column address for which is included in the request
packet. At clock cycle 50, the controller transmits the strobe
signal for transaction 2. The timing of the strobe signal
indicates to the DRAM when the DRAM is to begin retriev-
30 DRAM is to begin retrieving and sending data for transac-
tion 3. In response to the strobe signal, the DRAM begins to
retrieve data [rom the specified columns at clock cycle 66,
and begins sending the data over BusData[8:0J lines at clock
cycle 72. The controller transmits the terminate signal for
transaction 3 over the EusCtrl line at clock cycle 67. The
35 timing of the terminate signal indicates to the DRAM when
to stop sending data [or transaction 3. In response to the
terminate signal, the DRAM ceases to retrieve data after
clock cycle 70, and ceases to transfer data after clock cycle
75. A total of one octbyte data packet is transmitted for
40 transaction 3.
The controller transmits the wakeup signal for the trans-
action 4 over the BusCtrl line at clock cycle 48. The
controller transmits the request packet for transaction 4 over
the BusCtr1line and the BusData[8:0J lines from clock cycle
45 52 to clock cycle 54. The controller does not transmit
column address information over the BusEnable line
because transaction 1 involves only one octbyte data packet,
the column address for which is included in the request
packet. At clock cycle 58, the controller transmits the strobe
50 signal for transaction 4. The timing of the strobe signal
indicates to the DRAM when the DRAM is to begin retriev-
ing and sending data for transaction 4. In response to the
strohe signal, the DRAM hegins to retrieve data from the
specified columns at clock cycle 59, and begins sending the
55 data over BusData[8:0J lines at clock cycle 64. The control-
ler transmits the terminate signal for transaction 4 over the
BusCtrlline at clock cycle 59. The timing of the terminate
signal indicates to the DRAM when to stop sending data for
transaction 4. In response to the terminate signal, the DRAM
ceases to retrieve data after clock cycle 62, and ceases to
60 transfer data after clock cycle 67. A single octbyte data
packet is transmitted for transaction 4.
The transactions described above illustrate how the pro-
tocol employed by the present invention enables a controller
to dynamically adjust numerous parameters relating to the
65 timing and interleave of signals on the channel. For
example, each of the transactions illustrates how the con-
troller uses strobe and terminate signals to determine the
Case: 13-1623 Document: 10 Page: 164 Filed: 11/04/2013
A221
US 6,591,353 B1
23
timing and size of data transfers. Thus, the size of the request
packets for     1 and transaction 3 are equal, but four
times as mu(;h data is transmilled in transadion 1 as in
transaction 3 because of the relative delay between the
strobe and terminate signals for transaction 1.
In addition, the controller can dynamically adjust the time
between a request packet and the transmission of the data
associated with the request. For example, three clock cycles
elapse between the transmission of the request packet and
the transmission of the strohe signal that dictates when the 10
DRAM starts to send data for transaction O. In contrast,
twenty-one clock cycles elapse between the transmission of
the request packet for transaction 2 and the strobe signal that
dictates when the DRAM starts to send data for transaction
2.
24
allowing any given set of data transactions to be completed
within a shorter period of time.
In the foregoing spe(;i[l(;alion, the invention has been
described with reference to specific embodiments thereof. It
will, however, be evident that various modifications and
changes may be made thereto without departing from the
broader spirit and scope of the invention. The specification
and drawings are, a(;(;ordingly, to be regarded in an illus-
trative rather than a restrictive sense.
APPENDIX A
Explanation of Transaction Templates
1.0 Introduction
This appendix contains a transaction template that shows
the information that is communicated over a channel and the
internal DRAM core states that occur during a series of
transactions.
Timing information proceeds down the template, with
each horizontal row representing a clock cycle or two bus
samples. Each row represents 4 ns at 500 MHz or 3.75 ns at
533 MHz.
1.1 Clk Cyc Column
Because the controller is able to adjust the time between 15
the transmission of a request packet of a transaction and the
transmission of data involved in the transaction, the con-
troller can delay the transmission of data to allow the
(;hannel to be used for other purposes prior to the transmis-
sion of data. For example, the only signals sent over the 20
BusCtrl and BusData[8:0] lines between the request packet
for transaction 0 and the strobe for transaction 0 is a wakeup
signal for transaction 1. Therefore, the strobe signal for
transaction 0 is sent three clock cycles after the request
packet for transaction O. In contrast, the signals sent over the
BusCtrl and BusData[8:0] lines between the request packet
for transaction 2 and the strobe signal for transaction 2
include the data for transaction 1, the terminate signal for
transadion 1, the wakeup signal for transadion 3, the
request packet for transaction 3 and the wakeup signal for
transaction 4. To allow all of this information to be sent
before the data for transaction 3, the strobe signal for
transaction 3 is not sent until 24 clock cycles after the
25 The first column, labeled clock cycles, represents the time
in clock cycles since the beginning of this template.
1.2 BE Column
The 2nd column labeled BE, is the state of the BusEnable
pin during that clock cycle. BusEnable is only used to send
30 serial addresses to the RDRAM.
request packet for transaction 3. .
'lhe transactions illustrated in Appendix C also illustrate
that the protocol of the present invention enables a controller 35
to alter the retirement order of transa(;lions. In a typi(;al
DRAM system, transactions are serviced in the same order
in which they are requested. However, the protocol of the
present invention enables a controller to retire transactions
out of order. In the example illustrated in Appendix C, the 40
requesl pa(;ket for transadion 3 is transmiLled at do(;k (;yde
1.3 BC Column
The 3rd column labeled BC, is the state of the BusCtrl pin
during that clock cycle. BusCtrl is used to send request
packets, strobe, terminate and wakeup information. During
a request packet, this fields identifies the request number, so
requests and data (;an be lra(;ked, the requesl lype, and the
value of the Pend field for that transaction. For wakeup,
strobes, and terminates it also indicates which transaction is
being started, strobed and terminated, by the value carried
with it, i.e. (strobe 0)
1.4 BD[8:0] Column
The 4th column, labeled BD[8:0], is the state of the
BusData wires during that clock cycle. During the data
packet it indicates the transaction number and the octbyte
44 and the request packet for transaction 4 is transmitted 8
clock cycles later at clock cycle 52. However, the strobe to
start the data transfer for transaction 4 is transmitted at clock
cycle 58, while the strobe to start the data transfer for
transa(;lion 3 is not transmilled until do(;k (;yde 66.
Consequently, transaction 4 is completely retired before the
transmission of the data involved in transaction 3 even
begins.
The transactions illustrated in Appendix C also illustrate
that the protocol of the present invention enables a controller
to adiust the interleave in a manner that causes the number
45 heing sent or received. During request packets it indicates
the stale of the (;ontrol bits Open and Close. These bits are
used to tell the RDRAM what core operations to perform.
The state that is assumed for the bank being accessed and the
addressed bank is also included in the last field of a request
50 packet.
of tra'nsactions outstanding on the channel to vary over time.
For example, at clock cycle 15, two transactions have been
requested and none have been completed. Thus, two 55
requests are outstanding. At clock cycle 55, five transactions
have been requested and two have been completed. Thus,
three are outstanding.
As explained above, the protocol of the present invention
enables a controller to dynamically adjust (1) the time at
which data is sent relative to the time at which it is 60
requested, (2) the retirement order of transactions, and (3)
1.5 DRAM Internal Stale Columns
The 5th through 9th Columns represent the activity in an
RDRAM labeled 0, with the 5th column being it's CAS
activity, and the next four being the activity or state of each
of the 4 banks (Bank[0:3]). The 10th through 14th Columns
represent the a(;tivity in any other RDRAM, labeled 1, with
the 10th column being it's CAS activity, and the next four
being the activity or state of each of the 4 banks (Bank[0:3]).
1.6 Column Encoding
The column encodings consist of two numbers. The first
is the request number. The se(;ond is the odbyte number.
1.7 Bank[0:3] Encodings
the number of outstanding requests. In addition, the proto(;ol
enables a controller to dictate the core operations to be
performed by the DRAM, and the sequence in which the
DRAM is to perform the core operations. The enhanced
channel control bestowed by the protocol gives the control-
ler the llexibililY ne(;essary to maximize the (;hannel usage,
These columns include a symbol that represents an opera-
65 tion and the number of the transaction that caused the
operation. The meaning of the symbols is given in the table
below.
Case: 13-1623 Document: 10 Page: 165 Filed: 11/04/2013
A222
US 6,591,353 B1
25 26
Symbol Name Meaning Length
p Precharge Precharge is the closing of a page (deassertion of RAS) 8 Clock,
and can be caused by closing at the end of a transaction,
or opening a page that has not previously been precharged
Sense Sense is the operation of loading the sense amps to prepare 8 Clocks
for a CAS and is caused by a command with Open required
RAS RAS always follows the sense, and is needed to 8 Clocks
insure that the minimum RAS low time of the core is met.
Non-interleaved prcchargcd 4 oct 1 bank RWWRR
Clk 10 Bank !1 Bank
Cye BE BC BD r8:01 !Col L !Col 2 3:
wakeup 0
req 0 open
read close
pend 0 precharged 0
9
10 sO
11 sO
12 sO
13 sO
14 sO
15 o 1 sO
16 o 1 sO
17 o 1 strobe 0 sO
18 o 1 00 rO
19 02 00 fO
20 02 00 rO
21 02 00 rO
22 02 turn o 1 rO
23 03 data 0 0 o 1 rO
24 03 data 0 0 o 1 rO
25 03 data 0 0 o 1 rO
26 03 data 0 0 02
27 data 0 1 02
28 data 0 1 02
29 uaLa 0 1 02
30 term 0 data 0 1 03
31 data a 2 03
32 data 0 2 03
33 data 0 2 03
34 data 0 2
35 wakellp 1 data 0 3 pO
36 data 0 3 pO
37 data 0 3 pO
38 data 0 3 pO
39 req 1 open pO
40 write close pO
41 pend 0 pre charged 0 pO
42 pO
43
44 1 1
45 1 1 sl
46 1 1 sl
47 1 1 strobe 1 sl
48 1 2 data 1 0 sl
49 1 2 data 1 0 sl
50 1 2 data 1 0 sl
51 1 2 data 1 0 s1
52 1 3 dala 1 1 sl
53 1 3 data 1 1 1 0 r1
54 1 3 data 1 1 1 0 r1
55 1 :1 uaLa 1 1 1 0 r1
56 data 1 2 1 0 r1
57 data 1 2 1 1 rl
58 data 1 2 1 1 rl
59 data 1 2 1 1 r1
60 term 1 data 1 3 1 1 r1
61 data 1 3 1 2
62 data 1 3 1 2
Case: 13-1623 Document: 10 Page: 166 Filed: 11/04/2013
A223
US 6,591,353 B1
27 28
-continued
63 data 1 3 1 2
64 1 2
65 1 3
66 1 3
67 wakeup 2 1 3
68 1 3
69 pI
70 pI
71 req 2 open pI
72 wTiLe close pl
73 pend a prcchargcd 0 pI
74 pi
75 pI
76 2 1 pI
77 2 1 s2
78 2 1 s2
79 2 1 strobe 2 s2
80 22 data 2 a s2
81 22 data :2 0 s2
82 22 uaLa 2 0 s2
83 22 data 2 0 s2
84 23 data :2 1 s2
85 23 data 2 1 20 r2
86 23 data 2 1 20 r2
87 23 data :2 1 20 r2
88 data 2 2 20 r2
89 data 2 2 21 r2
90 data 2 :2 21 r2
91 data 2 2 21 r2
92 term 2 data 2 3 21 r2
93 data 2 3 22
94 data :2 3 22
95 data 2 3 22
96 22
97 23
9g 23
99 wakeup 3 23
100 23
101 p2
102 p2
103 req 3 open p2
104 read close p2
105 pend a precharged 0 p2
106 p2
107 p2
109 p2
109 s3
110 s3
111 s3
112 s3
113 s3
114 3 1 83
115 3 1 s3
116 3 1 strobe 3 s3
117 3 1 30 r3
118 32 30 13
119 32 30 r3
120 32 30 r3
121 :1 2 lum :) 1 r3
122 33 data 3 a 3 1 r3
123 33 data 3 0 3 1 r3
124 33 data 3 0 3 1 r3
125 33 data 3 a 32
126 data 3 1 32
127 data 3 1 32
128 data 3 1 32
129 term 3 data 3 1 33
130 data 3 2 33
131 uaLa 3 2 33
132 data 3 2 33
133 data 3 2
134 wakeup 4 uaLa :) :) p3
135 data 3 3 p3
136 data 3 3 p3
137 data 3 3 p3
138 req 4 open p3
139 read close p3
140 pend 0 precharged 0 p3
141 p3
Case: 13-1623 Document: 10 Page: 167 Filed: 11/04/2013
A224
US 6,591,353 B1
29 30
-continued
142
143
144 s4
145 84
146 84
147 84
148 84
149 4 1 84
150 4 1 84
151 41 sLTOhe 4 s4
152 4 1 40 r4
153 42 40 r4
154 42 40 r4
155 42 40 r4
156 42 turn 41 r4
157 43 data 4 0 41 r4
158 43 data 4 0 41 r4
159 43 data 4 0 41 r4
160 43 data 4 0 42
161 dala 4 1 42
162 data 4 1 42
163 data 4 1 42
164 term 4 data 4 1 43
165 data 4 2 43
166 data 4 2 43
167 data 4 2 43
168 data 4 2
169 data 4 3 p4
170 data 4 3 p4
171 data 4 3 p4
172 data 4 3 p4
173 p4
174 p4
175 p4
176 p4
APPENDIX B being sent or received. During request packets it indicates
Explanation of Transaction Templates
1.0 Introduction
111is appendix contains a transaction template that shows
the information that is communicated over a channel and the
35 the state of the control bits Open and Close. These bits are
used to tell the RDRAM what core operations to perform.
The state that is assumed for the bank being accessed and the
addressed hank is also included in the last field of a request
internal DRAM core states that occur during a series of 40
transactions.
Timing information proceeds down the template, with
each horizontal row representing a clock cycle or two bus
samples. Each row represents 4 ns at 500 MHz or 3.75 ns at
533 MHz.
1.1 Clk Cyc Column
The first column, laheled clock cycles, represents the time
in dock cycles since the beginning of this template.
45
packet.
1.5 DRAM Internal State Columns
The 5th through 9th Columns represent the activity in an
RDRAM labeled 0, with the 5th column being it's CAS
activity, and the next four being the activity or state of each
of the 4 banks (Bank[0:3]). The 10th through 14th Columns
represent the activity in any other RDRAM, labeled 1, with
1.2 BE Column
111e 2nd column labeled BE, is the state of the BusEnable
pin during that clock cycle. BusEnable is only used to send
serial addresses to the RDRAM.
50 the 10th column being it's CAS activity, and the next four
being the activity or state of each of the 4 banks (Bank[0:3]).
1.3 BC Column
The 3rd column labeled BC, is the state of the BusOr! pin 55
during that clock cycle. BusOr! is used to send request
packets, strohe, terminate and wakeup information. During
a request packet, this fields identifies the request number, so
requests and data can be tracked, the request type, and the
value of the Pend field for that transaction. For wakeup, 60
strobes, and terminates it also indicates which transaction is
being started, strobed and terminated, by the value carried
with it, i.e. (strobe 0)
1.6 Column Encoding
The column encodings consist of two numbers. The first
is the request numher. The second is the octhyte numher.
1.7 Bank[0:3] Encodings
1.4 BD[8:0] Column
The 4th column, labeled BD[8:0], is the state of the
BusData wires during that clock cycle. During the data
packet it indicates the transaction number and the octbyte
These columns include a symbol that represents an opera-
65 tion and the number of the transaction that caused the
operation. The meaning of the symbols is given in the table
below.
Case: 13-1623 Document: 10 Page: 168 Filed: 11/04/2013
A225
US 6,591,353 B1
31 32
Symbol Name Meaning Length
p Precharge Precharge is the closing of a page (deassertion of RAS) 8 Clock,
and can be caused by closing at the end of a transaction,
or opening a page that has not previously been precharged
Sense Sense is the operation of loading the sense amps to prepare 8 Clocks
for a CAS and is caused by a command with Open required
RAS RAS always follows the sense, and is needed to 8 Clocks
insure that the minimum RAS low time of the core is met.
Interleaved prccharged 4 oct 2 bank RWWRWWRRR
Clk 10 Bank !1 Bank
Cye BE BC BD r8:01 !Col L !Col 2 3:
wakeup 0
req 0 open
read close
pend 1 precharged 0
9
10 sO
11 sO
12 sO
13 sO
14 sO
15 sO
16 sO
17 sO
18 00 rO
19 00 fO
20 o 1 wakeup 1 00 rO
21 o 1 00 rO
22 o 1 strobe 0 00 rO
23 o 1 00 rO
24 02 reg 1 open 00 rO
25 02 write close 00 rO
26 02 pend 2 precharged 1 00
27 02 turn o 1
26 03 data 0 0 o 1
29 0:1 uaLa 0 0 01
30 03 data 0 0 o 1 sl
31 03 data 0 0 02 s1
32 data 0 1 02 81
33 data 0 1 02 sl
34 data 0 1 02 s1
35 term 0 data 0 1 03 sl
36 data 0 2 03 sl
37 duta 0 2 03 sl
38 data 0 2 03 r1
39 data 0 2 r1
40 wakeup 2 data 0 3 pO r1
41 data 0 3 pO r1
42 uaLa 0 :) pO ,1
43 data 0 3 pO r1
44 1 1 req 2 open pO r1
45 1 1 write close pO rl
46 1 1 pend 2 precharged 0 pO
47 1 1 strobe 1 pO
46 1 2 data 1 0
49 1 2 data 1 0
50 1 2 data 1 0 s2
51 1 2 data 1 0 s2
52 1 3 dala 1 1 82
53 1 3 data 1 1 1 0 s2
54 1 3 data 1 1 1 0 s2
55 1 :1 uaLa 1 1 1 0 s2
56 data 1 2 1 0 s2
57 data 1 2 1 1 82
58 data 1 2 1 1 r2
59 data 1 2 1 1 r2
60 term 1 data 1 3 1 1 r2
61 data 1 3 1 2 r2
62 data 1 3 1 2 r2
Case: 13-1623 Document: 10 Page: 169 Filed: 11/04/2013
A226
US 6,591,353 B1
33 34
-continued
63 data 1 3 1 2 r2
64 2 1 req 3 open 1 2 r2
65 2 1 read close 1 3 r2
66 2 1 pend 3 precharged 1 1 3
67 2 1 strobe 2 1 3
68 22 data 2 0 1 3
69 22 data 2 0 pI
70 22 data 2 0 pI
71 22 data:2 0 pI
72 2 :1 uaLa 21 pl
73 23 data 2 1 20 pI
74 23 data :2 1 20 pI
75 23 data 2 1 20 pI
76 data 2 2 20 pI
77 data 2 :2 21
78 data 2 2 21 s3
79 data 2 2 21 s3
80 term :2 data 2 3 21 s3
81 data :2 3 22 s3
82 uaLa 2 3 22 83
83 data 2 3 22 s3
84 22 s3
85 23 83
86 23 r3
87 23 r3
88 3 1 wakellp 4 23 r3
89 3 1 30 p2 r3
90 3 1 strobe 3 30 p2 r3
91 3 1 30 p2 r3
92 32 req 4 open 30 p2 r3
93 32 write close 30 p2 r3
94 32 pend :2 precharged 0 30 p2
95 32 tUlll 3 1 p2
96 33 data 3 0 3 1 p2
97 33 data 3 0 3 1
9g 33 data 3 0 31 84
99 33 data 3 0 32 s4
100 data 3 1 32 s4
101 data 3 1 32 s4
102 data 3 1 32 s4
103 term 3 data 3 1 33 s4
104 data 3 2 33 s4
105 data 3 2 33 s4
106 data 3 2 33 r4
107 data 3 2 r4
109 wakeup 5 uaLa 3 3 r4 p3
109 data 3 3 r4 p3
110 data 3 3 r4 p3
111 data 3 3 r4 p.'
112 4 1 req 5 open r4 p3
113 4 1 write close r4 p3
114 4 1 pend 2 precharged 1 p3
115 4 1 strobe 4 p3
116 42 data 4 0
117 42 data 4 0
118 42 data 4 0 85
119 42 data 4 0 s5
120 43 data 4 1 s5
121 43 uaLa 41 40 s5
122 43 data 4 1 40 s5
123 43 data 4 1 40 s5
124 data 4 2 40 85
125 data 4 2 41 s5
126 data 4 2 41 r5
127 data 4 2 41 r5
128 terill 4 data 4 3 41 r5
129 data 4 3 42 r5
130 data 4 3 42 r5
131 uaLa 4 3 42 r5
132 5 1 req 6 open 42 r5
133 5 1 read close 43 r5
134 51 pend 0 pTecharged 0 43
135 5 1 strobe 5 43
136 52 data 5 0 43
137 52 data 5 0 p4
138 52 data 5 0 p4
139 52 data 5 0 p4
140 53 data 5 1 p4
141 53 data 5 1 50 p4
Case: 13-1623 Document: 10 Page: 170 Filed: 11/04/2013
A227
US 6,591,353 B1
35 36
-continued
142 53 data 5 1 50 p4
143 53 data 5 1 5U p4
144 data 5 2 50 p4
145 data 5 2 5 1
146 data 5 2 5 1 86
147 data 5 2 5 1 86
148 terill 5 data 5 3 5 1 sG
149 data 5 3 52 86
150 data 5 3 52 86
151 uaLa 5 :) 52 so
152 52 86
153 53 86
154 53 r6
155 53 r6
156 6 1 wakeup 7 5 3 r6
157 6 1 6 a r6 p5
158 6 1 strobe 6 6 a r6 p5
159 6 1 6 a r6 p5
160 6 2 req 7 open 6 a r6 p5
161 62 read close 6 a r6 p5
162 62 pend 2 prcchargcd 1 6 a p5
163 62 turn 6 1 p5
164 6 3 data 6 0 6 1 p5
165 6 3 data 6 0 6 1
166 6 3 data 6 0 6 1 87
167 6 3 data 6 0 62 s7
168 data 6 1 62 87
169 data 6 1 62 87
170 data 6 1 62 87
171 term 6 data 6 1 63 87
172 data 6 2 63 87
173 data 6 2 63 87
174 data G 2 G 3 17
175 data 6 2 70 r7
176 data 6 3 70 p6 r7
177 data 6 3 70 p6 r7
178 data 6 3 70 p6 r7
179 data 6 3 70 p6 r7
180 70 p6 r7
181 70 p6 r7
IgZ 7U p6
183 70 p6
184 7 1 wakeup 8 70
185 7 1 70
186 7 1 strobe 7 70
187 71 70
188 72 req 8 open 70
189 72 read close 70
190 72 pend 2 precharged 0 70
191 72 turn 71
192 73 data 7 0 7 1
193 73 data 7 0 71
194 73 data 7 0 71 88
195 73 data 7 0 72 88
196 data 7 1 72 88
197 data 7 1 72 s8
198 data 7 1 72 88
199 term 8 data 7 1 73 88
200 uaLa 7 2 73 s?<;
201 data 7 2 73 88
202 data 7 2 73 r8
203 data 7 2 80 r8
204 8 1 wakeup 9 data 7 3 80 r8 p7
2U5 g 1 data 7 3 gU rg p7
206 8 1 strobe 8 data 7 3 80 r8 p7
207 8 1 data 7 3 80 18 p7
208 82 80 r8 p7
209 82 80 r8 p7
210 82 80 p7
211 82 turn 8 1 p7
212 83 data 8 0 8 1
213 g :1 uaLa g 0 81
214 83 data 8 0 8 1
215 83 data 8 0 82
216 data 8 1 82
217 data 8 1 82
218 data 8 1 82
219 term data 8 1 83
220 data 8 2 83
Case: 13-1623 Document: 10 Page: 171 Filed: 11/04/2013
A228
US 6,591,353 B1
221
222
223
224
225
226
227
228
229
230
231
data 8 2
data g 2
data 8 2
data 8 3
data 8 3
data 8 3
data 8 3
37
-continued
p8
p8
p8
p8
p8
p8
pR
p8
Al'l'ENDlX C
Explanation of Transaction Templates
1.0 Introduction
38
15 being started, strobed and terminated, by the value carried
with it, i.e. (strobe 0)
1.4 BD[8:0] Column
This appendix contains a transaction template that shows
the information that is communicated over a channel and the 20
The 4th column, labeled BD[8:0], is the state of the
BusData wires during that clock cycle. During the data
packet it indicates the transaction number and the octbyte
being sent or received. During request packets it indicates internal DRAM core states that occur during a series of
transactions.
Timing information proceeds down the template, with
each horizontal row representing a clock cycle or two bus
samples. Each row represents 4 ns at 500 MHz or 3.75 ns at
533 MHz.
1.1 Clk Cyc Column
The first column, labeled clock cycles, represents the time
in clock cycles since the beginning of this template.
1.2 BE Column
The 2nd column labeled BE, is the state of the BusEnable
pin during that clock cycle. BusEnable is only used to send
serial addresses to the RDRAM.
1.3 lIC Column
'lhe 3rd column labeled BC, is the state of the BusCtrl pin
during that clock cycle. BusOr! is used to send request
packets, strobe, terminate and wakeup information. During
a request packet, this fields identifies the request numher, so
requests and data can be tracked, the request type, and the
value of the Pend field for that transaction. For wakeup,
strobes, and terminates it also indicates which transaction is
Symbol Name
the state of the control bits Open and Close. These bits are
used to tell the RDRAM what core operations to perform.
The state that is assumed for the bank being accessed and the
25 addressed bank is also included in the last ficld of a request
packet.
1.5 DRAM Internal State Columns
The 5th through 9th Columns represent the activity in an
RDRAM laheled n, with the 5th column heing it's CAS
30 activity, and the next four being the activity or state of each
of the 4 banks (Bank[O:3]). The 10th through 14th Columns
represent the activity in any other RDRAM, labeled 1, with
the 10th column being it's CAS activity, and the next four
35
being the activity or state of each of the 4 banks (Bank[O:3]).
1.6 Column Encoding
The column encodings consist of two numbers. The first
is the request number. The second is the octbyte number.
1.7 Bank[O:3] Encodings
These columns include a symhol that represents an opera-
40 tion and the number of the transaction that caused the
operation. The meaning of the symbols is given in the table
below.
Meaning Length
p Precharge Precharge is the closing of a page (deassertion of RAS) 8 Clocks
Clk
Cye
2
3
4
7
8
anu can be caused by dosing aL Lhe enu of a Lram;aclion,
or opening a page that has not previousl y been prcchargcd
Sense Sense is the operation of loading the sense amps to prepare 8 Clocks
for a CAS and is caused hy a command with Open required
RAS RAS always follows the sense, and is needed to 8 Clocks
insure that the minimum RAS low time of the core is met.
Vary data size, retirement order, outs tan dig requests, data time
:0 Bank !1 Bank
BE BC BD l8:0J :Col 2 lCol 2 31
wakeup 0
req U no-open
read no-close
pend 1 sensed 0
o 1 wakeup 1
Case: 13-1623 Document: 10 Page: 172 Filed: 11/04/2013
A229
US 6,591,353 B1
39
-continued
o 1
10 U 1 strobe U
11 o 1 00
12 req 1 no-open 00
13 read no-close 00
14 pend 2 sensed 0 00
15 terill 0 tUlll o 1
16 data 0 0 o 1
17 data 0 0 o 1
lR uaLa 0 0 01
19 data 0 0
20 1 1 wakeup 2 data 0 1
21 1 1 data 0 1
22 1 1 strobe 1 data 0 1
23 1 1 data 0 1 1 0
24 1 2 req 2 no-open 1 0
25 1 2 read no-close 1 0
26 1 2 pend 3 sensed 0 1 0
27 1 2 turn 1 1
28 1 3 dala 1 0 1 1
29 1 3 data 1 0 1 1
30 1 3 data 1 0 1 1
31 1 3 data 1 0 1 2
32 data 1 1 1 2
33 data 1 1 1 2
34 data 1 1 1 2
35 term 1 data 1 1 1 3
36 data 1 2 1 3
37 data 1 2 1 3
38 data 1 2 1 3
39 data 1 2
40 wakeup 3 data 1 3
41 data 1 3
42 data 1 3
43 data 1 3
44 req ., open
45 read no-close
46 pend 5 sensed 0
47
48 wakeup 4
4Y
50 strobe 2 p3
51 terill 2 20 p3
52 req 4 no-open 20 p3
53 read no-close 20 p3
54 pend 0 sensed n 20 p:1
55 turn p3
56 data 2 0 p3
57 data 2 0 p3
58 strobe 4 data 2 0 s3
5Y term 4 data 2 0 s3 --- 4 U
60 83 --- 40
61 s3 --- 40
62 s3 --- 40
63 turn s3
64 data 4 0 s3
65 data 4 0 s3
66 strobe 3 data 4 0 30 r3
67 Lerm :1 JaLa 4 0 30 r3
68 30 r3
69 30 r3
70 30 r3
71 turn r3
72 data 3 U r3
73 data 3 0 r3
74 data 3 0
75 data 3 0
What is claimed is:
1. A method of operation in a memory device that includes
a plurality of memory cells, the method comprising:
receiving a command to sample data;
deferring sampling a first portion of the data until an
external strobe signal is detected; and
sampling the first portion of the data from an external
signal line in response to detecting the external strobe
signal.
40
60 2. The method of claim 1, wherein the first portion of the
data is sampled synchronously with respect to an external
clock signal.
3. The method of claim 2, further comprising sampling a
second portion of the data synchronously with respect to the
external clock signal, wherein the first portion of the data is
65 sampled during an odd phase of the external clock signal,
and the second portion of the data   ~ sampled during an even
phase of the exlernal dock signal.
Case: 13-1623 Document: 10 Page: 173 Filed: 11/04/2013
A230
US 6,591,353 B1
41
4. The method of claim 3, wherein the first and second
portions of the data are both sampled during a first clock
cycle of the external clock signal.
5. The method of claim 1, further comprising:
detecting an external terminate signal; and
sampling additional portions of the data during a time
interval between detection of the external strobe signal
and detection of the external terminate signal.
6. The method of claim 1, wherein the external strobe
signal is detected using an external clock signal. 10
7. The method of claim 1, wherein the command to
sample data comprises a write operation code bit.
8. The method of claim 1, wherein the command to
sample data is included in a write request packet.
9. The method of claim 1, wherein the command to 15
sample data comprises:
precharge information that specifies whether to precharge
sense amplifiers used in storing the first portion of the
data in the plurality of memory cells; and
address information that specifies where to store the first
portion of the data.
10. The method of claim 1, further comprising:
detecting an external terminate signal; and
20
sampling additional portions of the data during a plurality 25
of clock cycles of an external clock signal that elapse
bel ween detection of the external strobe signal and
detection of the external terminate signal.
11. A method of controlling a memory device that
includes a plurality of memory cells, the method compris- 30
ing:
42
15. The method of claim 11, fllfther comprising sampling
data from another memory device during the first time
period, wherein the data sampled from the other memory
device corresponds to a read operation.
16. The method of claim 11, wherein the first write
command is included in a write request packet.
17. The method o[ daim 11, further comprising:
issuing a terminate signal to the memory device; and
issuing additional portions of the data to the memory
device during a plllfality of clock cycles of an external
clock signal that elapse between issuance of the strobe
signal and issuance of the terminate signal.
18. The method of claim 11, further comprising issuing a
second write command to another memory device during the
first period.
19. A memory device having a plurality of memory cells,
the memory device comprising:
a plurality of input receiver circuits to receive a write
command and sample data that corresponds to the write
command in response to detecting a strobe signal that
is delayed relative to the write command by a first time
period.
20. The memory device of claim 19, further comprising a
clock generator circuit coupled to the plllfality of input
receiver circuits, the clock generator circuit receiving an
external dock signal wherein the data is sampled synchro-
nously with respect to the external clock signal.
21. The memory device of claim 19, wherein the plurality
of input receiver circuits sample a first portion of the data
and a second portion of the data, wherein the first portion of
the data is sampled during an odd phase of an external clock
signal, and the second portion of the data is sampled during
issuing a first write command to the memory device, the
memory device being configured to defer sampling data
that corresponds to the first write command until a
strobe signal is detected;
35 an even phase of the external clock signaL
delaying for a first time period after issuing the write
command; and
after delaying [or the first time period, issuing the strobe
signal to the memory device to initiate sampling of a
first portion of the data by the memory device.
12. The method of claim 11, further comprising issuing
the first portion of the data and a second portion of the data
to the memory device, wherein the first portion of the data
22. The memory device of daim 21, wherein the first and
second portions of the data are both sampled during a first
clock cycle of the external clock signal.
23. The memory device of daim 19, wherein the plurality
40 of input receiver circuits receive additional portions of the
data before detection of a terminate signal.
24. The memory device of claim 19, wherein the plurality
of input receiver circuits further receive:
precharge information that specifics whether to precharge
sense amplifiers used in storing the data that corre-
sponds to the write command; and
is sampled during an odd phase of an external clock signal, 45
and the second portion of the data is sampled during an even
phase of the external dock signal.
address information to identify where to store the data.
25. The memory device of claim 19, wherein the strohe
signal is detected synchronously with respect to an external
50 clock signal.
13. The method of claim 12, wherein the first and second
portions of the data are hoth issued during a common clock
cycle of the external clock signal.
14. The method of claim 11, further comprising:
issuing additional portions of the data to the memory
device; and
issuing a terminate signal to the memory device to signal
to the memory device to stop sampling data.
26. The memory device of claim 19, wherein the first time
period elapses during an interval spanning a plurality of
clock cycles of an external clock signaL
* * * *
Case: 13-1623 Document: 10 Page: 174 Filed: 11/04/2013

United States Court of Appeals
for the Federal Circuit
In Re Rambus, No. 2013-1623

CERTIFICATE OF SERVICE

I, Robyn Cocho, being duly sworn according to law and being over the age
of 18, upon my oath depose and say that:
Counsel Press was retained by OBLON, SPIVAK, MCCLELLAND,
MAIER & NEUSTADT, L.L.P., attorneys for Appellant to print this document. I
am an employee of Counsel Press.
On November 4, 2013, counsel for Appellant has authorized me to
electronically file the foregoing Brief for Appellant Rambus, Inc. with the Clerk
of Court using the CM/ECF System, which will serve via e-mail notice of such
filing to all counsel registered as CM/ECF users.
Additionally two copies will be served via Express Mail and email upon this
date:
Nathan K. Kelley
Acting Solicitor
Scott C. Weidenfeller
U.S. Patent & Trademark Office
Mail Stop 8
P.O. Box 1450
Alexandria, VA 22313-1450
Nathan.Kelley@uspto.gov
Scott.Weidenfeller@uspto.gov
571-272-9035
Attorneys for the U.S. Patent &Trademark Office


Upon acceptance by the Court of the e-filed document, six paper copies will
be filed with the Court, via Federal Express, within the time provided in the
Court’s rules.
November 4, 2013 /s/ Robyn Cocho
Counsel Press

Case: 13-1623 Document: 10 Page: 175 Filed: 11/04/2013


CERTIFICATE OF COMPLIANCE WITH TYPE-VOLUME
LIMITATION, TYPEFACE REQUIREMENTS AND TYPE STYLE
REQUIREMENTS

1. This brief complies with the type-volume limitation of Federal Rule of
Appellate Procedure 32(a)(7)(B).

X The brief contains 5,938 words, excluding the parts of the brief
exempted by Federal Rule of Appellate Procedure 32(a)(7)(B)(iii),or

The brief uses a monospaced typeface and contains lines of
text, excluding the parts of the brief exempted by Federal Rule of
Appellate Procedure 32(a)(7)(B)(iii).

2. This brief complies with the typeface requirements of Federal Rule of
Appellate Procedure 32(a)(5) and the type style requirements of Federal Rule of
Appellate Procedure 32(a)(6).

X The brief has been prepared in a proportionally spaced typeface using
MS Word 2007 in a 14 point Times New Roman font or

The brief has been prepared in a monospaced typeface using
in a ___ characters per inch_________ font.

Dated: November 4, 2013 /s/ Greg H. Gardella
Greg H. Gardella
OBLON SPIVAK LLP

Attorney for Appellant
Rambus, Inc.
Case: 13-1623 Document: 10 Page: 176 Filed: 11/04/2013

Sign up to vote on this title
UsefulNot useful