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Intel® Data Plane Development Kit (Intel® DPDK) Overview Packet Processing on Intel® Architecture

December 2012

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Agenda 1. Intel’s Packet Processing Motivation and Value Proposition 2. Overview of Intel® DPDK

3. Intel® DPDK Performance Benchmarks 4. Lead Ecosystem Offerings
5. Intel® DPDK Website and Collateral 6. Summary

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CID Mission “TRANSFORMING COMMUNICATIONS” ACCESS NETWORKS EDGE/CORE NETWORKS ENTERPRISE NETWORKS + Intel Architecture Ecosystem + Standards WIRELESS BASE STATION WIRELESS INFRASTRUCTURE INTELLIGENT EDGE ROUTERS AND SWITCHES MEDIA PROCESSING NETWORK APPLIANCES NETWORK SECURITY >10 Years Serving Communications and Networking Segments 4 4 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS .

Compression Next Generation Packet Processing Signal Processing NPU/ASIC Intel® Data Plane Development Kit DSP DSP Intel® Signal Processing Development Kit One Instruction Set Architecture One Tool Suite Multiple Opportunities 5 TRANSFORMING COMMUNICATIONS .4:1 Workload Consolidation Assets Unleashed by Multi-Core IA and Software 2011 Application Processing Control Processing 2012 2013 Intel® Xeon® Processor C3500/C5500 Intel® QuickAssist Software Library Intel® Communications Chipset Series 89xx for Cryptography.

multiworkload IA capability.Intel’s Data Plane Value Proposition Datacom/Telecom convergence increasing Data Plane processing requirements exponentially TCO concerns leading customers to seek single architecture design topto-bottom Intel addresses TCO and TTM concerns with single architecture. allied to an industry-leading beat-rate of process and uArchitectural advancements (Tick-Tock Model) Optimized Data Plane Software solutions will help unleash IA platform potential 6 6 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS .

000 14.The Engineering Problem Statement … 10Gbps Line Rate 16.88 Million each way 67.000 10.2 Million each way Packet arrival rate 2 GHz Clock cycles 3 Ghz Clock cycles 835 ns 1670 cycles 2505 cycles 2 GHz Clock cycles 3 Ghz Clock cycles 135 cycles 201 cycles 7 7 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS 1504 64 .000 From a CPU perspective: • A Last-level-cache (L3) hit on Intel® Xeon® processor 5500 is ~40 cycles  L3 miss.000.000 4.000. making high performance Packet Processing on IA a reality! PPS 0 136 640 100 172 208 244 280 316 352 388 424 460 496 532 568 604 676 712 748 784 820 856 892 928 964 1252 1000 1036 1072 1108 1144 1180 1216 1288 1324 1360 1396 1432 1468 Packet Size Network Infrastructure Packet Sizes Packet Size 10G Packets/second Packet arrival rate 64 bytes 14.000.000. memory read is ~70ns (201 cycles at 3 GHz)  This problem gets much worse at 40 Gb and 100 Gb rates Packets per second 12.000.000 Intel Silicon and Software advances are proactively addressing this problem statement.2 ns Typical Server Packet Sizes Packet Size 10G Packets/second 1024 bytes 1.000.000 6.000.000 8.000.000 2.

4S Configurations Intel® Hyper-Threading Technology Integrated Memory Controller(s) Integrated High BW PCIe gen3 2 QPI Links for 2S Configurations Up to 20MB of L3 Cache Intel® Pentium® 4 Processor Extreme Edition Supporting Hyper-Threading Technology Netburst microarchitecture Intel® Extended Memory 64 Technology. QuickPath. 2S.Ongoing Silicon Architectural Enhancements Packet Processing Enhancements: Pipeline Depth Direct Cache Access Integration of Memory Controller Integration of High Bandwidth PCIe Gen3 New AVX Extensions Intel® Virtualization Technology (Intel® VT) Intel® Data Direct I/O Technology (Intel® DDIO) Intel® Core™ 2 Microarchitecture Hyper-Threading. 4C. Hyperthreading Improved Packet Processing Capability 8 8 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS . 2C Product Choices 1S. Smart Cache. Power Management Intel® Xeon® processor E52600 Microarchitecture Intel® Core™ i5 / i7 Microarchitecture Enhanced Intel® Core Microarchitecture 8C. Integrated Memory Controller. SSE2/SSE3/SSE4 Instructions Multi-Core Introduction Advanced Smart Cache Wide Dynamic Execution SSE2/SSE3. 6C.

667 MHz FSB 2.33 GHz.0 GHz PCIe* Gen2 Performance Standard “off-the-shelf” IA platform can deliver huge performance.33 GHz.IA Performance over the Years IPv4 Layer 3 Forwarding on an IA Platform 90 Introduction of Integrated PCIe* Controller 80 70 Introduction of Integrated Memory Controller + Intel® DPDK 80 Mpps DPDK R1.40 GHz 2011 1S Intel® Xeon® Processor E5-2600 (B0 stepping) 1 x 8 Core 2. 1333 MHz FSB 2. Memory architecture (iMC) + Intel® DPDK 9 9 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS . 1333 MHz FSB 2009 2S Intel® Xeon® processor E5540 2 x 4 Core 2. Performance jump can be attributed to Core.1 60 50 40 30 20 10 0 Mpps 2006 2007 2008 DP Intel® Xeon® DP Intel® Xeon® DP Intel® Xeon® Processor LV Processor E5345 Processor E5410 2 x 2 Core 2 x 4 Core 2 x 4 Core 2.53 GHz 2010 2S Intel® Xeon® processor E5645 2 x 6 Core 2.0 GHz.

Compression 2010/2011 Intel® Xeon® processors E5540/E5640 2012/2013 Intel® Xeon® processor E5-2600 2013/14 Next Tick/Tock Processors 1010 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS . Compression Next Gen Chipset for Cryptography.2 128-bit SSE CRC32 Faster Cache Data Direct IO 1 GB pages Faster AES instructions Software & Hardware performance enhancements over the next 2-3 years Core Increasing Cache Sizes Increasing Core Count PCIe* Gen 2 Integrated PCI-E (Latency) PCIe* Gen 3 40G Networking silicon (Intel) Platform Increasing I/O bandwidth Increasing memory bandwidth Acceleration AES-NI instruction Intel® Communications Chipset Series 89xx for Cryptography.Evolution of Data Plane Support Integrated Memory Controller SSE 4.

Enterprise Servers Typically have Control and Data Plane on same board AdvancedTCA* Typically Control and Data Plane on different boards Value Proposition is Consolidation of DP + CP • Customers have come up with solutions to add additional 3rd party boards for Data Plane • IA can fill both roles Value Proposition single blade for multiple purposes • Normally many more Packet Processing Blades • IA allows a single Blade Architecture for both now Value proposition of Intel® DPDK is workload consolidation: Provides framework and performance for NPU workloads on IA cores 1111 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS . Control & Data Plane Environments Typically more Data Plane elements than Management/Control Plane Ecosystem or Data Proprietary Plane Packet Processing Packet Processing Processor Switch Switch Processor Packet Processing Packet Processing Intel Provided Intel® DPDK Control Plane Data Plane Processor Blade Control Plane Packet Processing Blade Data Plane Rack Mount Server.Management.

Agenda 1. Lead Ecosystem Offerings 5. Intel’s Packet Processing Motivation and Value Proposition 2. Overview of Intel® DPDK 3. Summary 1212 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS . Intel® DPDK Website and Collateral 6. Intel® DPDK Performance Benchmarks 4.

Goals of this Overview Section • Look into the Intel® DPDK architecture and see how it’s designed to squeeze the best packet processing performance out of an IA-based platform Be able to articulate the most common performance bottlenecks for packet processing software on IA Understand the optimization tricks to remove them • • 1313 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS .

all devices accessed by polling • Supports 32-bit and 64-bit with/without NUMA • Scales from Intel® Atom™ to Intel® Xeon® processors • Number of Cores and Processors not limited • Optimal packet allocation across DRAM channels Control Plane Data Plane • Must run on any IA CPU ‒ From Intel® Atom™ processor to the latest Intel® Xeon® processor family ‒ Essential to the IA value proposition Provide software examples that address common network performance deficits ‒ ‒ ‒ ‒ Best practices for software architecture Tips for data structure design and storage Help the compiler generate optimum code Address the challenges of achieving 80 Mpps per CPU Socket • Focus on the fast-path ‒ Sending large number of packets to the Linux Kernel /GPOS will bog the system down 1414 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS .The Intel® DPDK Philosophy Intel® DPDK Fundamentals • Implements a run to completion model or pipeline model • No scheduler .

1515 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS . Uses standard tool chain (gcc/icc.Run-time Environment Low overhead.BSD-licensed & source downloadable from Intel and leading ecopartners Provided under a very flexible BSD licensing model Offered as a free. eases application porting effort User Space Kernel Space Environment Abstraction Layer . Poll-Mode NIC Drivers (1/10GbE).Data Plane Libraries and Optimized NIC Drivers in Linux User Space Queue & Buffer Management. Packet Flow Classification. run-to-completion model optimized for fastest possible data plane performance Environment Abstraction Layer . gdb.Environment Abstraction Layer and Boot Code Primarily platform-specific boot guidelines and initialization code. unsupported standalone solution by Intel or as part of commercial solutions and offerings from leading ecopartners Linux Kernel Platform Hardware The Intel® DPDK is a great starting point for customers and the industry in general – delivering breakthrough packet processing performance.Intel® Data Plane Development Kit (Intel® DPDK) Intel® DPDK embeds optimizations for the IA platform: . and more! Simple API Interface. profiling tools) Intel® DPDK Libraries Buffer Management Queue/Ring Functions Customer Application Packet Flow Classification NIC Poll Mode Library Customer Application Customer Application .

• Flow Classification: Provides an efficient mechanism which incorporates Intel® Streaming SIMD Extensions (Intel® SSE) to produce a hash based on tuple information so that packets may be placed into flows quickly for processing. interrupt-based signaling mechanisms. while avoiding unnecessary wait times. thus greatly improving throughput. A pool is created in huge page memory space and uses a ring to store free objects. The Intel® DPDK pre-allocates fixed size buffers which are stored in memory pools. • Queue Manager:: Implements safe lockless queues. which greatly speeds up the packet pipeline. • Poll Mode Drivers: The Intel® DPDK includes Poll Mode Drivers for 1 GbE and 10 GbE Ethernet* controllers which are designed to work without asynchronous.Intel® DPDK Libraries and Drivers • Memory Manager: Responsible for allocating pools of objects in memory. instead of using spinlocks. that allow different software components to process packets. 1616 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS . It also provides an alignment helper to ensure that objects are padded to spread them equally on all DRAM channels. • Buffer Manager: Reduces by a significant amount the time the operating system spends allocating and de-allocating buffers.

Component Overviews • • • • EAL Memory Management Overview Queue/Ring Overview Buffer Management Overview Flow Classification Overview 1717 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS .

pools. or any other performance-critical structures • Always backed by Huge Page (2 MB/1 GB page) memory Ring: Ring: Memory Pool: mbuf_pool Memory Zone: MP_mbuf_pool RX_RING_0 TX_RING_0 Memory Zone: RG_RX_RING_0 Memory Zone: RG_TX_RING_0 Memory Segment 0 Memory Segment 1 Memory Segment N 2MB page 2MB page 2MB page 2MB 2MB page page 2MB 2MB page page 2MB 2MB page page 2MB 2MB page page 2MB 2MB page page Physically contiguous memory 1818 Physically contiguous memory Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS . LPM routing tables.Memory Usage • Basic unit for runtime object allocation is the memory zone • Zones contain rings.

single or multi.consumer enqueue/dequeue ‒ Supports bulk enqueue/dequeue to support packet-bunching ‒ Implements high & low watermark thresholds for back-pressure/flow control • Essential to optimizing throughput ‒ Used to decouple stages of a pipeline 1919 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS .Queue/Ring Management API • Effectively a FIFO implementation in software ‒ Lockless implementations for single or multi-producer.

‒ Typical usage is packet buffers. etc.The Buffer Management API (mempool) • The Buffer Manager allocates memory from the EAL and creates pools with fixed element sizes. ‒ Intent is to speed up runtime allocation/deallocation ‒ Does not support runtime resizing of pools Memory Pool Pkt Buffers (60K 2K buffers) Events (2K 100B buffers) Events (2K 100B buffers) • Multi-producer/multi-consumer safe ‒ Pools are based on Intel® DPDK rings so are multiproducer and multi-consumer safe ‒ No locking. descriptor ring buffers. use CAS instructions ‒ Pools can also be used in multi-process environments Rings for Cached buffers Data Plane Processor 0 • Optimized for performance ‒ Cache alignment ‒ Per core buffer caches for each buffer pool so that allocation/freeing can be done without using shared variables ‒ Bulk allocation/freeing support Data Plane Data Plane Data Plane Intel® DPDK C1 Intel® DPDK C2 Intel® DPDK C3 Intel® DPDK C4 10G 10G 2020 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS .

Flow Classification API • • The Intel® DPDK provides a Flow Classification API • Not expecting every customer to use it – more of a showcase to demonstrate how to do optimization for IA Classification is something that is very customer-specific – Each customer/segment has different needs ‒ ‒ Router implementations typically use “longest-prefix-match” Security implementations need to identify individual flows and can use flow classification • • • The Flow classification API is designed to take advantage of current and future hardware-based flow classification capabilities Intel® 82599 10GbE Ethernet Controller implements flow classification (limited in number of flows) Future Chipsets are expected to implement an extensive classifier 2121 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS .

30.000 ft Overview of Packet Flow 1. Initialization Initialization – Initialize memory zones and pools – Initialize devices and device queues – Start the packet forwarding application – Poll devices’ RX queues and receive packets in bursts – Allocate new RX buffers from per queue memory pools to stuff into descriptors – – Transmit the received packets from RX Free the buffers used to store the packets Polling 2. Packet Reception (RX) RX Packets to send 3. Packet Transmission (TX) TX 2222 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS .

as all external memory accesses are in cache line increments. really slow compared to CPU operation Process a bunch of packets (e.Overcoming The Challenge of Achieving 80 Mpps (and More…) Per CPU Socket Memory and PCIe* access is really. 4 packets at a time) to minimize external memory and PCIe bandwidth. Access to shared data structures is a bottleneck in the application Figure out clever access schemes that reduce the amount of sharing (e. Avoid read-modify-write transactions in favour of single write.g. The Challenge can be Overcome with Smart Programming and Hardware assists!! 2323 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS . Use CPU core isolation and thread affinities for 1:1 mapping of SW threads to HW threads. use Direct Data IO (available on Intel® Xeon® processor E5 Product Family) to read data directly into cache. The system can’t keep up with the amount of interrupts for packet Rx Switch from an interrupt-driven network device driver to a polled-mode driver. and multiple reads in favour of single read. Intel® PTU Tool indicates that page tables are constantly evicted (D-TLB Thrashing) Use 2MB or 1G Huge Pages in Linux* to reduce TLB misses. The out-of-the-box Linux* Scheduler causes too much overhead to task switch Bind a single software thread to a logical core.g. Data doesn’t seem to be near the CPU when it needs it (and so it waits) For memory access. use HW or SW controlled prefetching and align data structures to cache line size (64 Byte) to minimize external memory and PCIe* bandwidth. use lockless queues for message passing as semaphores/spinlocks are costly). for PCIe access.

PCIe* connectivity and core usage Using run-to-completion or pipeline software models NUMA Physical Core 0 Linux* Control Plane Pkt Pkt Pool Caches Queue/Rings Buffers NUMA Processor 0 QPI PCIe Pkt Pkt Pool Caches Queue/Rings Buffers Processor 1 10 GbE Physical Rx Core 0 Tx Intel® DPDK Physical Core 1 Intel® DPDK PMD Packet I/O Flow Classification 10 GbE PCIe Physical Core 1 Intel® DPDK PMD Packet I/O Packet work Rx Tx PCIe 10 GbE Pkt App A App B App C Pkt Physical PMD Packet I/O Core 2 Flow work Intel® DPDK Physical PMD Packet I/O Core 3 Flow Classification Intel® DPDK App A. B. C Physical PMD Packet I/O Core 4 Flow Classification Intel® DPDK App A. C Rx Tx 10 GbE Physical Core 2 Intel® DPDK Physical Core 3 Intel® DPDK PCIe PCIe App A App B App C Rx Tx Pkt Pkt Rx Tx 10 GbE RSS Mode Physical Core 4 Intel® DPDK Physical Core 5 Intel® DPDK Rx Tx Run to Completion model • I/O and Application workload can be handled on a single core • I/O can be scaled over multiple cores Pipeline model • I/O application disperses packets to other cores • Application work performed on other cores 2424 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS . B. B. C Physical PMD Packet I/O Core 5 Flow Classification Intel® DPDK App A.

intel.com 2525 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS .Tools for Optimizing Intel® DPDK Intel® VTune™ Amplifier XE profiles performance Intel® Performance Tuning Utility (Intel® PTU) offers specific tuning advice Download both tools at whatif.

Agenda 1. Lead Ecosystem Offerings 5. Intel’s Packet Processing Motivation and Value Proposition 2. Intel® DPDK Website and Collateral 6. Intel® DPDK Performance Benchmarks 4. Overview of Intel® DPDK 3. Summary 2626 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS .

operations and functions.2 100 50 93 Mpps DPDK R1. Any change to any of those factors may cause the results to vary. software.1 GHz PCIe Gen2 Performance 2012 2S Intel® Xeon® E5-2658 processors C1 Stepping 2 x 8 Core 2.1 GHz PCIe Gen2 Performance 2012 2S Intel® Xeon® E5-2658 processors C1 Stepping 2 x 8 Core 2. cores capability is not maxed out!! 2727 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS .2 0 Mpps 2009 2S Intel® Xeon® processor E5540 2 x 4 Core 2. such as SYSmark and MobileMark. we are still I/O limited – i. including the performance of that product when combined with other products. are measured using specific computer systems. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases.Performance Going Forward IPv4 Layer 3 Forwarding on an IA Platform 250 200 150 Introduction of Integrated Memory Controller + Intel® DPDK Introduction of Integrated PCIe* Controller Testing with PCIe* Gen3 expected to be higher 164. components. Performance tests.53 GHz 2010 2S Intel® Xeon® processor E5645 2 x 6 Core 2.e.1 GHz PCIe Gen3 Performance (Estimate ONLY) Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors.9 Mpps DPDK R1.40 GHz 2011 1S Intel® Xeon® E5-2658 processors C1 Stepping 1 x 8 Core 2. PCIe* Gen 3 will offer better performance and more options In the case of IPv4 Layer 3 forwarding.

Intel® DPDK Native and Virtualized Forwarding Performance 2828 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS .

Summary 2929 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS . Intel® DPDK Website and Collateral 6. Lead Ecosystem Offerings 5.Agenda 1. Overview of Intel® DPDK 3. Intel’s Packet Processing Motivation and Value Proposition 2. Intel® DPDK Performance Benchmarks 4.

unsupported standalone package for integration with proprietary customer stacks Data Plane Applications Dispatch Loop Services Memory & Buffer API PMD Intel® DPDK Core 1 .com/go/dpdk Intel Provided: Intel® DPDK – Free. Unsupported Package 3030 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS . visit www.n Ecosystem Provided: Intel® DPDK Integrated into Commercial Solutions and Intel® DPDK services offerings For more information about ecosystem solutions.intel.Intel® DPDK Go To Market Options Intel® DPDK free.

Intel® DPDK Performance Benchmarks 4. Summary 3131 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS . Intel® DPDK Website and Collateral 6. Lead Ecosystem Offerings 5.Agenda 1. Overview of Intel® DPDK 3. Intel’s Packet Processing Motivation and Value Proposition 2.

com/go/dpdk under Video: Intel® Data Plane Development Kit (Intel® DPDK) 3232 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS .Intel® DPDK www. Found on EDC site at www.intel. pod casts • Ecosystem information and articles Examples See the Video: “Intel® Data Plane Development Kit (Intel® DPDK)”.com/go/dpdk Your One-Stop-Shop for: • Documentation and articles.intel. white papers.

Intel® DPDK Website and Collateral 6. Summary 3333 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS . Lead Ecosystem Offerings 5. Overview of Intel® DPDK 3. Intel® DPDK Performance Benchmarks 4. Intel’s Packet Processing Motivation and Value Proposition 2.Agenda 1.

Summary Intel® DPDK enables multi-workload/single architecture potential by making IA extremely competitive for packet processing workloads Distribution of enabling software under flexible and cost-free licensing model enabling maximum customer usability Fully featured and supported IA Data Plane software solutions via Intel’s lead Ecosystem partners 3434 Intel Restricted Secret TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS .

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