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•ΩΩ


•–


–°°



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4
3
1
2
DE
D
RE
R
6
7
A
B
LOGIC DIAGRAM (POSITIVE LOGIC)
5
4
2
3
DE
D
RE
R
12
11
A
B
10
9
Y
Z
SN65MLVD202A, SN65MLVD205A
SN65MLVD200A, SN65MLVD204A

≤°

°

°
°






±

±

±

–°°

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–°

°
°

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–≤

–≤


π

π

°

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π

π

°

≤–

≤–

≤–

≤–

≤–≤

≤–

π

π

π

°

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°

°

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V
AB
or V
YZ
A/Y
B/Z
I
A
or I
Y
V
B
or V
Z
V
A
or V
Y
V
OS
V
A
+ V
B
2
V
I
D
V
CC
V
Y
+ V
Z
2
or
I
B
or I
Z
I
I
V
AB
or V
YZ
49.9 Ω
3.32 kΩ
3.32 kΩ
_
+
-1 V ≤ V
test
≤ 3.4 V
A/Y
B/Z
D
V
OS
R1
24.9 Ω
A/Y
C3
2.5 pF
V
OS(PP)
nV
OS(SS)
V
OS(SS)
≈ 1.3 V
B/Z
A/Y
≈ 0.7 V
B/Z
D
R2
24.9 Ω
C1
1 pF
C2
1 pF
V
Test
+
-
A/Y
B/Z
I
OS
0 V or V
CC
-1 V or 3.4 V

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Output
A/Y
Output
t
pLH
t
pHL
Input
C3
0.5 pF
B/Z
D
0 V
0.9V
V
0 V
t
f
t
r
V
CC
V
CC
/2
0 V
SS
SS
0 V
0.1V
SS
SS
C1
1 pF
C2
1 pF
V
P(H)
V
P(L)
R1
50 Ω
A/Y
B/Z
R1
24.9 Ω
t
pZH
t
pHZ
t
pZL
t
pLZ
V
CC
V
CC
/2
0 V
∼ 0.6 V
0.1 V
0 V
∼ -0.6 V
0 V
-0.1 V
DE
Output With
D at V
CC
Output 0 V or V
CC
DE
Output With
D at 0 V
C1
1 pF
R2
24.9 Ω
C4
0.5 pF
C2
1 pF
D
C3
2.5 pF

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A/Y
B/Z
0 V or V
CC
1.62 kΩ , ±1% V
A
, V
B
, V
Y
or V
Z
t
c(n)
1/f0
0 V
0 V
Period Jitter
0 V Diff
Peak to Peak Jitter
1/f0
PRBS INPUT
OUTPUT
V
A
-V
B
or V
Y
-V
Z
V
A
-V
B
or V
Y
-V
Z
CLOCK
INPUT
IDEAL
OUTPUT
ACTUAL
OUTPUT
V
CC
V
CC
/2
t
jit(per)
= t
c(n)
-1/f0
t
jit(pp)
0 V
V
CC
V
CC
/2
0 V
V
A
-V
B
or V
Y
-V
Z
V
A
-V
B
or V
Y
-V
Z
(V
A
+ V
B
)/2
I
O
R
V
CM
V
O
V
ID
V
A
I
A
A
B
I
B
V
B

±

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1.2 V
1.0 V
t
pLH
0.2 V
-0.2 V
V
A
V
B
V
ID
90%
V
OH
V
OL
t
pHL
10%
t
f
t
r
V
O
V
CC
/2
V
O
V
ID
V
B
V
A
C
L
0 V
15

pF


–––
––––

–––
–––


±

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15

pF
t
pZL
t
pLZ
V
OL
V
OL
+0.5 V
V
O
R
L
499 Ω
_
+
V
TEST
B
A
RE
1.2 V
Inputs
V
CC
1 V
V
CC
V
CC
/2
0 V
V
CC
V
CC
/2
V
TEST
A
RE
R
0 V
1.4 V
A
t
pZH
t
pHZ
0 V
V
OH
-0.5 V
V
CC
V
CC
/2
0 V
V
OH
V
CC
/2
RE
V
O
R
Output
V
TEST
C
L


±

±

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t
c(n)
1/f0
Period Jitter
Peak to Peak Jitter
1/f0
PRBS INPUT
OUTPUT
CLOCK INPUT
IDEAL
OUTPUT
ACTUAL
OUTPUT
t
jit(per)
= t
c(n)
-1/f0
t
jit(pp)
V
A
-V
B
INPUTS
V
A
-V
B
0.2 V - Type 1
0.4 V - Type 2
V
IC
1 V
V
OH
V
CC
/2
V
OL
V
OH
V
OL
V
CC
/2
V
OH
V
OL
V
CC
/2
V
A
V
B

SN65MLVD202AD (Marked as MLVD202A)
SN65MLVD205AD (Marked as MLVD205A)
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
R
RE
DE
D
GND
GND
V
CC
V
CC
A
B
Z
Y
NC
NC - No internal connection
1
2
3
4
8
7
6
5
R
RE
DE
D
V
CC
B
A
GND
SN65MLVD200AD (Marked as MF200A)
SN65MLVD204AD (Marked as MF204A)
(TOP VIEW)

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INPUTS OUTPUT
V
ID
= V
A
- V
B
L H
- 50 mV < V
ID
< 50 mV L ?
V
ID
≤ - 50 mV L L
X H Z
TYPE-1 RECEIVER (200A, 202A)
V
ID
≥ 50 mV
Open Circuit L
RE
?
R
TYPE-2 RECEIVER (204A, 205A)
H = high level, L = low level, Z = high impedance, X = Don’t care, ? = indeterminate
INPUT OUTPUTS
L
H
OPEN
X
X
DRIVER
D DE A OR Y
H
H
H
OPEN
L
L
H
L
Z
Z
H
L
H
Z
Z
ENABLE
B OR Z
X Open Z
INPUTS OUTPUT
V
ID
= V
A
- V
B
L H
50 mV < V
ID
< 150 mV L ?
V
ID
≤ 50 mV L L
X H Z
V
ID
≥ 150 mV
Open Circuit L
RE
L
R
X Open Z

360 kΩ
400 Ω
V
CC
DRIVER INPUT AND DRIVER ENABLE
D or DE
7 V
400 Ω
V
CC
RE
7 V
RECEIVER ENABLE
V
CC
7 V
10 Ω
10 Ω
RECEIVER OUTPUT
360 kΩ
DRIVER OUTPUT
A/Y or B/Z
R
V
CC
200 kΩ
250 kΩ
200 kΩ
250 kΩ
100 kΩ 100 kΩ
V
CC
RECEIVER INPUT
B A

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0
5
10
15
20
25
30
−40 −15 10 35 60 85
I


S
u
p
p
l
y

C
u
r
r
e
n
t



m
A
C
C
T
A
− Free-Air Temperature − °C
V
CC
= 3.3 V
f = 50 MHz
V
ID
= 200 mV
V
IC
= 1 V
Rx
Tx
0
5
10
15
20
10 20 30 40 50
I
f − Frequency − MHz


S
u
p
p
l
y

C
u
r
r
e
n
t



m
A
C
C
Tx
Rx
V
CC
= 3.3 V
V
ID
= 200 mV
V
IC
= 1 V
T
A
= 25°C
−90
−60
−50
−40
−30
−20
0 1 2 4


R
e
c
e
i
v
e
r

H
i
g
h

L
e
v
e
l

O
u
t
p
u
t

C
u
r
r
e
n
t



m
A
V
OH
− High Level Output Voltage − V
3
I
O
H
−80
−70
V
CC
= 3.0 V
−10
0
V
CC
= 3.6 V
V
CC
= 3.3 V
T
A
= 25°C
0
30
40
50
60
70
0 1 2 4


R
e
c
e
i
v
e
r

L
o
w

L
e
v
e
l

O
u
t
p
u
t

C
u
r
r
e
n
t



m
A
V
OL
− Low Level Output Voltage − V
3
I
O
L
10
20
V
CC
= 3.6 V
V
CC
= 3.3 V
V
CC
= 3.0 V
T
A
= 25°C

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3
3.20
3.40
3.60
3.80
4
−40 −15 10 35 60 85
R
e
c
e
i
v
e
r

P
r
o
p
a
g
a
t
i
o
n

D
e
l
a
y



n
s
T
A
− Free-Air Temperature − °C
V
CC
= 3.3 V
V
ID
= 200 mV
V
IC
= 1 V
f = 1 MHz
C
L
= 15 pF
t
pLH
t
pHL
2
2.2
2.4
2.6
2.8
−40 −15 10 35 60 85
D
r
i
v
e
r

P
r
o
p
a
g
a
t
i
o
n

D
e
l
a
y



n
s
T
A
− Free-Air Temperature − °C
V
CC
= 3.3 V
f = 1 MHz
R
L
= 50 Ω
t
pHL
t
pLH
20
28
36
44
52
60
20 40 60 80 100
Signaling Rate − Mbps
A
d
d
e
d

D
r
i
v
e
r

P
e
a
k
-
T
o
-
P
e
a
k

J
i
t
t
e
r



p
s
V
CC
= 3.3 V
T
A
= 25°C
2
15
-1 PRBS NRZ
0
6
12
18
24
30
10 20 30 40 50
Clock Frequency − MHz
A
d
d
e
d

D
r
i
v
e
r

C
y
c
l
e
-
T
o
-
C
y
c
l
e

J
i
t
t
e
r



p
s
V
CC
= 3.3 V
T
A
= 25°C
Input = Clock

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10
16
22
28
34
40
10 20 30 40 50
Clock Frequency − MHz
A
d
d
e
d

R
e
c
e
i
v
e
r

C
y
c
l
e
-
T
o
-
C
y
c
l
e

J
i
t
t
e
r



p
s
V
CC
= 3.3 V
T
A
= 25°C
V
IC
= 1 V
Type-1
V
ID
= 200 mV
Type-2
V
ID
= 400 mV
40
48
56
64
72
80
−40 −15 10 35 60 85
A
d
d
e
d

D
r
i
v
e
r

P
e
a
k
-
T
o
-
P
e
a
k

J
i
t
t
e
r



p
s
T
A
− Free-Air Temperature − °C
V
CC
= 3.3 V
V
IC
= 1 V
f = 100 Mbps
2
15
-1 PRBS NRZ
0
60
120
180
240
300
20 40 60 80 100
A
d
d
e
d

R
e
c
e
i
v
e
r

P
e
a
k
-
T
o
-
P
e
a
k

J
i
t
t
e
r



p
s
Signaling Rate − Mbps
Type-2
V
ID
= 400 mV
Type-1
V
ID
= 200 mV
V
CC
= 3.3 V
T
A
= 255C
V
IC
= 1 V
2
15
-1 PRBS NRZ
0
60
120
180
240
300
−40 −15 10 35 60 85
T
A
− Free-Air Temperature − °C
A
d
d
e
d

R
e
c
e
i
v
e
r

P
e
a
k
-
T
o
-
P
e
a
k

J
i
t
t
e
r



p
s
Type-2
V
ID
= 400 mV
Type-1
V
ID
= 200 mV
V
CC
= 3.3 V
V
IC
= 1 V
2
15
-1 PRBS NRZ

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Horizontal Scale = 2 ns/div
V
e
r
t
i
c
a
l

S
c
a
l
e

=

1
2
7
.
2

m
V
/
d
i
v
Horizontal Scale = 2 ns/div
V
e
r
t
i
c
a
l

S
c
a
l
e

=

4
0
0

m
V
/
d
i
v

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-100
-50
0
50
100
150
200
Type 1
Transition Regions
Type 2
Low
High
Low
High
-

D
i
f
f
e
r
e
n
t
i
a
l

I
n
p
u
t

V
o
l
t
a
g
e

-

m
V
V
I
D

–≤

≤≤


–≤

≤≤

PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
SN65MLVD200AD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65MLVD200ADG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65MLVD200ADR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65MLVD200ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65MLVD202AD ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65MLVD202ADG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65MLVD202ADR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65MLVD202ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65MLVD204AD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65MLVD204ADG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65MLVD204ADR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65MLVD204ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65MLVD205AD ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65MLVD205ADG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65MLVD205ADR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65MLVD205ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 8-Jan-2007
Addendum-Page 1
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Jan-2007
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)
W
(mm)
Pin1
Quadrant
SN65MLVD200ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65MLVD202ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN65MLVD204ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65MLVD205ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65MLVD200ADR SOIC D 8 2500 340.5 338.1 20.6
SN65MLVD202ADR SOIC D 14 2500 333.2 345.9 28.6
SN65MLVD204ADR SOIC D 8 2500 340.5 338.1 20.6
SN65MLVD205ADR SOIC D 14 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 2
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
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