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INDUSTRIAL AUTOMATION
SEQUENCE CONTROL
Output Signals
Y1 Y2 Y3 ..................... Y4

Sensor Inputs

Data Processing

X1 X2 X3 X4 X5 .....................

LOGIC

CIRCUIT

Fixed Automation Relays Electronic Gates Microprocessors Pneumatic Valves Moving-Part Logic (MPL) Semi-Flexible Automation Programmable Counters Drum Programmers Fixed Automation Programmable Controllers (PLC) Microprocomputers

Ym

Xn

TYPICAL OUTPUT DEVICES
Pneumatic or Hydraulic Cylinders Pneumatic or Hydraulic Motors Solenoid Valves Electric Motors - Pumps - Conveyor Belts - Lifting Devices - Robot Arms Heaters Timers Lamps Audioble Signals (Bells, Buzzers, Sirens) Numerical Displays 

PART 1
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List of Figures
27, 2003

PART 1 Introduction

Updated : July

CHAPTER 0
0-1 0-2 0-3 0-4 0-4 0-4 0-4

Fig. 0-1 Fig. 0-2 (a-d) Fig. 0-3 (a-g) Fig. 0-4 (a-b)

Formal Infromation Silabus Subjects List Silabus - General Subject Definition Information Types Binary Switching Elements Self Correction

CHAPTER 1
Fig. 1-1 Fig. 1-2 Fig. 1-3 Fig. 1-4 Fig. 1-5 (a-g) Fig. 1-6 Fig. 1-7 Fig. 1-8 Fig. 1-9 1-1 1-1 1-1 1-1 1-1 1-1 1-1 1-2 1-2

Motion Actuators
Solenoid ForceStep Motor Pneumatic Cylinder With Air Cushions Basic Cylinder Types Fifteen Ways of Using Cylinder Eight Types of Pneumatic Rotary Actuators Air Motor

CHAPTER 2
Fig. 2-1 (a-d) Fig. 2-2 Fig. 2-3 Fig. 2-4 (a-b) Fig. 2-5 (a-c) Fig. 2-6 (a-g) Fig. 2-7 Fig. 2-8 Fig. 2-9 Fig. 2-10 Fig. 2-11 Fig. 2-12 (a-d) Fig. 2-13 Fig. 2-14 Fig. 2-15 Fig. 2-16 Fig. 2-17 (a-b) Fig. 2-18 Fig. 2-19 Fig. 2-20 Fig. 2-21 Fig. 2-22 Fig. 2-23 (a-b) 2-1 2-1 2-1 2-1 2-1 2-2 2-2 2-2 2-2 2-2 2-2 2-3 2-3 2-3 2-3 2-3 2-3 2-3 2-3 2-4 2-4 2-4 2-4

Sensors
Common Actuation Methods for Limit Switches Common Contacts Arrangements Limit Switch Symbols for Different Contact Configurations SPDT switch type BBM and MBB Three Operation Methods of Photoelectric Sensores Methods for Actuating Reed Switches Use of Reed Switch to Sense Piston Position Arc Suppression Methods for Protecting Relay Contacts Proximity Sensor Proximity Sensor Applications Use of Magnetic Proximity Sensor Four Basic Types of Pressure Switches Pressure Switch Level Switch Two Flow Switches Symbols for various Sensor Switches Sensor Switch with/without dead band Pneumatic Limit Valves And Their Fluid-Power Symbols Limit Valve Back Pressure Sensor Back Pressure Sensor With Overtravel Protection Using Back Pressure Sensor Annular Back Pressure Sensor

Fig. 2-24 Fig. 2-25 Fig. 2-26 Fig. 2-27 Fig. 2-28

2-4 2-4 2-4 2-4 2-4

Interruptable Jet Sensor Interruptable Jet Sensor Interruptable Jet Sensor Ultrasonic Sensor and Several Applications Spring Sensor

CHAPTER 3
Fig. 3-1 (a-I) Fig. 3-2 (a-f) Fig. 3-3 (a-c) Fig. 3-4 (a-d) Fig. 3-5 Fig. 3-6 Fig. 3-7 Fig. 3-8 Fig. 3-9 Fig. 3-10 Fig. 3-11 Fig. 3-12 Fig. 3-13 Fig. 3-14 Fig. 3-15 Fig. 3-16 Fig. 3-17 Fig. 3-18 (a-b) Fig. 3-19 (a-d) Fig. 3-20 (a-f) Fig. 3-21 Fig. 3-22 (a-e) Fig. 3-23 (a-d) Fig. 3-24 (a-b) Fig. 3-25 Fig. 3-26 Fig. 3-27 Fig. 3-28 (a-b) Fig. 3-29 (a-c) Fig. 3-30 (a-c) Fig. 3-31 (a-b) Fig. 3-32 (a-b) Fig. 3-33 Fig. 3-34 Fig. 3-35 (a-c) Fig. 3-36 (a-b) Fig. 3-37 Fig. 3-38 Fig. 3-39 Fig. 3-40 (a-b) Fig. 3-41 Fig. 3-42 (a-b) 3-1 3-2 3-2 3-2 3-3 3-3 3-3 3-3 3-3 3-3 3-4 3-4 3-4 3-4 3-4 3-4 3-4 3-5 3-5 3-5 3-6 3-6 3-6 3-7 3-7 3-7 3-7 3-7 3-7 3-8 3-8 3-8 3-8 3-8 3-9 3-9 3-9 3-9 3-9 3-9 3-9 3-9

Introduction to Switching Theory
Boolean Algebra Concept Algebric Minimization 1 Algebric Minimization 2 Karnaugh Maps Concept 4-Variables Karnaugh Map Example 1 4-Variables Karnaugh Map Example 2 4-Variables Karnaugh Map Example 3 4-Variables Karnaugh Map Example 4 4-Variables Karnaugh Map Example 5 4-Variables Karnaugh Map Example 6 4-Variables Karnaugh Map Example 7 4-Variables Karnaugh Map Example 7.1 4-Variables Karnaugh Map Example 8 4-Variables Karnaugh Map Example 8.1 4-Variables Karnaugh Map Example 9 4-Variables Karnaugh Map Example 10 4-Variables Karnaugh Map Example 11 Majority Function Motor Operation Control BCD to 7-Segment Various Switches & Relays Types Majority Function Circuit 3-To-8 Decoder Circuit 3D 5-Variable Karnaugh Map, And Its Development Optional Method of Constructing 5-Variable Karnaugh Map Simplification of 5-Variable Function Exercise 3D 6-Variable Karnaugh Map, And Its Development Simplification of 6-Variable Function Creation of 7-Variable Karnaugh Map Simplification of 7-Variable Function Creation of 8-Variable Karnaugh Map Simplification of 8-Variable Function Number of Variable Required to Define a Cell Saving Contacts and Contact Springs Use of Relay Use of Logic Gate Logic Gate Symbols Minimize by Selecting Non-Prime Cells Multiple Output System Minimize by Selecting Non-Prime Cell in a Multiple Output System

CHAPTER 4
Fig. 4-1 (a-k) Fig. 4-2 (a-b) Fig. 4-3 (a-b) Fig. 4-4 (a-b) Fig. 4-5 (a-e) Fig. 4-6 (a-b) Fig. 4-7 Fig. 4-8 Fig. 4-9 : Fig. 4-10 Fig. 4-11 Fig. 4-12 Fig. 4-13 (a-m) Fig. 4-14 (a-b) Fig. 4-15 Fig. 4-16 Fig. 4-17 Fig. 4-18 (a-e) Fig. 4-19 Fig. 4-20 Fig. 4-21 Fig. 4-22 Fig. 4-23 Fig. 4-24 Fig. 4-25 4-1 4-2 4-2 4-2 4-2 4-2 4-3 4-3 4-3 4-3 4-3 4-3 4-4 4-5 4-5 4-5 4-5 4-6 4-7 4-7 4-7 4-8 4-8 4-9 4-9

Industrial Switching Elements
Typical Simple Gates Packages (SSI Small Scale Integrated) Equivalent Circuits For Function AB+CD+EF Equivalent Circuits For Function ABCDEFGH Static Hazard Elimination Switch Bounce Elimination I/O Modules for Electronic Gates Optical Coupler Relay Construction Typical Relay Shapes Typical Relay Contacts Solenoid Valve Pneumatic Valve Gates Operation of 5/2 Spool Valve Shuttle Valve (OR Gate) Pneumatic Universal Gate (Samsomatic) Pneumatic Universal Gate (Dreldea) Pneumatic Gates (Telemechanique) Fluid Flip-Flop Fluid OR-NOR Gate Fluid NOR Gate Pneumatic Binary Amplifier (Single Stage) Pneumatic Binary Amplifier (Two Stage) Flow-Chart Showing Elements used in Binary Control System Comparison Between Switching Methods

CHAPTER 5
Fig. 5-1 Fig. 5-2 (a-c) Fig. 5-3 (a-b) Fig. 5-4 (a-b) Fig. 5-5 (a-c) Fig. 5-6 (a-b) Fig. 5-7 (a-g) Fig. 5-8 Fig. 5-9 (a-b) Fig. 5-10 Fig. 5-11 Fig. 5-12 (a-d) Fig. 5-13 (a-d) Fig. 5-14 (a-d) Fig. 5-15 (a-d) Fig. 5-16 (a-b) Fig. 5-17 (a-b) Fig. 5-18 Fig. 5-19 Fig. 5-20 Fig. 5-21 (a-k) 5-1 5-1 5-1 5-1 5-1 5-1 5-2 5-3 5-3 5-3 5-3 5-4 5-4 5-5 5-5 5-6 5-6 5-6 5-6 5-6 5-7

Electrinc Ladder Diagrams
Ladder Diagram Set-Reset Relay Flip-Flop Flip-Flop Implementation Example Cylinder Actuation Valves Positions of Cylinder Limit-Switches Graphic Symbols of Limit-Switches Cascade Method Target & Rules Typical Process Definition Typical Groups Partitioning Typical Initial Cascade Circuit Relays Cascade Design Process 1 (No Return Springs) Relays Cascade Design Process 1 (With Return Springs) Relays Cascade Design Process 2 (No Return Springs) Relays Cascade Design Process 2 (With Return Springs) Sequential System Stability Definition Huffman Method Design Steps Huffman/PLC Combination Merge Flow Lines Rules Huffman Process For Sequence A+,A- (With Return Springs)

Fig. 5-22 Fig. 5-23 Fig. 5-24 Fig. 5-25 Fig. 5-26 Fig. 5-27 Fig. 5-28 Fig. 5-29 Fig. 5-30 Fig. 5-31 Fig. 5-32 Fig. 5-33 Fig. 5-34 Fig. 5-35 Fig. 5-36

(a-k) (a-k) (a-k) (a-d) (a-h) (a-b) (a-e) (a-e)

5-7 5-8 5-8 5-9 5-9 5-10 5-10 5-10 5-10 5-10 (a-h) 5-11 5-12 5-12 5-12 5-13

Huffman Process For Sequence A+,A- (No Return Springs) Process For Sequence A+,A-,A+,A-(With Return Springs) Process For Sequence A+,A-,A+,A-(No Return Springs) Automatic Mixing System Cascade Method Automatic Mixing System Huffman Method Full/Partial Input Streams A+,A-,A+.AFull/Pseudo Karnaugh Maps Pseudo Map for A+,A-,A+,APseudo Map for 2 Cylinders & 4 States Pseudo Map for 4 Cylinders & 8 States Pseudo Karnaugh Map Example GRAFSET for Automatic Mixing System of Fig. 5-36 GRAFSET for Alternative Parallel Paths GRAFSET for Simultaneous Parallel Paths GRAFSET for Drilling Station

CHAPTER 6 Inputs
Fig. 6-1 Fig. 6-2 Fig. 6-3 Fig. 6-4 Fig. 6-5 (a-m) (a-l) (a-k) (a-j) (a-i)
6-2 6-3 6-1 6-4

Swquential Systems with Random
Thickness Detector System Design Traffic Light Control System Design Alarm System Design Motor Direction Detection System Design Combination Lock System Design

6-5

List of Figures
20, 2003

PART 2 Pneumatic Control Circuits

Updated : July

CHAPTER 7
Fig. 7-1 Fig. 7-2 Fig. 7-3 (a-b) Fig. 7-4 Fig. 7-5 Fig. 7-6 Fig. 7-7 (a-c) Fig. 7-8 (a-g) Fig. 7-9 Fig. 7-10 Fig. 7-11 (a-b) Fig. 7-12 Fig. 7-13 Fig. 7-14 (a-e) Fig. 7-15 (a-d) Fig. 7-16 (a-e) Fig. 7-17 Fig. 7-18 (a-d) Fig. 7-19 Fig. 7-20 Fig. 7-21 (a-b) Fig. 7-22 (a-b) Fig. 7-23 Fig. 7-24 Fig. 7-25 Fig. 7-26 Fig. 7-27 Fig. 7-28 (a-f) Fig. 7-29 (a-h) Fig. 7-30 (a-c) Fig. 7-31 Fig. 7-32 Fig. 7-33 Fig. 7-34 (a-d) Fig. 7-35 Fig. 7-36 Fig. 7-37 Fig. 7-38 Fig. 7-39 Fig. 7-40 7-1 7-1 7-1 7-1 7-1 7-2 7-2 7-3,4 7-5 7-5 7-6 7-6 7-6 7-6 7-6 7-7 7-8 7-8 7-9 7-9 7-9 7-9 7-10 7-11 7-12 7-13 7-14 7-14 7-15 7-16 7-16 7-16 7-16 7-16 7-17 7-17 7-17 7-17 7-17 7-17

Intuitive Design Of Sequence A+,B+,A-,BIntuitive Design Of Sequence A+,B+,B-,ACascade Design Of Sequence A+,B+, B-, A-,C+.CCascade Design Of Sequence A+,A-,A+,AMultiple Limit-Valves Replacement Pneumatic Cascade Basic Concept Pneumatic Cascade Group Configurations Pneumatic Cascade Design Process Steps Pneumatic Cascade Example 1 Pneumatic Cascade Example 2 Flip-Flop Valve & Steering Valve Two Steering Valves Providing Three Addresses Three Steering Valves Providing Four Addresses Design Sequence A+,A-,A+,A-,A+,ADesign Sequence A+,B+,A-,B-,(A+/B+),A-,BDesign Sequence A+,B+,B-,C+,B+,B-,C-,ASimplified Input Map Design a Sequence With Passive States Examples of Complex Functions Function Tables Background Function Tables Arrangement 3/2 Valve Connections yielding Single Output Function Valve Connections With 2 Separate Outputs, 2-Variables Input Valve Connections With 2 Separate Outputs, 3-Variables Input Valve Connections With 2 Separate Outputs, 4/5-Variables Input Valve Connections yielding Flip-Flop Output Functions Example 1 Example 2 (Huffman Solution for Sequence A+,A-,A+,A-) Solution for Sequence A+,B+,B-,A-,B+,BStop-Restart With Single Button & Separate Buttons Stop-Restart With Multiple Remote-Control Stop Buttons Electronic Circuit for Fig. 7-31 Emergency Stop Modes Definition Pneumatic / Electric

CHAPTER 8 Systems
Fig. 8-1 (a-h) Fig. 8-2 Fig. 8-3 Fig. 8-4 Fig. 8-5 Fig. 8-6 Fig. 8-7 (a-b) Fig. 8-8 Fig. 8-9 Fig. 8-10 (a-c) Fig. 8-11 (a-b) Fig. 8-12 (a-d) Fig. 8-13 (a-c) Fig. 8-14 Fig. 8-15 Fig. 8-16 Fig. 8-17 Fig. 8-18 Fig. 8-19 Fig. 8-20 (a-d) Fig. 8-21 Fig. 8-22 Fig. 8-23 Fig. 8-24 Fig. 8-25 Fig. 8-26 Fig. 8-27 (a-j) Fig. 8-28 Fig. 8-29 Fig. 8-30 (a-c) Fig. 8-31 Fig. 8-32 (a-c) Fig. 8-33 (a-g) Fig. 8-34 (a-f) Fig. 8-35 (a-g) Fig. 8-36 Fig. 8-37 Fig. 8-38 Fig. 8-39 8-1 8-1 8-1 8-1 8-1 8-1 8-1 8-1 8-1 8-2 8-2 8-2 8-2 8-3 8-3 8-3 8-3 8-3 8-4 8-4 8-4 8-4 8-5 8-5 8-5 8-6 8-6 8-6 8-6 8-7 8-7 8-7 8-8 8-8 8-9 8-10 8-10 8-10 8-10

Miscellaneous Switching Elements &
Sequence Chart for Common Timers Modes -Delay OffSequence Charts for Pulse Shaper Relay Pulse Shaper Pneumatic Pulse Shaper Basic Set-Reset Flip-Flop (SR) Toggle Flip-Flop (T) T Flip-Flop Implementation - Counters D Flip-Flop Implementation Shift Register 10-Stage Shift Register Shift Register With 4 Parallel Tracks Schmitt-Trigger Response Schmitt-Trigger Response to Fuzzy Waveform Truth Table for Error-Checking of BCD code Truth Table for 2-Out-of-5 Code Use of Karnaugh Map to Obtain Cyclic Code Reflected Cyclic Code for Six Numbers Binary 8-Section Encoder Typical 8-Section Encoder Single-Output Incremental Encoder Two-Output Incremental Encoder Motor Direction Detection System Design (Copy of Fig. 6-4) Simplified Block Diagram of a Closed-Loop NC System Block Diagram of Open-Loop NC System Adder for 2-Bit Numbers Iterative Adder Block Diagram Iterative Binary Adder Design Iterative Parity Checker Iterative 2 Out of n Checker Iterative Binary Numbers Comparator Comparison Between Natural-Binary & Reflected Cyclic Code Iterative Circuit for Translating Natural-to-Reflected Cyclic Code Iterative Circuit for Translating Reflected Cyclic to Natural Truth Table for Translating Natural-to-Reflected Cyclic Code

CHAPTER 9 Semi-Flexible Automation Hardware Programmers
Fig. 9-1 Fig. 9-2 Fig. 9-3 (a-b) Fig. 9-4 (a-b) Fig. 9-5 Fig. 9-6 Fig. 9-7 Fig. 9-8 Fig. 9-9 (a-e) Fig. 9-10 (a-e) Fig. 9-11 (a-c) Fig. 9-12 (a-c) Fig. 9-13 (a-e) Fig. 9-14 Fig. 9-15 Fig. 9-16 Fig. 9-17 Fig. 9-18 9-1 9-2 9-2 9-2 9-2 9-2 9-2 9-2 9-3 9-3 9-4 9-4 9-4 9-5 9-5 9-5 9-5 9-6 Drum Programmer Drum Programmer Solution Patch Board & Matrix Board Schematic Representation of Programmable Counter Programmable Counter With a Single-Cycle Start Mode Sequence A+,B+,C+,A-,(B-/C-),A+,A- - No Return Springs Sequence A+,B+,C+,A-,(B-/C-),A+,A- - With Return Springs Programmer Based on 1/n Code Programmer Based on 2/n Code Programmable Counter Example 1 Programmable Counter Example 2 2/n Stability Cases 1/n Code Programmer for Two Simultaneous Parallel Paths 1/n Code Programmer for Two Alternative Parallel Paths 1/n Code Programmer With Skipped Steps Option 1/n Code Programmer With Repeated Steps Option Flow Chart for Selecting System Design Method

CHAPTER 10 Flexible Automation Programmable Controller
Fig. 10-1 10-1 Fig. 10-2 10-1 Fig. 10-3 10-1 Fig. 10-4 10-1 Fig. 10-5 10-1 Fig. 10-6 10-1 Fig. 10-7 10-1 Fig. 10-8 (a-b) 10-1 Fig. 10-9 10-2 Fig. 10-10 10-2 Fig. 10-11 10-2 Fig. 10-12 10-3 Fig. 10-13 10-3 Fig. 10-14 10-3 Fig. 10-15 (a-e) 10-4 Fig. 10-16 (a-g) 10-4 Fig. 10-17 10-5 Fig. 10-18 10-5 Fig. 10-19 10-5 Fig. 10-20 10-5 Fig. 10-21 10-5 Fig. 10-22 10-5 Fig. 10-23 10-5 Fig. 10-24 (a-f) 10-6 Fig. 10-25 (a-b) 10-7 Block Diagram of Programmable Controller (PLC) PLC Classifications According to Size Discrete Input Devices to PLC Discrete Output Devices Actuated by PLC Standard Discrete I/O Interface Modules Type of Electronic Memories I/O Connection Diagram PLC- Different I/O Connections Locations Typical PLC Memory Map PLC Programming Languages Ladder Diagram Section Appearing on Screen PLC Configuration Typical PLC Control System PLC Network (Macro) PLC I/O Variables Assignment PLC Motor Control System Forward/Reverse Circuit Example of Ladder Diagram Segment I/O Assignment for Fig. 10-18 Ladder Diagram of Fig. 10-18 in PLC Format PLC Program for Fig. 10-20 Use of LIFO Memory Stack PLC Program for Fig. 10-22 PLC Cascade Design for sequence (A+/B+),C+,A-,C-,C+,(B-,C-) Multiple Use of LIFO Stack

Fig. 10-26 (a-b) 10-7 Fig. 10-27 (a-b) 10-7 Fig. 10-28 10-7 Fig. 10-29 (a-b) 10-7 Fig. 10-30 10-7 Fig. 10-31 (a-b) 10-7 Fig. 10-32 (a-c) 10-7 Fig. 10-33 10-8 Fig. 10-34 (a-b) 10-8 Fig. 10-35 (a-c) 10-8 Fig. 10-36 (a-d) 10-9 Fig. 10-37 (a-c) 10-9 Fig. 10-38 (a-c) 10-10 Fig. 10-39 (a-c) 10-10 Fig. 10-40 (a-d) 10-10 Fig. 10-41 (a-c) 10-10 Fig. 10-42 10-11 Fig. 10-43 (a-b) 10-11 Fig. 10-44 10-11 Fig. 10-45 10-11 Fig. 10-46 10-11 Fig. 10-47 10-11 Fig. 10-48 10-11 Fig. 10-49 10-12 Fig. 10-50 10-12 Fig. 10-51 10-12 Fig. 10-52 10-12 Fig. 10-53 10-12 Fig. 10-54 10-12 Fig. 10-55 10-13 Fig. 10-56 10-13 Fig. 10-57 10-13 Fig. 10-58 10-13 Fig. 10-59 10-13 Fig. 10-60 10-13 Fig. 10-61 (a-f) 10-14 Fig. 10-62 (a-e) 10-14 Fig. 10-63 (a-l) 10-15 Fig. 10-64 (a-e) 10-16 Fig. 10-65 (a-i) 10-17

Rearrangement of Ladder-Diagram to Simplify Program Timer Set for 20 Sec PLC Program for Fig. 10-27 Counter Set to Count to 25 PLC Program for Fig. 10-29 PLC Light-Flash Program PLC Up/Down Counter Program Two-Hand Safety Circuit Using PLC PLC Design for Sequence 6x(D+,D-),D+,10 sec delay.DLadder Diagram and Program for sequence of Fig. 10-34 Timers and Counters Master-Control-Relay Command (MCR) Jump Command (JMP) Equivalent PLC and Relay Circuits

Effect of Scanning Action on Internal States of Relays
Importance of Proper Rung Order Trigger Flip-Flop Circuit for PLC PLC Sequence Chart for Fig. 10-44 Analog Input Devices for PLC Standard Analog-Input Interface Modules Analog Output Devices Actuated by PLC Standard Analog-Output Interface Modules Storing an Analog Input Value Instruction Block Transferring a Word to Analog Output Module

Logic Operations Data Commands PLC Micro/Macro Definition Several Possible LAN Topologies PLC Design of Thickness Detector System PLC Design of Traffic Light Control System PLC Design of Alarm System PLC Design of Motor Direction Detector System Combination Lock System

CHAPTER 11 Automation
Fig. 11-1 11-1 Fig. 11-2 11-1 Fig. 11-3 (a-c) 11-1 Fig. 11-4 11-1 Fig. 11-5 11-1 Fig. 11-6 11-1 Fig. 11-7 11-2 Fig. 11-8 11-2 Fig. 11-9 11-2 Fig. 11-10 11-2 Fig. 11-11 11-2 Fig. 11-12 11-2

Introduction to Assembly

Bladed Wheel Hopper Feeder Central Board Hopper Feeder Shape of Centerboard Slot Rotary Centerboard Hopper Feeder Design Sheet for Reciprocating Tube Hooper Feeder Revolving Hook Hopper Feeder Design Sheet for Tumbling Magnetic-Disk Hopper Feeder Vibratory Bowl Feeder Design Sheet for Vibratory Bowl Feeder Disk Feeder Slide Escapement

CHAPTER 12
Fig. 12-1 (a-b) 12-1 Fig. 12-2 12-1 Fig. 12-3 12-1 Fig. 12-4 12-1 Fig. 12-5 12-1 Fig. 12-6 12-1

Robotics and Numerical Control

Cartesian Robot and Coordinate System Cylinde Robot and Coordinate System Spherical Robot and Coordinate System Articulated Robot and Coordinate System Robot Work Envelope RCC Device

CHAPTER 13
13-1 13-3 13-7

Simester Exams

Simester Exam Example - Questions Simester Exam Example Responses Typical Simester Exam Questions - Questions

0-4 INDUSTRIAL AUTOMATION
Automation of Mechanical Industrial Production Systems Control Section On-Off (Binary) Elements and Information Various Methodes to Obtain Low-Cost Systems START
S? SW SPDT SW DPDT S?

a. Electrical Switches

Fig. 0-1 Subject Definition
K?

K?

Value

Value

RELAY SPST RELAY DPDT

b. Electro-Mechanical Relays

2-Input AND
1 3 2

3-Input AND

2-Input NAND
1 3 2

Time

Time

a. Analog
Value Value

2-Input OR
1 3 2

2-Input NOR
2 1 3

Inverter

c. Electronic Gates

+

-

+

Time

Time

b. Digital
Value Value

+

-

+

-

+

d. Pneumatic Valves

a1,a2 = 00
a1
+

a2

Time

Time

-

(open)

(open)

c. Binary (Logic, "Digital")
Value Signal

A+

A-

"High"

LOGIC IMPLEMENTATION

e. Electrical Limit Switches

"Unspecified"

"Low" Time

(d)
d. Logic Levels

+

A+

A-

Fig. 0-2 Information Types
f. Pneumatic Limit Valves

Logic

BINARY SENSORS : Out Pressure , Flow , Temperature , Height etc g. Various Elements

In

Element

(a)

(b)

Relay SPDT

Fig. 0-4 Self Correction

Fig. 0-3 Binary (Switching) Elements

-

CHAPTER 1
MOTION ACTUATORS
Linear and Angular Motion Electrical Linear Actuators Electrical Rotary Actuators Fluid-power Linear Actuators Fluid-power Rotating Actuators Boolean Functions Standard Formats

CHAPTER 2
SENSORS
Electric Position Sensors Contacts Symbols Photoelectric Sensors Reed Switches Proximity Sensors Pressure, Flow and Level Switches Pneumatic Limit Valves Back-Pressure Sensors

CHAPTER 3

INTRODUCTION TO SWITCHING THEORY
Boolean Algebra Truth Tables Functions Algebric Minimization DeMorgan Theorem Universal Systems Boolean Functions Standard Formats Karnaugh Maps Maximal Cells Essentoal (Maximal) Cells Adjucent Cells Minimzation By Karnaugh Maps 4-Variables Minimization Examples 5 8 Variables Implementation

BOOLEAN ALGEBRA
Logic Theory Implementation in Switching George Boole False and True replaced by 0 and 1 Binary Items and Variables Logic , Boolean , Binary , Digital Switch or Relay ON/OFF Position : Contacts : Open / Closed Net : Connected / Not-connected Binary sensors (Temperature, Pressure, etc) Representations : "0 / "1" "ON" / "OFF" "HIGH" / "LOW"
NAND (NOT AND) : NOR (NOT OR) : XOR (Exlussive OR) INHIBITION IMPLICATION X nand Y = (X.Y)' X nor Y = (X+Y)' X xor Y = X'Y+XY' X.Y' X+Y'

3-1

f. More Useful Operators

(A.B)' = A'+B' (A+B)' = A'.B' Implementations : (A.B+A'.C)' = (A'+B').(A+C') (AB(C'+DE'))' = A'+B'+C(D'+E)

a. Basic Definitions

g. DeMorgan Theorem

AND 0.0 0.1 1.0 1.1 = = = = 0 0 0 1

OR 0+0 0+1 1+0 1+1 = = = = 0 1 1 1 {*}

NOT 0' = 1 1' = 0 AND , OR , NOT AND , NOT OR , NOT NAND A+B = (A'.B')' A.B = (A'+B')' A' = (A.A)' = (A NAND A) A+B = (A'.B')' = ((A.A)'.(B.B)')' = = (A NAND A) NAND (B NAND B) NOR A' = (A+A)' = (A NOR A) A.B = (A'+B')' = ((A+A)'+(B+B)')' = = (A NOR A) NOR (B NOR B)

b. Basic Operators
X.0 = 0 X.1 = X X.X = X X.X' = 0 X+0 = X X+1 = 1 X+X = X X+X' = 1

X+X.Y = X X+X'.Y = X+Y X(Y+Z) = XY+XZ (X+Y).(X+Z) = X+YZ XY+X'Z+YZ = XY+X'Z

h. Universal Systems

c. Basic Relations
A XY+X'Z+YZ = XY+X'Z F1 = XY+X'Z+YZ X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 F1 0 1 0 1 0 0 1 1 F2 = XY+X'Z F2 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1

1. Universal Sum-of-Products : 2. Universal Products of Sum : 3. Minimal Sum-of-Products : 4. Minimal Products of Sum :

d. Minimization - Truth Table
1. Universal Sum-of-Products : f(A,B,C,D) = A'B'CD'+A'B'CD+A'BC'D'+A'BC'D+A'BCD+ + AB'CD'+AB'CD+ABCD'+ABCD XY+X'Z+YZ = XY+X'Z F1 = XY+X'Z+YZ If Z=0 then : F1 = XY+X'.0+Y.0 = XY If Z=1 then : F1 = XY+X'1+Y.1 = = XY+X'+Y = X'+Y F2 = XY+X'.1 = = X'+XY = X'+Y F2 = XY+X'.0 = XY F2 = XY+X'Z 2. Universal Products of Sum : f'(A,B,C,D) = A'B'C'D' + A'B'C'D + A'BCD' + AB'C'D' + + AB'C'D + ABC'D' + ABC'D f(A,B,C,D) = (A+B+C+D)(A+B+C+D')(A+B'+C'+D)(A'+B+C+D). .(A'+B+C+D')(A'+B'+C+D)(A'+B'+C+D') 3. Minimal Sum-of-Products : f(A,B,C,D) = A'BC'+AC+B'C+CD 4. Minimal Products of Sum : f(A,B,C,D) = (A'+C)(B+C)(A+B'+C'+D)

e. Minimization - Math Operations

i. Functions Basic Representations

Fig. 3-1 : Boolean Algebra Concepts

3-2
Karnaugh Maps

INSURANCE COMPANY REQUIREMENTS
AN INSURANCE COMPANY SELECTS CLIENTS ACCORDING TO THE FOLLOWING CRITERIA : NATIONALITY, GENDER, AGE AND HAVING DRIVING-LICENSE. CLIENT MUST SATISFY AT LEAST ONE OF THE FOLLOWING CONDITIONS :
and/or ISRAELI and/or NON-ISRAELI UNDER 50 WITH DRIVING LICENSE and/or NON-ISRAELI MAIL 50 OR ABOVE FIND THE MINIMAL REQUIRED CONDITIONS

NON-ISRAELI UNDER 50 WITHOUT DRIVING LICENSE

a. System Definition
CRETERIA VARIABLE 1 0

* Visual method for boolean functions minimization * Each variable occupies half map * n variables split map into 2 n basic cells, named map Elements * Each element is represented by a n-variable boolean product, named "Minterm" * Any two adjacent elements are represented by two "Adjacent" minterms * Merging two adjacent elements produces a 2-elements cell, represented by a product of (n-1) variables

NATIONALITY GENDER AGE
LICENSE

A B C D

ISRAELI MALE 50 OR ABOVE HAS LICENSE

NON-ISRAELI FEMAIL UNDER 50 DOESN'T HAVE LICENSE

b. Boolean Variables Assignment
T = A+A'C'D+A'BC+A'C'D' = A+A'(C'D+BC+C'D') = A+C'D+BC+C'D'= A+C'(D'+D)+BC= A+C'+CB= A+B+C'

* Two adjacent 2-element cells may be merged Into a 4-elements cell, represented by a product of n-2 variables, and so on a. Map Concepts and Basic Properties
B
A B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 T

c. Direct Minimzation
B' B

T= = = = = = =

A+A'B'C'D'+A'B'C'D+A'BC'D'+A'BC'D+A'BCD'+A'BCD A+A'(B'C'D'+B'C'D+BC'D'+BC'D+BCD'+BCD)' = A+B'C'D'+B'C'D+BC'D'+BC'D+BCD'+BCD' = A+B'C'(D'+D)+BC'(D'+D)+BC(D'+D)' A+B'C'+B.C'+BC = A + B'C' + B(C'+C) = A + B'C' + B A + C' + B

0 0 0 0 0 0 0 0 1 1 1

e. Truth Table Minimzation
SIMPLIFIED RESULT : and/or ISRAELI and/or UNDER 50 MALE

1 1 1 1 1

1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1

A' A A

B A
0 1 0 1

B

A

d. Truth Table

f. Minimal Requirements

b. 2-Variables Map Representations

Fig. 3-2 : Algebric Minimization (1)
BC AN OCTAL NUMBER IS DEFINED BY THE BINARY COMBINATION X2,X1,X0 A 0 A COMBINATIONAL SYSTEM DETECETS IF THE NUMBER IS DIVIDABLE BY EITHER 2 OR 3 1
AB'C' AB'C ABC ABC'

00
A'B'C'

01
A'B'C

11
A'BC

10
A'BC'

B

WHERE N(X2,X1,X0)=4.X2+2.X1+1.X0

A

a. System Definition
X2 X1 X0 T

C c. 3-Variables Map Representations

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 0 1
X1 X1 X1

CD
COMBINATIONAL CIRCUIT

T

AB 00 01

00

01

11

10

C

b. Block Diagram
1 1 0 1 0

T = X2'X1'X0'+X2'X1.X0'+X2'X1.X0 + + X2.X1'X0'+X2.X1.X0'= =X0'(X2'X1'+X2'X1+X2X1'+X2X1)+X2'X1X0= =X0'(X2'(X1'+X1)+X2(X1'+X1))+X2'X1X0= =X0'(X2'+X2)+X2'X1X0= =X0'+X2'X1X0= =X0'+X2'X1

B
11

A
10

D d. 4-Variables Map Representations

c. Truth-Table

d. Minimization Steps

Fig. 3-4 : Karnaugh Maps Concept

Fig. 3-3 : Algebric Minimization (2)

C

C

C

C

1 1
A

1 1 1 1
D B A

1 1 1 1
D

1 1
B

Fig. 3-5 : Example 1
Essential cells : 3 Non-Essential cells : 0 Minimal solutions : 1 F = AD + C'D + A'CD'

1 1
A

1 1 1 1 1
D B A

Fig. 3-6 : Example 2

Maps Definitions I II III IV V Function "Area" All (Maximal) Cells Minimal Solution 1 Minimal Solution 2 Minimal Solution 4

1 1

1 1
II

1 1

1 1 1
D

1 1 1

1

B

Essential cells : 4 Non-Essential cells : 1 Minimal solutions : 1 F = A'C'D + ACD + A'BC + ABC'

I

I

II

C

2

C

C

C

Fig. 3-7: Example 3
Essential cells : 2 Non-Essential cells : 2 Minimal solutions : 2 F1 = BC + B'C'D + A'BD F2 = BC + B'C'D + A'C'D

1 1
A

1 1 1 1 1
I
C B A

1 1 1 1 1
II
C B A

1 1 1 1 1
III
B A

1 1

1 1

1 1

1 1
D

1
B

1
IV

1
D

D

D

C

Fig. 3-8 : Example 4

1 1
A D

1
B

1 1
A D

1
B

1 1
A

1
B

1

1 1 1 1 1
I

1

1 1 1 1 1
II

1

1 1 1
D

1 1
III

Essential cells : 3 Non-Essential cells : 2 Minimal solutions : 1 F = AC + B'C + A'BC' + CD

C

C

C

C

C

C

Fig. 3-9 : Example 5
Essential cells : 2 Non-Essential cells : 4 Minimal solutions : 4 F1 = A'C' + AC + ABD + AB'D' F2 = A'C' + AC + ABD + B'C'D' F3 = A'C' + AC + BC'D + AB'D' F4 = A'C' + AC + BC'D + B'C'D'

1 1
A

1 1 1 1 1
D

1 1 1 1
I
B A

1 1 1 1 1
D B

1 1
A

1 1 1 1 1
D B

1 1
A

1 1 1 1 1
D B

1 1
A

1 1 1 1 1
D B

1 1
A

1 1 1 1 1
D B

1 1
II

1 1
III

1 1
IV

1 1
V

1 1
VI

1

1

1

1

1

1

C

C

C

C

Fig. 3-10 : Example 6

1
A

1 1 1
D

1 1
I

B A

1

1 1
D

1 1 1
II

B A

1

1 1
D

1 1 1
III

B A

1

1 1
D

1 1 1
IV

B

Essential cells : 0 Non-Essential cells : 6 Minimal solutions : 2 F1 = ABC + BC'D + A'BD' F2 = BCD' + ABD + A'BC'

3-3

C

C

C

C

C

C

Fig. 3-11 : Example 7

A

1 1 1 1

1 1 1
D

1 1 1 1

1
B

1 1
I
C

A

1 1 1 1

1 1 1
D

1 1 1 1

1
B

1 1
II
C

A

1 1 1 1

1 1 1
D

1 1 1 1

1
B

1 1
III
C

A

1 1 1 1

1 1 1
D

1 1 1 1

1
B

1 1 1 1

1 1
IV

A

1 1 1
D

1 1 1 1

1
B

1 1
A

1 1 1
D

1 1 1 1

1
B

Essential cells : 0 Non-Essential cells : 12 Minimal solutions : 6 F1 = F2 = F3 = F4 = F5 = F6 = A'C' + B'D'+ AB + CD BD+ AC + A'B'+ C'D' AD'+ BC'+ CD + A'B' A'D + B'C + AB+ C'D'

Maps Definitions I II III IV V Function "Area" All (Maximal) Cells Minimal Solution 1 Minimal Solution 2 Minimal Solution 4

1 1
V

1 1

1 1
VI

Fig. 3-12 : Example 7.1

0
A

B A

0 0

B A

0 0

B

Essential cells : 2 Non-Essential cells : 0 Minimal solutions : 1 F' = A'BCD' + AB'C'D

0
D

I
C

D

II
C

D

F = (A + B' + C' + D).(A' + B + C + D') III
C C C

Fig. 3-13 : Example 8

C

1 1 1 1
D C

1
B A

1 1 1 1 1
D C

1
B A

1 1 1 1
D

1
B

A

1 1 -

1 -

I

II

1 1 -

Essential cells : 2 Non-Essential cells : 1 (+2) Selected Don't Cares : All Minimal solutions : 1 F = AD' + A'B' + BCD

0
A

0 0
B A

0 0
B A

Fig. 3-14 : Example 8.1

III
C

0 0 0
D

0

I

0 0

0 0
D

0 0 0
D

0 0

III

B

Essential cells : 0 Non-Essential cells : 8 Selected Don't Cares : None Minimal solutions : 1 F' = AB'D + A'BD' + BC'D F = (A'+B+D').(A+B'+D).(B'+C+D')

II

A

1 1

1 1 1 1 D

1 1

- 1
B A

1 1 1 1 1 D

1 1

B A

Fig. 3-15: Example 9
Essential cells : 0 Non-Essential cells : 3 (+5) Selected Don't Cares : None Minimal solutions : 1 F = AC' + C'D + A'CD'

1 1 1 1
D

1 - 1

I
C

II
C

1 1

- III

B

1 1
A

1 1
D

-

1 1

I

B A

1 1

- 1 - 1 1 - 1 - D

B A

1 1 1 1 - 1 - 1
D

C

Fig. 3-16 : Example 10
Essential cells : 2 Non-Essential cells : 1 Selected Don't Cares : Partial Minimal solutions : 1 F = AD + A'D'

B

II

III

C

C

B A

C

C

Fig. 3-17 : Example 11
Essential cells : 1 Non-Essential cells : 5 Selected Don't Cares : Partial Minimal solutions : 2 F1 = ACD + AB + A'C' F2 = ACD + AB + A'D' Note : F1 and F2 are equivalent but not identical

1 1
A

1
D

B A

- 1 1 1
I

1 1 - 1 1 1
1
D

1 1 - 1 1 1
1
D

B A

1 1 - 1 1 1
1
D

B

3-4

II

III

IV

X

Y

Z

M

3-5
BCD to 7-SEGMENTS CONVERTER Design a combinational circuit that gets a BCD input, and converts it to 7-Segment display. BCD is short form of Binary-Coded-Decimal. It Represents 10 decimal digits (0-9) in 4-bit binary code (0000-1001). Binary combinations 1010-1111 (above decimal 9) may not appear as inputs, and are refered as don't-care.
Y,Z

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 1 0 1
1 X 0 00 01 11 10

a. System Definition
0 0 0 1 1 1 0 1

1

b. 7-Sigments Arrangement
M = XY+XZ+YZ

1

b. Karnaugh-Map a. Truth-Table

Fig. 3-18 : Majority Function

D3 D2 D1 D0

A B C D E F G

G B C D A E F

c. Block Diagram
Y,Z X Y Z A B C X 0 1 00 01 11 10

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 1 1 1 1 1 1

0 0 0 1 0 1 1 1

0 0 0
X

0 1

1 1

1 1

1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

D3 D2 D1 D0

A B C

D E F G

A=X+Y+Z
Y,Z 00 0 01 11 10

0 0 0 0 1 1 1 0 1 0
1

0 0
X Y,Z 00 0 1

B = XY + XZ + YZ

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 1 1 1 1 1 0 1 1

-

1 1 1 1 1 0 0 0 1 1

-

d. Truth-Table (Partial)
01 11 10

1

0 0

0 0

0 1

0 0

D3,D2 D1,D0 00 01 11 10

a. Truth-Table

00

1 1 1 1

1 0 0 0

-

1 1 -

C = XYZ

01

b. Karnaugh-Maps
11 X Y 10

A
Z

F=D2'+D1'D0'
X Y X Z Y X Y Z

e. Karnaugh Map of "F"
B

*

D3,D2 D1,D0 00 00 01 11 10

D3,D2 D1,D0 00 01 00 01 11 10

C

0 0

1 1 0 1

c. Contact Circit Realization
X Y Z X X Z Y X Y Z Y

01

*

-

*

1 1

0 0 1 1

1 1 0 1

-

1 1 -

A

11

*

1 1

-

11

10

10

B
A=D3+D2.D1'+D2'D1+D1.D0'=

C

=D3+D2.D1'+D2'D1+D2.D0'

f. Karnaugh Map of "A"
SWITCH-X SWITCH-Y SWITCH-Z

d. Electrical Diagram

Fig. 3-19 : Motor Operation Control
(Exer1-7)

Fig. 3-20 : BCD to 7-Segments

3-6
SW PUSHBUTTON RELAY SPST SW SPST RELAY 4PST SW SPDT RELAY SPDT
SW DPDT SW DPST

LAMP

M1 M2 A M3

RELAY DPST RELAY 4PDT

RELAY DPDT

B M4 C M5

Fig. 3-21 : Various Switches and Relays Types

T = AB + AC + BC = AB + (A + B)C

M6 M7

b. Majority Boolean Function

A

B C
M

COMMON

a. Block-Diagram

b. Switches-Operated Circuit
A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC

A A B

B C A B C

c. Contacts Circuit

A

B

C B' d. Switches Remote Operation 9 Long Lines, Carrying High Current A B c. Contacts Circuit
+

A
A

B C

e. Relays Remote Operation 3 Long Lines, Carrying Low Current

Fig. 3-22 : "MAJORITY" Function Circuit

-

+

b. Switches-Operated Circuit

C'

B' A' B

A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC

+

C C'
C

M

C' C C' C

M

B

C

B A
A B

C

-

+

C COMMON

A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC

d. Relays-Operated Circuit

Fig 3-23 : 3-TO-8 DECODER CIRCUIT

E'

C

E

C

C

3-7
B

B A D A D

B
A D D E

a. 3-D Representation

b. Flat Representation

Fig. 3-24 : Three-Dimentional Five-Variable Karnaugh Map, and Its Developmenet

Fig. 3-25 : Optional Construction of Five-Variable Karnaugh Map (Not Recommended)

E'

C

E

C

T=A'B'C'D'+A'BDE'+A'B'CDE'+AB'C'D'+A'BC'DE+ABCDE+ABCD'E

1 0 0
A

0 1 0 0
D

1 1

0 0 0
B A

1

0

0 0

0
B

with impossible conditions :

A'B'CD''=1

ACDE'=1

0 *1 0 1 0 0
D

a. Original Function T=B'C'D'+A'BC'D+CDE'+ABCE c. Simplified Function

*1

-

1 *1 0 0

b. Karnaugh Map *
E' C E C

Fig. 3-26 : 5-Variable Minimzation Exercise (With Solution)

T=A'B'C'E'+A'B'CD'+ABC'DE'+AB'C'E'+AB'CD'E'+B'C'D'E+A'B'C'DE+CD'E a. Original Function

B A D A D

B

T= c. Simplified Function

b. Karnaugh Map

Fig. 3-27 : 5-Variable Minimzation Exercise, (Without Solution)
E

F

b. Flat Representation a. 3-D Representation

Fig. 3-28 : Three-Dimentional sIx-Variable Karnaugh Map, and Its Developmenet
1
E

T=A'BC'F'+AB'C'DE'F+ABDF+ACDE+ACD'E+ +A'C'DE'+A'C'DEF'

0 0

1

0 0 0 0

0 0 0 0
3

0 0 0

1 1 1 1

0 0

0

0 0 0
4
F

0 0 1 0

0 0 1 1

0

1 0 0
2

1 1 0 0

0 0

0 0

1* 1 0 0

0

1 1

with impossible conditions : A'B'C'D'=1 A'BCD'F=1 a. Original Function

1* 0 0

1 *1 1 1

T=A'C'F'+ACE+C'DE'F+ABDF
1 2 3 4

b. Karnaugh Map

c. Simplified Function

Fig. 3-29 : 6-Variable Minimzation Exercise (With Solution)

3-8
E

C E B G F D A

a. Upper Level

b. Lower Level

G

Fig. 3-30 : Seven-Variable Karnaugh Map, and Its Developmenet
1

F

c. Flat Representation

AB'C'D'EF'G'

E

1 *1
T=A'C'D'G'+ABCF'+B'D'FG+A'C'EF'
1 2 3 4

1 1 1* 1 1 1

1 1

1 1

- - 1 1
4

*

b. Simplified Function
G

1

1

1 *1 1 1 1 1

1 1 1 *1
F

1

1
2 3

Fig. 3-31 : 7-Variable Minimzation Exercise (With Solution)

a. Function Karnaugh Map

E

C

G

F G H A D

B

1

1 1 1

-

1 1 1

-

- H

1 1

1 1 1 1 1

-

-

- - 1 - - 1 -

1

1

a. Upper Level

a. Lower Level

Fig. 3-32 : Eight-Variable Karnaugh Map, and Its Developmenet

1

1 1 1 1

Number of Variables in The Function Size of Cell 2 3 4 5 6 7 8 Single Square 2 3 4 5 6 7 8 2-Square Cell 1 2 3 4 5 6 7 4-Square Cell 1 2 3 4 5 6 8-Square Cell 1 2 3 4 5 16-Square Cell 1 2 3 4 32-Square Cell 1 2 3 64-Square Cell 1 2 128-Square Cell 1
Fig. 3-34 : Number of Variables Required to Define Certain Cell Address

E

-

-

1

-

1 1

-

-

1 1

-

-

F

1
Fig. 3-33 : 8-Variable Minimzation Exercise

Y1 Y2 Y1 Y2

X2 X1
1

Y1
1 2 2

3-9
CR1

X2 X1

Y1

X1

(X1') (X1) (X2') (X2)

X2

CR1
2

CR1
X1 Y2
1

X2

Y2

1

X1

X2

2

CR1=Y1.X2+Y2.X2'+Y1.X1'+Y2.X1 8 Contacts , 16 Springs

CR1=Y1(X1'+X2)+Y2(X1+X2') 6 Contacts , 12 Springs

CR1=Y1(X1'+X2)+Y2(X1+X2') 4 Contacts , 10 Springs

a. Original Function

b. Saving Contacts

c. Saving Contact Springs

Fig. 3-35 : Saving Contacts and Contacts Springs
Exitation Function (Y) Y2 Y3 Y1 T Y1 Y1 Y2 Y3 Y2 Y3 Y2 Y3 T Output Variables (y,y') y y y RELAY y' y' y'

Y

Fig. 3-37 : Use of Relay
Input Variables (x') Output Function (T) T GATE

T=Y2.Y3+Y1.Y3+Y1.Y2.Y3'

T=Y2.Y3+Y1.Y3+Y1.Y2.Y3'+(Y2.Y3')

a. Original Function

b. Sneak Path Y2.Y3'

x1 x2 x3 x4

Fig. 3-36 : Sneak Path Creation Fig. 3-38 : Use of Gate

NOT
Old European Symbols Old USA Symbols

AND

OR

EXCLUSIVE OR

NOR

NAND

IMHIBITION

FLIP-FLOP
S R y y'

S FF R

y y'

New Symbols Recommended by ISO

1

&

>1

=1

>1

&

&

S R

y y'

Fig. 3-39 : Logic Gate Symbols
C C C C

A

- - - 0 - 1 - 0 0 0 0 1
D
T=BC'+A'C'D= =C'(B+A'D)

B A

- - - 0 - 1 - 0 0 0 0 1
D
T=B'C'D+A'C'D= =(B+A')C'D

0 0
B A
Input Variables

0

0 1 1 0
D

0 0 0 0
B A

1 0 0 0

1 0 0 0
D

1 1 1 0

1 0 0 0
B

1 1

1 1

Output Variables T1 RELAY T2 T3

a. 5 Gates

b. 4 Gates

A B C D E

T1=AC'+BCD (Instead of A'C+BD)

T2=A'B+BCD

a. Function T1

b. Function T2

Fig. 3-40 : Minimize by Selecting Non-Prime Cells

Fig. 3-41 : Multiple Output System

Fig. 3-42 : Minimize by Selecting Non-Prime Cells, in Multiple-Ourtut System

CHAPTER 4
INDUSTRIAL SWITCHING ELEMENTS
Electronic Gates Electronic Gates Implementation Input/Output Module Electric Relays Moving Parts Logic (MPL)

7

VCC
14 13

SN54LS00 SN74LS00
12 11 10 9 8 14 13 12 11 10 9 8

4-1

1

2

3

4

5

6

7

GND

1

2

3

4

5

6

7

a. Quad 2-Input NAND Gate SN54LS32 SN74LS32
VCC
14 13 12 11 10 9 8

g. Chip Configuration

SN54LS00 SN 54 LS 00

1

2

3

4

5

6

GND

b. Quad 2-Input OR Gate

Vendor Family

Function (Serial Number) Technology
h. Chip Name "Code"

VCC
14 13

SN54LS27 SN74LS27
12 11 10 9 8

1

2

3

4

5

6

7

GND

c. Tripple 3-Input NAND Gate

74 : Commercial Family 54 : Military Family Difference : Temperature Range

VCC
14 13

SN54LS20 SN74LS20
12 11 10 9 8

Many More Families
i. Families

1

2

3

4

5

6

7

GND

d. Dual 4-Input NAND Gate

High High High High

/ / / /

Low Low Low Low

Speed Power Dissipation Power Drive (Fan-Out) Power Supply Voltage

VCC
14 13

SN54LS04 SN74LS04
12 11 10 9 8

And Many More
j. Technologies Characteristics

1

2

3

4

5

6

7

GND

e. Hex INVERTER SN54LS76 SN74LS76
GND
16 15
7

14

13

12

11
2

10

9

k. Grid-Array Package
(not SSI)

PR

J CLK

Q

J CLK K

PR

9 6 12

11

4 1

Q

15

CL

K

Q

CL

10

16

Q

14

8

3

1

2

3

4

5

6

7

8

VCC

f. Dual J-K FLIP-FLOP

Fig. 4-1 : Typical Simple Gates Packages (SSI - Small Scale Integrated)

4-2
A B C D E F AB A B AB+CD+EF C D E F (AB)' ((AB}'.(CD)'.(EF)')' = = AB+CD+EF (EF)'

CD

(CD)'

EF

a. AND-OR-NOT system

b. NAND system

Fig. 4-2 : Equivalent Circuits for Function AB+CD+EF

B A

AB

B A AB+A'C A'

(AB)' AB+A'C

A' C

A'C C

(A'C)'

a. AND-OR-NOT system 4 Gates , 3 Packages

b. NAND system 4 Gates , 1 Package

Fig.4- 3 : Equivalent Circuits for Function AB+A'C

(Save Packages)

A,B C 00 0
6 5 9 8 10 12 11 13 1 3 2 4 6 5 9 8 10

01

11

10

A B C D E F G H

1 3 2 4

0 0

0 1

1 1
AB

0 1

1

(a)

T

B A

1 2
A

AB+A'C

a. 7 Gates , 2 Packages , 7xT delay

A' C

A'C

(b)

A B C D E F G H

1 3 2 1 3 2 4 6 5 9 8 10 9 8 10 4 6 5 12 11 13

T

A'C

AB

b. 7 Gates , 2 Packages , 3xT delay

AB+A'C

(c)

Fig. 4-4 : Equivalent Circuits for Function ABCDEFGH (Increase Speed)
PRESS BOUNCE
A B

Transition From 011 to 111 (Gate 1 Slower Than Gate 2)
A,B

RELEASE BOUNCE ANTI-BOUNCE CIRCUIT C 0 1
1

00

01

11

10

A

1 3 2

0 0

0 1

1 1
AB

0 1

(d)
OUT
3 2

OUT

a. Contact Bounce (A,B) and Required Signal (OUT)

B

A B A' C B C

AB+A'C+BC CD

b. Eliminate Bounce by a Simple Flip-Flop

EF

(e)

Fig. 4-6 : Switch Bounce Elimination Fig. 4-5 : Hazard Elimination

4-4
A
+

A
+

B
+

B
+

T=A

T=A'

A

T=A.B A

T=A+B

a. YES Gate

b. NOT Gate

c. AND Gate

d. OR Gate

B
+

B A
+

T=A.B' A

A

T=A+B' C B

+

T=A.C+A'B

e. INHIBITION Gate

f. IMPLICATION Gate

g. SELECTOR Gate

A
+

B
+

B
+

T=A' T=A
-

A
-

T=A+B T=A.B

A
-

T=A.B' T=A+B'

h. YES/NOT Gate

i. AND/OR Gate

j. INHIBITION/IMPLICATION Gate

A

Hot

Hot

(T=A+B) Cold Cold

B k. Non-Valve "OR" Element l. Almost equal HOT/COLD pressure - No Flow m. COLD Pressure Less Than HOT HOT Flows Into COLD

Fig. 4-13: Pneumatic Valve Gates

D

E

4-5
P2

P1

A

B

C

a. Position 1
X1 D E T=X1+X2 X2

P1

P2

Fig. 4-15 : Shuttle Valve
(OR Gate) A B C

b. Position 2

Fig. 4-14 : Operation of 5/2 Spool Valve

X2

X4

T=X5(X1'+X2)+X4.X1.X2'

X1

X5

Fig. 4-16 : Pneumatic Universal Gate (MPL)
(Samsomatic, W. Germany)

X1 X3

X4 X2

T T=X3(X1'+X2)+X4(X1+X2')

Fig. 4-17 : Pneumatic Universal Gate (MPL)
(Dreloea, E.Germany)

Fig. 4-18 : Pneumatic Gates (TELEMECHANIQUE, France)

Fig. 4-19 : Fluid Flip-Flop (Wall Attachment Principle)

Fig. 4-20 : Fluid OR-NOR Gate

4-8

Fig. 4-21 : Fluid NOR Gate (Impact Modulator, AIR Logic, USA)

Fig. 4-22 : Pneumatic Binary Amplifier (Single Stage, AIR LOGIC, USA)

Fig. 4-23 : Pneumatic Binary Amplifier (Two Stage, CLIPPARD, USA)

4-9

Fig. 4-25 : Comparison Between Switching Methods

4-10

Fig. 4-25 : Comparison Between Switching Methods

CHAPTER 5
ELECTRIC LADDER DIAGRAMS
Ladder Diagram Relays, Cylinders, Valves Symbols Sequential Sequences Relays Cascade Implementation Huffman Methode Flow Diagram Primitive and Merged Flow Tables State Assignment Output and Exitation Functions

Switching Circuit-1 Switching Circuit-2 Switching Circuit-3 Switching Circuit-4

+

Load-1

a1
-

a2

5-1

A+ Load-2

A-

Load-3

a. Valve Without Return Spring
Load-4

| | |
Switching Circuit1-n

| | |
+

a2 a1
-

Load-n A+

Fig. 5-1 : Ladder Diagram

b. Valve With Return Spring

START

STOP CR1

Fig. 5-4 : Cylinder Actuation Valves

CR1

a. Basic Circuit
a1,a2 = 10
CR1
+ -

START CR1

STOP

a1

a2

b. Basic Contacts Circuit

(Closed) A+ A-

(open)

Set Circuit
CR1

Reset Circuit

CR1

a. Position "-"

c. General Circuit

a1,a2 = 00
a1
+ -

Fig. 5-2 : Set-Reset Relay Flip-Flop
A+ START STOP CR1
CR1 CR1 Red Lamp

a2

(open) A-

(open)

b. Position "Moving"

a1,a2 = 01
CR1 Red Lamp
+ -

a1

a2

a. Example - Schematic Circuit
START
Voltage 8 7 1 2

(open) A+ A-

(Closed)

STOP

c. Position "+"

Fig. 5-5 : Positions of Cylinder Limit Switches

6

RELAY CR1
5 4

3

Red Lamp

Red Lamp

a. Normally Open
b. Example - Wiring Diagram

b. Normally Closed

Fig. 5-6 : Graphic Symbols of Limit Switches

Fig. 5-3 : Flip-Flop Implementation Example

START,A+,A-,B+,10 Sec delay,B(STEPS : 1 2 3 4 5)

5-2

a. Process Sequence (No Return Springs)
b1
START

A+ b1

START

cr1

A+

b. Step 1 : Actuate A+

a2 cr1

b2 CR1

b1 a2

START

A+ cr1 Acr1 a1

A-

B+

PROBLEM Long Start causes Actuation of A+ and A- simultaneously

b2

TMR BAdd reset (b2') to CR1

c. Step 2 : Actuate Atmr

b1 a2

START

cr1

A+ A-

f. Correct problems of (e)

cr1 CR1 a1 PROBLEM B+ is also actuated before cycle starts a2 B+ b1 cr2 b2 CR1 cr1 cr1 b1 a2 CR1 cr1 cr1 Ab2 cr1 a1 B+ tmr b2 TMR tmr BBTMR cr3 B+
START START

cr1 CR2 A+

d. Step 3 : Correct and Actuate B+

A-

cr1

A+ cr1 a1 CR3

g. Isolate Limit Swithes from Solenoids Current

PROBLEM B+ and B- are actuated simultaneously. CR1 is actuated infinitily

e. Steps 4-5 : Correct and Actuate TMR and B-

Fig. 5-7 : "Intuitive" Design Problems

RELAYS CASCADE SYSTEMS
* Avoid conflicting actuation of a cylinder * Distinguish between situations where a cylinder performs more than a single cycle

5-3

START , A+ , A- , B+ , C+ , I II

CA+ III

, A- , IV

B-

Fig. 5-10 : Typical Groups Partitioning
* Maximal size groups (to obtain minimum number of group relays) * Same "Letter" may appear no more than once in a group (to avoid conflicted commands to a cylinder) * Except for specific cases, groups Partitioning doesn't depend on having or not having valves return springs
START

cr3'

cr4'

cr2'
CR1

cr1 cr1
Group 1 Termination

Fig. 5-8 : Cascade Method Target & Rules

cr3'
CR2

cr2 cr2
Group 2 Termination

cr4'
CR3

cr3

START , A+ , A- , B+ , C+ ,

CA+

, A- ,

B-

cr3 cr4

Group 3 Termination

Group 4 (Last) Termination

CR4

a. Sequence List Representation

1 A+ AB+ BC+ CSTART a2 a1 b2

2

3

4

5

6

7

8

9

Group(s)

cr

A+ Condition(s)

Group(s)

cr

ACondition(s)

Group(s)

cr

B+ Condition(s)

Group(s)

cr

BCondition(s)

Group(s) b1 c2 c1 Group(s)

cr

C+ Condition(s)

cr

CCondition(s)

b. Flow Chart Representation

Fig. 5-11 : Typical Initial Cascade Circuit, of 3-Cylinder / 4-Groups Process

Fig. 5-9 : Typical Process Definition

START , A+ ,

AB+

, C+ ,

CA+ , A- , BSTART , A+ ,
I

AB+
II

, C+ ,

CA+
III

START , A+ , , A- ,
IV

AB+

, C+ ,

CA+ , A- , BAB+
I II
B+ duration

B-

1. Cylinders are actuated by 5/2 valves without return springs. 2. Valves are actuated electrically (solenoids).

1. Cylinders are actuated by 5/2 valves with return springs. 2. Valves are actuated electrically (solenoids). START , A+ ,

, C+ ,

CA+
III

, A- , BIV

b. Groups Partitions a. Process Sequence Information

a. Process Sequence Information

b. Groups Partitions

START

cr3' cr4' cr1

cr2'
CR1

START

cr3' cr4' cr1

cr2'
CR1

START

START

cr3' cr4' cr1

cr2'
CR1

cr3' cr4' cr1

cr2'
CR1

cr1 cr2 cr2 cr3 cr3 cr4

cr3'
CR2

cr1

a2 cr2

cr3'
CR2

cr1 cr2

cr3'
CR2

cr1

a2 cr2

cr3'
CR2

cr4'
CR3

cr2

c2 cr3

cr4'
CR3

cr2 cr3

cr4'
CR3

cr2

c2 cr3

cr4'
CR3

CR4

cr3

c1 cr4

a2

b1
CR4

cr3 cr4

cr3
CR4

c1 cr4

a2

b1
CR4

cr

A+

cr1 cr3

A+
cr

cr1

A+

A+ B+ C+

cr3 cr2 cr3 cr4 a1 a1 b2

cr

A-

cr2 cr3

A-

cr cr

B+

cr

B+ BC+ C-

cr2

B+
c. Total Initial Circuit

cr2

C+

cr cr cr
c. Total Initial Circuit

cr2 cr2 cr3

a1

Bd. Complete Circuit b2

a1

C+ Fig. 5-13 : Relay Cascade Design Process 1 (With Return Springs) C-

d Complete Circuit

5-4

Fig. 5-12 : Relay Cascade Design Process 1 (No Return Springs)

START , A+ , B+ , C+ , C- , A- , D+ , A+ , D- , B- , A- , 1. Cylinders are actuated by 5/2 valves without return springs. 2. Valves are actuated electrically (solenoids).

START , A+ , B+ , C+ , C- , A- , D+ , A+ , D- , B- , A- , 1. Cylinders are actuated by 5/2 valves with return springs. 2. Valves are actuated electrically (solenoids).

a. Process Sequence Information
START , A+ , B+ , C+ , C- , A- , D+ , A+ , D- , B- , A- ,

a. Process Sequence Information
B+ A+ D+

I

II

III

(IV)

START , A+ , B+ , C+ , C- , A- , D+ , A+ , D- , B- , A- ,

I

II

III

(IV)

b. Groups Partition
cr2'
START

cr3' cr4' cr1

cr2'
CR1

START cr3' cr4'

cr2'
CR1

b. Groups Partition
cr2'
CR1

cr1 cr3'
CR2

START cr3'

START cr3'

a1

cr2'
CR1

cr1 cr1 cr2 cr2 cr3 cr3 cr4 cr3 cr4'
CR3

cr1 cr3'
CR2

cr1 cr1

c2 cr2

cr3'
CR2

cr1 b1
CR3

cr1

c2 cr2

cr3'
CR2

cr2

d2 cr3 b1 cr4

cr2 cr2 cr2

CR3

d2 cr3

b1
CR3

a1
CR4

cr3

CR4

cr1 cr A+ cr1 cr3 cr Acr2 cr4 cr cr cr cr cr cr B+ BC+ CD+ Dcr1 cr3 cr1 cr2 cr2 cr3 a1 a2 a2 d1 b2 B+ BC+ cr1 CD+ Dcr1 c1 Acr1 A+

A+

cr1 cr3 cr3 c1

A+

B+

cr1 cr2 cr3

a2

B+

d1 b2 a1 a2 C+ D+

C+ D+

cr2 cr2 cr3

c. Total Initial Circuit

d. Complete Circuit

c. Total Initial Circuit

d. Complete Circuit

Fig. 5-15 : Relay Cascade Design Process 2 (With Return Springs)

5-5

Fig. 5-14 : Relay Cascade Design Process 2 (Without Return Springs)

5-6
* System requirements definition
External Inputs External Outputs

Combination System

* * * *

Primitive flow diagram Primitive flow table Merge options Diagram Merge groups selection

Internal State

Memory System

* Merged flow table * States assignment
Memory Exitation

* Output table * Flip-flops exitation expressions * Outputs expressions
External Outputs Z1

a. General Block Diagram
External Inputs X1 Xn Yk Y1
S R

* System Logic Circuit

Fig. 5-18 : Huffman Design Steps

Combination System

Zm

Y

Huffman method is very effective in reducing the number of relays flip-flops. It is also effective for design of systems with Random Inputs.
Set-Reset Control

Y

S R

Internal State

b. General Detailed Block Diagram

Fig. 5-16 : Sequential System
Set

Design process by Huffman method may become very complex, from "State Assignmsnt" step, and on. Furthermore, it is based on Karnaugh maps, which eliminate the number of involved variables. When system realization is based on PLC, number of "relay" flip-flops doesn't actually effect system cost. The Huffman-PLC method implements flip-flop for each state, but eliminates the complexity of Huffman method, and also enables to implement large Pseudo Karnaugh maps.

Reset Electrical Delay Mechanical Delay

td1

td3

td2

td4

Fig. 5-19 : Huffman/PLC Combination
Unstable State Stable State Unstable State

a. Relay Flip-Flop Transition Response Each transition is combined of Unstable State, followed by a Stable State. Unstable State duration is the time delay from the command start (set/reset) to its fully execution. Refering to relay flip-flop, unstable State duration is the time delay from the set (or reset) start until relay contact closing (or releasing). Unstable state i will be represented by its number : i. Stable state i will be represented by its number surround by a circle : i b. Stability Definition Two (or more) lines in flow table can be merged, as long as they don't conflict. Merging lines reduce internal states, reduce number of required flip-flops, and make design more simple.

1 1 1

2 2 2

3 3

4

-

Line i Line j

4

Merged Lines (i,j)

Fig. 5-20: Merge Flow Lines Rules

Fig. 5-17 : Stability States

START , A+ , A- Sequence a.

{1,2) , (3,4)

f. Selected Groups
a1,a2
10 00 01 3 11

START , A+ , Aa. Sequence

{1,2) , (3,4)

f. Selected Groups
a1,a2
10 00 01 3 11

START
CONTROL

a1 a2

SYSTEM

A+

1
1

2 4

-

START
CONTROL

3

a1 a2

SYSTEM

A+

1
1

2 4

-

3

b. Basic Block Diagram
START

g. Merged Flow-table
a1,a2

b. Basic Block Diagram
START

g. Merged Flow-table
a1,a2
CR1 10 0 1 00 01 3 11

1

10/1

00/0

4 3

2
01/0

00/1

CR1 0 1

10

00

01 3

11

1

10/1

1
1

2 4

-

00/0

4 3

2
01/0

00/1

1
1

2 4

-

3

3

c. Primitive Flow-diagram
a1,a2
10 00 2 01 11

h States Assignment
a1,a2
CR1 0 10 1 00 1 0 01 11

c. Flow-diagram (primitive)
a1,a2
10 00 2 01 11 CR1 0 1

h States Assignment
a1,a2
10 00 01 11

1

,1

3

-

-

2 ,1
4

0

1

1

3 ,0

-

-

1

10

-0 3

01

10

-0 0-

01

10 0 1 00 01 11

-

2
4

01

4 ,0

-

A+ i Output Table
S1 = a2 (S1 =cr1'. a1'.a2) (R1 =cr1. a1.a2')

1

3
0-

CR1

a1,a2
10 0 1 00 11 CR1

a1,a2

4

d. Primitive Flow-table
a1,a2
10 00 2 01 11 A+ 1 1 0

-

-

1

0

0

d. Primitive Flow-table
a1,a2
10 00 2 01 11 A+ A-

-

-

0

0

1

-

A-

-

R1 = a1 A+ = cr1'

1

3

-

A+

i. Output Tables

A+ = START.a1 + a1'.cr1'

-

2
4

j. Exitation and Output Functions
a1 CR1

1

3

-

1

0 0
1

1

3

a2

2
4

0 0

S1 = a2 R1 = a1 A+ = cr1'
A+ = START.a1

(S1 = cr1'.a1'.a2)
(R1 = cr1.a1.a2')

4

-

0

1

3

A- = cr1

cr1
START

4

-

-

k. Exitation and Output Functions
a2 a1

d.1 . Primitive Flow-table
(Different Format)

a1

d.1. Primitive Flow-table A+
(Different Format)

CR1
cr1

1

cr1

a1

1

START

a1

4 3

2

A+ A-

k. Relays Ladder Diagram

4

2
cr1

e. Merge Diagram

Fig. 5-21 : Sequence A+,A- (Huffman Method) (With Returned Springs)

3 e. Merge Diagram

5-7

j. Relays Ladder Diagram

Fig. 5-22 : Sequence A+,A- (Huffman Method) (Without Returned Springs)

START , A+ , A- , A+ , Aa. Sequence
START

a1,a2
10 00 01 11

1 5

2 4 6 8

3 3 7 7

START

START , A+ , A- , A+ , Aa1,a2
10 00 01 11

a. Sequence
1 2 4 6 8 3 3 7 7 5
CONTROL SYSTEM

CR

a1,a2
10 00 01 11

a1 a2

CONTROL SYSTEM

A+

5 1

-

CR1 CR2 CR3 CR4

1 5 5 1

2 4 6 8

3 3 7 7

-

b. Basic Block Diagram
10/1
START

g. Merged Flow-table
a1,a2
10 00 01 11

a1 a2

A+ A-

5 1

1 2 00/1 3 01/0 4 00/0 5 10/1

b. Basic Block Diagram
2 4 6 8 3 3 7 7

g. Merged Flow-table
CR a1,a2
10 00

h. States Assignment
01 11

00/0 01/0

8 7

CR1 CR2 CR3

1 5 5 1

-

10/10
START

1 2 00/-0 3 01/01 4 00/05 10/10
CR a1,a2
10 00

00/001/01 00/-0

8 7 6

CR1 CR2 CR3 CR4

10

-0 0-0 0-

00/1 6

CR4

10

h. States Assignment
CR a1,a2
10 00 01 11

c. Primitive Flow-diagram
a1,a2
10 00 01 11

11

- 01 - 01 CR a1,a2
10 00 01 11

A+ , A01

CR1
2 2 4 4
1 0 1

1 1 -

1 0 1 0 A+

0 0

a1,a2
10 00 10 01 11

1

1

3 3
0

5 5

-

CR2 CR3 CR4

c. Primitive Flow-diagram

CR1 CR2 CR3 CR4

1

-

1

2 2 4 4
0-0

i. Output Table
S1 = cr4.a1 R1 = cr2 (R1 = cr2.a2) S2 = cr1.a2 R2 = cr3 (R2 = cr3.a1) S3 = cr2.a1 R3 = cr4 (R3 = cr4.a2) S4 = cr3.a2 R4 = cr1 (R4 = cr1.a1) S1 = a1(cr2+cr3)' = a1.cr2'.cr3' A+ = cr1 + cr3 A+ = START.cr1.a1 + cr1.a1' + cr3

3 3
01

5 5

-

- - - 0 0 1 - - - 0 0 A+

CR1 CR2 CR3 CR4

0

- - - 1 - 0 0 - - 1 0 A-

6 6
1

1

i. Output Tables

7 7
0

-

8 8
0

-

10 6

1

6 8 8

d. Primitive Flow-table 1 8 2 3 6 4

-0

7 7
01

j. Exitation and Output Functions
a1 cr2 cr3 cr1 cr1 a2 cr2 cr2 a1 cr3 cr3 a2 cr4
START

0-

-

S1 = cr4.a1 R1 = cr2 (R1 S2 = cr1.a2 R2 = cr3 (R2 S3 = cr2.a1 R3 = cr4 (R3 S4 = cr3.a2 R4 = cr1 (R4 S1 = a1(cr2+cr3)' = a1.cr2'.cr3' A+ = cr1 + cr3 A+ = START.cr1 + cr3 A- = a2

= = = =

cr2.a2) cr3.a1) cr4.a2) cr1.a1)

cr2
CR1

d. Primitive Flow-table 1

j. Exitation and Output Functions
a1 cr2 cr3 cr1 cr2
CR1

cr3
CR2

7

8
cr4
CR3

2
cr1 a2 cr2 cr2 a1 cr3 cr3 a2 cr4
START

cr3
CR2

5 e. Merge Diagram

7
cr1
CR4

3 6 4

cr4
CR3

{1,2) , (3,4) , (5,6) , (7,8)

cr1 a1 cr3

a1

A+

f. Selected Groups

5 e. Merge Diagram
{1,2) , (3,4) , (5,6) , (7,8)

cr1
CR4

cr1

cr1 cr3 a2

A+

f. Selected Groups
Fig. 5-23 : Sequence A+,A-,A+,A- (Huffman Method) (With Returned Springs)

A-

5-8

k. Relays Ladder Diagram

Fig. 5-24 : Sequence A+,A-,A+,A- (Huffman Method) (Without Returned Springs)

k. Relays Ladder Diagram

A mixing system requires filling a tank with liquid, mix it for a specific time and then drain the liquid out. An automatic process is represented as follows : 1. Sequence starts by pressing START buttom. This opens FIll valve. 2. Liquid fills tank until HIGH level switch is operated. 3. At that time FILL valve is closed, mixing motor is turned on, and a timer is activated 4. On timeout, motor is turned off, and DRAIN valve is opened. 5. When tank is empty, LOW level switch is opened, and DRAIN valve is closed. Fill Valve F Mixer Motor M Level Switch H (High)
LHT

Process is same as defined ai Fig. 6-25/a .

5-9

a. Process definitions
000 100 110 111 101 F D M Ymr

1

2 2

3 3

4 4

5 5

1 1 0 0 0 0

0 0 0 1 1 1

0 0 1

0 0 1 1 0 0

1

6 6

-

0 0

-

-

b. Primitive Flow Table

1
Level Switch L (Low) Drain Valve D Start L H
T

6 5
MIXING SYSTEM
TMR

2

3 4

F D M

c. Merge Diagram {1 , 2 , 3} , {4 , 5 , 6} d. Selected Groups Partition

Timer

a. Process presentation and requirements definitions

F' START , F , (H) M TMR

D

LHT

L.H 000 100 110 111 101

, (T)

M'

, (L')

D'

CR 1 0

1 1

2 6

3

4 4

5

CR,T
00

00

10

11

01

1

6 5

4 4 3

-

b. Process Sequence

-

01 11 10

1

2

e. Merged Flow Table
F' START , F , M TMR
I II

D , D' M'
CR,T
III IV 00

f. "Path" Map
L.H 00 10
START

L.H

START

11

01

CR,T
00

00

10

11

01

c. Groups Partition

0
1

0

-

-

0
0

1 1 0

1 0

-

01 11

START L cr1 cr1 H cr2 cr2 cr3 cr1 cr2
T

cr3

cr2
CR1 10

0 0 - (0) 1 0 -

01 11 10

F
cr3
CR2 CR,T
00 L.H L.H

D
11 01 CR,T
00

00

10

00

10

11

01

L CR3

01 11 10

(0) 0 - 0 - 0 0

-

-

(0) 0 0

-

-

1

01 11 10

0 1 - (1) 0 1 -

F

M
g. Output Tables

TMR

M Tmr cr3 D S = L'.START R = tmr F = H'.CR D = L.CR' M=H TMR = H

h. System Functions

d. Cascade Contacts Circuit

Fig. 5-26 : Automatic Mixing System Huffman Method

Fig. 5-25 : Automatic Mixing System Cascade Method

1
10

2
00

3
01

4
00

5
10

6
00

7
01

8
00

1
10

1
10

2
01

3
10

4
01

1
10

5-10

a. Sequence Inputs

b. Ignore Input 00

Fig. 5-27 : Full/Partial Input Stream (A+,A-,A+,A-)
a1,a2
CR CR1 CR2 CR3 CR4
00 01 11

a1
10

a1,a2
CR CR1 CR2 CR3 CR4
00 01 11 10

a1

a2

1

a2

1

a1.a2'.F a1'.a2.F

a1.F a2.F

Column 00 not required Column 11 merge
b. Reduced Columns

c. Pseudo Map

a. Column 11 Merge

Fig. 5-28 : Full/Pseudo Karnaugh Maps

a1

a2

A+

A-

a1

a2

A+

A-

a1

a2

a1

a2

1 3 3 1

2 2 4 4

1 0 1 0

0 1 0 1

CR1 CR2 CR3 CR4

1 3 3 1

2 2 4 4

1 0 1 0

0 1 0 1

1

0

CR1 CR2 CR3 CR4

0

1

1

0

0

1

S1 S2 S3 S4

= = = =

CR2'.CR3'.a1.Start CR1.a2 CR2.a1 CR3.a2 A+ = CR1+CR3 A- = a2

R1 R2 R3 R4

= = = =

CR2.a2 CR3.a1 CR4.a2 CR1.a1

*

0

-

a. Primitive Flow Table

b. State Assignment

c. A+ Map

d. A- Map

e. System Functions

Fig. 5-29 : Pseudo Map For A+,A-,A+,A-

* Assigned "0" to "rest" state
b1 b2
a2.b1 a2.b2 a1.b2 a1.b1

a1
CR1 CR2 CR3 CR4

b1
CR1 CR2 CR3 CR4

a2

b2

a1

a2

a1

Fig. 5-30 : Pseudo Map For 2 Cylinders & 4 States
b1 d1
CR5 CR6 CR7 CR8

b2

d2

CR1 CR2 CR3 CR4

a1 a2 c1 c2 c1

a1

Fig. 5-31 : Pseudo Map For 4 Cylinders & 8 States

1
a2 a1 b2 b1 c2 c1

2

3

4

5

6

7

8

1

5-11
START , A- , B+ C+ A+ CB- , A- , C+ , C- , A+

a. Sequence Inputs
1

a2.b1.c1 a1.b1.c1 a1.b2.c2 a2.b2.c1 2 1

a1.b1.c2

A+

A-

B+

B-

C+

C-

8

2

5 5

2

3 3

4 4

6 6 8 8

-

-

7 7

1

0 0 1

0 0 1

0 1

0 1

0 1 0 0 0 1 0 0
6 5 4 7 3

0 0 1

0 0 0 0 0

0 0 0 1

1

0

-

-

0 1

c. Merge Diagram {1,2},{3,4,5,6},{7,8} {1,2},{3,7,8},{4,5,6) {1,2,3},{4,5,6},{7,8} d. Merge Options
Selected

-

b. Primitive Flow Table

a1

a2

a1

a1
CR1 CR2 CR3

a2

a1

CR1 CR2 CR3

(b2.c1) (a2.b1) (b2.c2) (a2.b2) (b1.c2) a2.b1.c1 a1.b1.c1 a1.b2.c2 a2.b2.c1 a1.b1.c2 3 2 1 5 1 6 8 3 4 7 7

CR1 CR2 CR3

2 6 8
b1

1 5 1

4

b2 c1

-

7 7
b1

c2

b2

3 3

-

-

-

e. Merged Flow Table f. Path Map
a1
CR1 CR2 CR3

a2

a1

a1
CR1 CR2 CR3

a2

a1

a1
CR1 CR2 CR3

a2

a1

a1
CR1 CR2 CR3

a2

a1

0 0 1
b1

0 0

c1

b2

-

0 0
b1

c2

b2

1

0
b1

1 1

0

-

c1

b2

-

b1

c2

b2

0

-

A+

A-

a1
CR1 CR2 CR3

a2

a1

a1
CR1 CR2 CR3

a2

a1

a1
CR1 CR2 CR3

a2

a1

a1
CR1 CR2 CR3

a2

a1

1 0 0
b1

0 0 0

0

b2 c1

-

0 0
b1

c2

b2

-

0

b1

c1

1

b2

-

b1

c2

b2

0 0

-

S1 = Start.a2.CR2' S2 = b2 S3 = b1.c2 R1 = b2 R2 = b1.c2 R3 = CR1.a2

B+

B-

a1
CR1 CR2 CR3

a2

a1

a1
CR1 CR2 CR3

a2

a1

a1
CR1 CR2 CR3

a2

a1

a1
CR1 CR2 CR3

a2

a1

1 1 0
b1

0 0 0

0

b2 c1

-

0
b1

c2

b2

0

0 0

-

b1

c1

b2

-

1
b1

c2

b2

1

-

A+ = CR3.c1+b2 A- = a2.b1 B+ = CR1.a1 B- = a2 C+ = a1.b1(CR1+CR2) C- = c2

C+
g. Output Maps

C-

h. System Functions

Fig. 5-32 : Pseudo Karnaugh Map Example

i
1 Wait "Ready" Signal Xi-P START - L' A1 2 F XA1 H A2 3 F' M Ytmr XA2 ..... Ytmr ZA2 ZA1

Zi

i
Xi Xi-P

Zi

B1

ZB1

A1

ZA1

B1

ZB1

XB1

XA1

XB1

B2

ZB2

A2

ZA2

B2

ZB2

XB2 .....

XA2 .....

XB2 ..... XBk-1 ZAj Bk ZBk Zi+1

XAJ-1 4 M' D Aj L' XAj 5
END

XBk-1

XAJ-1

ZAj

Bk

ZBk

Aj

XBk XAj.XBk

D'

Valve D is Closed

i+1
Xi+1

Zi+1

i+1
Xi+1

Fig. 5-33 : GRAFCET for Automated Mixing System (Fig. 5-25)

Fig. 5-34 : GRAFCET for Alternate Parallel Paths

Fig. 5-35 : GRAFCET for Simultaneous Parallel Paths

5-12

i
1 Wait "Ready" Signal Xi-P START - L' A1 2 F XA1 H A2 3 F' Ytmr M Ytmr XA2 ..... XAJ-1 4 L' XAj 5
END

ZB1

i
Xi Xi-P

Zi

ZA1

B1 XB1

ZB1

A1 XA1

ZA1

B1 XB1

ZB1

ZA2

B2 XB2 .....

ZB2

A2 XA2 .....

ZA2

B2 XB2 XBk-1 Bk .....

ZB2

XBk-1 Bk XBk ZBk Aj

XAJ-1 ZAj

M'

D Aj ZAj ZBk

D' Valve D is Closed

XAj.XBk

i+1
Xi+1

Zi+1

i+1
Xi+1

Zi+1

Fig. 5-33 : GRAFCET for Automated Mixing System (Fig. 5-25)

Fig. 5-34 : GRAFCET for Alternate Parallel Paths

Fig. 5-35 : GRAFCET for Simultaneous Parallel Paths

5-12

\
1 Start AND Initial Conditions 2 Advance Loader Piece Loaded Retract Loader Loader Retracted 4 Wait 5 Advance Clamp Piece Clamped Discend Drill Drill Down Rase Drill Drill Up Retract Clamp Piece Unclamped 9 Wait 14 Wait 10 Discend Gauge T=2s Gauge Down AND T<2s 11 Raise Gauge Gauge Up Advance Ejector Piece Ejected Retract Ejector Ejector Retacted 15 T>2s Raise Gauge Gauge Up 3 6 7 12 16 Manual Reset 8 13 =1 Rotate Plate Plate Rotated 17

Fig. 5-37 : GRAFCET for Drilling Station
(From Telemechanique TSX T607 Manual)

5-13

CHAPTER 6
SEQUENTIAL SYSTEMS WITH RANDOM INPUTS
Random Signals Examples Design as Input to PLC System

1. 2. 3. 4. 5.

Different size elements are transferred on a conveyor belt. All elements that are below specific thickness must be rejected. Reject is performed by opening a reject door - Z=1. Photocells X1 and X2 are placed in specific locations. X2 is covered by all sizes. X1 is covered by elements over specific thickness.
X1 X2

{1,2,5},{3,4}

6-1

{1,5},{2,3,4} f. Merge Options

{1,5},{2,3,4} g. Selected Options
X1,X2

00

10

11

01

1

2 2

3

5 4

a. System Definition
Photocell 1 Photocell 2 X1 X2
THOCKNESS DETECTOR SYSTEM

1
T Reject Door

h. Merged Flow Table
X1,X2

b. System Block Diagram

CR

00

10

11

01

0 00/0
1

1 1

2 2

3

5 4

10/0
2

11/0
3

01/0
4

1

i. State Assignment
X1,X2 CR

01/1
5

00

10

11

01

c. Primitive Flow Diagram

0 1

0 (0)

(0) 0

0

1 0

X1,X2

00

10

11

01

Z

j. Output Table S = X1 R = X1'.X2' Z = X2.CR' (S = X1.X2')

1

2 2

3 3

5

0 0 0 0 1

1 1

4 4 5

-

-

k. System Functions

X1

X1
CR1

d. Primitive Flow Table
CR X2 X2

1
CR

Z

5

2
X1

l. Relays Implementation

S R

Q Q'

(CR = Q)

3 4
e. Merge Diagram
X2

Z

m. Gates Implementation

Fig. 6-1 : Thickness Detector System Design

A red light signal is placed in the junction of road and raillway. Train must operate red light as soon as it enters "junction area", far from the junction, and turn it off as soon as last waggon leaves the railway (near junction). Trains may go in two direction, but the following assumption are known : * Only a single train crosses the junction area, at a time. * Train doesn't changes direction within the junction area. L
Junction Area

6-2

RAILWAY ROAD

L One of the tracks is connected to common node (Ground), while the other track is splitted - within the junction area into 3 sections, that are physically joined, but electrically isolated from the tracks outside the junction area. Mid-section is also isolated from the other 2 sections (that are connected electrically).

L

Junction Area

L

A B When the junction area is empty (no trains inside) all 3 sections are disconnected from common track, thus providing "0" signal on each section. When the train crosses a track section, it connects it electrically to the common track, thus changing its signal into "1". Signal returns to "0" as soon as last waggon leaves the appropriate section. Signaling control system senses A and B signals, and turns red light on or off, accordingly. a. System description
1

AB
2

A B

CONTROL SYSTEM

L

5

CR1 0 1

00 0 (0)

01 1 0

11 (1) 1

10 1 (0)

b. Basic Block Diagram
00/0 AB/L 01/0

4

3

1 4
3

e Merge Diagram 2
11/1
01/1

L j. Output Table

{1,2,5) , (3,4) {3.,4,5) , (1,2)

f. Merge Options
{1,2,5) , (3,4)

5 01/1 c. Flow-diagram (primitive)

g. Selected Groups
AB 00 01
2 4

S1 = AB R1 = B'

(R1' = B)

L = A + CR1'.B 11
3 3

10
5 5
A

AB 00 1 0 01 2 2 1 4 4 0 11 10

k. Control Functions
B CR1 B CR1

1 1

3 3 1

5

1

h. Merged Flow-table
AB CR1 0 00
1 1
CR1

B

3

5 1

01
2 4

11
3 3

10
5 5
A

L

-

-

1

d. Primitive Flow-table

l. System circuit i. States Assignment

Fig. 6-2 : Traffic-Light Control System Design

1. External alarm sets X1=1. It must activate siren Z1, until operator confirmation 2. Operator confirms by pressing X2 buttom. This de-activates siren. 3. If alarm signal still exists, flash light is activated. 4. After confirmation, flash also is de-activated.

6-3
{3,4,5} {2.6} {1} {1,5} {2.6} {3,4} f. Merge Options

a. System Definition

Danger Signal Confirmation

X1 X2

ALARM SYSTEM

Z1 Z2

ALARM SIREN ALARM FLASH

{1,5} {2.6} {3,4} g. Selected Options

b. System Block Diagram
00 CR1
00/00 1 10/10 2 11/01 3 10/01 4

10

11

01

1 6 1

2 2 4

3 3 3

5 5 5

CR2 CR3

01/00 5

00/10 6

h. Merged Flow Table & States Assignment

c. Primitive Flow Diagram
00 00 10 11 01 z1 z2 CR1 CR2 CR3 10 11 01 00 CR1 CR2 CR3 10 11 01

0 1 (0)

1 0

(0) (0) 0

0

0 0

(0) 0 1

1

0 (0)

1 6

2 2 4 4

3 3 3 3

5

0 1 0 0 0 1

0 0 1 1 0 0

(0)

5

-

-

1 1 6

i. Output Table of Z1

j. Output Table of Z2

5 5

2

S1 = X1'.X2'.CR2' + X1'.X2 = X1'(X2 + CR2') S2 = CR1.X1.X2' S3 = X1.X2 R1 = CR2.X1.X2' + X1,X2 = X1(X2 + CR2) R2 = X1'.X2 + X1.X2 = X2 R3 = CR1.X1'.X2' + CR1.X1'.X2 = CR1.X1' Z1 = CR2.X2' Z2 = CR3

-

d. Primitive Flow Table

1 6 2

*

k. Exitation & Output Functions

5 4
e. Merge Diagram

3

Fig. 6-3 : Alarm System Design

A

B

6-4

a. Disk Partitions ans Sensors Arrangement

90

0

Change Direction

360

0

A
1

B
"UP" direction (A leads B) "DOWN" direction (B leads A)
7

8

2

3

b. Encoder Code Waveforms for Both Directions
6 4 5

A B

CONTROL SYSTEM

D

f. Merge Diagram

c. Contro,l System Block Diagram

AB
00 01 11 10

AB
00 01 11 10

CR1

1 6 6 1

5 5

8 3 3 8

2 2 7 7

CR1 CR2 CR3 CR4

O 1
(1) (0)

1

(1) (0)

01/1
5

00/1
6

10/1
7

11/1
8

CR2 CR3 CR4

(1) (0) O (0)

4 4

O 1
D

1
(1)

O

00/0
1

10/0
2

11/0
3

01/0
4
g. Merged Flow-table & State Assignment

h. Output Table

d. Primitive Flow-diagram

S1 = CR4.A.B' + CR2.A'B' S2 = CR1.AB' + CR3.A.'B' S3 = CR2.A.B + CR4.A.B'

R1 = CR2.A.B' + CR4.A.B R2 = CR1.A'B + CR3.AB R3 = CR2.A'.B' + CR4.A'B R4 = CR1.A'.B' + CR3.AB'

AB
00 01 11 10 D

1 6 1 1 6 6 -

5 4 4 5 5 4

3 3 8 8 3 8

S4 = CR1.A.B + CR3.A'B

2 2 7 2 7 7

O O O O 1 1 1 1

D = CR1.B + CR2.A' + CR3.B' + CR4.A i. Exitation and Output Functions

Initially, while A=B=0, and all Flip-flops are in reset state (CRi=0). At that state, Flip-flop 1 must be set, with no confilict later, that is to say, while CR1 and CR2 are not set. S1 = A'B'.CR2'.CR3' j. Corrected System Initialization

e. Primitive Flow-table

Fig. 6-4 : Motor Direction Detection System Design

6-5
1. A security door is controlled by two input switches : X1 and X2 . 2. The door is opened and closed, by entering the following sequence : X1,X2 = 00 , 10 , 11 , 10 , 11 ..... 00
Open (T=1) Close (T=0)

Actually, door is opened when latest 5 inputs satisfy the sequence 00 , 10 , 11 , 10 , 11 , and closed as soon as input becomes 00.

a. System Definition

Switch X1 Switch X2

Improper Sequence

Proper Sequence

Combination Lock

T

Open Door

X1,X2 / T
01/0 8 00/0 1 01/1 7 11/0 9 10/0 10 10/1 6 11/1 5 10/0 4 10/0 2

b. System Block Diagram

11/0 3

X1,X2

00

01

11

10

T

1 1

8

3 3 5 5 5 5 9 9 9

2 2 4 4 6 6

0 0 0 0 1 1 1 0 0 0

c. Primitive Flow Diagram

8

1

1 10 2 3 4 7 6
e. Merge Diagram
X1,X2

7

1 1 1

7 8 8

9 8 5

10 10

1

-

d. Primitive Flow Table

X1,X2

00 CR1 CR2 CR3 CR4 CR5

01

11

10

00 CR1 CR2 CR3 CR4 CR5

01

11

10

{1,2},{3},{4},{5,6,7},{8,9,10}

1

8 8

3 3 5 5 9

2 4 4 6 10

0

1 1 1

7 8

-

1 0

0

0

f. SelectedMerge Partitions

0 1 0

1 0

S1 = X1'.X2' S2 = CR1.X1.X2 S3 = CR2.X1.X2' S4 = CR3.X2 S5 = CR4'.X1'.X2

R1 = CR2.X1.X2 + CR5.X1'.X2 R2 = CR3.X1.X2' + CR5.X1'.X2 R3 = CR4.X1.X2 +X1'.X2' R4 = X1'.X2' R5 = X1'.X2'

g. Merged Flow Table & States Assignment

h. Output Table

T = CR4

i. System Functions

Fig. 6-5 : Combination Lock System Design

PART 2
Chapters 7 - 12

List of Figures
July 20, 2003

PART 2 Pneumatic Control Circuits

Updated :

CHAPTER 7
Fig. 7-1 Fig. 7-2 Fig. 7-3 (a-b) Fig. 7-4 Fig. 7-5 Fig. 7-6 Fig. 7-7 (a-c) Fig. 7-8 (a-g) Fig. 7-9 Fig. 7-10 Fig. 7-11 (a-b) Fig. 7-12 Fig. 7-13 Fig. 7-14 (a-e) Fig. 7-15 (a-d) Fig. 7-16 (a-e) Fig. 7-17 Fig. 7-18 (a-d) Fig. 7-19 Fig. 7-20 Fig. 7-21 (a-b) Fig. 7-22 (a-b) Fig. 7-23 Fig. 7-24 Fig. 7-25 Fig. 7-26 Fig. 7-27 Fig. 7-28 (a-f) Fig. 7-29 (a-h) Fig. 7-30 (a-c) Fig. 7-31 Fig. 7-32 Fig. 7-33 Fig. 7-34 (a-d) Fig. 7-35 Fig. 7-36 Fig. 7-37 Fig. 7-38 Fig. 7-39 Fig. 7-40 7-1 7-1 7-1 7-1 7-1 7-2 7-2 7-3,4 7-5 7-5 7-6 7-6 7-6 7-6 7-6 7-7 7-8 7-8 7-9 7-9 7-9 7-9 7-10 7-11 7-12 7-13 7-14 7-14 7-15 7-16 7-16 7-16 7-16 7-16 7-17 7-17 7-17 7-17 7-17 7-17

Intuitive Design Of Sequence A+,B+,A-,BIntuitive Design Of Sequence A+,B+,B-,ACascade Design Of Sequence A+,B+, B-, A-,C+.CCascade Design Of Sequence A+,A-,A+,AMultiple Limit-Valves Replacement Pneumatic Cascade Basic Concept Pneumatic Cascade Group Configurations Pneumatic Cascade Design Process Steps Pneumatic Cascade Example 1 Pneumatic Cascade Example 2 Flip-Flop Valve & Steering Valve Two Steering Valves Providing Three Addresses Three Steering Valves Providing Four Addresses Design Sequence A+,A-,A+,A-,A+,ADesign Sequence A+,B+,A-,B-,(A+/B+),A-,BDesign Sequence A+,B+,B-,C+,B+,B-,C-,ASimplified Input Map Design a Sequence With Passive States Examples of Complex Functions Function Tables Background Function Tables Arrangement 3/2 Valve Connections yielding Single Output Function Valve Connections With 2 Separate Outputs, 2-Variables Input Valve Connections With 2 Separate Outputs, 3-Variables Input Valve Connections With 2 Separate Outputs, 4/5-Variables Input Valve Connections yielding Flip-Flop Output Functions Example 1 Example 2 (Huffman Solution for Sequence A+,A-,A+,A-) Solution for Sequence A+,B+,B-,A-,B+,BStop-Restart With Single Button & Separate Buttons Stop-Restart With Multiple Remote-Control Stop Buttons Electronic Circuit for Fig. 7-31 Emergency Stop Modes Definition Pneumatic / Electric

CHAPTER 8 & Systems
Fig. 8-1 (a-h) Fig. 8-2 Fig. 8-3 Fig. 8-4 Fig. 8-5 Fig. 8-6 Fig. 8-7 (a-b) Fig. 8-8 Fig. 8-9 Fig. 8-10 (a-c) Fig. 8-11 (a-b) Fig. 8-12 (a-d) Fig. 8-13 (a-c) Fig. 8-14 Fig. 8-15 Fig. 8-16 Fig. 8-17 Fig. 8-18 Fig. 8-19 Fig. 8-20 (a-d) Fig. 8-21 Fig. 8-22 Fig. 8-23 Fig. 8-24 Fig. 8-25 Fig. 8-26 Fig. 8-27 (a-j) Fig. 8-28 Fig. 8-29 Fig. 8-30 (a-c) Fig. 8-31 Fig. 8-32 (a-c) Fig. 8-33 (a-g) Fig. 8-34 (a-f) Fig. 8-35 (a-g) Fig. 8-36 Fig. 8-37 Fig. 8-38 Fig. 8-39 8-1 8-1 8-1 8-1 8-1 8-1 8-1 8-1 8-1 8-2 8-2 8-2 8-2 8-3 8-3 8-3 8-3 8-3 8-4 8-4 8-4 8-4 8-5 8-5 8-5 8-6 8-6 8-6 8-6 8-7 8-7 8-7 8-8 8-8 8-9 8-10 8-10 8-10 8-10

Miscellaneous Switching Elements
Sequence Chart for Common Timers Modes -Delay Offlinder Retraction Sequence Charts for Pulse Shaper Relay Pulse Shaper Pneumatic Pulse Shaper Basic Set-Reset Flip-Flop (SR) Toggle Flip-Flop (T) T Flip-Flop Implementation - Counters D Flip-Flop Implementation Shift Register 10-Stage Shift Register Shift Register With 4 Parallel Tracks Schmitt-Trigger Response Schmitt-Trigger Response to Fuzzy Waveform Truth Table for Error-Checking of BCD code Truth Table for 2-Out-of-5 Code Use of Karnaugh Map to Obtain Cyclic Code Reflected Cyclic Code for Six Numbers Binary 8-Section Encoder Typical 8-Section Encoder Single-Output Incremental Encoder Two-Output Incremental Encoder Motor Direction Detection System Design (Copy of Fig. 6-4) Simplified Block Diagram of a Closed-Loop NC System Block Diagram of Open-Loop NC System Adder for 2-Bit Numbers Iterative Adder Block Diagram Iterative Binary Adder Design Iterative Parity Checker Iterative 2 Out of n Checker Iterative Binary Numbers Comparator Comparison Between Natural-Binary & Reflected Cyclic Code Iterative Circuit for Translating Natural-to-Reflected Cyclic Code Iterative Circuit for Translating Reflected Cyclic to Natural Truth Table for Translating Natural-to-Reflected Cyclic Code

CHAPTER 9 Semi-Flexible Automation Hardware Programmers
Fig. 9-1 Fig. 9-2 Fig. 9-3 (a-b) Fig. 9-4 (a-b) Fig. 9-5 Fig. 9-6 Fig. 9-7 Fig. 9-8 Fig. 9-9 (a-e) Fig. 9-10 (a-e) Fig. 9-11 (a-c) Fig. 9-12 (a-c) Fig. 9-13 (a-e) Fig. 9-14 Fig. 9-15 Fig. 9-16 Fig. 9-17 Fig. 9-18 9-1 9-2 9-2 9-2 9-2 9-2 9-2 9-2 9-3 9-3 9-4 9-4 9-4 9-5 9-5 9-5 9-5 9-6 Drum Programmer Drum Programmer Solution Patch Board & Matrix Board Schematic Representation of Programmable Counter Programmable Counter With a Single-Cycle Start Mode Sequence A+,B+,C+,A-,(B-/C-),A+,A- - No Return Springs Sequence A+,B+,C+,A-,(B-/C-),A+,A- - With Return Springs Programmer Based on 1/n Code Programmer Based on 2/n Code Programmable Counter Example 1 Programmable Counter Example 2 2/n Stability Cases 1/n Code Programmer for Two Simultaneous Parallel Paths 1/n Code Programmer for Two Alternative Parallel Paths 1/n Code Programmer With Skipped Steps Option 1/n Code Programmer With Repeated Steps Option Flow Chart for Selecting System Design Method

CHAPTER 10 Flexible Automation Programmable Controller
Fig. 10-1 10-1 Fig. 10-2 10-1 Fig. 10-3 10-1 Fig. 10-4 10-1 Fig. 10-5 10-1 Fig. 10-6 10-1 Fig. 10-7 10-1 Fig. 10-8 (a-b) 10-1 Fig. 10-9 10-2 Fig. 10-10 10-2 Fig. 10-11 10-2 Fig. 10-12 10-3 Fig. 10-13 10-3 Fig. 10-14 10-3 Fig. 10-15 (a-e) 10-4 Fig. 10-16 (a-g) 10-4 Fig. 10-17 10-5 Fig. 10-18 10-5 Fig. 10-19 10-5 Fig. 10-20 10-5 Fig. 10-21 10-5 Fig. 10-22 10-5 Fig. 10-23 10-5 Fig. 10-24 (a-f) 10-6 Fig. 10-25 (a-b) 10-7 Fig. 10-26 (a-b) 10-7 Fig. 10-27 (a-b) 10-7 Block Diagram of Programmable Controller (PLC) PLC Classifications According to Size Discrete Input Devices to PLC Discrete Output Devices Actuated by PLC Standard Discrete I/O Interface Modules Type of Electronic Memories I/O Connection Diagram PLC- Different I/O Connections Locations Typical PLC Memory Map PLC Programming Languages Ladder Diagram Section Appearing on Screen PLC Configuration Typical PLC Control System PLC Network (Macro) PLC I/O Variables Assignment PLC Motor Control System Forward/Reverse Circuit Example of Ladder Diagram Segment I/O Assignment for Fig. 10-18 Ladder Diagram of Fig. 10-18 in PLC Format PLC Program for Fig. 10-20 Use of LIFO Memory Stack PLC Program for Fig. 10-22 PLC Cascade Design for sequence (A+/B+),C+,A-,C-,C+,(B-,C-) Multiple Use of LIFO Stack Rearrangement of Ladder-Diagram to Simplify Program Timer Set for 20 Sec

Fig. 10-28 10-7 Fig. 10-29 (a-b) 10-7 Fig. 10-30 10-7 Fig. 10-31 (a-b) 10-7 Fig. 10-32 (a-c) 10-7 Fig. 10-33 10-8 Fig. 10-34 (a-b) 10-8 Fig. 10-35 (a-c) 10-8 Fig. 10-36 (a-d) 10-9 Fig. 10-37 (a-c) 10-9 Fig. 10-38 (a-c) 10-10 Fig. 10-39 (a-c) 10-10 Fig. 10-40 (a-d) 10-10 Fig. 10-41 (a-c) 10-10 Fig. 10-42 10-11 Fig. 10-43 (a-b) 10-11 Fig. 10-44 10-11 Fig. 10-45 10-11 Fig. 10-46 10-11 Fig. 10-47 10-11 Fig. 10-48 10-11 Fig. 10-49 10-12 Fig. 10-50 10-12 Fig. 10-51 10-12 Fig. 10-52 10-12 Fig. 10-53 10-12 Fig. 10-54 10-12 Fig. 10-55 10-13 Fig. 10-56 10-13 Fig. 10-57 10-13 Fig. 10-58 10-13 Fig. 10-59 10-13 Fig. 10-60 10-13 Fig. 10-61 (a-f) 10-14 Fig. 10-62 (a-e) 10-14 Fig. 10-63 (a-l) 10-15 Fig. 10-64 (a-e) 10-16 Fig. 10-65 (a-i) 10-17

PLC Program for Fig. 10-27 Counter Set to Count to 25 PLC Program for Fig. 10-29 PLC Light-Flash Program PLC Up/Down Counter Program Two-Hand Safety Circuit Using PLC PLC Design for Sequence 6x(D+,D-),D+,10 sec delay.DLadder Diagram and Program for sequence of Fig. 10-34 Timers and Counters Master-Control-Relay Command (MCR) Jump Command (JMP) Equivalent PLC and Relay Circuits

Effect of Scanning Action on Internal States of Relays
Importance of Proper Rung Order Trigger Flip-Flop Circuit for PLC PLC Sequence Chart for Fig. 10-44 Analog Input Devices for PLC Standard Analog-Input Interface Modules Analog Output Devices Actuated by PLC Standard Analog-Output Interface Modules Storing an Analog Input Value Transferring a Word to Analog Output Module

Logic Operations Data Commands PLC Micro/Macro Definition Several Possible LAN Topologies PLC Design of Thickness Detector System PLC Design of Traffic Light Control System PLC Design of Alarm System PLC Design of Motor Direction Detector System Combination Lock System

CHAPTER 11 Automation
Fig. 11-1 11-1 Fig. 11-2 11-1 Fig. 11-3 (a-c) 11-1 Fig. 11-4 11-1 Fig. 11-5 11-1 Fig. 11-6 11-1 Fig. 11-7 11-2 Fig. 11-8 11-2 Fig. 11-9 11-2 Fig. 11-10 11-2 Fig. 11-11 11-2 Fig. 11-12 11-2

Introduction to Assembly

Bladed Wheel Hopper Feeder Central Board Hopper Feeder Shape of Centerboard Slot Rotary Centerboard Hopper Feeder Design Sheet for Reciprocating Tube Hooper Feeder Revolving Hook Hopper Feeder Design Sheet for Tumbling Magnetic-Disk Hopper Feeder Vibratory Bowl Feeder Design Sheet for Vibratory Bowl Feeder Disk Feeder Slide Escapement

CHAPTER 12
Fig. 12-1 (a-b) 12-1 Fig. 12-2 12-1 Fig. 12-3 12-1 Fig. 12-4 12-1 Fig. 12-5 12-1 Fig. 12-6 12-1

Robotics and Numerical Control

Cartesian Robot and Coordinate System Cylinde Robot and Coordinate System Spherical Robot and Coordinate System Articulated Robot and Coordinate System Robot Work Envelope RCC Device

CHAPTER 13
13-1 13-3 13-7

Simester Exams

Simester Exam Example - Questions Simester Exam Example Responses Typical Simester Exam Questions - Questions

CHAPTER 7
PNEUMATIC CONTROL CIRCUITS
Pneumatic Cascade Design Pneumatic Flow Table Design Valves Function Tables Emergency Stop Modes

7-1
CYLINDER "A"
+ -

a1

a2

CYLINDER "B"
+ -

b1

b2

CYLINDER "A"
+ -

a1

a2

CYLINDER "B"
+ -

b1

b2

A-

+

-

A+
START

B-

B+
+ -

A-

+

-

A+
START

B-

+

-

B+

Fig. 7-1 : Intuitive Design for Sequence Start , A+,B+,A-,B-

START (A+) Conflicts With A- Actuation (by b1) More Conflicting States

Fig. 7-2 : Sequence Start , A+,B+,B-,A-

CYLINDER "A"
+ -

a1

a2

CYLINDER "B"
+ -

b1

b2

CYLINDER "C"
+ -

c1

c2

A-

+

-

A+

B-

+

-

B+

C-

+

-

C+

I II 1
+ -

2

Start , A+ , B+ , B- , A- , C+ , CI II I
b. Cascade Circuit

a. Cascade Groups Partitioning

Fig. 7-3 : Cascade Design for Sequence Start , A+,B+,B-,A-,C+,C-

CYLINDER "A"

a1
+

a2

A-

+

-

A+

-

I II III IV 2
+ -

.....

+

+

+

3
+ -

Fig. 7-5: Multiple Limit Valves Replacement

1
+

4

Fig. 7-4 : Cascade System for Sequence Start , A+,A-,A+,A- (Cascade)

+

Pure pneumatic control system Simplicity and realiability Limited to control cylinders with actuation valves that satisfy the following restrictions : * Valves do not have return springs * Valves are operated pneumatically (no solenoids) Group Partitioning differences between pneumatic and relays cascade are : * There is always an active group, even when not operating (START is also included within a group) * Last Group may be merged with first group, provided that groups do not conflict

7-2

Fig. 7-6 : Pneumatic Cascade Basic Concept

I II

2 GROUPS
1
+ -

2

a. 2-Groups Manifold Lines Configuration

I II III 2
+ -

3 GROUPS
1
+ -

3

b. 3-Groups Manifold Lines Configuration

I II III IV 2
+ -

3
+ -

4 GROUPS

1
+

4

c. 4-Groups Manifold Lines Configuration

Fig. 7-7 : Pneumatic Cascade Group Configurations

7-3
ORIGINAL SEQUENCE SEQUENCE GROUPS

B+ START, A+, C+ , B-,

B+ , A-

BSTART, A+, CI

B+ , B-, C+
II

B+ , AIII

BCIV

a. Process Sequence Definition

b. Sequence Groups Partioning

1. cylinder actuated by valves without return springs. 2. A set of two limit valves.

1. cylinder actuated by valves without return springs. 2. Two sets of two limit valves. 3. A two-input OR gate for each valve control.

CYLINDER "A"

a1
+ -

a2
CYLINDER "B"

A+ -

A+
+ -

b1

b2

B+ -

B+

c. Single-Cycle Cylinder Requirement d. Two-Cycle Cylinder Requirement

1. System consists of 3 cylinders, each equipped with limit-valves 2. Cylinders "A" and "C" perform single cycle (each), and require a single set of limit valves. 3. Cylinder "B" performs two cycles, and requires two sets of limit-valves, and OR valves. 4. A START valve is also required.

CYLINDER "A"

a1
+ -

a2

CYLINDER "B"

CYLINDER "C"

c1

c2

b1
+ -

b2
+ -

A+ -

A+

B+ -

B+

C+ -

C+

START

e. System Cylinders Requirements

Fig. 7-8 : Pneumatic Cascade Design Process Steps

7-4
CYLINDER "A"
+ -

a1

a2

CYLINDER "B"

CYLINDER "C"

c1

c2

b1
+ -

b2
+

A-

+

-

A+

B-

+

-

B+

C-

+

-

C+

START

-

I II III IV
+ -

2

B+
+ -

B+ , B-, , AII III

BCIV

3

START, A+, C+

1

-

+

4

I

f. System Components

CYLINDER "A"

CYLINDER "B"

a1
+ -

a2 b1
+ -

CYLINDER "C"

c1

c2

b2
+

A-

+

-

A+

B-

+

-

B+

C-

+

-

C+

START

-

I II III IV
2
+ -

3
+ -

1

4
+

g. Complete System

Fig. 7-8 : Pneumatic Cascade Design Process Steps (Cont'd)

A+ START , B+ , B- , A- ,

C+ , D+

DSTART , C-

A+ , B- , A- , B+

C+ , D+

DC-

7-5

I
CYLINDER "A" CYLINDER "B"

II
c1

I
c2
CYLINDER "D"

CYLINDER "C"

a1
+ -

a2 b1
+ -

d1

d2

b2
+ + -

A+ -

A+

B-

+

-

B+

C-

+

-

C+

D-

D+
+ -

START

I II

2

+

-

1

Fig. 7-9 : Pneumatic Cascade Example 1
(from semester exam September 2002)

ASTART, A+, B+, C+

,

BSTART, A+, B+, CI

AC+
II

,

BCIII
CYLINDER "C"

CYLINDER "A"

a1
+ -

a2

CYLINDER "B"

c1

c2

b1
+ -

b2
+ -

A-

+

-

A+

B-

+

-

B+

C-

+

C+

START

I II

III
+ -

2

1

+

-

3

Fig. 7-10 : Pneumatic Cascade Example 2
(from semester exam July 2002)

y R
+

y' S c2.y1.y2 R2
+

7-6
c2.y1.y2.y3 c2.y1.y2' S2 R2
+

c2.y1.y2.y3'
+

R3

-

S3 c2.y1.y2' S2 c2.y1'

a. Flip-Flop Valve

c2.y R
+

c2.y' S R1
+

c2.y1' S1 R1
+

S1

c2 b. Steering Valve

c2 c2

Fig. 7-11 : Flip-Flop Valve and Steering Valve

Fig. 7-12 : Two Steering Valves providing 3 addresses

Fig. 7-13 : Three Steering Valves providing 4 addresses

START,A+,A-,A+,A-,A+,Aa. Process sequence

START,A+,B+,A-,B-,

A+ ,A-,BB+

a. Process sequence

a1.b1 a1
1 2 3 4 5 6 b. Flow Table

a2.b1

a2.b2

a1.b2

A+ A- B + B-

a2

A+ A-

a1
y1' 1 R 3

a2
2 S1 R2

A+ A-

y1' 1

1
1 R2

1 1 1 1 1 1

1
y3'

1
y2'

1 1 1 1 1

y1.y2'

3 R4
y3.y4' 4 S2

S3

3 R3
y3'

1
4 S1

1 1 1 1 1

y1

5 s2
y2 6 S3 y3 7 R 1

y1.y2

5 S4
y3.y4

6 R1

c. Complete Flow Table

b. Complete Flow Table

S1= a2.y3' R1 = a2.y3.y4

S2 = a2.y3.y4' R2 = a2.y3'

S3 = a1.y1.y2' R3 = a1.y1'

S4 = a1.y1.y2 R4 = a1.y1.y2'

S1 = a1.b2.y3' R1 = a1.b2.y3

S2 = a1.b1.y1 R2 = a2.b1

S3 = a2.b2.y2 R3 = a2.b2.y2'

A+ = a1.y1'.Start+a1.y1.y2'+a1.y1.y2 = a1.y1'.Start+a1.y1 A- = a2.y3'+a2.y3.y4'+a2.y3.y4 = a2.y3'+a2.y3 = a2 d. Exitation and Output Functions

A+ = a1.b1.y1'.Start+a1.b1.y1 = a1.b1.Start+a1.b1.y1 A- = a2.b2.y2'+a2.b2.y2 = a2.b2 B+ = a2.b1+a1.b1.y1 B- = a1.b2.y3'+a1.b2.y3 = a1.b2 c. Exitation and Output Functions

S4 R2

a1.y1.y2

a1.y1.y2'

S3 R4 R1

a2.y3.y4 R4
-

a2.y3.y4'
+

S2 A+ B+

-

+

S2 A+

S4

a1.y1 R3 R1
+

a2.y3
START

S3 R3 S1 R2 S2 R1 R2 A(a2.b1) a1
-

R1 S1 a1.b2.y3 a1.b2.y3'
+

a1.y1' S1

a2.y3' R3
+

a2.b2.y2 a1.b1.y1 a1.b1.y1'
+

a2.b2.y2'
+

S3

S1

R2

-

S2

R3

-

S3

(a1.b1)
+

Aa2
+

a2.b2

Ba1
+

a1.b2

a1 e. Control Circuit

a2 a2 b2 d. Control Circuit b2

b1

Fig. 7-14 : Pneumatic Flow-Table Design for
sequences START,A+,A-,A+,A-,A+,A-

Fig. 7-15 : Pneumatic Flow-Table Design for
Sequence START,A+,B+,A-,B-, A+ ,A-,BB+

START,A+,B+,B-,C+,B+,B-,C-,Aa. Process sequence

7-7

a1.b1.c1 (a1) 1 R1

a2.b1.c1

a2.b2.c1 (b2.c1)

a2.b1.c2 (b1.c2)

a2.b2.c2 (b2.c2)

A+ A- B+ B- C+ C1

y1' 2 S1 3 R2 y1.y2' 4 R3 y3' 5 6 S3 y3 7 S2 y1.y2 8
b. Complete Flow Table

1 1 1 1 1 1 1

a1 c1 c2 b1

a2

X

X X X X
b2 b1

a1 a2 a2 a2

b1 b2 b1 b2

c1 c1 c2 c2

a1 b2 a1 b1 c2 b2 c2

S1 = b2.c1 R1 = a1 A+ = a1.START

S2 = b1.c2.y3 R2 = b2.c1

S3 = b2.c2 R3 = a2.b1.c1.y1.y2' A- = a2.b1.c1.y1.y2 B- = b2.c1+b2.c2 = (b2) C- = b1.c2.y3

c. Simplifiying Input Map

B+ = a2.b1.c1.y1'+b1.c2.y3' C+ = a2.b1.c1.y1.y2'

d. Exitation and Output Functions

S2

C-

B+

A-

R3 C+

S3

S1

R2 B-

A+

R1

a2.b1.c1.y1.y2

a2.b1.c1.y1.y2'
+

R2

-

S2

b1.c2.y3

b1.c2.y3'

a2.b1.c1.y1'

R3

-

+

S3
(b1.c1)

S1

-

+

R1
(b2.c2) (b2.c1)
+

(b1.c2)

a2.b1.c1
+

c1

-

+

c2

c1

-

c2

b1

a2

b2

a1

e. Control Circuit

Fig. 7-16 : Pneumatic Flow-Table Design for Sequence START,A+,B+,B-,C+,B+,B-,C-,A-

a1 c1

a2 c1 d1 c2 d2 c1

a1

a2

a1 b1 c1 d1 e1
d1

a1 a1 e2 a2 b1 c1 d1 b2 c2 d2

7-8

X

X

X X X

a1 b1 c1 d1 e2 a2 b1 c1 d1 e2 a2 b2 c1 d1 e2 a2 b1 c2 d1 e2 a2 b1 c1 d2 e2

c2 c1 b1 b2 b1

d2

X
b1 b2 b1

e1

e2

Fig. 7-17 : Simplifiying Input Map for Sequence START,E+,A+,B+,B-,C+,C-,B+,B-,D+,D-,A-,E-

a1 a2 a3 a4
+ -

a. Cylinder Type

START,A+,(a4),A-,A+(a3),A-,A+,(a2),Ab. Required Sequence

a1
y1' 1 R3 R4

a2

a3

a4

A+ A-

1
y3' 1 P y4' 3 P

4 R2
y4' 5 P y3' 6 P y1.y2' 7 S4 y3' 8 P y4 y3' 10 P y1.y2 11 S3 y3 12 R 1

S1

1

1 1 1 1

9 S2

c. Simplified Flow-Table

S1 = a4 R1 = a2.y3

S2 = a3.y4 R2 = a4

S3 = a1.y1.y2 R3 = a1.y1' A- = a4+a3.y4+a2.y3

S4 = a1.y1.y2' R4 = a1.y1'

A+ = a1.y1'.START+a2.y1 = = a1.START+a2.y1

d. System Functions

Fig. 7-18 : Design a Sequence With Passive States

Efficient Use of Directional-Control Valves in Fluid-Logic Circuits
A+B AB B
+ -

T P
+

T S
+ -

R

1

A 0

A.B' A+B'

Various types of directional-control valves have been systematically analized to determine the logic output functions obtained for different input-signal combinations. It was found that a surprisingly large variety of fairly complex logic functions can be obtained with a single valve.The results are summarised in five tables which include 186 (i.e. all the significant) input-signal combinations. Several examples are presented, illustrating how the tables can be used to implement given fluid-logic functions with a minimum number of valves. It thus becomes possible to exploit the logic capacity of these valves to their fullest extent, which can result in considerable reduction in the number of valves.
P
+

2

3

2

3

3/2 Valve Gate
T1 T2 P
+

3/2 Valve Flip-Flop
T1 T2 S
+ -

R

2

3

4

2

3

4

5/2 Valve Gate

5/2 Valve Flip-Flop

B

+

-

D.W. Pessen
0 A 1

.

..

P1 2 3 4 5 2 3 4

P2

AC+BC'

AC'+BC

Associate Professor Dept of Mechanical Engineering, Technion - Israel Institute of Technology, Haifa, Israel Mem ASME

6/2 Valve Gate

5/3 Valve Gate Note : Use of shuttle valves is uaually less expensive.

a. Valves Pins Assignment

Fig. 7-20 : Function Tables Background
C
+ -

T

A

B A

P

+

Fig. 7-19 : Examples of Complex Functions
a. 3/2 Valve , Single Output Function b. Two Separate Output Function, 2 Input Variables
1 2 3 4 5 6 7 YES NOT AND OR INHIBITION IMPLICATION SELECTOR

2 3

Line No. 1 2 3 4 5 6 7 8 9

Function Name YES NOT AND AND OR OR INHIBITION IMPLICATION SELECTOR

Boolean Function T=A T = A' T = AB T = AB T = A+B T = A+B T = AB' T = A+B' T = AC+AC'

P A A B B B B B B C

2 1 0 A A 1 B 0 A A

3 0 1 0 B A A A 1 B

c. Two Separate Output Function, 3 Input Variables d. Two Separate Output Function, 4/5 Input Variables e. Two Separate Flip-Flop Output Function b. Tables List

b. 3/2 Valve Connections yielding Single Output Function

a. Function Search Order

7-9

Fig. 7-21 : Function Tables Arangement

Fig. 7-22 : 3/2 Valve Connections yielding Single Output Function and Valves Pins Assignment

7-10

7-11

No.

FUNCTION NAME

BOOLEAN FUNCTION 1 T2=C T2=AB T2=AC T2=AC T2=AC T2=BC T2=AC T2=B+C T2=B+C T2=B+C T2=B+C T2=A+C T2=A+C T2=A+C T2=B+C T2=B+C

BOOLEAN FUNCTION 2

Valve 5/2 P234

Valve 6/2 P2345 CAB10 CAB01

Valve 5/3 P1 P2 2 3 4

59 60 61 66 70 73 75 79 81 84 85 86 87 90 91 94 95 96 97 99 100 101 103 104 105 107 109 110 112 113 114 115 117 118 119 120 121 122 127 128 129 131 132 133 134 135

YES/SELECTOR NOT/SELECTOR AND/OR AND/AND AND/INHIBITION AND/IMPLICATION AND/SELECTOR AND/SELECTOR OR/OR OR/OR OR/INHIBITION OR/INHIBITION OR/IMPLICATION OR/SELECTOR OR/SELECTOR OR/SELECTOR OR/SELECTOR INHIBITION/INHIBITION INHIBITION/INHIBITION INHIBITION/IIMPLICATION INHIBITION/IIMPLICATION INHIBITION/SELECTOR INHIBITION/SELECTOR IMPLICATION/IMPLICATION IMPLICATION/IMPLICATION IMPLICATION/SELECTOR IMPLICATION/SELECTOR SELECTOR/SELECTOR AND+AND/AND+AND AND+AND/AND+ AND+AND/INHIBITION AND+AND/IMPLICATION AND+INHIBITION/AND+INHIBITION AND+INHIBITION/INHIBITION+ AND+INHIBITION/OR AND+INHIBITION/AND AND+INHIBITION/INHIBITION AND+INHIBITION/IMPLICATION AND+/AND+ AND+/INHIBITION AND+/IMPLICATION INHIBITION+/INHIBITION+ INHIBITION+/OR INHIBITION+/AND INHIBITION+/INHIBITIOM INHIBITION+/IMPLICATION

T1=B+C T1=BC T1=BC

BABC CA0B0 CA0B CA0B1 CAB0 CABA0 C1B1A CCBCA C1B0A CCB0A CB1A C1AB CCAB C1BAB CCBAB C0A0B B C 0 A 0 C0AB1 B C 0 A 1 C0AB C0BAB CA1B1 C CAB1 CABA1 CABA BC1A1

T1=A+C T1=A+C

T2=AB+AC T2=AB+AC T2=AB+AC T2=AB+AC

T1=AC+BC T1=A+BC

T1=B+C T1=BC

T2=A+BC T2=A+BC T2=A+BC T2=

T1=C+AB

T1=B+C T1=BC

C C C C B B B B B B A A A C C C C C

A A A A C C C C C C C C C B B B B B

A A A A A A A A A A A A A A A A A A

B C B A B 0 B 1 0 A B A B C 0 B B 0 0 1 B C B 0 B 1 1 A 1 B B C 1 0 B 1

Fig 7-24 : Valve Connections Yielding 2 Separate Output Functions, 3 Variables

7-12

7-13

No.

Output 1 No Input Variables T=y

Output 2

3/2 Valve 2 3

5/2 Valve 2 3 4

161 162 163

1 0 T2=y 0 1 0 1 0 1

T1=y One Input Variables T=Ay T2=Ay T1=Ay T1=Ay T1=y T=A+y T1=A+y T2=A+y T2=y T2=A+y T1=A+y Two Input Variables T1=Ay T2=B+y A B T2=By T1=A+y Three Input Variables T2=Ay A 1 1 A

164 165 166 167 168 169 170 171 172 173 174 175 176 177

A 0 0 A 0 A A 1 A 0 0 0 0 A 1 A

1 A A 0 0 1

A 1 1 1 A A

1 A 0 A 1 0

178 179 180 181 182 183 184 185

A 0 B A 1 B A A 0 1 A B B A A B 0 1 B B A

186

A B C

Fig. 7-26 : Valve Connections Yielding Flip-Flop Output Functions

Required Functions

7-14
Start a1
CONTROL SYSTEM

F1 = X1.X2' F2 = X1.X2 + X2'.X3
F1 is Inhibition Function F2 is Selector Function

A+

a2

Search in 3-variables table Found Functions 101 and 103 Only 101 satisfies requirements F1 = X1.X2'
X2

Y1

Y Y'

1

S R

S1 R1 S2 R2

F2 = X1.X2 + X2'.X3

Y2

Y Y'

2

S R

+

-

1 X1 X3

d. System Solution Block Diagram
(Huffman Method Realization)

Fig. 7-27 : Example 1
START,A+,A-,A+,Aa. Process Sequence
Start a1 a2
CONTROL SYSTEM

* Start , a1, a2 are external signals * y1 ,y2 are outputs of internal flip-flops * S1,R1,S2,R2 are Set/Reset of those flip-flops
A+

* Functions that contain only external variables are to be searched in first 4 tables * Function that contain internal variables (y) are to be searchedfirst in fifth table * In current system, all functions contain internal variables, so they are to be searched in fifth table

b. System Block Diagram

S1=Start.a1.y2' S2=a2.y1

R1=a1.y2 r2=a2.y1'

e. Design Considerations
A+ = y1.y2'+y1'.y2 A- = a2 C. Huffman Method Solution

A+

y1.y2'+y1'.y2

Start.a1.y2' R2 S1 a2.y1' a1.y2 S2 a2.y1

S2

-

+

R2

a1.y2' S1

180
S1
-

y1'

y1
+

R1 R1 S2 R2

-

+

R1

-

+

166
A-

162

166 a1 a2

f. System Valve Circuit

Fig. 7-28 : Example 2

START,A+,B+,B-,A-,B+,Ba. Process Sequence

7-15 1

a1b1
1

a2b1
2 2 4 4

a2b2

a1b2

A+ A1 0 0 0 1

B+ B0 1 0 0 1 0

3 3

5 5 1

-

-

6 6

0 1

6

2

0 0 0

0 1

5 4
c. Merge Diagram

3

-

b. Primitive Flow Table
y b1 0 1 b2 b1 b2 b1 b2

{1,2,6} {3,4,5} d. Selected Option

1 5
a1

2 4 a2

3 3

6 6
a1

0 1

0

0

1

0 0
a1

0 1

0
a1

0 a2

0 0

1
a1

a1

a2

-

e. Merged Flow Table & States Assignment
b1 0 1 b2 b1 b2 b1

S = a2.b2

R = a1.b2

f. Exitation Functions
b2 b1 b2

y

1 0
a1

0 a2

0

0 0
a1

0 1

0

0 1 a2

0 0

-

a1

a1

0 1

0 1
a1

1 0 a2

0

0

0 1

0
a1

0

1 a2

1

a1

-

a1

A+ = Start.b1.y'

A- = b1.y

B+ = a2.y'+a1.y

B- = b2

g. Output Functions
BB+ a2.y'+a1.y 180 R
+ -

A-

A+

b1.y

b1.y'

S

R 166
(a2.b2)
+

-

+

S

a2 c1

b1

166
a2
-

(a1.b2)

a1

b2

h. System Valve Circuit

Fig. 7-29 : Solution for Sequence START,A+,B+,B-,A-,B+,B-

7-16

EMERGENCY STOP
Stop process due to emergency condition Easy accessible buttons Safety continuation Restart (Continue) Different modes Add-on a. Target & Definition
RESTART STOP

STOP

CONTINUE

CONTINUE RESTART

b. Single STOP-RESTART button

c. Separate STOP/RESTART buttons

Fig. 7-30 : STOP-RESTART Single/Separate Buttons

STOP

STOP

STOP

RESTART

STOP

CR1
STOP

STOP cr1 RESTART

+

-

cr1 CONTINUE CONTINUE

Fig. 7-31 : STOP-RESTART With Multiple Remote-Control STOP Buttons

Fig. 7-32 : Electric STOP-RESTART System With Multiple Remote-Control STOP Buttons

No Change
Cylinder at rest must remain at rest. Cylinder in motion must complete its stroke, and remain at rest.

C
+

C

No Motion
Cylinder at rest must remain at rest. Cylinder in motion must be disconnected from pressure and move until stopped by friction (or end stroke).

To limit valves

To limit valves

Lock Piston
Cylinder at rest must remain at rest. Cylinder in motion must be locked at its current position.

a. No-Change Mode Pneumatic Actuation

b. No-Change Mode Electric Actuation

Safety Position
Cylinder must be moved to its either (+) or (-) position, which been pre-definrd as "Safety Position".

C
+

C

No-Change/No-Motion
Combination of No-Change and No-Motion modes.

To cylinder valves

To cylinder valves

No-Change/Lock-Piston
Combination of No-Change and Lock-Piston modes.

c. No-Motion Mode Pneumatic Actuation

d. No-Motion Mode Electric Actuation

No-Change/Safety-Position
Combination of No-Change and Safety-Position modes.

Fig. 7-34 : No-Change & No-Motion Circuits

Fig. 7-33 : Emergency Stop Modes Definition

7-17
Cylinder "A" Cylinder "A"
+ -

+

-

+

+

A-

-

+

A+

C C A+

a1+a2 a1 a2

A+

Fig. 7-35 : "Lock-Piston" Mode Circuit
Fig. 7-38 : "No-Change/No-Motion" Mode Circuit

Cylinder "A"
A+ A-

0
C VA+
+

C
+

A-

VA-

A+
a1

-

+

- - - 0 0
C

0 0

1 1 1

0
a2 a1

1 0

0 0

1 1

1 0

+

-

0

- - - - 0 1 C

a2

VA+ = C(A+)

VA- = C(A-)+C'.a2'

Fig. 7-36 : "Safety-Position" Mode Circuit (Applied to an Individual Cylinder)

Fig. 7-39 : Karnaugh Maps for "No-Change/Safety-Position"Circuit

Cylinder "A"

Cylinder "A"

from control circuit

+

+

-

C

-

C VA+

VA-

-

+

VA+=A+

A+

Aa2'

VA+

A+

+

from control circuit

Aone valve per cylinder To all shuttle valves

C'
C
+

C

air supply to control circuit

Fig. 7-40 : "No-Change/Safety-Position" Mode Circuit

continue cycle

one valve for the whole system

Fig. 7-37 : "Safety-Position" Mode Circuit
(Applied to Entire System)

+

CHAPTER 8
SWITCHING ELEMENTS
AND

SYSTEMS
Timers Flip-Flops (FF) FF Implemntation for Binary Counters FF Implemntation for Shift Registers Endocers Iterative Circuits Binary Codes

Output

Control Delay Output

Control

Delay A
Output

Control Signal
Delay B

Volume

+

-

Bias Pressure (from pressure regulator)

a. On-Delay
Control

e. On-Delat Off-Delay
irrelevant

Fig. 8-5 : Pneumatic "On-Delay" Timer Using Bias Pressure

Control Output Delay

Output

Delay A Delay B

A
+ -

START

b. Off-Delay
irrelevant Control Output Delay Control

f. Delayed Interval ADelay B

+

-

A+

Delay A Output

c. Interval

g. Monitored Delayed Interval Volume
+

Control Output Delay

Control Output

d. Monitored Interval

h. Repeat Cycle

Fig. 8-6 : "On-Delay" Timer for Automatic Cylinder Retraction
1 1

Fig. 8-1 : Sequence Chart of Common Timer Modes
Input (Output)' Needle Valve Volume
+

0 1

Input

0 1

Output Output

0

Output a. Pulse Shorening

0

Control Signal Check Valve

b. Pulse Stretching

Fig. 8-7 : Sequence Chart for a Pulse Shaper (Monostable, One-Shot)

Fig. 8-2 : Pneumatic "On-Delay" Timer
(Output)' Output
START

Y1
y1

Control Signal

Volume

+

Y2
y2 Output

y1

Fig. 8-3 : Pneumatic "Off-Delay" Timer Fig. 8-8 : Relay Pulse Shaper
(Output)' Control Signal Output Output

Volume

+

Control Signal

Volume

+

8-1

Fig. 8-4 : Pneumatic "On-Delay Off-Delay" Timer Fig. 8-9 : Pneumatic Pulse Shaper

8-2
S (SET)
2 1 3

Q

S R

Q Q'

S (Set)
Clock

1 3 2 3 2 1

Q

2 1

2 1 3 3 1

R (RESET)

3

Q'

R (Reset)

2

Q'

a. Logic Circuit

b. Short Symbol

c. Clocked SR Flip-Flop

Fig. 8-10 : Basic Set-Reset Flip-Flop (SR)

1 3 1 3 2

1

S R

Q Q'

Q Q'

2

S R

Q Q'

3 2

S R

Q Q'

Q Q'

T
1 3 2

T
1 3 2 1 3 2

a. Basic Logic Circuit

b. Master-Slave Type

Fig. 8-11 : Toggle Flip-Flop (T)
Q3 FF3 Q2 FF2 Q1 FF1 Q0 FF0 Q3 FF3 Q2 FF2 Q1 FF1 Q0 FF0

Q T Q'

Q T Q'

Q T Q'

Q T Q'
CLOCK

Q T Q'

Q T Q'

Q T Q'

Q T Q'
CLOCK

a. "UP" Counter

c. "DOWN" Counter
UP
1 3 2

Q0 T Q1 Q2 Q3
3

1 2 1 3 2

Q T Q'
DOWN RESET

Q3 Q2 Q1 Q0

: : : :

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

0 0 0 0

0 0 0 1

... ... ... ...

b. "UP" Counter Timing Waveforms

d. "UP/DOWN" Selector

Fig. 8-12 : T Flip-Flop Implementation - Counters

D D CP
1 3 2

1 3 2

1

S R

Q Q'

3 2

S R

Q Q'

Q Q'

S R

Q Q'

Q Q'

CP

1 3 2

1 3 2

1 3 2

a. Delay Flip-Flop (D) b. Master-Slave Type

IN

D CP

Q Q'

D CP

Q Q'

D CP

Q Q'

D CP

Q Q'

D CP

Q Q'

D CP

Q Q'

D CP

Q Q'

OUT

CP

c. Shift Registerr Based on D Flip-Flops

Fig. 8-13 : D Flip-Flop Implementation - Shift Register

8-3
Input x Shift

1

0

0

1

1

0

1

1

0

1

Fig. 8-14 : 10 Stages Shift Register

X1 X2 Inputs X3 X4 Shift

0 1 1 1

0 1 0 0

1 0 0 1

0 1 0 1

1 0 0 0

1 0 1 1

0 1 1 0

1 0 0 0

0 1 1 1

0 1 0 0

Fig. 8-15 : Shift Register With Four Parallel Tracks

Output Voltage

HI (3.4V)

LO (0.3V) Input Voltage 0.95V 1.8V

Fig. 8-16 : Schmitt-Trigger Response

Fig. 8-17 : Schmitt-Trigger Response to Fuzzy Waveform

Weight 8 Number 0 1 2 3 4 5 6 7 8 9 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 1 1 1 1 0 0 2 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 P 0 1 1 0 1 0 0 1 1 0 P = Parity Bit

Fig. 8-18 : Truth Table for an Error Checking BCD Code
(Even Parity Check)

Weight 7 Number 0 1 2 3 4 5 6 7 8 9 1 0 0 0 0 0 0 1 1 1 4 1 0 0 0 1 1 1 0 0 0 2 0 0 1 1 0 0 1 0 0 1 1 0 1 0 1 0 1 0 0 1 0 P 0 1 1 0 1 0 0 1 0 0 P = Parity Bit

8-4

Fig. 8-19 : Truth Table for 2-out-of-5 Code
(Even Parity Check)

C

B

B

B B A C D

A C

A C

A

(a)

(b)

(c)

(d)

Fig. 8-20 : Use of Karnaugh Map to Obtain Cyclic Codes

1 1 0 0

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1

1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

1 1 1 0 0 0

1 0 0 0 0 1

0 0 1 1 0 0

Fig. 8-21 : Reflected Cyclic Code for 6 Numbers

Fig. 8-22 : Construction of "Reflected" Cyckic Code

A 000 B 001

H 111 G 110 100 110 101 111 E G F H WRONG OK OK WRONG

8-5

C 010

F 101 011 D 100 E

c. Sections Border Problem

b. Encoder Photo-Cells

a. Encoder Plate

Fig. 8-23 : Binary 8-Sections Encoder
Absolute Coordinates

A 011 B 010 C 000

H 111 G 110 110 G 100 F F 100 OK OK

c. Border Problem Solved

001 D b. Encoder Photo-Cells

101 E

a. Encoder Plate

Fig. 8-24 : Typical 8-Sections Encoder
Absolute Coordinates

b. Encoder Photo-Cells

a. Encoder Plate

c. Incremental Encoder Output No Sense for Direction

Fig. 8-25 :Single Output Incremental Encoder

A

B

8-6
1 8 2

a. Disk Sensors Arrangement Change Direction 360
0

7

3

90

0

6

A
5

4

B
"UP" direction (A leads B) "DOWN" direction (B leads A)

d. Merge Diagram

AB
00 01 11 10

b. Encoder Code Waveforms for Both Directions

Fig. 8-26 : Two Output Incremental Encoder

CR1 CR2 CR3

1 6 6 1

5 5 4 4

8 3 3 8

2 2 7 7

A B

CONTROL SYSTEM

D

CR4

a. Control System Block Diagram

e. Merged Flow-table & State Assignment

AB
00 01 11 10

01/1
5

00/1
6

10/1
7

11/1
8

CR1 CR2 CR3

O 1

1

(1) (0) O 1 (1)

(1) (0)

(1) (0) O (0) O 1

00/0
1

10/0
2

11/0
3

01/0
4

CR4

D f. Output Table b. Primitive Flow-diagram
S1 = CR4.A.B' + CR2.A'B' AB
00 01 11 10 D

R1 = CR2.A.B' + CR4.A.B R2 = CR1.A'B + CR3.AB R3 = CR2.A'.B' + CR4.A'B R4 = CR1.A'.B' + CR3.AB'

S2 = CR1.AB' + CR3.A.'B' S3 = CR2.A.B + CR4.A.B' S4 = CR1.A.B + CR3.A'B

1 6 1 1 6 6 -

5 4 4 5 5 4

3 3 8 8 3

2 2 7 2 7 7

O O O O 1 1 1 1

D = CR1.B + CR2.A' + CR3.B' + CR4.A

g. Exitation and Output Functions Initially, A=B=0 and all Flip-flops are in reset state (CRi=0). At that state, Flip-flop 1 must be set, with no confilict later, that is to say, while CR1 and CR2 are not set.
S1 = A'B'.CR2'.CR3'

h. Corrected System Initialization

8

Fig. 8-27 : Motor Direction Detection System Design (Copy of 6-4)

c. Primitive Flow-table

Tachometer Servo Motor or Servo Valve

Program

Digital Comparator

Error

D/A Converter Binary Signal

Amplifier

Load

Encoder

Position

Fig. 8-28 : Simplified Block Diagram of a Closed Loop NC System (One Control Axis)

Program

Control Logic

Pulses Direction

Step Motor

Load

Fig. 8-29 : Block Diagram of an Open-Loop NC System (One Control Axis)

8-7
X1 X0 Y1 Y0 Z2 Z1 Z0

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 1

0 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1

0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0

Z2 = X1.Y1 + X1.X0.Y0 + X0.Y1.Y0 Z1 = X1'X0.Y1'Y0 + X1.X0.Y1.Y0 + X1.Y1'Y0' + + X1.X0'Y1' + X1'Y1.Y0' + X1'X0'Y1 Z0 = X0.Y0' + X0'Y0

b. Sum Output Minimized Functions

* * * *

3-Bit Numbers Adder requires 6-Variable Map 4-Bit Numbers Adder requires 8-Variable Map 32-Bit Numbers Adder requires 64-Variable Map Karnaugh Map Metode Is Limited to 4-Bit Numbers

c. Karnaugh Map Methose Limitation

a. Truth Table

Fig. 8-30 : Adder for 2-Bit Numbers

Xn Yn

Xn-1 Yn-1

Xi

Yi

X1 Y1

X0 Y0

Cn+1

Cn

FA

FA

Cn-1

Ci+1

FA

Ci

C2

C1

FA

FA

C0=0

Sn

Sn-1

Si

S1

S0

Fig. 8-31 : Iterative Adder Block Diagram

00/0 01/1 10/1 C=0

Xi,Yi/Si

01/0 10/0 11/1 C=1 Ci Xi Yi
4 1 3 2 5 6

00/1 11/0

Si

a. General Cell (FA) Flow Chart
1 3 2

4 6 5 5 4 6

Ci+1

Ci Xi Yi Ci+1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1

Si 0 1 1 0 1 0 0 1

1 3 2

c. FA Logic Circuit

Si = (XI) xor (Yi) xor (Ci) Ci+1 = Xi.Yi+ Ci (Xi + Yi)

b. FA Truth Table

Fig. 8-32 : Iterative Binary Adder Design

DESIGN OF A PARITY CHECKER Checker detects if number of "1" in a binary vector, is odd or even. It produces a single output line P, where : P=1 denotes odd parity P=0 denotes even parity

DESIGN OF 2-OUT-OF-5 CHECKER A specific code consists of vectors that contain exactly two "1"'s, and all other bits are "0". (11000000, 00101000, 010000001 etc). Design a circuit that checks vectors and announces Z=1 when detected vector been found valid.

8-8

a. Requirements Definition

a. Requirements Definition

X (Vector)

P

X (Vector)

Z

b. Simplified Block Diagram
Xn
Pn+1 Pn Pi-1

b. Simplified Block Diagram
0

Xi
Pi P1

0
P0

0 N=0 1 N=1 1

0 N=2 1

0 N>2

1

c. Iterative Block Diagram

A

B

C

D

c. General Cell Flow Chart
0 1 P=0 1 P=1
"1" An+1 "0" Bn+1 "0" Cn+1 "0" Dn+1 An Bn Cn Dn Ai-1 Bi-1 Ci-1 Di-1 Ai Bi Ci Di A1 B1 C1 D1 A0 B0 C0 D0

0
Xn Xi X0

d. General Cell Flow Chart
Pi-1 Xi Pi

*

0 0 1 1

0 1 0 1

0 1 1 0
Ai-1

d. Iteratice Block Diagram
Bi-1 Ci-1 Di-1 Xi Ai Bi Ci Di

1 1

e. General Cell Truth Table

Pi = Pi-1.Xi' + Pi-1'.Xi = Pi-1 xor X f. General Cell Function
Xi

-

- - - - 1 - 1 - - 1 - 1 - - 1 - - 1
Ai Bi Ci Di

0 1 0 1 0 1 0 1

1 0 0 0 0 0 0 0

0 1 1 0 0 0 0 0

0 0 0 1 1 0 0 0

0 0 0 0 0 1 1 1

e. General Cell Truth Table
4 6

Pi-1

5

Pi

g. General Cell Logic Circuit

= Ai-1.Xi' = Ai-1.Xi + Bi-1.Xi' =Bi-1.Xi + Ci-1.Xi' =Ci-1.Xi +Di-1

f. General Cell Function

Fig. 8-33: Iterative Parity Checker

Fig. 8-34 : Iterative 2-Out-of-n Checker

8-9
DESIGN OF A BINARY COMPARATOR Comparator compares 2 binary numbers X,Y (of equal length), and produces 3 output signals: Line A : A=1 if X>Y Line B : B=1 if X=Y Line C : C=1 if X<Y Design refers to positive numbers of n+1 bits, where n may vary according to case.

a. Requirements Definition

X (Vector) Y (Vector)

A B C

(X>Y) (X=Y) (X<Y)

b. Simplified Block Diagram

Xn Yn
An+1 Bn+1 Cn+1 An Bn Cn

Xn-1 Yn-1
An-2 Bn-2 Cn-2 Ai-1 Bi-1 Ci-1

Xi

Yi
Ai Bi Ci A1 B1 C1

X0 Y0
A0 B0 C0

0 1 0

c. Iterative Block Diagram

AB

00 A=B 01

11

A<B

10 A>B

Ai = Ai-1 + Bi-1.Xi.Yi' Bi = Bi-1(Xi.Yi+Xi'.Yi') = Bi-1(Xi xor Yi)' Ci = Ci-1 + Bi-1.Xi.'Yi f. General Cell Functions

d. General Cell Flow Chart
Xi
Ai-1 Bi-1 Ci-1 Xi Yi Ai Bi Ci

Yi

1 0 0 0 0 0

0 0 1 1 1 1

0 1 0 0 0 0

0 0 1 1

0 1 0 1

1 0 0 0 1 0

0 0 1 0 0 1

0 1 0 1 0 0
Ci-1 Ci Ai-1
4 6 5

Ai Bi

Bi-1

e. General Cell Truth Table

g. General Cell Logic Circuit

Fig. 8-35 : Iterative Binary Numbers Comparator

8-10

Decimal Value

Natural Binary Code

Reflected Cyclic Code

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0

0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

Fig. 8-36 : Comparison Between Natural-Binary and Reflected-Cyclic Code

N(m)

C(m) C(m) C(m-1)

N(m) N(m-1) N(m-2) N(m-3)

N(m-1) C(m-2) N(m-2) C(m-3) N(m-3)

C(m-1) C(m-2) C(m-3)

Fig. 8-37 : Iterative Circuit for Translating Natural-Binary into Reflected-Cyclic Code

Fig. 8-38 : Iterative Circuit for Translating Reflected-Cyclic into Natural-Binary Code

N(i) N(i-1) C(i-1) 0 0 1 1 0 1 0 1 0 1 1 0

C(i-1)= N(i) N(i-1)= N(i)

N(i-1) C(i-1)

Fig. 8-39 : Truth Table for Translating Natural-Binary into Reflected-Cyclic Code

CHAPTER 9
SEMI-FLEXIBLE AUTOMATION HARDWARE PROGRAMMERS
Drum Programmers Programmable-Counter 1/n Programmable-Counter 2/n

DRUM PROGRAMMER (STEPPING SWITCHED)

MATRIX BOARDS
x2 1 2 3 In Out 6 7 8 9 10 A B C D 5 1 2 3 4

Y
+ -

9-2

y1

y2
+

X
-

x1

Y+

Y-

X+

Cylinders D,E,F Types

Cylinders A,B,C Types

4

START , A+, B+, B-, C+, C-, D+, A-,

D, F-, F+, F-, F+, EF+ FE+
Switches V VI VII VIII Connected to D+ D- E+ E- F+ IV

E b. Matrix Board

a. Patch Board

Fig. 9-3 : Boards
IX FX Motor

Step 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15-24

Desired Event / A+ B+ BC+ CD+ AE+ F+ FF+ FF+ DEFGo Home

I Signal to Advance A+ Start a2 X b2 X b1 X c2 X c1 X d2 X a1 e2 f2 f1 f2 f1 f2 d1 e1 f1 /

II B+

III C+

X

1
X X X X X X X X X X X X

2

3

4 A B C D

1

2

3

4

A B C D a. With Sneak Path

b. Without Sneak Path

Fig. 9-4 : Matrix Board

Fig. 9-2 : Drum Programmer Solution

PROGRAMMABLE COUNTERS (SEQUENCERS)
X1 X2 X3 X4 X5 X6 Xn START X1 X2 X3 X4 Xn-1

Xn

&
1 2 3 4 5 6 --n
Connected to Module 1

1

2

3

4

5

---

n

n+1

Connected to Module 1

Z1

Z2

Z3

Z4

Z5

Z6

Zn

Not Used Z1 Z2 Z3 Z4 Z5 Zn

Fig. 9-5 : Schematic Representation of Programmable Counter
b1 c1 Start a2 b2 c2 a1 a2 a1 Start

Fig. 9-6 : Programmable Counter With Single-Cycle START mode
b1 c1 a2 b2 c2 a1 a2 a1

&
1 2 3 4 5 6 7 8 1 2 3 4 5

&
6 7 8

Not Used

Not Used

Not Used

>1
A+ B+ C+ BC-

>1
>1 >1

AA+ B+

>1
C+

START , A+, B+, C+ , A- ,

BC, A+ , A-

Fig. 9-7 : Programmable Counter Circuit for Sequence With Parallel and Repeated Events (Actuating Valves Without Return Springs)

Fig. 9-8 : Programmable Counter Circuit for Sequence of Fig 9-7, While Actuating Valves Have Return Springs

Xi Si
-

X1

X2

X3

X4

9-3
-

Si+1
+

Si
+ + + + + + + + +

Ri Zi Z1 Z2 Z3 Z4

a. Actual General Cell
Xi X1

b. Actual Counter Configuration
X2 X3 X4

&
SET

From Zi+1
RESET

&
SET RESET

&
SET RESET

&
SET RESET

&
SET RESET

y

y'

y

y'

y

y'

y

y'

y

y'

From Zi-1 To Zi-1 RESET

To Zi+1 SET y1 Zi Z1 y2 Z2 y3 Z3 y4 Z4
step y1 y2 y3 y4 y5

c. Equivalent General Cell

d. Equivalent Counter Configuration

Fig. 9-9 : Programmer Based on 1/n Code

1 2 3 4 5

1 0 0 0 0

0 1 0 0 0

0 0 1 0 0

0 0 0 1 0

0 0 0 0 1

e. Counter cycle states

Xi

X1

X2

X3

X4

Si
-

Si+1
-

+

+

+

+

Ri

Zi

Z1

Z2

Z3

+

Z4

a. actual General Cell
From Zi+1
SET RESET

b. Actual Counter Configuration

From Zi-1

SET

RESET

SET

RESET

SET

RESET

SET

RESET

step y y' y y' y y' y y' y y'

y1 y2 y3 y4 y5

Xi

X1 y1

X2 y2

X3 y3

X4 y4

1 2 3 4 5

1 0 0 0 1

1 1 0 0 0

0 1 1 0 0

0 0 1 1 0

0 0 0 1 1

&
To Zi+1 SET To Zi-1 RESET

&

&

&

&

e. Counter cycle states

Zi

Z1

Z2

Z3

Z4

c. Equivalent General Cell

d. Equivalent Counter Configuration

Fig. 9-10 : Programmer Based on 2/n Code

B+

START , A+ , A- , B+ , C+ , B- . Ca. Sequence

START ,

A+ , A-

, C+ , D+ , D- , C- , Ba. Sequence

a1

b2

a1

a2

start
Start a2 a1 b2 c2 b1 c1

a2

a1 b2

c2

d2

d1

c1

b1
A+

&
B+

(a)
a1

(b)
b2 c2
B+

1 1 2 3 4 5 6 7 A+

2 B+

3 C+
(B+)

4 D+
(B+)

5
(D-) (B+) (C+)

6
(B+)

7
(B-)

8
Start b2

&

A-, C+

,B-

>1

>1

OR OR

A+

B+

C+

B+

b. 1/n Prog.Counter Circuit

A+

D+

C+

B+

>1
(c)
B+ C+

b. 1/n Prog.rammable Counter Circuit

start
Start a2 a1 b2 c2 b1 c1

a2

a1 b2

c2

d2

d1

c1

b1

(d)
- - - - A- , B+ , C+ , C- , B- - - - a1 b2 c2 c1

&
1 A+
FLIP-FLOP

1

2

3

4

5

6

7

2 B+
(A-)

3 C+
(B+)

4 D+

5
(D-) (B+) (C+)
RESET SET FLIP-FLOP

6
(B+) (A-)

7
(B-)

8

S

Q

R

>1

>1
RESET SET FLIP-FLOP RESET SET FLIP-FLOP

(B+)

(B+) (C-)

(B-)

A+

C+ B+ c. 2/n Programmable Counter Circuit

B+

C+

(Both B and C require flip-flops)

A+

B+

D+

C+

(e)

c. 2/n Programmable Counter Circuit

9-4

Fig. 9-11 : Programmable Counter Example 1
(With Return Springs)

Fig. 9-12 : Programmable Counter Example 2
(With Return Springs)

Fig. 9-13 : 2/n - Different Stability Cases
(With Return Springs)

B1

B2

B3

Bm

9-5

A1

A2

An

1

2

2

---

m
D1 D2 Dp

1

2

---

3

ZB1

ZB2 C2

ZB2 Ck

ZBm

&
ZA1 ZA2 ZAn

1

2

---

p

ZD1

ZD2

ZDp

1

2

---

k

ZC1

ZC2

ZCk

Fig. 9-14 : 1/n Programmer fot Two Simultaneous Parallel Paths
B1 P A1 A2 An B2 B3 Bm

&

1

2

2

---

m
D1 D2 Dp

1

2

---

3

ZB1

ZB2 C2

ZB2 Ck

ZBm

>1
ZAn

1

2

---

p

ZA1

ZA2

ZD1

ZD2

ZDp

&
P'

1

2

---

k
Path B for P=1 Path C for P=0

ZC1

ZC2

ZCk

Fig. 9-15 : 1/n Programmer for Two Alternative Parallel Paths (Parallel)

A1

A2

An

B1

B2

Bm

P'

C1

C2

Ck

& 1 2 --3 & 1 2 --m >1 1 2 --k

ZA1

ZA2

ZAn

P

ZB1

ZB2

ABm

Skip for P=0

ZC1

ZC2

ACk

Fig. 9-16 : 1/n Programmer for Program With Skip Steps Option

A1

A2

An

B1

B2

Bm

C1 P

C2

Ck

1

2

---

3

>1

1

2

---

m

&

1

2

---

k

ZA1

ZA2

ZAn

&

ZB1

ZB2

ABm

ZC1 Repeat for P=0

ZC2

ACk

P'

Fig. 9-17 : 1/n Programmer for Program With Repeated Steps Option

Is design YES flexibility requested? NO

YES Programmable counter

Is design simplicity more important than element econpmy?

NO

YES

Are relays used?

NO

Relay cascade method

YES

Are valves used?

NO

YES

Are valves used?

NO

YES

Are there repeated events?

NO

YES

More than 4 or 5 cylinders?

NO

Huffman method

YES

More than 4 or 5 cylinders?

NO

YES

Are there repeated events?

NO

Programmable counter

Flow-Table method

Pneumatic cascade method

Programmable counter

Operationtable method

Pneumatic cascade method

Flow-Table or Huffman method

Fig. 9-18 : Flow Chart for Selecting Sequence-Control System Design Method

9-6

CHAPTER 10
PROGRAMMABLE LOGIC CONTROLLER
Introduction PLC Configuration PLC Programming Implementation in Ladder Diagram Implementation in Huffman Metode

PLC CONSTRUCTION

RAM ROM PROM EPROM EEPPOM

Programming Unit

Central Processing Unit (CPU) Memory

Input Modules Output Modules PLC

Controlled System

Random-Access Memory Read-Only Memory Programmable Read-Only Memory Erasable Programmable Read-Only Memory Electrically Erasable Programmable Read-Only Memory

Fig. 10-6 : Type of Electronic Memories
Input Modules 000 Output Modules 000 001 PLC Program Coding 002 003 004 PL1 Rdy Set 1 Open PL2 #1 Set 2 Open PL3 #2

Fig. 10-1 : Block Diagram of Programmable Controller (PLC)
Memory Size (Words) I/O Capacity (Modules)

Start PB1

Reset PB2

001 Micro PLC Small PLC Medium PLC Large PLC Up to 64 Up to 128 Up to 512 > 512
Temp TS3 Level FS4 Level FS5

002 003 004

Fig. 10-2 : PLC Classification According to Size
Limit Switches Proximity Switches Photoelectric Switches Sensor Switches (Level, Pressure, Temperature etc) Push-Button Switches Selector Switches Relay Contacts

.........

n

Fig. 10-7 : I/O Connection Diagram

Fig. 10-3 : Discrete Input Devices to PLC
Contact Relay Coils Valve Solenoids Pneumatic or Hydraulic Cylinders and Motors Lights Audible Alarms (Bells,Buzzers,Sirens) Fans Heaters Motor Starters

Controlled System

Controlled System ..........

..........

I/O Modules (Field Mounted with Multiplexer)

.........
m

.......... I/O Modules (PLC Mounted) PLC PLC

Fig. 10-4 : Discrete Output Devices Actuated by PLC

12, 24, 48, 120, 230 Volt AC 12, 24, 48, 120, 230 Volt DC 5V DC (TTL Level) Conract Relay Output

a. PLC-Mounted I/O

b. Remote-Mounted I/O

10-1

Fig. 10-8 : Different I/O Connection Location

Fig. 10-5 : Standard Discrete I/O Interface Modules

Word Adress (Octal)
0000 (8 Words) 0007 0010 (8 Words) 0017 0020 (8 Words) 0027 0030 (256 Words) 0427 0430 (3816 Words) 7777

17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

10-2

Input Table - 128 Bits

Output Table - 128 Bits

Internals - 128 Bits

Registers

User Memory

Fig. 10-9 : Typical PLC Memory Map
Programming the PLC 1. Ladder Diagramms or Graphic Programing - entered either by drawing the Ladder diagram on screen, or by Boolean Mnemonics. 2. Boolean Mnemonics or Logic Instruction Set. 3. GRAFCET or Function Chart Used by : Telemechanique, France (GRAFCET) Allen Bradley, USA (SFC = Sequential Function Chart) Siemens, Germany (Graph 5) 4. Enhansed Ladder Diagrams (Ladder Diagrams with "Instruction Blocks"). 5. Computer Language such as BASIC, with additional commands.

Fig. 10-10 : Programming Languages

10036 12 10124 03

10047 16 10107 86 10113 86 04 86 10113 82 08114 10

O0033

( (

)
O0034

14

)

02

O0034

(
TIMER ON 0.1 SECOND PR = 3200 AC = 520 ADDR T 0045 TP0045 TA0045

)
T0045

17

10118 01 10112 83 10054 16

(EN) 17
T0045

(TC) 15
O0075

(

)

15

Fig. 10-11 : Ladder Diagram Section Appearing On Screen
(Allen Bradley Co. PLC)

INPUT DEVICES

INPUT MODULES

CPU

OUTPUT MODULES

OUTPUT DEVICES

10-3

SENSOR 1

HIGH/LOW VALUES HIGH/LOW VALUES

INPUT MODULE 1 INPUT MODULE 2

LOGIC LEVEL LOGIC LEVEL

X1 X2

Y1

LOGIC LEVEL LOGIC LEVEL

OUTPUT MODULE 1 OUTPUT MODULE 2

HIGH/LOW VALUES HIGH/LOW VALUES

LOAD 1 LOAD 2

SENSOR 2

PLC
CR1 CRk

Y2

SENSOR n

HIGH/LOW VALUES

INPUT MODULE N

LOGIC LEVEL

Xn
(LOGIC LEVEL)

Ym

LOGIC LEVEL

OUTPUT MODULE M

HIGH/LOW VALUES

LOAD m

Fig. 10-12 : PLC Configuration

PLC SYSTEM
START
+

CYLINDER SYSTEM a1
-

Start

INPUT MODULE 1

X0

a2

CPU
a2 a1
INPUT MODULE 2 INPUT MODULE 3

Y1

X1 X2 Y2

OUTPUT MODULE 1

A+
+ -

OUTPUT MODULE 2

A-

Fig. 10-13 : Typical PLC Control System

PROCESS 5

PROCESS 6

PLC 6
PROCESS 4

PLC 6 PLC 7
PROCESS 7

PLC 4

PROCESS 3

PLC 3

PLC 8
HOST PROCESSOR

PROCESS 8

PROCESS 2

PLC 2

PLC 9

PROCESS 9

PLC 1

PLC n

PROCESS 1

PROCESS n

Fig. 10-14: PLC Network (Macro)

10-4
D+ START , A+ , C+ , C- , A- , B+ , A+ , C+ , B- , D- , CAStart

X0 X1 X2 X3 X4 X5 X6 X7 X8 Y1
Y2 Y3 A+

a. Process sequence

a1 a2

AB+ BC+ CD+ D-

INPUT TABLE

OUTPUT TABLE (NO RETURN SPRING)

OUTPUT TABLE (WITH RETURN SPRING) Y1 Y2 Y3 Y4 A+ B+ C+ D+

b1

b2 c1 c2 d1 d2

Y4 Y5 Y6 Y7 Y8

X0 X1 X2 X3 X4 X5 X6 X7 X8

START

Y1
Y2 Y3

A+

a1 a2
b1

b2 c1 c2 d1 d2

Y4 Y5 Y6 Y7 Y8

AB+ BC+ CD+ D-

PLC
(with return springs) d. Output Table (no return springs) e. PLC and I/O System

(no return springs) c. Output Table

b. Input Table

Fig. 10-15 PLC I-O Variables Assignment

(Temperature Switch)
START STOP

T.S. CR1

X17 C R1

X18

X19
CR1

C R1

MOTOR
C R1
(Motor current must be isolated from sensors)

C R1
MOTOR

Y13

a. Relay Ladder Diagram for Motor Control

e. PLC "Internal" Ladder Diagram

Start Stop T.S.

INPUT MODULE

OUTPUTM ODULE

System

Motor

Start Stop
T.S. MOTOR

X17 X18 X19 Y13

X17
Y13

X18

X19
Y13

b. Block Diagram

(No isolation problem since all I/O are isolated by modules)

c. I/O Assignment Table

f. Simplified Ladder Diagram

Start Stop
T.S.

Input Module Input Module Input Module

X17

STORE
Y1

X17 NOT NOT Y13 X18 X19 Y13

X18

Output Module

Motor

MOTOR

OR AND AND OUT

PLC
X19

d. PLC Ladder Diagram

g. PLC Program

Fig. 10-16 PLC Motor Control System

Stop

000
Reverse

000

001

002

032

003

030

M1 030

f
Forward PL1

x3

cr1 cr2

cr3 CR2 X5 Y12

030 001 000 001 002 030 002 000 002 001 030 004 032 032 031 031

...

cr2 M2

x4 Y13 cr6

Forward

...

r
Fig. 10-20 : Ladder Diagram of Fig. 10-18 in PLC Format

cr1 003 cr2 004 003 000 002

032 001 032 033 Reverse PL2 033 OL1 Fault PL2 034 OL2 Fault PL2 035

034

004

035

Fig. 10-17 : Forward/Reverse Circuit (Using Two Motors M1 na M2, and Overload Switches OL1 and OL)

0 1 2 3 4 5 6 7 8 9 10

STORE NOT AND OR AND NOT OUT AND OUT STORE AND OR OUT

X1 CR1 CR2 CR3 CR2 X5 Y12 CR2 X4 CR6 Y13

Fig. 10-21 : Program for Fig. 10-20
a2 cr1 cr2 cr3 CR2 d2 b2 cr6 B+ C+ X2 X4 cr10 Y5 cr11

Fig. 10-22 : Use of LIFO Memory Stack Fig. 10-18 : Ladder Diagram Segment Illustrating Repeated Actuation of Solenoid C+
0 1 2 3 4 5 STORE NOT AND STORE NOT AND OR OUT X2 CR10 X4 CR11 STORE Y5

Input Module X3 X4 X5

Output Module

Y12 Y13

Connected to a2 b2 d2 B+ C+

10-5

Fig. 10-23 : Program for Fig. 10-22

Fig. 10-19 : I/O Assignment Table for Fig. 10-18

START

cr3' cr1

cr4'

cr2'
CR1

A+ START B+ I II III C+ ACC+

BCIV STORE AND NOT AND NOT OR AND NOT OUT
Y1

cr1 cr2

c2

cr3'
CR2

a. Process sequence Groups partitining
X0 cr3' y1 cr3' y4' y2'

X0 CR3 Y4 Y1 Y2 Y1 X6 Y2 CR3 Y2 X5 CR3 Y4 CR3 X6 Y4 X3 X5 STORE Y4 Y1 Y3 X2 X4 CR3 Y5 Y2 X1 Y4 Y6

cr2 cr3

c1

cr4'
CR3

START a1
c2 b1
CR4

x0 x1 x2 x3 x4 x5 x6 Y1 Y2 Y3 Y4 Y5 Y1 = CR1 Y6 Y2 = CR2 Y4 = CR4
y2 y4 y1 cr3 y2 y1

X6 y2

cr3 cr4

Y2

AND OR AND NOT OUT AND OR AND NOT OUT AND OR STORE NOT OR NOT AND OUT STORE OUT AND AND OR OUT STORE AND OR OUT

c1

a2 b1

X5 cr3

y4'

cr1

A+

b2 c1

CR3

cr2

A-

c2 A+ AB+

X6 y4

X3'

Y4
X5'

cr1

B+

cr4

B-

Y3
y1 cr3 X2 x4

cr1 cr3

a2

b2

C+

BC+

Y5

cr2 cr4

a1

C-

C-

X1

Y6

b. Relays Cascade Circuit

c. PLC Variables Assignment

d. Optimize CR Relays

f. PLC Program e. PLC Cascade Circuit

10-6

Fig. 10-24 : PLC Cascade System Design

X1 X2

CR5 CR6

CR10 CR2

CR11 CR3

X1 CR1 X2
CTR (25)

F1 CR1 F2

CTR (n)

CR1

a. Ladder Diagram
STORE NOT AND STORE NOT AND NOT OR STORE NOT AND NOT STORE AND NOT OR AND OUT X1 CR5 X2 CR6 STORE CR10 CR11 CR2 CR3 STORE STORE CR1

X1= O-->1 One count X2=1 Counter Enabled

X2=0 Counter is Reset

F1= O-->1 One count F2=1 Counter Enabled

F2=0 Counter is Reset

a. Specific Case

b. General Case

Fig. 10-29 : Counter to Count 25 (Texas Instruments PLC)
STORE STORE CTR1 25 OUT X1 X2

empty

CR1

Fig. 10-30 : Program for Fig. 10-29 (a)
LOAD NOT OUT 5 LOAD OUT 5 LOAD AND OUT TMR2 TMR1 TMR1 TMR2 X1 TMR1
Y1

b. PLC Programming

Fig. 10-25 : Multiple Use of LIFO Stack
TMR2 X1 X3 STORE STORE STORE AND OR AND OUT X2 X4 X1 X2 X3 X4 STORE
STORE

TMR1 TMR1 TMR2

(0.5 Sec) (0.5 Sec) (Light Valve)

CR1

X3

X4 X2

X1

CR1 TMR1 X3 X4

Y1

STORE AND OR AND OUT

X3 X4 X2 X1 CR1

a. Ladder Duagram

b. Programmable of (a)

Fig. 10-31 : Making Light Flash While X=1 (General Electric PLC)

CR1

a. Original Circuit

b. Programmable Simplified Circuit

Fig. 10-26 : Rearrangement of Ladder Diagram for Simpler Programming
X1 X2 (Up/Down) (Event) (Reset)
CTRi (120)

F1 F2 F3 Y2

(Up/Down) (Event) (Reset)
CTRi (n)

TIMERS AND COUNTERS
X1 X2
TMR (200)

X3

LOAD NOT LOAD NOT LOAD NOT OUT 120 LOAD OUT Y2

X1 X2 X3 CTR3 CTR3 Y1

F1 CR1 F2

CTR3
TMR (n)

CTRi

CR1

c. Programmable of (a) X1 determines UP or DOWN mode X2= O-->1 One count X3=1 Counter Enabled X3=0 Counter is Reset F1 determines UP or DOWN mode F2= O-->1 One count F3=1 Counter Enabled F3=0 Counter is Reset

X1=1 Timer Run X2=1 Timer Enabled

X1=0 Timer Stops X2=0 Timer is Reset

F1=1 Timer Run F2=1 Timer Enabled

F1=0 Timer Stops F2=0 Timer is Reset

a. Specific Case

b. General Case

a. Specific Case

Fig. 10-27 : Timer Set for 20 Seconds (Texas Instruments PLC)
STORE STORE TMR1 200 OUT X1 X2

b. General Case

10-7

Fig. 10-32 : UP/DOWN Counter (General Electric PLC)

empty

CR1

Fig. 10-28 : Program for Fig. 10-27 (a)

X3 X5 X3 X5

TMR
(5)
(0.3 Sec)

10-8
CR1

X3

X3

CR1

Y1
y1

Fig. 10-33 : Two-Hands Circuit Using PLC

D

START,(D+,D-) repeat 6 times,D+,10 Sec DELAY,Dd1 d2

a. Required Cycle

+

D-

D+

b. Cylinder Type

Fig. 10-34 : Process Definition

Input Modules X0 X1 X12

Output Modules

Y0 Y1

Connected to d1 d2 START DD+

CR5 CR7

X1 (d2)

-

Y0

a. Assignment Table

STORE AND NOT OUT
Y1

X0 CR5 Y1 CR5 CR7 X1 Y0 X0 X12

X0 (d1)

CR5

X1 (d2)

CR5 CR7

Y0

STORE NOT OR AND OUT STORE STORE NOT CTR1 6 (NOT USED) OUT AND OUT STORE TMR1 100 (NOT USED) OUT

X0 (d1)
COUNTER 1

CR3

X12 (Start)

(6)

X1 (d2) CR6 CR6

CR3

CR6

CR3 X1 CR6 CR6

TIMER 1

(100)
(10 Sec)

CR7

b. Ladder Diagram

Fig. 10-35 : Design PLC Program for Sequence of Fig.10-34

CR7

c. PLC Programm

10-9
X1

TMR1
COUNT OUT

(120)
TMR1

LOAD OUT 120

X1 TMR1

An elevator exists in a 5-floor building. Elevator runs automatically (without human control), from 1st floor to 5th floor, and vica versa, while stopping for 10 seconds in each floor. Each floor is equipped by a unique contact, that is closed when the elevator reaches that floor. These contacts are implemented as input sensroes for PLC control system. a. System Description

a. General-Electric PLC Timer

1st COUNTER (GE) X1 X2 X3 CTR1 LOAD LOAD LOAD 120 OUT CTR1 X1 X2 X3 5th 4th
UP/DOWN

INPUT MODULE INPUT MODULE INPUT MODULE INPUT MODULE INPUT MODULE

X1

2nd
OUT

PLC
X2 Y1

CTR1
EVENT

OUTPUT MODULE OUTPUT MODULE

UP
MOTOR

(120)
RESET

3rd

X3

Y2

MOTOR

DOWN X4

X5

b. General-Electric PLC Counter b. PLC System Configuration

X1

COUNT

TMR1 (120)

OUT

CR1
X1 X2

X2 CR1

RESET

STORE STORE TMR1 120 (empty) OUT

X1 X2

X3

CR0

X4 X5

CR1

CR0

COUNT

TMR1

c. Texas-Instruments PLC Timer

OUT

CR1

CR0

(100)
RESET

X1 X5 X1
EVENT

CR2
OUT

CR2

CTR1 (120)

CR1

CR1 CR2 CR0 CR1 Y1

X2 CR1

RESET

STORE STORE CTR1 120 (empty) OUT

X1 X2

CR2 CR0

Y0

Notes : CR2 control elevator direction Y1 - Up direction Y2 - Down direction

CR1

d. Texas-Instruments PLC Counter

c. PLC Ladder Diagram

Fig. 10-36 : PLC Timers and Counters

Fig. 37 : "Saturday" Elevator

10-10
X6 MCR(3) STORE MCR ... ... X6 3

A. Ladder Diagram

b. Programming Lines

If X6=0, then the next (3) outputs are kept at logic "0" (shut off)

c. Command Definition

Fig. 10-38 : Master Control Relay (MCR) Command

X6

JKP(3)

STORE JMP ...

... X6 3

A. Ladder Diagram

b. Programming Lines

If X6=0, then the next (3) outputs are frozen, and the PLC continues its scan at the rung following the third output

c. Command Definition

Fig. 10-39 : Jump (JMP) Command

X1 X3 X4 X5

X2

CR1

X1 X3 X4 X5

X2

CR1

CR2

X3

CR2

a. Relay Ladder Diagram
CR1 = X1.X2 + X3.X4.X2 CR2 = X3.X5 + X1.X4.X5

c. PLC Ladder Diagram
CR1 = X1.X2 + X3.X4.X2 CR2 = X3.X5

b. Boolean Function Un-expected Sneak Path - X1.X4.X5

d. Boolean Function No Sneak Path

Fig. 10-40 :Differences Between Relay and PLC Ladder Diagram Sneak Path

X1 X5 X2

X3

CR1

X1 X2

X2 X3 X5 X5 X4 X3

CR1

X4

X1 X2

a. Relay Ladder Diagram

b. PLC Ladder Diagram

CR1 = X1.X3+X2.X4+X1.X5.X4+X2.X5.X3

c. Boolean Function

Fig. 10-41 :Differences Between Relay and PLC Ladder Diagram Multiple Contacts

X1

cr2 cr2

y1 CR1 cr1 Y1

Rung 1
I/O Update
at Beginning of Scan

Variables States This Scan Next Scan Y7=0 , CR2=0 CR4=0 , CR6=0 X4=1 , Y7=1 X4=1 , CR4=1 Y7=1 , CR5=1 CR6=0 , Y8=0 CR6=1 , Y8=1 Y7=1 , CR2=1

X1

Rung 2
y1 X1

y7 cr4

CR2 CR6

Rung 3
CR4=1 , CR6=1

CR1

x4 Y7 x4 CR4 y7 CR5 cr6 Y8

Fig. 10-44 : Trigger (Toggle) Flip-Flop for PLC
1 2 3 4 5 6 7 8 9 10 11 12 13

PLC Scan X1 (Input) Rung 1 : CR1 Rung2 : Y1 (Output) Rung 3 : CR2

Fig. 10-42 : Effect of Scanning Action on Internal States of Relay Coils

Fig. 10-45 : PLC Sequence Chart for Fig. 10-44 USE OF PLC WITH ANALOG I/O
X1 X1 CR1 cr1 Y1

STORE AND NOT OUT STORE OUT a. Proper Rung Order

X1 CR1 Y1 X1 CR1

X1 Y1 Scan Period

Pressure Transducers Temperature Transducers Flow Transducers Humidity Transducers Load Cells Potentiometers

Fig. 10-46 : Analog Input Devices to PLC
4 - 20 mA 0 - 1 volt DC 0 - 5 volt DC 0 - 10 volt DC 1 - 5 volt DC +/- 5 volt DC +/- 10 volt DC

X1 CR1 X1 cr1 Y1

STORE OUT STORE AND NOT OUT

X1 CR1 X1 CR1 Y1

X1 Y1

b. Improper Rung Order

Fig. 10-47 : Standard Analog-Input Interfaces Nodules
Analog Valves Pneumatic or Hydraulic Cylinders or Motors Recorders Electric Motors

Fig. 10-43 : Importance of Proper Rung Order

10-11

Fig. 10-48 : Analog-Output Devices Actuated by PLC

4 - 20 mA 10 - 50 mA 0 - 5 volt DC 0 - 10 volt DC +/- 5 volt DC +/- 10 volt DC PID Controller

Analog instruction used

Voltage Signal 0 0 1 0 1 1 0 1 1 0 0 1
12 bits Register holding analog value Analog Output module D/A

Return Line

Analog Transducer

Fig. 10-49 : Standard Analog Output Interface Modules

Analog instruction used

Not Used

Analog Transducer

Voltage Signal Return Line
A/D 12 bits Analog input module

0 0 1 0 1 1 0 1 1 0 0 1
Register holding analog value

0 0 0 0 0 0 1 0 1 1 0 1 1 0 0 1

Word location or Register Storage location

Data Table

Fig. 10-52 : Tranferring a Word to Analog Output Module
0 0 1 0 1 1 0 1 1 0 0 1
Word location or Register Storage location

ANALOG OUTPUT
Data Table

Since A/D converters are expensive, they are often shared by several 4 to 8 channels. One channel is read and stored on every scan.

Rack 4 Slot 05 Number of channels 4 Source register 300

(Rack with 4 slots) (Slots 0 to 7 per rack) (Octal code 300 = 192)

Fig. 10-50 : Storing an Analog Input

Fig. 10-53 : Typical "Analog Out" Instruction Block

PID CONTROLLER ANALOG IN Rack o Slot 03 Number of channels 8 Destination register 200 (Rack with 8 slots) (Slots 0 to 7 per rack) (Octal code 200 = 128) Control (Enables Outputs) Connected to Register 1. Controlled Variable 2. Controller Output 3. K (P-control) 4. R (I-control) 5. T (D-control) 6. Set Point (Given by analog input module) (Sent to analog output module) (Active loop control) (High alarm limit) (Low alarm limit)

(Since there are 8 channels, the 8 slots would be assigned the Destination Register 200 8 to 207 8)

Track (Tracks incoming variables, even if "Control" is off)

Fig. 10-51 : Typical "Analog In" Instruction Block

In some PLC's, the PID Controller is implemented by a special output module, i.e. by hardware. In others, it is programmed using a special Insrtuction Block, such as shown here.

10-12

Fig. 10-54 : Typical "PID Controller" Instruction Block

ENHANCED LADDER DIAGRAM INSTRUCTIONS
(Enhanced ladder diagram instructions are handeled very differently in different PLC models. Therfore, only a few typical examples are shown here.)

Data Conversion
These change the contenta of a specified register. Typical Conversions :

LATCH (UNLATCH) GOTO ADD ADD
Control (Enable) Register X Overflow Output

BCD to Binary Binary to BCD Absolute Value Complement (multiplied by -1) Invert (inverts all bits) Logical Shifts : Moves all bits of a register to right or left Data Transfer Instructions :
There are many such instructions, used to move data within the PLC

+ Register Y = Register Z

Fig. 10-55 : Typical "ADD" Instruction Block

Fig. 10-58 : Data Commands MICRO-AUTOMATION versus MACRO-AUTOMATION

SUBTRACT MULTIPLICATION DIVISION SQUARE ROOT COMPARE COMPARE
Control (Enable) Register X Register Y

Micro-Automation :

Automation of a single machine, or a small group of machines, also called an "Automation Island". (This course deals with Micro-Automation). Automation of a large plant, consisting of many individual automation islands. Uses a large computer or a large PLC, that coordinates the operation of the individual automation islands. Each automation island is uusually controlled by its own control system, such as a small or medium-sized PLC ("Distributed Control").

Macro-Automation :

> = <

Macro-automation makes use of a LAN (Local-Area-Network), which links the various stations or automation islands with the central supervising computer or PLC. The use of a LAN provides : 1. Distributed Control 2. Centralized Data Aquisision The LAN can be organized according to any one of a several possible LAN Topologies (arrangements), such as "Common Bus", "Star" or "Ring".

Fig. 10-56 : Typical "COMPARE" Instruction Block

AND OR XOR NAND NOR NOT

Fig. 10-59 : PLC Micro/Macro Systems Definition

Fig. 10-57 : Logic Operations
(or correcponding bits of two specified registers)

BUS

STAR

RING

10-13

Fig. 10-60 : Several Possible LAN Topologies

1. 2. 3. 4. 5.

Different size elements are transferred on a conveyor belt. All elements that are below specific thickness must be rejected. Reject is performed by opening a reject door - Z=1. Photocells X1 and X2 are placed in specific locations. X2 is covered by all sizes. X1 is covered by elements over specific thickness.
Road X1 X2

10-14

Railway

See Fig. 6-3

a. System Configuration a. System Configuration
A B CR1 B CR1

00/0
1

10/0
2

11/0
3

01/0
4

CR1

B

L
A

01/1
5

b. Primitive Flow Diagram

b. System Relay Ladder Diagram

S = X1.X2' R = X1'.X2' Z = X2.CR1'

(S = X1)

PLC X1 X2 Y1

I/O

A B
L

c. System Functions (See Fig. 6-2) c. PLC Variables Assignment
PLC X1 X2 Y1 I/O

X1 X2
Z

X1

X2 CR1

X2 CR1

d. PLC Variables Assignment
X1 X1
CR1

CR1

X2

Y1 X1

CR1 CR1

X2 X2
Y1

d. PLC Relay Ladder Diagram
1 4 3 4 5 6 7 8 9 STORE AND OR AND OUT STORE NOT AND OR OUT X1 X2 CR1 X2 CR1 CR1 X2 X1 Y1

e. PLC Ladder Diagram
1 2 3 4 5 6 7 8 9 STORE OR STORE OR AND OUT STORE NOT AND OUT X1 CR1 X1 X2 STORE CR1 CR1 X2 Y1

e. PLC Program

f. PLC Program

Fig. 10-61 : Thickness Detector System

Fig. 10-62 : Traffic-Light Control System

Danger Signal Confirmation

X1 X2

ALARM SYSTEM

Z1 Z2

ALARM SIREN ALARM FLASH

{3,4,5} {2.6} {1} {1,5} {2.6} {3,4} f. Merge Options

10-15

a. System Block Diagram (According to Fig.6-1)

* Cannot ignore multiple input changes "simultaneously" * No race or hazards. Action depends on commands Order

{1,5} {2.6} {3,4} g. Selected Options

b. Different Considerations in Relay/PLC Systems

X1,X2

00
00/00 10/10 11/01 10/10

10

11

01

1

2

3

4

CR1 CR2

1 6 1

2 2 4

3 3 3

5 5 5

01/00

00/10

5

6

X1,X2/Z1,Z2

CR3

h. Merged Flow Table & States Assignment c. Primitive Flow Diagram
X1,X2 X1,X2 X1,X2

00 CR1

10

11

01

00 CR1 CR2 CR3

10

11

01

0 1

- 1 0

0

0 0

0 1

1

0

00

10

11

01

z1

z2 CR2

1 6 1 1 1 6

2 2 4 4 2 2

0

-

-

3 3 3 3 3 3

5 5 5 5 5 5

0 1 0 0 0 1

0
CR3

-

-

0 1 1 0 0 S1 S2 S3 R1 R2 R3 = = = = = = X1'.X2'.CR2' + X1'.X2 = X1'(X2' + CR2') CR1.X1.X2' X1.X2 CR2.X1.X2' + X1.X2 = X1(X2 + CR2) X1'.X2 + X1.X2 = X2 CR1.X1'.X2' + CR1.X1'.X2 = CR1.X1' Z2 = CR3

i. Output Table of Z1

j. Output Table of Z2

d. Primitive Flow Table

1 6 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14

Z1 = CR2

k. Exitation & Output Functions

5 4
e. Merge Diagram

3

STORE NOT OR NOT AND NOT OR STORE NOT AND NOT OR NOT AND OUT AND AND NOT OR AND NOT OUT

CR2 X2 X1 CR1 X2 CR2 X1 STORE CR1 X1 X2 CR2 X2 CR2

15 16 17 18 19 20 21 22 23 24

STORE AND OR STORE NOT OR AND OUT OUT STORE OUT

X1 X2 CR3 CR1 X1 STORE CR3 Z2 CR2 Z1

l. PLC Program

Fig. 10-63: PLC Design of Alarm System

Set 1
A B

See Fig. 6-4
Reset 1'

a. System Configuration

STORE NOT AND NOT AND NOT AND NOT OR STORE NOT OR STORE NOT OR NOT AND OR NOT AND OUT AND STORE AND NOT OR AND NOT OR STORE NOT OR STORE NOT OR NOT AND OR NOT AND OUT AND STORE AND NOT OR AND OR STORE NOT OR STORE NOT OR NOT AND OR AND OUT AND NOT STORE AND OR AND OR STORE NOT OR STORE NOT OR NOT AND OR AND OUT STORE AND STORE AND NOT OR STORE AND NOT OR STORE AND OR OUT

X1 X2 CR2 CR3 CR1 CR2 X2 CR4 X2 STORE X1 STORE CR1 X1 CR3 X1 STORE X2 CR2 CR1 X1 CR3 X1 STORE X2 STORE CR2 X2 CR4 X2 STORE X1 CR3 CR2 X2 CR4 X2 STORE X1 STORE CR3 X1 CR1 X1 STORE X2 CR4 CR1 X1 CR3 X1 STORE X2 STORE CR4 CR1 X2 CR2 X1 STORE CR3 X2 STORE CR4 X1 STORE Y1

10-16

S2 = CR1.A.B' + CR3.A'B' S3 = CR2.A.B + CR4.A.B' S4 = CR1.A.B + CR3.A'B S1 = A'B'.CR2'.CR3' R1 = CR2.A.B' + CR4.A.B R2 = CR1.A'B + CR3.A.B R3 = CR2.A'.B' + CR4.A'B R4 = CR1.A'.B' + CR3.A.B' = A(CR2.B' + CR4.B) = B(CR1.A' + CR3.A) = A'(CR2.B' + CR4.B) = B'(CR1.A' + CR3.A)

Set 2

Reset 2'

D = CR1.B + CR2.A' + CR3.B' + CR4.A

b. System Original Functions (from 6-4)
Set 3

PLC X1 X2 Y1

I/O

A B
D

Reset 3'

c. PLC Variables Assignment

Set 4 Set Functions S1 = X1'X2'.CR2'.CR3' S2 = CR1.X1.X2' + CR3.X1'X2' = X2'(CR1.X1 + CR3.X1') S3 = CR2.X1.X2 + CR4.X1.X2' = X1(CR2.X2 + CR4.X2') S4 = CR1.X1.X2 + CR3.X1'X2 = X2(CR1.X1 + CR3.X1') Inverted Reset Functions R1' = X1' + (CR2'+X2)(CR4'+X2') R2' = X2' + (CR1'+X1)(CR3'+X1') R3' = X1 + (CR2'+X2)(CR4'+X2') R4' = X2 + (CR1'+X1)(CR3'+X1') Output Function Y1 = CR1.X2 + CR2.X1' + CR3.X2' + CR4.X1 Reset 4'

Y1

d. PLC System Functions

Fig. 10-64 : Motor Direction Detector

e. PLC Program

1. A security door is connected to a combination lock, that is controlled by two input switches : X1 and X2 . 2. The door is opened and closed, by entering the following sequence : X1,X2 = 00 , 10 , 11 , 10 , 11 ..... 00
Open (T=1) Close (T=0)

10-17

Actually, door is opened when latest 5 inputs satisfy the sequence 00 , 10 , 11 , 10 , 11 , and closed as soon as input becomes 00.

a. System Definition

Switch X1 Switch X2

Improper Sequence

Proper Sequence

Combination Lock

T

Open Door

X1,X2 / T
01/0 8 00/0 1 01/1 7 11/0 9 10/0 10 10/1 6 11/1 5 10/0 4 10/0 2

b. System Block Diagram

11/0 3

X1,X2

00

01

11

10

T

1 1 1 1 1 1 1 1 1 1

8 8 8 8 7 7 7 8 8 8

9 3 3 5 5 5 5 9 9 9

2 2 4 4 6 6 6 10 10 10

0 0 0 0 1 1 1 0 0 0

c. Primitive Flow Diagram

1 10 2 3 4 7 6
e. Merge Diagram
X1,X2

9 8 5

{1},{2},{3},{4},{5,6,7},{8,9,10} f. Merge Selection

d. Primitive Flow Table

X1,X2

00 CR1 CR2 CR3 CR4 CR5 CR6

01

11

10

00 CR1 CR2 CR3 CR4 CR5 CR6

01

11

10

1 1 1 1 1 1

8 8 8 8 7 8

9 3 3 5 5 9

2 2 4 4 6 10

- - - - 1 - 0
0

0

0

0 1 0

S1 = X1'.X2' S2 = CR1.X1.X2' S3 = CR2..X1.X2

R1 = CR2.X1.X2'+CR6.X2 R2 = CR2.X1.X2+CR.'.X2+X1'.X2' R3 = CR3.X1.X2'+CR6.X1'+X1'.X2'

1 0

S4 = CR3.X1.X2' R4 =CR5.X1.X2+CR6.X2+X1'.X2' S5 = CR4.X1.X2 R5 = X1'.X2' S6 = CR1.X1.X2 +CR5'.X1'.X2 R6 = X1'.X2' T = CR5

g. Merged Flow Table & States Assignment

h. Output Table

i. System Functions

Fig. 10-65 : Combination Lock System

CHAPTER 11
INTRODUCTION TO ASSEMBLY AUTOMATION
Nonvibratory Feeding & Orienting Devices Vibratory Feeding & Orienting Devices Parts Transfer

CHAPTER 12
ROBOTICS AND NUMERICAL CONTROL
Basic Robot Definitions Basic Geometry Numeric Control (NC) Systems

CHAPTER 13 APPENDIX

Simester Exam Example Simester Exam Solution Typical Simester Exam Questions

13-1

13-2

13-3

01.07.2003 - QUESTION 1
1 2 3 4

T = CDE'F + B'C'D'E'G + A'BDF + A'B'CD'E' + +A'BC'DE + B'CDEF + A'B'E'FG + A'C'DE'F
5 6 7 8

13-4
7

01.07.2003 - QUESTION 2

FLOW DIAGRAM
1
00/1

PRIMITIVW FLOW TABLE
00 1 3 10 2 2 11 5 5 01 4 4 4 A 1 0 0 0 0

4
01/0

5
11/0

2
10/0

3 1

3
00/0

-

1

MINIMAL MERGE OPTIONS

2 5

A B

{1,4,5},{2,3} {2,3,5},{1,4}

*

4

3
MERGED FLOW TABLE (A)

00 1 3 1 0

10 2 2 0

11 5 5 0

01 4 4 0

13-5

01.07.2003 - QUESTION 3

B+ START , A+ , C+ , C- , C+ ,

B, CA-

START a1 a2 b1 b2 c1 c2 A+ B+ C+

X0 X1 X2 X3 X4 X5 X6 Y1 Y2 Y3

I

II

III

(IV)

STORE AND NOT
START

X0 CR3 X5 CR1 CR2 CR1 X6 CR2 CR3 CR2 X5 CR3 X1 X3 STORE CR3 X6 CR1 CR2 Y1 Y2 CR1 X2 X4 CR3 Y3

cr3'

c1

cr2'
CR1

x0
cr1

cr3'

x5

cr2'
CR1

cr1 cr1 cr2
a1

AND OR AND NOT OUT AND OR AND NOT OUT AND OR STORE NOT OR NOT AND OUT AND NOT OR OR OUT OUT STORE AND AND OR OUT

c2

cr3'
CR2

cr1 cr2

x6

cr3'
CR2

x1' cr2 x5
CR3

cr2 cr3

c1
b1

x3'

CR3

cr3

cr1 cr2 cr3
c2

A+

cr1
Y1

cr2 cr3 x6'

B+

Y2

cr1 cr3

a2

b2 C+

cr1 cr3

x2

x4
Y3

PLC BASED DIAGRAM RELAY BASED DIAGRAM

13-6
01.07.2003 - QUESTION 4
SEQUENCE
B+ START , A+ , A, C+ , D+ , D- , C- , B- ,

start

a2

a1 b2

c2

d2

d1

c1

b1

&
1 2 3 4 5 6 7 8

1/n

A+

B+

C+
(B+)

D+

(D-) (B+) (C+)

(B+)

(B-)

OR

OR

A+

D+

C+

B+

start

a2

a1 b2

c2

d2

d1

c1

b1

&
1 2 3 4 5 6 7 8

2/n

A+

B+
(A-)

C+
(B+)

D+

(D-) (B+) (C+)

(B+) (A-)

(B-) Cell 1 : Unknown length of START. May cause pulse on A+ Cell 2 : A- function opens a2 Causes pulse on B+ Cell 5 : D- function opens d2 Causes pulse on B+ and C+

RESET SET FLIP-FLOP RESET SET FLIP-FLOP RESET SET FLIP-FLOP

A+

B+

D+

C+

13-7

13-8

13-9

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