Unconventional applications of conventional IBIS models

Nitin Kumar Chhabra
AMSIP/TRnD STMicroelectronics Pvt. Ltd Greater Noida (U.P.), India nitin.chhabra@st.com

Vishrant Goyal
AMSIP/TRnD STMicroelectronics Pvt. Ltd Greater Noida (U.P.), India vishrant.goyal@st.com

Abstract • Unconventional applications of conventional IBIS model is presented in this paper. It overcomes the limitation of existing pure IBIS modeling techniques to model the differential drivers with data dependent multi voltage leveled response. A new methodology is proposed to model such drivers with the help of two examples where the output having various voltage levels depends on the input data patterns. First example is that of HDMI transmitter with 3 levels of programmable pre-emphasis tap. Another example deals with Ethernet which works on mlt3 (Multi-Level Transmit) encoding where the output of driver comprises three voltage levels, depending on the bit patterns. Keywords ! IBIS , pre-emphasis , mlt3 , HDMI , Ethernet.

modeling [7][8]. But all the methods have some inherent limitations which will be discussed in subsequent sections. In this paper, a simple technique to model such drivers using traditional IBIS is presented. The rest of this paper is organized as follows. Section II focuses on modeling HDMI driver with programmable pre-emphasis. Present solutions and there limitations are presented. The proposed methodology is explained with its advantages over the existing one and has been verified using experimental results. Section III describes the modeling of Ethernet driver. Limitations of traditional modeling technique are explained. The proposed design methodology and results are also presented. Section IV concludes the paper and its generalized applications. II. A. EXAMPLE 1: MULTI TAP PROGRAMMABLE PREEMPHASIS MODELING



An IBIS model is one of the most common ways to represent the behavior of an I/O driver [1]. They are used in place of SPICE models that contain low level circuit details of the buffer [2]. As the speed and complexity of the I/O drivers increase, they are required to be operated at multi voltage levels for proper communication. Examples of such multilevel voltage operations are pre-emphasis [3][4] and mlt-3 line encoding [5]. Pre-emphasis is required for enhancing the high-frequency components of the transmitted signals, in order to compensate for the low-pass distortion effect of interconnects. As driver technology is advancing and complexity of the I/O circuits is increasing, pure IBIS modeling technique fails to represent advanced features such as multi-tap programmable pre-emphasis and de-emphasis. On other hand line encoding is applied in communication systems. For example, Ethernet driver in 100Base-TX mode (IEEE standard 802.3_2008 Ethernet specification) works on MLT-3 line encoding [5] which has three voltage levels for data transmission. MLT-3 encoding has many advantages such as emitting less electromagnetic interference, requiring less bandwidth than unipolar, polar, and bipolar signals operating at the same data bit rate. Traditional IBIS modeling technique is not able to cater this type of models also. Several methodologies have been proposed in past like driver schedule [3][4] , VHDL/ Verilog-AMS [6] or IBIS macro-

Problem Statement To model a High-Definition Multimedia Interface (HDMI) transmitter, which is a buffer with three level of tap preemphasis, where each level has programmable pre-emphasis strength. It has 11 values of pre-emphasis in first tap (0 to 5mA current at step of 0.5mA), 7 values in second tap (0 to 3mA current at step of 0.5mA) and 4 values in third tap(0 to 1.5mA current at step of 0.5mA).

B. Present Solutions and their limitations One of the initial approaches for IBIS modeling of buffer with pre-emphasis is with the help of Driver Schedule keyword [3][4]. Using the same approach it will take 308 different models (11*7*4) to be developed in order to accommodate 11 values of pre-emphasis in first tap, 7 values in second tap and 4 values in third tap. In addition to that, Driver Schedule has few limitations as well [4]: • There is no provision for clock input so the delay is !hard coded". It has to be changed manually or by using different Driver Schedule settings for each frequency.

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minimum and maximum). Dp-1/Dn-1 corresponds to one previous bit input while Dp-2/Dn-2 corresponds to two previous bit input.• • Delay parameter does not have typical. Second solution to the same problem is using multi-lingual IBIS modeling where the model is written either in VHDLAMS or Verilog-AMS [6]. and previous two bit data (DataN-2) and so on. where the entire three tap pre-emphasis with maximum strengths are present. These standard IBIS models are prepared by the general approach as mentioned in IBIS cookbook [9][10]. The approach is basically the replication of the SPICE design by just replacing the main transmitter with its IBIS model after simplifying the design. or incorporates Spice sub-circuit. the required inputs to the system are the present data (DataN). Further this model can be run on any EDA tools. This approach has the proper delay for each corner case (typical. Obtaining a separate Model data for the Main and Boost buffers may still require the editing of the SPICE netlist. All basic buffers are present at all times just like in spice so the complete C_comp will remain same and their effect is also accounted properly. Experimental Results IBIS simulation results have been co-related with the spice simulations for various tap-level and pre-emphasis strengths. Dp Dp-1 Dp-2 Dn Dn-1 Dn-2 00001010011100 00000101001110 00000010100111 11110101100011 11111010110001 11111101011000 As shown in table I. Here one of the critical cases is discussed. so the final input is required before making proper top model. Moreover. minimum and maximum corners. Table II shows the signals for the pre-emphasis buffers: 213 . There is no hard coded bit delay or frequency factor in the model. The previous data(s) could be prepared by zero padding in case of stream line data or by simply right circular shift in case of repetitive pattern. For each set of input we have to develop a unique model. one just needs to edit the wrapper accordingly. The combinational logic and bank of IBIS buffer could be grouped together inside any simulator specific wrapper. the corresponding pre-emphasis strength is also required. driver schedule could not be used for real time data simulation in the present case. Table I shows the input patterns for this case: Figure 1: Basic Block Diagram Table I: Input Data As shown in the figure 1. the output of each buffer is wired together (shorted) to give the final output of the transmitter model. The user provides the required input and then depending on those inputs intermediate signals are generated. regarding proper handling of C_comp. C. till the entire tap levels are covered. The latter approach is also known as IBIS macro-modeling [7][8]. As shown in figure 2. For each tap level. These intermediate signals are supplied to the bank of IBIS buffers. Figure 2 : Buffer Configuration D. external model and S-parameter model. There are a still some open issues faced by users community. which are the combination of IBIS models of Main buffer and pre-emphasis buffers. New Methodology Advantages The proposed IBIS model is frequency independent. For the above inputs. New Methodology Figure 1 shows the basic block diagram representing the complete general approach of the IBIS modeling. Limitation of this approach is that all the EDA vendors do not support the macro-model. • • Thus. macro-models are not the conventional pure IBIS models. It is input dependent. Dp/Dn corresponds to present real time differential data input to the buffer for positive and negative node respectively. previous one bit data (DataN-1). E.

New Methodology EN_P_Up P_Up Et100bt_Up TxP EN_P_Dn P_Dn Figure 3: IBIS vs Spice correlation It can be observed from the output that the present case covers four different stages. shows the IBIS and the spice outputs. Table III: Comparison of simulation time Figure 3. III. Problem Statement To Model an Ethernet driver in 100Base-TX mode (IEEE standard 802.eps=1e-8) 7sec 8hrs 37min 57sec. while other tap pre-emphasis buffers are off. while there is no impact of any of the pre-emphasis buffer. shows the EYE diagrams of the differential signal created by IBIS and SPICE simulations. The two EYEDiagrams are also matching well. Table III shows the comparison between the simulation time taken by the IBIS model and the time taken by the Transistor # model. It would suffer from the limitations as already stated in section II The other solution can be Macro Modeling [7][8] or the use of the external keyword support for Verilog/VHDL-AMS modeling [6]. Initially only main buffer is on.Table II: Pre-emphasis Signals PE1A PE2A PE3A PE1B PE2B PE3B 11111010111101 11111111111101 11111111111101 11110101101111 11110111101111 11110111111111 Figure 4. IBIS Simulation Time (Linux. which clearly indicates the advantage of using the IBIS simulation over the normal SPICE simulation.16GB RAM) IBIS Macro-Model Transistor Model ELDO ELDO (100ns. Second stage is where all tap pre-emphasis buffers come in the picture and we have maximum pre-emphasis. While in the fourth stage first tap pre-emphasis and second-tap pre-emphasis buffer are on while third tap #pre-emphasis buffer is off.4*3. Different buffer stages are modeled separately and timing parameters are used to dictate final output.eps=1e-8) (100ns. DP SPICE EXAMPLE 2: IBIS MODELLING OF MLT-3 ENCODED DATA FOR ETHERNET DN A. The figure shows a very good co-relation between IBIS and spice output. Four different levels of DP (positive) and DN (negative) signals are clearly indicated in figure 3. C. IBIS EYE Et100bt_Dn EN_N_Up N_Up Et100bt_Up TxN SPICE EYE N_Dn Et100bt_Dn EN_N_Dn Figure 5 : Basic Implementation Methodology Figure 4 : IBIS vs SPICE EYE Diagram 214 . The limitation of this approach is that the lots of the PCB Signal Integrity tools don$t support AMS models.3GHz. Third stage is where only first tap pre-emphasis buffer is on. Present Solutions and their limitations The Driver Schedule keyword can be used to model multi-stage drivers [3][4].3_2008 Ethernet specification) in which driver gives MLT-3 encoded data at the output which has three voltage levels for data transmission B.

E. Minggang Hou. IBIS Summit at DesignCon 2005. CONCLUSIONS At present. Vol. Fran1on. many EDA vendors and product companies are not supporting the new IBIS standards (IBIS-5.eigroup. Input Data Stream P_Up P_Dn N_Up N_Dn En_P_Up EN_P_Dn EN_N_Up EN_N_Dn 10000111111110111100010010111111110 00000010001000010000000011000100011 00000111011100111000011111101110111 11111000100011000111100000010001000 11111101110111101111111100111011100 00000011001100011000000011100110011 11111100110011100111111100011001100 11111100110011100111111100011001100 00000011001100011000000011100110011 [3] Cuny R.25V to 0. December 2005 [6] Arpad Muranyi. where the macro-models itself are the IBIS files. 277#280.12th Topical Meeting Electrical Performance of Electronic Packaging (EPEP).2. in Asian IBIS Summit. New Methodology Advantages The new methodology is quite simple and easy to implement in any EDA tools with the help of corresponding wrapper. February 2006 [9] IBIS Specifications available at http://www. !The development of a macro-modeling tool to develop IBIS models. In this Et100bt_Up is a single ended ibis buffer model which switches between 0 to +1 (1. 2008 [7] Varma. IBIS Summit at PCB Conference East Westford. 2004.25V to 1. 2003.0 /AMI) [6] and they still require the traditional IBIS models with slight variations to suit the industry requirements. Shanghai China .EE Times. A. and P. The method is independent of the input data frequency. No. Steer. "Modeling Pre/de-emphasis buffers with [Driver Schedule] ! . REFERENCES [1] [2] Bob Ross.75V) and similarly Et100bt_Dn is the ibis buffer which switches between 0 to -1 (1. The approach is quite simple and easy to implement using basic traditional IBIS models. the output of the driver switches in three voltage levels (1. The other advantage of the proposed methodology is that it eliminates the use of any %hard codded$ bits in the buffer design. Table IV : Input Data Stream and corresponding signal IBIS TxP TxN SPICE Figure 6 : Spice vs IBIS results IV. 1. Figure 5 shows the configuration of these ibis buffers. al. NJ. [8] Bhyrav Mutnury. D. M. The other advantage of the methodology is that it takes care of capacitive effect and is frequency independent. Santa Clara Convention Center. !IEEE Std 802. Santa Clara. Experimental Results IBIS simulation results have been co-related with the spice simulation. A methodology has been developed where 2 single ended ibis buffers are used to create 3 level output signal. The spice vs. Arpad Muranyi.25V and 0. 2003 [4] Arpad Muranyi. Basically the proposed methodology is an extension of the IBIS macromodeling. pp. So these buffers are being used in combination with switches such that at a time only one buffer passes the data.3-2005 Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications. !IBIS Models for Signal Integrity Applications". The approach can be extended to any driver and the wrapper can be developed in any simulator. Glaser.75V) depending on the input pattern (MLT-3 encoded). CA January 31.75V.0". Oct.org/ibis/ [10] IBIS Open Forum. et. There is 100 termination between TxP and TxN at receiver side." IEEE. All the input signals required for this configuration are dependent on input data bit stream. This stimulus is applied to buffer configuration with termination resistance of 100 at 125 Gbps speed which gives the result as shown in Figure 6. Sep. The Basis for Signal Integrity Analyses". Ideal switches (Ron=1µ and Roff=1T) have been used in the configuration. Princeton. MA . There is no hard coded bit period. ! IBIS-AMI Support via VHDLAMS" . 1996. Table-IV shows the input data stream and the input signals required for configuration of ibis buffer. IEEE Transactions on Advanced Packaging. &Macromodeling of Nonlinear Digital I/O Drivers&. !IBIS modeling cookbook for IBIS version 4. S. 1. IEEE symposium. 1996. The driver is simulated at 125Mbps. 215 .In the Ethernet 100Base-TX mode. !SPICE and IBIS Modeling Kits. Lipa. Alternate approach can be the use of 3-state IBIS model which would remove the requirement of any ideal switches. pp 38-43.75V).October 21. 2005 [5] IEEE LAN/MAN Standards Committee. "Details on true Differential Buffer Characterization Revisited". The IBIS models of two buffers are developed from actual post layout design. November 11.. 29." in Proc. IBIS results of differential and single ended signal (TxP and TxN) are observed to be in good correlation. In this experiment the IBIS model is developed as output type so it requires a controllable switch.