INDUSTRIAL TRAINING REPORT

Chapter 1

INTRODUCTION

COMPANY PROFILE: BCS INNOVATIONS

Philosophy: “As an Organization, our goal is to contribute to society through broad -ranging activities in the areas of Software development and Technical Projects. Individually, we aim to combine good citizenship with the courage to innovate”

BCS Innovations is located in Bangalore, the Silicon Valley of India, where high technology is a way of life. Since 26th October 1996, BCS Innovations has successfully performed projects under various platforms and has delivered high quality competitively priced products and services to customers all over India. For over 17 Years, our customers and students have inspired us to create, manufacture and develop advanced technologies to meet the ever growing requirements, through stringent quality expectation, hostile operating conditions and timely targets demanded by our customers and students.

Aim: Recent rapid development in science and technology requires co- operation between University and industry. In response to this demand we aim to bridge and strengthen the collaboration between them.

E&C Department ,NMAMIT

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INDUSTRIAL TRAINING REPORT

Activities: BCS Innovations bring together member organizations, Scientists and Engineers and other leading experts to collaborate on solution to the challenges of technical requirements. These solutions span every area of design, development, testing, and implementation, including safety, health and environment. The mission is to be accomplished by:  Education in core and inter disciplinary areas of technical sciences, technology and engineering through R&D works.  Increasing public awareness of science and technology issues particularly among the young.  Adjust flexible target oriented organizational structure to be able to rapidly respond to new challenges and provides means for efficient technology transfer to the industry.

Our Associates Are:    BCS INNOVATIONS is one among Design Partners of Microchip[1] Prateek Technologies, Browseprice, Bangalore, (2001) (www.prateektech.com)

Bangalore, (2013) (www.browseprice.com)

INFRASTRUCTURE: Development Facilities BCS Innovations with more than 8000 sq. ft. area has good facilities. The workplace is well setup with all the latest equipment’s with good air, light and ventilation, thus providing a healthy atmosphere.

E&C Department ,NMAMIT

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1. Page 3 E&C Department . the products are upgraded. BCS INNOVATIONS is one among Design Partners of Microchip [1]. There are many knowledgeable and well experienced Technical Staff and Administration Staff. security. Good collection of technical books are maintained in the library. Research & Development: The Research and Development unit continuously monitor and provide support to the products. MCU/PIC Specialty  8bit.INDUSTRIAL TRAINING REPORT Training facilities BCS Innovations has the modern facilities to enable a clean and transparent interaction between the management and the staff. SPECIALTIES: BCS Innovations is a company that specializes in the development and service of various electronic and software products.NMAMIT . instrumentation and medical devices. BCS can also provide specialized services such as the design and construction of test jigs. We also provide back to base and field service of various products.16bit. manual and other technical periodicals. Our expertise spans a number of fields including telecommunications. thus keeping in par with the industrial requirements. supported with journals. With the technological advancement. apart from providing innovative solutions to the customers. Our involvement in the product development process can be as little as reporting on the feasibility of a design up to the complete project management of the product design and manufacturing cycle. Design expertise  Software and Hardware 2.

Application Specialty        Connectivity and networking: USB. brushed DC. Telecom. Analog specialty  Mixed signal.com raju@bcsinnovations.INDUSTRIAL TRAINING REPORT 3. Power supplies: analog and digital. BCS Innovations # 86. Manufacturing capabilities: outsource manufacturing.NMAMIT Page 4 . Medical. 5. Linear.560054 Telephone: 080-41748280. 4. Gokul Towers. AC induction. interface. Market Segment Specialty   Automotive. Mobile: Website: E-mail: 9845023627 www. RF.com E&C Department .M. 6. Utility metering: energy. Consumer. battery management.bcsinnovations.S.Bangalore . Infrared Home and building automation: security systems and lighting control Lighting: fluorescent Motor control: stepper. Home Appliances Industrial.com chbraju123@yahoo. Gokula. sensors. Other capabilities: audio and speech. 2nd Floor. Ramaiah Main Road.

This was followed by mini project assigned to us during the last 2 weeks of our Industrial Training. from 2nd September to 14th September. (2) logic gates used by designers.e. from 26th to 31st August training on Verilog HDL was conducted.1 ADVANCED DIGITAL DESIGN The key elements that the training focused include (1) Boolean logic. The training on FPGA Design Flow was given on fifth and sixth week of our Industrial training. The four phases were as follows     Advanced Digital Design Verilog HDL Introduction to XilinxISE FPGA Design Flow Each phase was completed as on schedule. The introduction to advanced digital design was carried on from 19th August to 24th August.NMAMIT Page 5 . the widespread availability of web based ancillary material prompted us to limit our discussion of field E&C Department . The very next week i.  Implementation of Booth 3 algorithm on FPGA 2. and (4) data path controller design—all from a perspective of designing digital systems. This focus led to elimination of material more suited for a course in electronics.e. (3) synchronous finite state machines. Additionally. Introduction to Xilinx ISE was followed by the next two weeks i.INDUSTRIAL TRAINING REPORT Chapter 2 TRAINING UNDERGONE In BCS Innovations the training was done in four phases for about six weeks starting from 19th August up to 28th September.

or NOR gates. 2. c) Gate Level Minimization This section covered the map method for simplifying Boolean expressions and the map method is also used to simplify digital circuits constructed with AND ‐OR. E&C Department .NMAMIT Page 6 .2 Summary of each Section a)Digital Systems and Binary Numbers: This section presented the various binary systems suitable for representing information in digital systems.2. NAND. All other possible two‐level gate circuits are considered. and the most useful logic gates used in the design of digital systems were identified.INDUSTRIAL TRAINING REPORT programmable gate arrays (FPGAs) to an introduction of devices offered by only one manufacturer. b) Boolean algebra and Logic Gates: This section presented the basic postulates of Boolean algebra and shows the correlation between Boolean expressions and their corresponding logic diagrams.1. All possible logic operations for two variables are investigated. The binary number system was explained and binary codes were illustrated. and their method of implementation was explained. rather than two.1 Sections covered         Digital Systems And Binary Numbers Boolean Algebra And Logic Gates Gate Level Minimization Combinational Logic Synchronous Sequential Logic Registers And Counters Memory And Programmable Logic Design At Register Transfer Level 2.

Combinational and sequential programmable devices such as ROMs. The gate structure of several types of flip ‐flops was presented together with a discussion on the difference between level and edge triggering. Frequently used digital logic functions such as parallel adders and subtractors. CPLDs. and multiplexers are explained. E&C Department . decoders. and their use in the design of combinational circuits were illustrated e) Synchronous Sequential Logic This section outlined the formal procedures for analyzing and designing clocked (synchronous) sequential circuits. These digital components are the basic building blocks from which more complex digital systems are constructed g) Memory and Programmable Logic This section dealt with random access memory (RAM) and programmable logic devices. PLAs. h) Design at Register Transfer Level This section dealt with the register transfer level (RTL) representation of digital systems. and FPGAs were presented. and counters. Specific examples were used to show the derivation of the state table and state diagram when analyzing a sequential circuit.NMAMIT Page 7 . shift registers. are introduced as design examples.INDUSTRIAL TRAINING REPORT d) Combinational Logic This section outlined the formal procedures for the analysis and design of combinational circuits. PALs. such as adders and code converters. Some basic components used in the design of digital systems. A number of design examples were presented with emphasis on sequential circuits that use D‐type flip‐flops f) Registers and Counters This section dealt with various sequential circuit components such as registers. Memory decoding and error correction schemes were discussed. encoders.

Verilog can be used to describe designs at four levels of abstraction:    Algorithmic level (much like c code with if.NMAMIT . The program can then be used to both simulate the operation of the circuit and synthesize an actual implementation of the circuit in a CPLD. Register transfer level (RTL uses registers connected by Boolean equations). The most widely used HDLs are VHDL and Verilog.2 VERILOG HDL The digital designers use hardware description languages (HDLs) to design digital systems. Both of these hardware description languages allow the user to design digital systems by writing a program that describes the behavior of the digital circuit. or an application specific integrated circuit (ASIC). case and loop statements). and are usually more readable than schematics. Verilog is a hardware description language that is designed to model digital logic circuits. 2. These block diagrams can then be compiled to produce Verilog or VHDL code. Gate level (interconnected AND. easy to design and debug.).HDL’s allows the design to be simulated earlier in the design cycle in order to correct errors or experiment with different architectures. It simply has the same syntax as the C programming language but the way it behaves is different. Another trend is to design digital circuits using block diagrams or graphic symbols that represent higher-level design constructs. NOR etc.INDUSTRIAL TRAINING REPORT The algorithmic state machine (ASM) chart was introduced. Verilog HDL is one of the most common Hardware Description Languages (HDL) used by integrated circuit (IC) designers. Designs described in HDL are technology-independent. Page 8 E&C Department . A number of examples demonstrated the use of the ASM chart and RTL representation. an FPGA. Verilog is based on the C programming language but it is not C. particularly for large circuits.

differences between modules and module instances in Verilog and described the components required for the simulation of a digital design by defining a stimulus block and design block. b) Basic concepts This section briefed us on lexical conventions for operators.2 Summary of each Section a)Hierarchical modeling concepts This section presented good understanding on top-down and bottom-up design methodologies for digital design. parameters. such as nets. simulation time. Some Verilog constructs are not synthesizable. whitespace. Also the way the code is written will greatly affect the size and speed of the synthesized circuit. E&C Department .INDUSTRIAL TRAINING REPORT  Switch level (the switches are MOS transistors inside gates). numbers string and identifiers.1 Sections covered        Hierarchical Modeling Concepts Basic Concepts Modules And Ports Gate Level Modeling Dataflow Modeling Behavioral Modeling Tasks And Functions 2. comments.2. More recently Verilog is used as an input for synthesis programs which will generate a gate-level description (a net list) for the circuit. The language also defines constructs that can be used to control the input and output of simulation.2. numbers. vectors. arrays. registers. Defined the logic value set and data types.NMAMIT Page 9 . 2.

expressions. implicit assignment delay. understanding instantiation of gates. stopping and finishing the simulation. gate symbols. sequential and parallel blocks. strings and tasks for displaying. restrictions on assign statement and the implicit continuous assignment statement. g) Tasks and functions This section briefed on differences between tasks and function. casex and casez statements. f) Behavioral modeling This section covered the significance of structured procedures always and initial in behavioral modeling. d) Gate level Modeling This section covered on identifying logic gate primitives. repeat and forever. event based timing control mechanism. Understanding of blocking and non-blocking procedural assignments. and net declaration delay for continuous assignment statements. operators and operands. It also covered theport connection rules in a module instantiation. E&C Department . e) Dataflow Modeling This section described the continuous assignment statement. naming of blocks and disabling of named blocks. function declaration and invocation. task declaration and invocation.NMAMIT Page 10 .INDUSTRIAL TRAINING REPORT memories. conditional statements using if and else and multi ways branching using case. Understanding of looping statements such as while. c) Modules and ports This section dealt with identifying the components of a Verilog module definition and understanding on how to define the port list for a module and declare it in Verilog. monitoring. for. It also covered assignment delay. and truth tables and constructing a Verilog description from the logic diagram of the circuit. delay based timing control mechanisms.

as well as the family of CPLDs.2 Creating a New Project To create a new project using the New Project Wizard.1Starting the ISE Design Suite To start the ISE Design Suite. 2.3. devices with a large number of I/O pins and large gate matrices are disabled. In the Location field. 2. perform timing analysis.NMAMIT Page 11 .3 Introduction to Xilinx ISE Xilinx ISE (Integrated Software Environment) is a software tool produced by Xilinx for synthesis and analysis of HDL designs. and configure the target device with the programmer. select File > New Project. do the following: 1. The New Project Wizard—Device Properties page appears. enter wtut_vhd or wtut_ver. examine RTL diagrams. In particular. simulate a design's reaction to different stimuli. meaning small developers and educational institutions have no overheads from the cost of development software. From Project Navigator. 2.INDUSTRIAL TRAINING REPORT 2. double-click the Project Navigator icon on your desktop. browse to c:\xilinx_tutorial or to the directory in which You installed the project. 3.3. E&C Department . The New Project Wizard appears. In the Name field. enabling the developer to synthesize ("compile") their designs. The low-cost Spartan family of FPGAs is fully supported by this edition. 4. It provides synthesis and programming for a limitednumberofXilinx devices. Verify that HDL is selected as the Top-Level Source Type. or select Start > All Programs > Xilinx ISE Design Suite > Xilinx Design Suite 14 > ISE Design Tools > Project Navigator. and click next. The Web Edition is a free version of Xilinx ISE that can be downloaded at no charge.

3 Creating an HDL-Based Module With the ISE Design Suite. Other properties can be left at their default values. 2. In the Select Source Type page.NMAMIT Page 12 .INDUSTRIAL TRAINING REPORT 5. The HDL code is then connected to your top-level HDL design through instantiation and is compiled with the rest of the design. E&C Department . Click next. Select Project > New Source. specifying the name and ports of the component. To create the source file. do the following: 1. you create a file using the New Source wizard. then Finish to complete the project creation 2. you can easily create modules from HDL code using the ISE Text Editor.3. The resulting HDL file is then modified in the ISE Text Editor. select VHDL Module or Verilog Module. 5. In this section. This will determine the default language for all processes that generate HDL files. Select the following values in the New Project Wizard —Device Properties page: • Product Category: All • Family: Spartan3 • Device: XC3S500E • Package: FG484 • Speed: -4 • Synthesis Tool: XST (VHDL/Verilog) • Simulator: ISim (VHDL/Verilog) • Preferred Language: VHDL or Verilog depending on preference.

Set the Direction field to input for sig_in and clk and to output for sig_out.NMAMIT Page 13 . 5. c. enter sig_in. In the File Name field. In the Define Module page.INDUSTRIAL TRAINING REPORT 3. clk and sig_out. E&C Department . Click Next. Leave the Bus designation boxes unchecked. enter debounce. 4. In the first three Port Name fields. b. enter two input ports named sig_in and clk and an output port named sig_out for the debounce component as follows: a.

surrounded by programmable input and output blocks and connected together via programmable interconnections.INDUSTRIAL TRAINING REPORT 6. E&C Department . Click Next to view a description of the module. 7. Click Finish to open the empty HDL file in the ISE Text Editor. A typical FPGA consists of an array of millions of logic blocks.W 2.NMAMIT Page 14 .4 FPGA DESIGN FLOW A field‐programmable gate array (FPGA) is a VLSI circuit that can be programmed at the user’s location. There is a wide variety of internal configurations within this group of devices. The performance of each type of device depends on the circuit contained in its logic blocks and the efficiency of its programmed interconnections.

000. These functions are realized from the lookup table. the Spartan family of devices initially offered a maximum of 40K system gates.4.000 logic blocks. and input–output (I/O) blocks (IOBs).NMAMIT Page 15 . For example.000 logic cells plus 4. Each evolution of devices brought improvements in density. and functionality. as shown in Fig. gates. A lookup table is a truth table stored in an SRAM and provides the combinational circuit functions for the logic block. performance. multiplexers.1 Sections Covered      Xilinx FPGA Basic Xilinx Architecture Xilinx Spartan 3 FPGAs FPGA Kit Interfacing And Configuration FPGA Design Flow 2. in the same way that combinational circuit functions are implemented with ROM [5].000 logic blocks [2]. a variety of local and global routing resources. 2.8Mb block RAM.2 Summary of each Section a) Xilinx FPGA Xilinx launched the world’s first commercial FPGA in 1985. and flip‐flops. 2 The XC3000 and XC4000 families soon followed. programmable I/O buffers. and an SRAM ‐based configuration memory. but today’s Spartan‐6 offers 150.Virtex-7 offers 2. Artex-7 offers 24.4.INDUSTRIAL TRAINING REPORT A typical FPGA logic block consists of lookup tables. with the vintage XC2000 device family. power consumption. setting the stage for today’s Spartan™. Kintex-7 offers 480. and Virtex™ device families.000 logic blocks. 2. b) Basic Xilinx Architecture The basic architecture of Spartan and earlier device families consists of an array of configurable logic blocks (CLBs). voltage levels.4. pin counts.1 E&C Department .

NMAMIT Page 16 . significantly reducing the cost per logic cell. These Spartan-3E FPGA enhancements. setting new standards in the programmable logic industry [4]. E&C Department .1: Basic architecture of Xilinx Spartan c) Xilinx Spartan-3 FPGAs The Spartan-3E family builds on the success of the earlier\Spartan-3 family by increasing the amount of logic per I/O.4. CLBs perform a wide variety of logical functions as well as store data. New features improve system performance and reduce the cost of configuration. combined with advanced 90 nm process technology. deliver more functionality and bandwidth per dollar than was previously possible.1 The Spartan-3E family architecture consists of five fundamental programmable functional elements. Summary of Spartan-3E FPGA Attributes is given in table 2.4. • Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that implement logic plus storage elements used as flip-flops or latches.INDUSTRIAL TRAINING REPORT Fig 2.

reprogrammable. Configuration and Display The LCD (Liquid Crystal Display) is included with the Spartan-3E Starter Board Kit sold by both Digilent. the configuration data is written to the FPGA. • Digital Clock Manager (DCM) Blocks provide self-calibrating.INDUSTRIAL TRAINING REPORT • Input/output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. dividing.4.512 33.1: Summary of Spartan-3E FPGA Attributes d) FPGA Kit Interfacing and Configuration Configuration: Spartan-3E FPGAs are programmed by loading configuration data into robust. the first being E&C Department . Device System Gates XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E 100K 250K 500K 1200K 1600K Equivalent Logic Cells 2.192 Max RAM Bits 72K 216K 360K 504K 648K 2 4 4 8 8 108 172 232 304 376 DCMs Max I/O Table 2.NMAMIT Page 17 . Double Data-Rate (DDR) registers are included. multiplying. • Block RAM provides data storage in the form of 18-Kbit dual-port blocks. The FPGA’s configuration data is stored externally in a PROM or some other non-volatile medium. delaying. After applying power. and phase-shifting clock signals.160 5.508 10. either on or off the board. fully digital solutions for distributing. • Multiplier Blocks accept two 18-bit binary numbers as inputs and calculate the product. static CMOS configuration latches (CCLs) that collectively control all functional elements and routing resources.476 19. Each IOB supports bidirectional data flow plus 3-state operation. There are three main steps in using the display. LCD Initialization. Supports a variety of signal standards including four high-performance differential standards.

INDUSTRIAL TRAINING REPORT the initialization of the four bit interface itself.4. Process: 1. 3. Design Entry Design Implementation Design Verification FPGA Configuration Fig 2. 2. Verify the hardware in software (Xilinx ISE 14.2 FPGA design flow E&C Department . the second being the commands to set the display options and the third being the writing of character data.NMAMIT Page 18 .6). Program the S3-E Starter Kit Board. Implement hardware to control the LCD.

A recoding scheme introduced by Booth reduces the number of partial products by about a factor of two.NMAMIT Page 19 . E&C Department . These circuits include a Partial-Product-Generator (PPG) and adders. The Booth 3 decoder and partial product selection logic is shown in fig 2.1 Booth’s Algorithm: The purpose of this project is to present a method of implementing high speed binary multiplication.INDUSTRIAL TRAINING REPORT Chapter 3 MINI PROJECT Efficient FPGA Implementation of Advanced Multiplier – (Booth 3) 3. Fig 1: Booth 3 multiplier. A generator that creates a smaller number of partial products will allow the partial product summation to be faster and use less hardware. Fig 1 shows the logical architecture of Booth-3 multiplier.

NMAMIT Page 20 . Each partial product could be E&C Department . Fig 3: Booth-3 dot diagram and Partial Product Selection table A Booth 3 dot diagram is shown in Fig 3.INDUSTRIAL TRAINING REPORT Fig 2: Booth 3 decoder and partial product selector logic. and each group is decoded to select a single partial product as per the selection table. The multiplier is partitioned into overlapping groups of 4 bits. and an example is shown in Fig 4.

E&C Department .The simulation result for the example shown in fig 4 is as follows.INDUSTRIAL TRAINING REPORT from the set {±0. ±3M. ±M.2 Simulation results: The Booth-3 algorithm is coded using VHDL-Verilog and simulation is performed using Xilinx ISE design suite version 14.NMAMIT Page 21 . ±4M}.6. All multiples with the exception of 3M are easily obtained by simple shifting and complementing of the multiplicand. Fig 4: 16-bit booth 3 example. ±2M. 3.

INDUSTRIAL TRAINING REPORT 3.3 Conclusion: The simplest partial product generator produces N partial products.NMAMIT Page 22 . this may reduce the hardware cost and improve performance. Since the amount of hardware and the delay depends on the number of partial products to be added. where N is the length of the input operands. By the use of Booth-3 algorithm the number of partial products gets reduced by about a factor of two. E&C Department .

Digital Design. [4] xilinx. ―Rapid prototyping of digital Systems‖ E&C Department .newanglemedia.Hamken.com/products/silicon-devices/fpga/spartan-3. 5th edition [3] Smair Palnitkar. Morris Mano and Michael D. A guide to Digital Design and Synthesis.html [5] James O.INDUSTRIAL TRAINING REPORT REFERENCES [1] microchip.com/partner_matrix/ [2] M. Cilett. Verilog HDL. Michael D. Hall. Tyson S.NMAMIT Page 23 .Furman.