L6563 L6563A

Advanced transition-mode PFC controller
Features
■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■

Very precise adjustable output overvoltage protection Tracking boost function Protection against feedback loop failure (Latched shutdown) Interface for cascaded converter's PWM controller Input voltage feedforward (1/V2) Inductor saturation detection (L6563 only) Remote ON/OFF control Low (≤ 90µA) start-up current 5mA max. quiescent current 1.5% (@ TJ = 25°C) internal reference voltage -600/+800 mA totem pole gate driver with active pull-down during UVLO SO14 package Block diagram
INV 1
TRACKING BOOST

SO-14

Applications
PFC pre-regulators for:
■ ■ ■

HI-END AC-DC adapter/charger Desktop PC, server, WEB server IEC61000-3-2 OR JEIDA-MITI compliant SMPS, in excess of 350W

Table 1. Device summary
Part number L6563 L6563TR L6563A L6563ATR Package SO-14 SO-14 SO-14 SO-14 Packaging Tube Tape & Reel Tube Tape & Reel

Figure 1.

COMP 2

MULT 3 Ideal diode

VFF 5 1/V2

TBO

6

1:1 CURRENT MIRROR 1:1 BUFFER

2.5V + Voltage references Vbias
(INTERNAL SUPPLY BUS)

MULTIPLIER

LINE VOLTAGE FEEDFORWARD

3V

from VFF

VOLTAGE REGULATOR

1.7V + INDUCTOR SATURATION DETECTION ( not in L6563A )

LEADING-EDGE BLANKING

4 CS

+ Q VCC
SAT

VCC

14 R R1 UVLO COMPARATOR + R2 VREF2 UVLO S

Q

15 V 13 GD Driver

GND

12

11 ZCD 10 RUN 1.4V 0.7V -

ZERO CURRENT DETECTOR

Starter OFF STARTER + 0.2V 0.26V PFC_OK 7

DISABLE 0.52V 0.6V ON/OFF CONTROL (BROWNOUT DETECTION) +

LATCH

SAT

9 PWM_STOP

8 PWM_LATCH

March 2007

Rev 4

-

Vbias

FEEDBACK FAILURE PROTECTION

-

+

+ 2.5V

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Contents

L6563 - L6563A

Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 3 4 5 6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Feedback Failure Protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Voltage Feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Tracking Boost function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Inductor saturation detection (L6563 only) . . . . . . . . . . . . . . . . . . . . . . . . 27 Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . . 28 Summary of L6563/A idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7 8 9

Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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L6563 - L6563A

Description

1

Description
The device is a current-mode PFC controller operating in Transition Mode (TM). Based on the core of a standard TM PFC controller, it offers improved performance and additional functions. The highly linear multiplier, along with a special correction circuit that reduces crossover distortion of the mains current, allows wide-range-mains operation with an extremely low THD even over a large load range. The output voltage is controlled by means of a voltage-mode error amplifier and a precise (1.5% @TJ = 25°C) internal voltage reference. The stability of the loop and the transient response to sudden mains voltage changes are improved by the voltage feedforward function (1/V2 correction). Additionally, the IC provides the option for tracking boost operation (where the output voltage is changed tracking the mains voltage). The device features extremely low consumption (≤ 90 µA before start-up and ≤ 5 mA running). In addition to an effective two-step OVP that handles normal operation overvoltages, the IC provides also a protection against feedback loop failures or erroneous output voltage setting. In the L6563 a protection is added to stop the PFC stage in case the boost inductor saturates. This function is not included in the L6563A. This is the only difference between the two part numbers. An interface with the PWM controller of the DC-DC converter supplied by the PFC preregulator is provided: the purpose is to stop the operation of the converter in case of anomalous conditions for the PFC stage (feedback loop failure, boost inductor's core saturation) in the L6563 only and to disable the PFC stage in case of light load for the DCDC converter, so as to make it easier to comply with energy saving norms (Blue Angel, EnergyStar, Energy2000, etc.). The device includes disable functions suitable for remote ON/OFF control both in systems where the PFC pre-regulator works as a master and in those where it works as a slave. The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable to drive high current MOSFETs or IGBTs. This, combined with the other features and the possibility to operate with the proprietary Fixed-Off-Time control, makes the device an excellent low-cost solution for EN61000-3-2 compliant SMPS in excess of 350W. Figure 2. Typical system block diagram
PFC PRE-REGULATOR DC-DC CONVERTER

Vinac

Voutdc

PWM is turned off in case of PFC’s anomalous operation for safety

L6563 L6563A

PWM or Resonant CONTROLLER

PFC can be turned off at light load to ease compliance with energy saving regulations.

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1 Pin connection Figure 3. Pin connection (top view) INV COMP MULT CS VFF TBO PFC_OK 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Vcc GD GND ZCD RUN PWM_STOP PWM_LATCH 1. shuts down the IC. The pin normally features high impedance but. A compensation network is placed between this pin and INV (pin 1) to achieve stability of the voltage control loop and ensure high power factor and low THD. a DC level equal to the peak voltage at pin MULT (pin 3). compensates the control loop gain dependence on the mains voltage.7V detects abnormal currents (e. reduces its consumption almost to the start-up level and asserts PWM_LATCH (pin 8) high. The current flowing in the MOSFET is sensed through a resistor. This pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. A capacitor and a parallel resistor must be connected from the pin to GND. The voltage at this pin.g.2 Pin description Table 2.L6563A 1. an internal current generator programmed by TBO (pin 6) is activated. due to boost inductor saturation) and. Pin description Pin N° Name Description Inverting input of the error amplifier. It sinks current from the pin to change the output voltage so that it tracks the mains voltage. Never connect the pin directly to GND.Description L6563 . 1 INV 2 COMP 3 MULT 4 CS 5 VFF 4/39 . A second comparison level at 1. They complete the internal peak-holding circuit that derives the information on the RMS mains voltage. This function is not present in the L6563A. Main input to the multiplier. Output of the error amplifier. The information on the output voltage of the PFC preregulator is fed into the pin through a resistor divider. Second input to the multiplier for 1/V2 function. if the tracking boost function is used. The voltage on this pin is used also to derive the information on the RMS mains voltage. Input to the PWM comparator. on this occurrence. the resulting voltage is applied to this pin and compared with an internal reference to determine MOSFET’s turn-off.

the output voltage is changed proportionally to the mains voltage (tracking boost). 7 PFC_OK 8 Output pin for fault signaling. the pin will be left floating. Ground. During normal operation this pin features high impedance. the pin will be left floating. Normally. The IC restarts as the voltage at the pin goes above 0. this pin is used to temporarily stop the operation of the DC-DC converter supplied by the PFC pre-regulator by disabling its PWM controller. Boost inductor’s demagnetization sensing input for transition-mode operation. A resistor connected between this pin and GND defines a current that is sunk from pin INV (pin 1).7V on CS (pin 4) of PWM_LATCH L6563 is detected the pin is asserted high.52V shuts down (not latched) the IC and brings its consumption to a considerably lower level.5V the IC is shut down. If these functions are not needed. A voltage below 0. Gate driver output. If not used. The totem pole output stage is able to drive power MOSFET’s and IGBT’s with a peak current of 600 mA source and 800 mA sink. PWM_STOP is asserted low. Normally. Supply Voltage of both the signal part of the IC and the gate driver. This function is used for protection in case the feedback loop fails. PWM_LATCH pin is asserted high.5V at PFC_OK (pin 7) or a voltage above 1. This pin provides a buffered VFF voltage. If either a voltage above 2.26V. In this way.2V the IC is shut down and its consumption is considerably reduced. If not used.L6563 .6V.5V on RUN (pin 10) the voltage at the pin is pulled PWM_STOP to ground. If the voltage at the pin exceeds 2. During normal operation this pin features high impedance. tie to INV (pin 1) if the function is not used.L6563A Table 2. Current return for both the signal part of the IC and the gate driver.5 V. this pin is used to stop the operation of the DC-DC converter supplied by the PFC pre-regulator by invoking a latched disable of its PWM controller. tie the pin to a voltage between 0. Remote ON/OFF control.26 and 2. Output pin for fault signaling. Connect this pin to VFF (pin 5) either directly or through a resistor divider to use this function as brownout (AC mains undervoltage) protection. Normal operation can be resumed only by cycling the Vcc. If the IC is disabled by a voltage below 0. its consumption goes almost to the start-up level and this condition is latched. This pin senses the output voltage of the PFC pre-regulator through a resistor divider and is used for protection purposes. Pin description (continued) Pin N° Name Description Description 6 TBO Tracking Boost function. A negativegoing edge triggers MOSFET’s turn-on. 9 10 RUN 11 12 13 14 ZCD GND GD VCC 5/39 . The high-level voltage of this pin is clamped at about 12V to avoid excessive gate voltages. If the voltage on this pin is brought below 0. If this function is not used leave this pin open. To restart the IC the voltage on the pin must go above 0. PFC pre-regulator output voltage monitoring/disable function.

4 to 6. sink current Zero current detector max.3 to 8 Self-limited 3 -10 (source) 10 (sink) 0. 3. Absolute maximum ratings Symbol VCC ----IPWM_STOP IZCD PTOT TJ TSTG Pin 14 Parameter IC supply voltage (Icc = 20mA) Value self-limited -0. 7 10 9 Max.Absolute maximum ratings L6563 .75 -25 to 150 -55 to 150 Unit V V V mA mA W °C °C 2. Thermal data Symbol RthJA Parameter Maximum thermal resistance junction-ambient Value 120 Unit °C/W 6/39 .L6563A 2 Absolute maximum ratings Table 3. pin voltage (Ipin = 1 mA) Max. 8 Analog inputs & outputs to 10 1. current Power dissipation @TA = 50°C Junction temperature operating range Storage temperature 3 Thermal data Table 4.

2 2. VVFF = VMULT VMULT = 0 to 3 V 0 to 3 9 2.3 V < Vcc < 22 V (2) Vcc = 10. VCC = 12V.5 2.3 11 8.44 2 -0.3 2.8V VCOMP = Upper clamp VMULT = 1 V.3 22 25 12 9.56 5 -1 mV µA 7/39 .L6563A Electrical characteristics 4 Electrical characteristics Table 5.7 2. slope IMULT = 1 mA VMULT=0 to 0. VINV = 0 to 4 V 2.34 -0.5V.2 9. VFF=0.8 180 1.45 0.7 28 V V V V V Supply current Istart-up Iq ICC Start-up current Quiescent current Before turn-on. Electrical characteristics ( -25°C < TJ < +125°C.535 V 2. Vcc = 10V After turn-on 50 3 3.375 0.5 2 90 5 5. CFF =1µF between pin VFF and GND.465 2.5 2.2 -1 µA V V V/V Gain (3) 0. unless otherwise specified) Symbol Supply voltage Vcc VccOn VccOff Hys VZ Operating range Turn-on threshold Turn-off threshold Hysteresis Zener Voltage Icc = 20 mA After turn-on (1) (1) Parameter Test condition Min Typ Max Unit 10.5 250 2. Co = 1nF between pin GD and GND.2 3 µA mA mA µA mA mA Operating supply current @ 70kHz Latched by PFC_OK > Vthl or Vcs > VCSdis Disabled by PFC_OK < Vth or RUN < VDIS During static/dynamic OVP Iqdis Idle state quiescent Current Iq Quiescent current Multiplier input IMULT VMULT VCLAMP ∆V cs -------------------∆V MULT KM Input bias current Linear operation range Internal clamp level Output max.L6563 .525 V Error amplifier VINV Voltage feedback input threshold Line regulation IINV Input bias current TJ = 25 °C 10.5 22 13 10. VCOMP= 4 V.3 V to 22V TBO open.

7 2.3 V 8/39 . VVFF = 3V VMULT = 3V.5 4.0 1.5 mA (2) -2 2.5 80 1 VCOMP = 4V.5 3 20 V mV (4) (2) 17 20 15 23 µA µA 2 2. Electrical characteristics (continued) ( -25°C < TJ < +125°C. unless otherwise specified) Symbol Parameter IINV = 1 mA Open loop Test condition Min 9 60 Typ 9.2 2. Co = 1nF between pin GD and GND.7 1.16 V Vcsoffset VCSdis mV 5 1.8 V Output overvoltage IOVP Hys Dynamic OVP triggering current Hysteresis Static OVP threshold Voltage feedforward VVFF ∆V Linear operation range Dropout VMULTpk-VVFF RFF = 47 kΩ to GND 0.4 -5 Max Unit V dB MHz mA mA V V VINVCLAMP Internal clamp level Gv GB ICOMP Voltage gain Gain-bandwidth product Source current Sink current Upper clamp voltage VCOMP Lower clamp voltage Current sense comparator ICS tLEB td(H-L) VCSclamp Input bias current Leading edge blanking Delay to output Current sense reference clamp Current sense offset Ic latch-off level (L6563 only) VCOMP = Upper clamp.6 V ISOURCE = 0. VVFF = VMULT =0.1 -3.Electrical characteristics L6563 .L6563A Table 5.7 2.5V VMULT = 0.4 V VCOMP = 4V.08 25 -1 300 µA ns ns 1. VINV = 2.6 1.15 2.5 6.5 mA ISINK = 0.5 5.25 6. VCC = 12V. VINV = 2. CFF =1µF between pin VFF and GND. VVFF = 3V (2) VCS = 0 100 200 120 1.

5 mA IZCD = .6 V V V µA V ITBO = 25 µA to 0. CFF =1µF between pin VFF and GND.25 mA 0 -3.3 5.VTBO Linear operation IINV .L6563A Electrical characteristics Table 5.1 mV mA % V PWM_LATCH Ileak VH Low level leakage current High level VPWM_LATCH=0 IPWM_LATCH = -0.5 2.5V IPFC_OK = 1 mA 9 2.7 1 0.2 0.25 3. Co = 1nF between pin GD and GND.5 -1 2.5 1 1 µA V V 9/39 .4 0.2.7 -1 µA V PWM_STOP Ileak VL Vclamp High level leakage current Low level Clamp voltage VPWM_STOP = 6V IPWM_STOP = 0.7 0 1. VCC = 12V.L6563 . unless otherwise specified) Symbol Parameter Test condition Min Typ Max Unit Zero current detector VZCDH VZCDL VZCDA VZCDT IZCDb IZCDsrc IZCDsnk Upper clamp voltage Lower clamp voltage Arming voltage (positive-going edge) Triggering voltage (negative-going edge) Input bias current Source current capability Sink current capability IZCD = 2.5 2.3 V V V V µA mA mA (4) VZCD = 1 to 4.5 mA (4) 5.4 2. Electrical characteristics (continued) ( -25°C < TJ < +125°C.25 mA VVFF = 4V (2) ITBO = 0.9 3 20 0.5 mA IPFC_OK = 2 mA 9 9.5 Tracking boost function ∆V ITBO Dropout voltage VVFF .0 -0.5 3.ITBO current mismatch VTBOclamp Clamp voltage PFC_OK Vthl Vth VEN IPFC_OK Vclamp Latch-off threshold Disable threshold Enable threshold Input bias current Clamp voltage Voltage rising (2) Voltage falling (2) Voltage rising (2) VPFC_OK = 0 to 2.1 9.26 -0.5 0.5 V -2.5 mA 3.

VCC = 12V.5 1 30 40 12 2. (2) Parameters tracking each other (3) The multiplier output is given by: V MULT ⋅ ( V COMP – 2.6 -1 0. CFF =1µF between pin VFF and GND.56 0. 10/39 .Electrical characteristics L6563 . functionality tested in production.52 0. Co = 1nF between pin GD and GND. Vcc = 20V Vcc=0 to VccOn.54 0.6 3 2 70 80 15 1.5 ) V CS = K M ⋅ -----------------------------------------------------------2 V VFF (4) Parameters guaranteed by design.64 µA V V Parameter Test condition Min Typ Max Unit (1). Isink=10mA 10 Dropout voltage IGDsource = 20 mA IGDsource = 200 mA IGDsink = 200 mA 2 2. Electrical characteristics (continued) ( -25°C < TJ < +125°C.1 V V V ns ns V V Start timer period 75 150 300 µs Input bias current Disable threshold Enable threshold VRUN = 0 to 3 V Voltage falling (2) Voltage rising (2) 0. unless otherwise specified) Symbol Run function IRUN VDIS VEN Start timer tSTART Gate driver VOHdrop VOLdrop tf tr VOclamp Current fall time Current rise time Output clamp voltage UVLO saturation IGDsource = 5mA.L6563A Table 5.5 0.

5 0.02 -50 0 50 100 150 2.5 0.1 0. VCC Zener voltage vs TJ Vccz (pin 14) (V) 28 27 26 25 24 Co = 1nF f = 70 kHz Tj = 25°C 23 22 -50 5 10 15 Vcc(V) 20 25 0 50 Tj (°C) 100 150 Figure 6.L6563 .05 IC consumption vs TJ Figure 7.5 (V) 4 3 2 Lower clamp 9 -50 0 50 Tj (°C) 100 150 1 -50 0 50 Tj (°C) 100 150 11/39 .5 2.01 0. (V) E/A output clamp levels vs TJ 12.05 0.L6563A Typical electrical performance 5 Figure 4.4 -50 0 50 Tj (°C) 100 150 Tj (°C) Figure 8.1 0.45 Before start-up 0.6 Operating Quiescent (mA) Vcc = 12 V 2.005 0 0 Typical electrical performance Supply current vs supply voltage Figure 5.5 10 VCC-OFF 9. Feedback reference vs TJ VREF (pin 1) (V) 2.5 5 11 10.55 Vcc = 12 V Co = 1 nF f = 70 kHz Disabled or during OVP Latched off 2. Icc 10 5 2 1 0.2 0. Start-up & UVLO vs TJ Figure 9. Icc (mA) 10 5 1 0.5 VCC-ON (V) 12 VCOMP (pin 2) 7 6 Upper clamp Vcc = 12 V 11.

2 2.2 1.4 Vcc = 12 V 1.1 1.884 2.0 Vcc = 12 V 300 (V) Vcc = 12 V 250 1.L6563A Figure 11.5 2. Current-sense offset vs mains voltage phase angle VCSoffset (pin 4) 120% Vcc = 12 V (mV) 30 Vcc = 12 V Tj = 25 ° 110% 25 20 VMULT = 0 to 3V VFF = 3V 100% 15 10 VMULT = 0 to 0. Delay-to-output vs TJ tD(H-L) (ns) Figure 15. Static OVP level vs TJ VCOMP (pin 2) (V) L6563 .7V VFF = 0. Dynamic OVP current vs TJ (normalized value) IOVP Figure 13.8 200 1.7V 90% 5 80% -50 0 50 Tj (°C) 100 150 0 0 0.14 θ (°) Figure 14.0 -50 0 50 Tj (°C) 100 150 12/39 .3 2.4 2. Ic latch-off level on current sense vs TJ (L6563 only) Vpin4 2.4 100 1. Vcs clamp vs TJ VCSx (pin 4) (V) 1.Typical electrical performance Figure 10.6 150 1.2 50 -50 0 50 Tj (°C) 100 150 1.628 1.512 3.1 2 -50 0 50 Tj (°C) 100 150 1 -50 0 50 Tj (°C) 100 150 Figure 12.5 Vcc = 12 V VCOMP = Upper clamp 2.3 1.256 1.

6 3.8 4.Vpin5 0.5 0.5 ZCDsrc (V) (mA) 0 Vcc = 12 V VZCD = lower clamp -2 5.0 4. Multiplier characteristics @ VFF = 1V Figure 17. Multiplier gain vs TJ KM Figure 21.0 (V) Vcc = 12 V Tj = 25 °C upper voltage clamp 5. ZCD source capability vs TJ V CS (pin 4) VCOMP (pin 2) Vcc = 12 V Tj = 25 °C upper voltage clamp 5.4 0.5 mA 0.0 2 1 0 Lower clamp 2.5 0.3 0.5 7 6 5 4 3 Upper clamp Vcc = 12 V IZCD = ±2.4 Vpin5 .5 5.0 4.6 2 0.L6563A Typical electrical performance Figure 16.1 0 3.5 -8 -50 0 50 Tj (°C) 100 150 VMULT (pin 3) (V) Figure 20.0 2.4 0.5 I (V) 0.8 1 1.2 -1 -50 0 50 Tj (°C) 100 150 VMULT (pin 3) (V) Figure 18. Multiplier characteristics @ VFF = 3V Figure 19.2 3.5 4.Vpin3 Vcc = 12 V Vpin3 = 2.5 2 2.0 -4 -6 0.9 V 0 0.6 0 0. ZCD clamp levels vs TJ VCS (pin 4) VCOMP (pin 2) VZCD (pin 11) (V) (V) 1 0.L6563 .6 0 0.2 0 3.6 0.5 3 3.2 0 -50 0 50 Tj (°C) 100 150 -2 -50 0 50 Tj (°C) 100 150 13/39 .4 0.8 4 0.5 1 1. VFF & TBO dropouts vs TJ (mV) 6 1 Vcc = 12 V VCOMP =4 V VMULT = V FF =1V Vpin6 .2 0.

5 mA 3.2 -2.25 Vcc = 12 V Isink = 0.7 -1.2 -2. TBO current mismatch vs TJ 100· I(INV)-I(TBO) I(INV) L6563 .1 -2.0 -50 2.5 (V) Figure 27.0 -2.Typical electrical performance Figure 22.30 3 2. PWM_STOP low saturation vs TJ Vpin9 5.0 0.0 Vcc = 12 V -0.8 -1.L6563A Figure 23.1 Vcc = 12 V Isource = 50 µA 5.6 -1.0 0.5 -50 0 50 Tj (°C) Isource = 500 µA 400 500 600 100 150 Figure 26.4 -1.0 -50 0 50 Tj (°C) 100 150 Figure 24.2 -2.3 (V) -1.0 0. RUN thresholds vs TJ Vpin10 (V) Vcc = 12 V 1.9 4.8 4.8 -2.5 -50 0 50 Tj (°C) 100 150 0 50 Tj (°C) 100 150 14/39 .0 0.7 4.8 -1.40 4.2 -1.4 ITBO = 250 µA 0.4 -50 0 50 Tj (°C) 100 150 0.9 -2.10 0 0.2 5.20 2. TBO-INV current mismatch vs TBO currents 100· I(INV)-I(TBO) I(INV) Figure 25.0 -1.0 3.50 (V) 0.75 Vcc = 12 V Vpin3= 4 V 1. PWM_LATCH high saturation vs TJ Vpin8 5.0 4.8 ON OFF 0.3 0 100 200 300 I(TBO) Vcc = 12 V Tj = 25 °C 5.6 -1.6 4.0 ITBO = 25 µA 0. TBO clamp vs TJ Vpin6 3.6 0.

L6563 .000 IGD(mA) Figure 32.8 0. Gate-drive output low saturation Vpin15 (V) 4 Tj = 25 °C Vcc = 11 V SINK 140 3 130 2 120 110 1 100 -50 0 50 Tj (°C) 100 150 0 0 200 400 600 800 1. PFC_OK thresholds vs TJ Vpin7 (V) 3. UVLO saturation vs TJ Vpin15 (V) 1.6 0.9 0.4.5 Tj = 25 °C Vcc = 11 V SOURCE 11.5 2.5 3. Start-up timer vs TJ Tstart 150 (µs) Vcc = 12 V Figure 31.5 10.0 -4. Gate-drive output high saturation Vpin15 (V) -1.5 0.0 Vcc --2.0 0.3 0.5 -4 Vcc . Gate-drive clamp vs TJ Vpin15clamp (V) 12 Vcc = 20 V Figure 33.0 Vcc --3.1 -50 0 50 Tj (°C) 100 150 0 50 Tj (°C) 100 150 Figure 30.0 Latch-off Vcc = 12 V Typical electrical performance Figure 29.5 11 -3 Vcc .1 Vcc = 0 V 1 0.3.5 10 -50 0 100 200 300 400 500 600 700 0 50 Tj (°C) 100 150 IGD (mA) 15/39 .2 OFF ON 0.5 -2 Vcc .2.0 2.L6563A Figure 28.5 -50 1.7 0.

and the external power transistor is switched off until the current falls approximately below 5 µA. the voltage at pin INV will be 2.5V by the local feedback of the error amplifier.5 + ∆V O I' R1 = --------------------------------------R1 The difference current ∆IR1 = I’R1 . the error amplifier will eventually saturate low hence triggering an internal comparator (Static OVP) that will keep the external power switch turned off until the output voltage comes back close to the regulated value. However. Neglecting the ripple components.= --------------------R1 R2 If the output voltage experiences an abrupt change ∆Vo the voltage at pin INV is kept at 2.5 ------.5V. in case the load is completely disconnected).Application information L6563 .5V as well. set by the ratio of the resistors R1 and R2 of the output divider. Considering that the non-inverting input of the error amplifier is internally biased at 2. This current is monitored inside the IC and when it reaches about 18 µA the output voltage of the multiplier is forced to decrease. The output overvoltage that is able to trigger the OVP function is then: Equation 3 ∆VO = R1 · 20 · 10-6 16/39 . under steady state conditions the current through R1 equals that through R2. the voltage control loop keeps the output voltage VO of the PFC pre-regulator close to its nominal value. a network connected between pins INV and COMP that introduces a long time constant.I’R1 = ∆VO/R1 will flow through the compensation network and enter the error amplifier (pin COMP). If the current exceeds 20 µA. if the overvoltage persists (e. thus reducing the energy drawn from the mains.g. the OVP is triggered (Dynamic OVP). Then the current through R2 remains equal to 2.5/R2 but that through R1 becomes: Equation 2 V O – 2.5 I R2 = I R1 = 2.1 Application information Overvoltage protection Normally.L6563A 6 6. then: Equation 1 V O – 2.

Since it is usually much smaller than Vo. R2 = 2.L6563 .15 = 6 V. OVP and FFP functions: internal block diagram Vout R3 { R3a R1 R3b { R1a 0. which means 15% tolerance on the ∆VO.36%. Example: VO = 400V. Output voltage setting.5·2MΩ·/(400-2. When either OVP is activated the quiescent consumption is reduced to minimize the discharge of the Vcc capacitor. Figure 34. Then: R1 = 40V/20µA = 2MΩ . The tolerance on the OVP level due to the L6563/A will be 40·0. Another advantage is the precision: the tolerance of the detection current is 15%. ∆VO = 40V.25V INV 1 9.58kΩ.5V - FAULT (latched) 2. that is ± 1. the former on the individual value of R1.5V + E/A - Static OVP + Dynamic OVP TBO FUNCTION 20 µA 2 COMP L6563 L6563A Frequency Compensation R4 R2 17/39 .26V + - FAULT (not latched) R1b PFC_OK 7 + 9. the tolerance on the absolute value will be proportionally reduced.5V ITBO 2.5) = 12.L6563A Application information An important advantage of this technique is that the overvoltage level can be set independently of the regulated output voltage: the latter depends on the ratio of R1 to R2.

usually larger than the maximum Vo that can be expected. reducing its consumption below 1 mA. This limit is considered when selecting the sense resistor to let the full load power pass under minimum line voltage conditions. It consists of deriving a voltage proportional to the input RMS voltage. For example. setting the gain of the error amplifier to get fc = 20 Hz @ 264 Vac means having fc ≅ 4 Hz @ 88 Vac. with some margin. Additionally.5/(475-2. so that the Vcc voltages of both the L6563/A and the PWM controller go below their respective UVLO thresholds. It cannot handle the overvoltage generated. i. When this function is triggered. Note that this function offers a complete protection against not only feedback loop failures or erroneous settings. feeding this voltage into a squarer/divider circuit (1/V2 corrector) and providing the resulting signal to the multiplier that generates the current reference for the inner current control loop (see Figure 35). resulting in a sluggish control dynamics. So does the crossover frequency fc of the overall open-loop gain because the gain has a single pole characteristic. 18/39 . intended for tripping a latched shutdown function of the PWM controller IC in the cascaded DC-DC converter. the slow control loop causes large transient current flow during rapid line or load changes that are limited by the dynamics of the multiplier output.87kΩ.2 Feedback Failure Protection (FFP) The OVP function above described is able to handle "normal" overvoltage conditions.3 Voltage Feedforward The power stage gain of PFC pre-regulators varies with the square of the RMS input voltage. At the same time the pin PWM_LATCH is asserted high. see Figure 34).5 mA load. PWM_LATCH is an open source output able to deliver 3.26 V. those resulting from an abrupt load/line change or occurring at start-up. its quiescent consumption is reduced below 250 µA and the condition is latched as long as the supply voltage of the IC is above the UVLO threshold. the gate drive activity is immediately stopped. R4 low. when the upper resistor of the output divider (R1) fails open: the voltage loop can no longer read the information on the output voltage and will force the PFC pre-regulator to work at maximum ON-time. with 0. for instance.L6563A 6. Either resistor of the PFC_OK divider failing short or open or a PFC_OK pin floating will result in shutting down the IC and stopping the pre-regulator. so that the entire unit is latched off. To restart the system it is necessary to recycle the input power. But a fixed current limit allows excessive power input at high line. causing the output voltage to rise with no control.5V if the output voltage exceeds a preset value. Example: VO = 400 V. Voltage Feedforward can compensate for the gain variation with the line voltage and allow overcoming all of the above-mentioned issues.2V will shut down the IC. then: R4 = 3MΩ ·2. Select: R3 = 3MΩ.7V min. This leads to large trade-offs in the design.e. also including worst-case load/line transients. but also against a failure of the protection itself. In this case both PWM_STOP and PWM_LATCH keep their high impedance status. A pin of the device (PFC_OK) has been dedicated to provide an additional monitoring of the output voltage with a separate resistor divider (R3 high. The PFC_OK pin doubles its function as a not-latched IC disable: a voltage below 0. This divider is selected so that the voltage at the pin reaches 2. whereas a fixed power limit requires the current limit to vary inversely with the line voltage. Vox = 475V. To restart the IC simply let the voltage at the pin go above 0.Application information L6563 . 6. the device is shut down.5) = 15.

Actually. complete an internal peak-holding circuit that provides a DC voltage equal to the peak of the rectified sine wave applied on pin MULT (pin 3). which can be in the hundred ms to achieve an acceptably low steady-state ripple and have low current distortion. which has its own time constant. A capacitor CFF and a resistor RFF . deriving a voltage proportional to the RMS line voltage implies a form of integration. resulting in excessive overshoot and undershoot of the pre-regulator's output voltage in response to large line voltage changes. the loop gain will be constant throughout the input voltage range.L6563 .L6563A Application information Figure 35. The device realizes Voltage Feedforward with a technique that makes use of just two external parts and that limits the feedforward time constant trade-off issue to only one direction. like in systems with no feedforward compensation.5 1 2 VFF=VMULT 3 4 In this way a change of the line voltage will cause an inversely proportional change of the half sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of the multiplier output will be halved and vice versa) so that the current reference is adapted to the new operating conditions with (ideally) no need for invoking the slow dynamics of the error amplifier. In this way. in case of sudden line voltage rise. Clearly a trade-off is required. If it is too small the voltage generated will be affected by a considerable amount of ripple at twice the mains frequency that will cause distortion of the current reference (resulting in high THD and poor PF). consequently the output voltage can experience a considerable undershoot. Voltage feedforward: squarer-divider (1/V2) block diagram and transfer characteristic Rectified mains current reference (Vcsx) E/A output (VCOMP) MULTIPLIER "ideal" diode 2 Vcsx 2 R5 1. which improves significantly dynamic behavior at low line and simplifies loop design.5V 5 0. 19/39 . Additionally.5 RFF 0 0 0.5 VCOMP=4V Actual Ideal + 1/V 3 MULT R6 1 L6563 L6563A VFF CFF 9. if it is too large there will be a considerable delay in setting the right amount of feedforward. CFF will be rapidly charged through the low impedance of the internal diode and no appreciable overshoot will be visible at the pre-regulator's output. both connected from the VFF (pin 5) pin to ground. in case of line voltage drop CFF will be discharged with the time constant RFF·CFF. RFF provides a means to discharge CFF when the line voltage decreases (see Figure 35).

The amount of 3rd harmonic distortion introduced by this ripple.1 f L= 60 Hz 0.Application information L6563 .5V. the IC will not work properly if the pin is either left floating or connected directly to ground. Figure 36.5V (see Figure 35). will be: Equation 5 100 D 3 % = --------------------------------2 π f L R FF C FF Figure 36 shows a diagram that helps choose the time constant RFF·CFF based on the amount of maximum desired 3rd harmonic distortion. related to the amplitude of its 2·fL component. is given by: Equation 4 2V MULTpk ∆V FF = --------------------------------------1 + 4f L R FF C FF where fL is the line frequency. This helps to prevent excessive power flow when the line voltage is lower than the minimum specified value (brownout conditions).L6563A The twice-mains-frequency (2·fL) ripple appearing across CFF is triangular with a peak-topeak amplitude that.01 0. Always connect RFF and CFF to the pin. with good approximation.1 1 10 D3 % The dynamics of the voltage feedforward input is limited downwards at 0. that is the output of the multiplier will not increase any more if the voltage on the VFF pin is below 0. RFF·CFF as a function of 3rd harmonic distortion introduced in the input current 10 1 f L = 50 Hz R FF· C FF [s] 0. 20/39 .

In this way the THD (Total Harmonic Distortion) of the current is considerably reduced. To overcome this issue the device forces the PFC pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. This effect is magnified by the highfrequency filter capacitor placed after the bridge rectifier.L6563 .L6563A Application information 6. THD optimizer circuit t 2 t t 1/V VFF COMP MULTIPLIER MULT + + to PWM comparator t OFFSET GENERATOR t @ Vac1 @ Vac2 > Vac1 t 21/39 . This will result in both minimizing the time interval where energy transfer is lacking and fully discharging the high-frequency filter capacitor after the bridge. Figure 37 shows the internal block diagram of the THD optimizer circuit. A major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very low. Figure 37. which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop.4 THD optimizer circuit The L6563/A is provided with a special circuit that reduces the conduction dead-angle occurring to the AC input current near the zero-crossings of the line voltage (crossover distortion).

THD optimization: standard TM PFC controller (left side) and L6563/A (right side) Input current Input current Rectified mains voltage Rectified mains voltage Imains Input current MOSFET's drainVdrain voltage Input current MOSFET's drainVdrain voltage Imains Essentially. To take maximum benefit from the THD optimizer circuit.3 on page 18 section) so as to have little offset at low line. the high-frequency filter capacitor after the bridge rectifier should be minimized. so that it becomes negligible as the line voltage moves toward the top of the sinusoid. where the key waveforms of a standard TM PFC controller are compared to those of this chip. The effect of the circuit is shown in Figure 38. This offset is reduced as the instantaneous line voltage increases.Application information L6563 . the circuit artificially increases the ON-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings.L6563A Figure 38.thus reducing the effectiveness of the optimizer circuit. introduces a conduction dead-angle of the AC input current in itself even with an ideal energy transfer by the PFC pre-regulator . and a larger offset at high line where the energy transfer gets worse. in fact. Furthermore the offset is modulated by the voltage on the VFF pin (see Section 6. compatibly with EMI filtering needs. A large capacitance. where energy transfer at zero crossings is typically quite good. 22/39 .

the voltage at the TBO pin is clamped at 3V. 23/39 . that is internally 1:1 mirrored and sunk from pin INV (pin 1) input of the error amplifier. leave the pin open: the device will regulate a fixed output voltage. ∆Vo = OVP threshold. Vox = absolute maximum limit for the regulated output voltage. This is commonly referred to as "tracking boost" or "follower boost" approach.L6563A Application information 6. In this way. The resistor defines a current.L6563 . Vo2 = regulated output voltage @ Vin = Vin2. Starting from the following data: ● ● ● ● ● ● Vin1 = minimum specified input RMS voltage. To avoid undesired output voltage rise should the mains voltage exceed the maximum specified value. equal to V(TBO)/RT. The TBO pin presents a DC level equal to the peak of the MULT pin voltage and is then representative of the mains RMS voltage. the output voltage will move in the opposite direction if the input voltage decreases. when the mains voltage increases the voltage at TBO pin will increase as well and so will do the current flowing through the resistor connected between TBO and GND. By properly selecting the multiplier bias it is possible to set the maximum input voltage above which input-to-output tracking ends and the output voltage becomes constant.5 Tracking Boost function In some applications it may be advantageous to regulate the output voltage of the PFC preregulator so that it tracks the RMS input voltage rather than at a fixed value like in conventional boost pre-regulators. Then a larger current will be sunk by INV pin and the output voltage of the PFC preregulator will be forced to get higher. If this function is not used. With this IC the function can be realized by connecting a resistor (RT) between the TBO pin and ground. Vo1 = regulated output voltage @ Vin = Vin1. Obviously. Vin2 = maximum specified input RMS voltage.

the upper resistor of the output divider: Equation 8 6 ∆Vo . Determine the input RMS voltage Vinclamp that produces Vo = Vox: Equation 6 Vox – Vo 1 Vox – Vo 2 .⋅ 10 R1 = ---------20 4.Application information L6563 . Determine R1.5 ) ⋅ Vin 2 – ( Vo 2 – 2.5 ) ⋅ Vin 1 RT = Vin 2 – Vin 1 2 ⋅ k ⋅ R1 ⋅ ----------------------------Vo 2 – Vo 1 24/39 .65V. Calculate the lower resistor R2 of the output divider and the adjustment resistor RT: Equation 9 Vin 2 – Vin 1 R2 = 2.5 ⋅ R1 ⋅ -------------------------------------------------------------------------------------------------( Vo 1 – 2.⋅ Vin 1 Vin clamp = -------------------------Vo 2 – Vo 1 Vo 2 – Vo 1 and choose a value Vinx such that Vin2 = Vinx < Vinclamp. Determine the divider ratio of the MULT pin (pin 3) bias: Equation 7 3 k = ----------------------2 ⋅ Vin x and check that at minimum mains voltage Vin1 the peak voltage on pin 3 is greater than 0.L6563A to set the output voltage at the desired values use the following design procedure: 1. This will result in a limitation of the output voltage range below Vox (it will equal Vox if one chooses Vinx = Vinclamp) 2.⋅ Vin 2 – -------------------------. 3.

= 40V Vo1:= 200V Vo2:= 385V Step 1 Vox – Vo 1 Vox – Vo 2 . Figure 41 shows the internal block diagram of the tracking boost function.= 400V ∆Vo . Design data Vin1 := 88V Vin2 := 264V Vox .27V choose: Vinx: = 270V Step 2 3 k: = ----------------------2 ⋅ Vin x k = 7.L6563A Application information 5. Check that the maximum current sourced by the TBO pin (pin 6) does not exceed the maximum specified (0. as an example.L6563 .⋅ Vin 2 – -------------------------.25mA): Equation 10 3–3 I TBOmax = -----≤ 0.⋅ 10 6 R1: = ---------20 R1 = 2 x 106 Ω 25/39 .25 ⋅ 10 RT In the following Mathcad® sheet. the calculation is shown for the circuit illustrated in Figure 40.⋅ Vin 1 Vin clamp : = -------------------------Vo 2 – Vo 1 Vo 2 – Vo 1 Vinclamp = 278.857 x 10-3 Step 3 ∆Vo .

142 mA Vo(Vi): = V MULTpk ← k ⋅ 2 ⋅ Vi V TBO ← if ( V MULTpk < 3.⋅ 10 3 I TBOmax : = -----RT ITBOmax = 0.V MULTpk . Output voltage vs.L6563A Step 4 Vin 2 – Vin 1 R2: = 2.5 ⋅ ⎛ 1 + R1 -------⎞ + V TBO ⋅ ------⎝ RT R2⎠ Vo(Vin1) = 200V Vo(Vin2) = 385V Vo(VinX) = 391.762 x 104 Ω Vin 2 – Vin 1 R T : = k ⋅ 2 ⋅ R1 ⋅ ----------------------------Vo 2 – Vo 1 RT = 2.307V Figure 39.5 ⋅ R1 ⋅ -------------------------------------------------------------------------------------------------( Vo 1 – 2.Application information L6563 .3 ) R1 2.5 ) ⋅ Vin 1 R2 = 4.5 ) ⋅ Vin 2 – ( Vo 2 – 2. input voltage characteristic with TBO 400 Vin 2 Vin x 350 Vo 2 Vo ( Vin ) 300 250 200 100 150 200 Vin 250 300 26/39 .114 x 104 Ω Step 5 3 .

This happens when the restart occurs at an unfavorable line voltage phase.L6563A Application information Figure 40. even a well-designed boost inductor may occasionally slightly saturate when the PFC stage is restarted because of a larger load demand.3 MΩ Vo=200 to 385 V Po=80W NTC C6 100 nF MOS STP8NM50 FUSE 4A/250V + BRIDGE 4 x 1N4007 C1 0. see Figure 42) that during the current sense propagation delay the current may reach abnormally high values.2nF C3 22m F C4 25V 470 nF R10 390 kΩ R4 21 kΩ C7 10 nF R7a. in the 27/39 .3 MΩ - 8 14 3 12 9 11 2 1 13 4 R6 10 Ω Vac (88V to 264V) L6563 5 10 6 7 C6 56 µF 400V R2 51. The voltage drop caused by this abnormal current on the sense resistor reduces the gate-to-source voltage.22 µF 400V R1b 3.6 Inductor saturation detection (L6563 only) Boost inductor's hard saturation may be a fatal event for a PFC pre-regulator: the current upslope becomes so large (50-100 times steeper. so that the output voltage may drop significantly below the rectified peak voltage.L6563 .5V ITBO IR2 R2 1:1 CURRENT MIRROR 3V + + - Rectified mains current reference MULTIPLIER E/A 1/V 2 "ideal" diode R5 3 MULT R6 L6563 L6563A ITBO 9.3 MΩ R3 68 kΩ R5 62 kΩ C5 1 µF R8a 1 MΩ R8b 1 MΩ R10a 3.3 to 22V R1a 3.5 kΩ R11 34. 80W.3 MΩ R10b 3. so that the MOSFET may work in the active region and dissipate a huge amount of power.5V INV 1 9. Tracking boost and voltage feedforward blocks Vout IR1 COMP 2 R1 2.5V 6 TBO RT VFF CFF 5 RFF 6.1 kΩ C2 2. As a result.b 0. wide-range-mains PFC pre-regulator with tracking boost function active D1 STTH1L06 T Supply Voltage 10. However.68 Ω 1/4 W R9 47. where the PFC pre-regulator is turned off at light load for energy saving reasons. in some applications such as ac-dc adapters.8 kΩ Figure 41. which leads to a catastrophic failure after few switching cycles.

Figure 42. The functions realized by the housekeeping circuitry ensure that transient conditions like power-up or power down sequencing or failures of either power stage be properly handled. with the aim of latching off the PWM controller of the cascaded DC-DC converter as well (Section 6. System safety will be considerably increased. A second communication line can be established via the disable function included in the PFC_OK pin (Section 6. there is little or no voltage available for demagnetization. Interface circuits like those shown in Figure 43. the L6563 is provided with a second comparator on the current sense pin (CS. in other words. which is normally open when the PFC works properly and goes high if it loses control of the output voltage (because of a failure of the control loop) or if the boost inductor saturates.2 on page 18 for more details ).1V. that is when the Vcc voltages of the L6563 and the PWM controller go below their respective UVLO thresholds.Application information L6563 .7 Power management/housekeeping functions A special feature of this IC is that it facilitates the implementation of the "housekeeping" circuitry needed to coordinate the operation of the PFC stage to that of the cascaded DCDC converter.L6563A boost inductor the inrush current coming from the bridge rectifier adds up to the switched current and. Also the cascaded DC-DC converter can be stopped via the PWM_LATCH pin that is asserted high. exceeds 1. Effect of boost inductor saturation on the MOSFET current and detection method 6. pin 4) that stops and latches off the IC if the voltage. it is also possible to cut down the supply voltage.7V. As already mentioned. furthermore. it powers both controllers and enables/disables the operation of the PFC stage. that the DC-DC stage starts first. To cope with a saturated inductor. the L6563A does not support this protection function. In this way the entire system is stopped and enabled to restart only after recycling the input power. PWM controller with standby function. can be used. This device provides some pins to do that. where the L6563/A works along with the L5991. 28/39 .2: Feedback Failure Protection (FFP) on page 18 for more details). To better suit the applications where a certain level of saturation of the boost inductor needs to be tolerated. normally limited within 1. to minimize the no-load input consumption. Needless to say. this operation assumes that the cascaded DC-DC converter stage works as the master and the PFC stage as the slave or. Should the residual consumption of the chip be an issue. one communication line between the IC and the PWM controller of the cascaded DC-DC converter is the PWM_LATCH pin. Typically this line is used to allow the PWM controller of the cascaded DC-DC converter to shut down the L6563/A in case of light load.

to its soft-start pin (Figure 44 b).g. It is important to point out that this function works correctly in systems where the PFC stage is the master and the cascaded DC-DC converter is the slave or. the pin RUN can be used to start and stop the main converter. An underlying assumption in order for that to work properly is that the UVLO thresholds of the PWM controller are certainly higher than those of the L6563/A. Interface circuits that let DC-DC converter’s controller IC disable the L6563/A at light load 16 ST-BY 16 ST-BY L5991/A 4 Vref 27 kΩ BC557 100 kΩ 150 kΩ L6563 7 PFC_OK L5991/A 4 Vref 27 kΩ BC557 100 kΩ 150 kΩ 150 kΩ Vcc L6563 14 BC557 Supply_Bus 100 nF 47 kΩ BC547 BC547 100 nF 100 nF 15 kΩ BC547 150 kΩ BC557 100 kΩ 10 kΩ Vcc 16 8. This function is quite flexible and can be used in different ways. where the PFC stage starts first.L6563A Application information Figure 43. desktop PC's silver box or hi-end LCD-TV). In systems comprising an auxiliary converter and a main converter (e.2 V 2.52V on the RUN pin. powers both controllers and enables/disables the operation of the DC-DC stage. which works in conjunction with the RUN pin (pin 10). The use of the soft-start pin allows the designer to delay the start-up of the DC-DC stage with respect to that of the PFC stage.2 kΩ 14 PFC_STOP Vcc 14 VREF 8 PFC_OK 7 L6563 L6563A (RUN) (10) L6668 L6563 L6563A L6668 2. that goes low if the device is disabled by a voltage lower than 0. if the chip is provided with it. The purpose of the PWM_STOP pin is to inhibit the PWM activity of both the PFC stage and the cascaded DC-DC converter. The pin is an open collector. 29/39 .L6563 . to enable/disable the PWM controller the PWM_STOP pin can be connected to either the output of the error amplifier (Figure 44 a) or.2 kΩ BC547 14 PFC_STOP 14 PFC_STOP PFC_OK (RUN) 7 (10) L6599 L6563 L6563A The third communication line is the PWM_STOP pin (pin 9). which is often desired. normally open. In the simplest case. where the auxiliary converter also powers the controllers of the main converter. in other words.

This condition may cause overheating of the primary power section due to an excess of RMS current. should the input voltage return abruptly to its rated value. thanks to the hysteresis provided.L6563A Figure 44. Brownout can also cause the PFC pre-regulator to work open loop and this could be dangerous to the PFC stage itself and the downstream converter. Another problem is the spurious restarts that may occur during converter power down and that cause the output voltage of the converter not to decay to zero monotonically. in systems where the PFC stage is the master) is brownout protection. the arrangement of Figure 45 lets the DC-DC converter start-up when the voltage generated by the PFC stage reaches a preset value. Interface circuits for actual power-up sequencing (master PFC) Another possible use of the RUN and PWM_STOP pins (again. 30/39 .Application information L6563 . the PWM controller is devoid of soft start. For these reasons it is usually preferable to shutdown the unit in case of brownout. Figure 45. The technique relies on the UVLO thresholds of the PWM controller. Interface circuits that let the L6563/A switch on or off a PWM controller If this is not the case or it is not possible to achieve a start-up delay long enough (because this prevents the DC-DC stage from starting up correctly) or. simply. Brownout protection is basically a not-latched device shutdown function that must be activated when a condition of mains undervoltage is detected.

Figure 46. Summary of L6563/A idle states Condition UVLO Feedback disconnected Saturated Boost Inductor AC Brownout Standby Caused or revealed by Vcc < 8.7 V PFC_OK > 2. Brownout protection (master PFC) AC mains L6563 L6563A 5 RUN 10 RUN 10 VFF L6563 L6563A RFF CFF 6.8 Summary of L6563/A idle states .5 mA IC behavior Auto-restart Latched Latched (L6563 only) Auto-restart Auto-restart 31/39 . the one on the right can be used if the bias levels of the multiplier and the RFF·CFF time constant are compatible with the specified brownout level and with the specified holdup time respectively.L6563A Application information IC shutdown upon brownout can be easily realized as shown in Figure 46 The scheme on the left is of general use.5 mA 1.7 V (L6563 only) RUN < 0.52 V PFC_OK < 0.5 V Vcs > 1.L6563 . Table 6. In Table 6 it is possible to find a summary of all of the above mentioned working conditions that cause the device to stop operating.2 V PWM_LATCH (pin 8) Open Active (high) Active (high) (L6563 only) Open Open PWM_STOP (pin 9) Open Open Open Active (low) Open Typical IC consumption 50 µA 180 µA 180 µA (L6563 only) 1.

5 Ω Vo=220 to 390 V Po = 80 W 120 kΩ 120 kΩ D2 20 V FUSE 4A/250V + P1 1W08G C1 0. real size: 64 x 94 mm) 32/39 . R7B 0.5 kΩ Boost inductor spec: E25x13x7 core.7 nF R10 15.1 mm Figure 48. Tracking Boost: Electrical schematic Daux 1N4007 T R3A R3B D3 1N4148 C6 R2 33 Ω R1 47 kΩ 9 11 2 1 13 7 4 R15 0Ω R6 22 Ω C8 1 µF D1 STTH2L06 NTC 2.L6563A 7 Application examples and ideas Figure 47.1 kΩ C11 4. 3C85 ferrite or equivalent 1.47 µF 400V R11A 1 MΩ R11B 1 MΩ Vac (88V to 264V) C7 4. Demo board (EVAL6563-80W) 80W.4 kΩ R13 10. EVAL6563-80W: PCB and component layout (Top view.7 nF 15 nF TP1 R4 39 kΩ R9A 1 MΩ R9B 1 MΩ R12A 1 MΩ C12 220 nF Q1 STP8NM50 R12A 1 MΩ R18 47 kΩ 8 14 3 12 L6563 6 5 10 C5 56 µF 400 V C4 100 nF TP2 R20 47 kΩ C9 470 nF R14 22. Wide-range.43 mH primary inductance Primary: 80 turns 20 x 0.Application examples and ideas L6563 .1 mm Secondary: 9 turns 0.8 kΩ C2 33 µF 25V R17 390 kΩ R7A C10 0.6 mm gap for 0.A.68 Ω 1/2 W N.68 Ω 1/2 W R8 37.

8 6.2 95.03 40.7 390.31 41.0 Vo (VDC) 219.5 8.0 90.39 40.998 0.1 43.80 80.7 ∆Vo (Vpk-pk) 8. EVAL6563-80W: PCB layout.2 85.2 Note: Measurements done with the line filter shown in Figure 51.0 307.28 81.951 0.974 THD (%) 3.7 Po (W) 40.1 95.999 0.0 88.6 15.7 307.8 96.8 6.9 83.4 95.989 0.7 4.0 7.6 14.L6563A Application examples and ideas Figure 49.85 η (%) 93.16 80.920 THD (%) 4. Table 8.7 83.7 9.8 45.994 0.5 Note: Measurements done with the line filter shown in Figure 51.10 40.33 80.3 PF 0. EVAL6563-80W: Evaluation results at half load Vin (VAC) 90 115 135 180 230 265 Pin (W) 43.5 264.4 42.0 Vo (VDC) 219.0 12.7 92.8 390. soldering side (Top view) Table 7.993 0.2 94.6 ∆Vo (Vpk-pk) 16.997 0.1 263.3 4.63 η (%) 94.64 80.1 PF 0. 33/39 .90 40.8 5.3 84. EVAL6563-80W: Evaluation results at full load Vin (VAC) 90 115 135 180 230 265 Pin (W) 85.7 6.6 43.6 46.997 0.9 244.9 14.7 6.7 356.4 9.5 13.7 7.3 7.1 93.0 13.5 95.5 85.1 Po (W) 79.L6563 .6 7.978 0.4 244.6 356.984 0.

Line filter (not tested for EMI compliance) used for EVAL6563-80W evaluation 34/39 . EVAL6563-80W: Vout vs. Vin relationship (tracking boost) L6563 .Application examples and ideas Figure 50.L6563A Figure 51.

5 Vout = 400V Pout = 350W L1 R4 1M Vcc 10. 3C85 ferrite or equivalent 1.87 M R11B 1.L6563 .8 Vac 88V to 264V - R2 10 k C3 10nF C4 470nF R7 12 k C7 560 pF C8 330 pF L1: core E42*21*15. main winding inductance 0.22 1W R10 12.9 mm air gap on centre leg.3 to 22 V R5 6.33 1W R14 12. wide-range-mains PFC pre-regulator with fixed output voltage and FOT control D1 1N5406 D2 STTH806DTI NTC1 2. wide-range-mains PFC pre-regulator with fixed output voltage L1 D1 1N5406 D2 STTH5L06 NTC1 2.5 mm gap for 150 µH primary inductance Primary: 74 turns 20xAWG30 ( 0.87 M R15B 1.3 mm) Secondary: 8 turns 0. 350W.C 0.L6563A Application examples and ideas Figure 52.5 k C6 330 pF 12 4 R9 6.8 k C5 1 µF R13A 1M R13B 1M R15A 1.7 k R12 20 k Boost Inductor (L1) Spec ETD29x16x10 core.55 mH 58 T of 20 x AWG32 ( 0.3 to 22 V R3 47 k R5 6.8 D4 1N4148 D5 1N4148 R10 6.8 k C4 1 µF R9A 1M R9B 1M R11A 1.87 M R1A 820 k R1B 820 k FUSE 8A/250V B1 KBU8M + C1 1 µF 400V 11 C2 1 µF 3 14 2 1 7 D3 1N4148 6 C8 150 µF 450 V L6563 13 10 8 9 12 4 R6 33 M1 STP12NM50 C6 470 nF 630 V Vac 88V to 264V 5 R7 390 k C7 10 nF R2 10 k C3 10nF C5 470nF R8A.1 mm Figure 53.B.5 Vout = 400V Pout = 250 W R4 1M Vcc 10. 250W.2 mm) 35/39 .7 k R16 20 k C11 220 µF 450 V L6563 13 11 R8 1.5 k TR1 BC557 9 2 1 7 D3 1N4148 6 M1A STP12NM50 C9 470 nF 630 V M1B STP12NM50 C10 10 nF R11 330 R12A. B2 material 1.87 M R1A 620 k R1B 620 k B1 KBU8M + FUSE 8A/250V C1 1 µF 400V 14 8 C2 1 µF 3 10 5 R3 390 k R6 1.B 0.

L6563A RZCD Vinac ZCD 9 CZCD Vout Rload L6563 L6563A Figure 55. Enhanced turn-off for big MOSFET driving Vcc 14 13 DRIVER GD Q BC327 L6563 L6563A 12 GND Rs 36/39 . Demagnetization sensing without auxiliary winding L6563 .Application examples and ideas Figure 54.

150 inch Typ Max 0.157 0. The category of second level interconnect is marked on the package and on the inner box label.25 0.st.25 8.L6563 .053 0.0 1.020 0.27 5. Typ Max 1.01 0.8 0.) Figure 56.75 4. ECOPACK is an ST trademark.004 1.40 6.344 0.013 0.65 0.10 0.004 0.043 0.065 0.244 0.20 0. in compliance with JEDEC Standard JESD97.337 0.35 0.50 1. SO-14 Mechanical data Dim. ECOPACK specifications are available at: www.10 0.050 0.75 0.050 0.80 E e H h L k ddd 0° (min. Min A A1 A2 B C D (1) mm.228 0.33 0.com Table 9. These packages have a Lead-free second level interconnect . Package dimensions 0016019D 37/39 . The maximum ratings related to soldering conditions are also marked on the inner box label.19 8.01 0.30 1.10 1.27 0.55 3.02 0. ST offers these devices in ECOPACK® packages.016 Min 0.012 0.).51 0.L6563A Package mechanical data 8 Package mechanical data In order to meet environmental requirements.069 0.007 0. 8° (max.

Changes 12-Mar-2007 4 38/39 .L6563A 9 Revision history Table 10. added Figure 37 on page 21 and minor editor changes.Revision history L6563 . Revision history Date 13-Nov-2004 24-Sep-2005 17-Nov-2006 Revision 1 2 3 First issue Changed the maturity from “Preliminary data” to “Datasheet” Added new part number L6563A (Table 2) Updated the Section 4 on page 7 & Section 7 on page 32 the document has been reformatted Replaced block diagram.

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