TUNNELING DEVICES

• Interband tunneling in Si end-of-roadmap devices

• Multiemitter tunneling HBT - good peformance with enhanced logic - ULSI-compatible (in principle) - no predictive (tunneling) device model

• Lateral interband tunneling diode on SOI - FET geometry with VG control of current - no inversion channel, different scaling - testbed for interband tunneling theory

Motivation: MOSFET scaling will end
ideal long-channel ID(VG) makes MOSFET a perfect switch

• subthreshold slope S > 2.3kT/q ~ 60 mV/decade • MOSFET degraded by short-channel effects: degraded S, DIBL

2002] ID (A/µm) V D = –1.2 V EOT= 1.2 nm LG = 6 nm tSi = 4–8 nm V D = –0. degraded subthreshold slope S • reduced current drive due to series resistance .Downscaling difficulties ultimate scaled planar transistors [Doris et al.05 V VG (V) • short channel effects.

Can tunneling help? annoyance in standard MOSFETs gate leakage S/D leakage BUT • • not apriori constrained by S = 60 mV/decade can provide highly nonlinear characteristics log J FET TT (tunneling transistor) VG .

Si) .INTERBAND TUNNELING DEVICES • Esaki tunnel diode (heavily-doped pn junction) [Esaki. 1958] p+ n+ reverse bias forward bias • current ITUN ~ strong (exponential) function of electric field F • note the same tunneling mechanism in reverse bias • no rigorous expression for ITUN in indirect materials (e.g.

Silvaco) use empirical expressions – quantitatively unreliable !! Can interband tunneling be useful in “end of roadmap” devices? .g.INDIRECT TUNNELING • direct tunneling conserves energy E and momentum k • analytically tractable for a known barrier shape U(z) U(z) E T( E ) ~ e –2 # [2m*(U(z)–E)/h2]1/2 dz E k k E EC EV Indirect material (like Si !!) means !k " 0 • simulators (e.

high current gain. 1994] first demonstration [Zaslavsky. Luryi et al. ultra-narrow HBT base. no base contact required for operation • control current due to interband emitter-base tunneling under reverse bias • enhanced logic due to emitter contact symmetry (xor and ornand functions in a single device) • easier fabrication. VLSI compatibility .MULTIEMITTER TUNNELING HBT Proposed [Gribnikov & Luryi.. 1997] E1 BACKWARD DIODE EMITTER-BASE JUNCTIONS E2 n -Si p -SiGe base n-Si C n -Si collector • two (or more) emitter contacts.

MULTIEMITTER BIASING VE2 VC IC IE IB forward bias injection reverse bias tunneling • note that tunneling base current is indirect (Si/SiGe) so no quantitative evaluation is possible .

!IB output current level for a given emitter V E2 (with VE1 = 0.GAIN AND TRANSCONDUCTANCE VE2 VC IC VE2 IE IB IC = IE . grounded) IB forward turn-on voltage schematic backward diode I(VEB ) VEB • VE2 splits between forward and reverse bias on EB junctions • small tunneling current IB controls IE1 ~ IC = $IB output current • gain $ depends on emitter-base parameters (large b in HBTs) • transconductance IC(VE2) depends on emitter-base I(VEB) • if VE1 = VE2 no current flows (floating base transistor) .

FIRST IMPLEMENTATION Emitter-base I(VEB) n-Si ~ 3x1018 p-SiGe ~ 4x1019 floating base Transistor characteristics IB = 0–10 µA $ ~ 400 floating second emitter • multiemitter biasing indistinguishable from standard HBT .

VC) curves IB = 0–5 µA $ ~ 1300 IC(VE2.VC) curves VE2 = 0.DEVICE OPTIMIZATION (a) Heavier E-B doping IC(IB.6–1 V .

ADDED LOGIC FUNCTIONALITY VE1 VE2 1 0 1 0 4.14 µA TIME 1 VE1 0 (b) ORNAND (3 emitters) low = 0 high = 0.9 V 0 IC 4 (mA) 2 0 0.42 6 5.23 mA (a) XOR (2 emitters) low = 0 high = 0.9 V VE2 VE3 1 0 1 0 6.24 2.31 mA 4.36 0 TIME • reasonable emitter symmetry • good on/off logic ratio (> 60 dB at room temperature) .65 IC 4 (mA) 2 0 <10 nA 2.22 5.90 2.

VLSI COMPATIBILITY collector p-SiGe base BiCMOS industry process (Agere Systems) with selective SiGe base epitaxy Comparable multiemitter HBT process collector • KEY PROBLEM: no predictive device model for circuit designer .

1964] • lateral interband tunneling transistor on thin SOI [Zaslavsky and Luryi.IDEAL TUNNELING DIODE STRUCTURE • surface-controlled avalanche transistor [Schockley. low CSD). ultra-short gate (low CG) • different scaling rules (no channel!) – implications unknown • complicated electrostatic problem for F(VG. VD) • in reverse bias (no minority carrier injection. 1999] VG n++-Si BOX p+-Si VD • thin Si channel (< 50 nm. low capacitance) – high-speed analog applications .

but requires area and adds CG .COMPETING MOSFET-BASED STRUCTURE · n-MOSFET with p-type drain [Koga and Toriumi. 1996-99] VG n p ninv • VG control of ID reported in forward bias to maintain negative differential resistance (NDR) • channel not needed.

FIRST DEVICE RUN (LETI-Grenoble) • simplest possible process. with the drain protected by a shifted active area mask • gate much wider than the junction depletion region gate overlaps junction. no additional masks VG1 n++(p+)-Si p+-Si VG2 • junction obtains by counterdoping. source and drain .

• shifted lithography • counterdoping of n-Si source. P = 8 keV. followed by in-situ doped poly-Si gate. tox = 4. standard subsequent processing . 5x1014 cm-2 • deposited gate oxide.6 nm.

TRANSISTOR CHARACTERISTICS T = 300 K LG = 0.35 µm • reverse bias tunneling ID shows VG control (either VG polarity. VG > 0 more effective) • soft reverse bias ID turn-on (insufficient junction doping!) • no dependence on gate length LG (as expected) .

8V 4.4V -4V VG = -3.10 0.8 0.2 0.4V 4.8 1.6V -4.5 V 1.0 0.5V VG = 0 0.0 0.8V -4.05 0.6 2.REVERSE-BIAS TUNNELING ID(VD) vs. but requires large VG . VG • heaviest doping (np 1020:6x1019) 1.15 0.4 0.4 0.0 0.2V 4V 3.6 0.2 1.0 REVERSE BIAS VD (V) • VG control of ID exists.0 TUNNELING ID (m A) 5V4.6V 4.00 0.2 -5V -4.25 TUNNELING ID (m A) 0.20 0.6 2.4 0.8 1.0 REVERSE BIAS VD (V) 0.

0x106 !MAX (V/cm) ideal ab rup t 4x1019 p n junction in 10 nm Si channel 4.0x106 3. IEEE EDL 27. 297 (2006) • subthreshold S < 60 mV/decade for low VD .SIMULATIONS FOR ABRUPT pn JUNCTION 5.0x106 -4 -2 0 2 4 VG (V) • taking empirical ITUN(VD. Zhang et al.VG) at face value: Q.0x106 real doub le-imp lanted p n junction 2.

enhanced logic .MULTIEMITTER TUNNELING HBT .requires BiCMOS process GATED INTERBAND TUNNELING DIODE .works in principle .works well.becoming «!popular!» in industry Infineon is publishing counterdoped FET designs INTERBAND TUNNELING MODEL ***key issue .better modeling/simulation needed .