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PROJECT REPORT ON METRO TRAIN PROTOTYPE

BY CETPA INFOTECH PRIVATE LIMITED

CONTENTS 1. 2. 3. $. 5. +. /. 8. !. 10. 8051 Microcontroller Architechture Variant in Atmel 8051 Microcontrollers Features o AT8!c51" AT8!c52 an# AT8!s51 Features o %C& 'se# Features o Ste((er Motor an# its &ri)er *C ,C- %a.out Source Co#e in Assem0. Com(onent %ist. A((en#i1 -i0lio2ra(h.

8051 Microcontroller Architechture AT8!C513


The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with ! b"tes of #lash programmable an$ erasable rea$ onl" memor" %&'(OM)* The $e+ice is manufacture$ using Atmel,s high-$ensit" non+olatile memor" technolog" an$ is compatible with the in$ustr"-stan$ar$ MCS-51 instruction set an$ pinout* The on-chip #lash allows the program memor" to be reprogramme$ in-s"stem or b" a con+entional non+olatile memor" programmer* -" combining a +ersatile 8-bit C&. with #lash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which pro+i$es a highl"-fle/ible an$ cost-effecti+e solution to man" embe$$e$ control applications*

,in Con i2urtion

The AT89C51 pro+i$es the following stan$ar$ features0 ! b"tes of #lash, 118 b"tes of (AM, 21 34O lines, two 15-bit timer4counters, a fi+e +ector two-le+el interrupt architecture, a full $uple/ serial port, on-chip oscillator an$ cloc6 circuitr"* 3n a$$ition, the AT89C51 is $esigne$ with static logic for operation $own to 7ero fre8uenc" an$ supports two software selectable power sa+ing mo$es* The 3$le Mo$e stops the C&. while allowing the (AM, timer4counters, serial port an$ interrupt s"stem to continue functioning* The &ower-$own Mo$e sa+es the (AM contents but free7es the oscillator $isabling all other chip functions until the ne/t har$ware reset*

Pin Description
VCC Suppl" +oltage* GND 9roun$* Port 0 &ort : is an 8-bit open-$rain bi-$irectional 34O port* As an output port, each pin can sin6 eight TT; inputs* <hen 1s are written to port : pins, the pins can be use$ as highimpe$ance inputs* &ort : ma" also be configure$ to be the multiple/e$ lowor$er

a$$ress4$ata bus $uring accesses to e/ternal program an$ $ata memor"* 3n this mo$e &: has internal pullups* &ort : also recei+es the co$e b"tes $uring #lash programming, an$ outputs the co$e b"tes $uring program +erification* '/ternal pullups are re8uire$ $uring program +erification* Port 1 &ort 1 is an 8-bit bi-$irectional 34O port with internal pullups* The &ort 1 output buffers can sin64source four TT; inputs* <hen 1s are written to &ort 1 pins the" are pulle$ high b" the internal pullups an$ can be use$ as inputs* As inputs, &ort 1 pins that are e/ternall" being pulle$ low will source current %33;) because of the internal pullups* &ort 1 also recei+es the low-or$er a$$ress b"tes $uring #lash programming an$ +erification* Port 2 &ort 1 is an 8-bit bi-$irectional 34O port with internal pullups* The &ort 1 output buffers can sin64source four TT; inputs* <hen 1s are written to &ort 1 pins the" are pulle$ high b" the internal pullups an$ can be use$ as inputs* As inputs, &ort 1 pins that are e/ternall" being pulle$ low will source current %33;) because of the internal pullups* &ort 1 emits the high-or$er a$$ress b"te $uring fetches from e/ternal program memor" an$ $uring accesses to e/ternal $ata memor" that use 15-bit a$$resses %MO=> ? @&T()* 3n this application, it uses strong internal pull-ups when emitting 1s* @uring accesses to e/ternal $ata memor" that use 8-bit a$$resses %MO=> ? (3), &ort 1 emits the contents of the &1 Special #unction (egister* &ort 1 also recei+es the high-or$er a$$ress bits an$ some control signals $uring #lash programming an$ +erification* Port 3 &ort 2 is an 8-bit bi-$irectional 34O port with internal pullups* The &ort 2 output buffers can sin64source four TT; inputs* <hen 1s are written to &ort 2 pins the" are pulle$ high b" the internal pullups an$ can be use$ as inputs* As inputs, &ort 2 pins that are e/ternall" being pulle$ low will source current %33;) because of the pullups* &ort 2 also ser+es the functions of +arious special features of the AT89C51 as liste$ below0 &ort 2 also recei+es some control signals for #lash programming an$ +erification*
RST

(eset input* A high on this pin for two machine c"cles while the oscillator is running resets the $e+ice*
ALE/PROG

A$$ress ;atch 'nable output pulse for latching the low b"te of the a$$ress $uring accesses to e/ternal memor"* This pin is also the program pulse input %&(O9) $uring #lash programming* 3n normal operation A;' is emitte$ at a constant rate of 145 the oscillator fre8uenc", an$ ma" be use$ for e/ternal timing or cloc6ing purposes* Aote, howe+er, that one A;'

pulse is s6ippe$ $uring each access to e/ternal @ata Memor"* 3f $esire$, A;' operation can be $isable$ b" setting bit : of S#( location 8'B* <ith the bit set, A;' is acti+e onl" $uring a MO=>

or MO=C instruction* Otherwise, the pin is wea6l" pulle$ high* Setting the A;'-$isable bit has noeffect if the microcontroller is in e/ternal e/ecution mo$e* PSEN &rogram Store 'nable is the rea$ strobe to e/ternal program memor"* <hen the AT89C51 is e/ecuting co$e from e/ternal program memor", &S'A is acti+ate$ twice each machine c"cle, e/cept that two &S'A acti+ations are s6ippe$ $uring each access to e/ternal $ata memor"* EA/VPP '/ternal Access 'nable* 'A must be strappe$ to 9A@ in or$er to enable the $e+ice to fetch co$e from e/ternal program memor" locations starting at ::::B up to ####B* Aote, howe+er, that if loc6 bit 1 is programme$, 'A will be internall" latche$ on reset* 'A shoul$ be strappe$ to = CC for internal program e/ecutions* This pin also recei+es the 11-+olt programming enable +oltage %= &&) $uring #lash programming, for parts that re8uire 11-+olt = &&* XTAL1 3nput to the in+erting oscillator amplifier an$ input to the internal cloc6 operating circuit* XTAL2 Output from the in+erting oscillator amplifier* Oscillator Characters >TA;1 an$ >TA;1 are the input an$ output, respecti+el", of an in+erting amplifier which can be configure$ for use as an on-chip oscillator, as shown in #igure 1* 'ither a 8uart7 cr"stal or ceramic resonator ma" be use$* To $ri+e the $e+ice from an e/ternal cloc6 source, >TA;1 shoul$ be left unconnecte$ while >TA;1 is $ri+en as shown in #igure 1* There are no re8uirements on the $ut" c"cle of the e/ternal cloc6 signal, since the input to the internal cloc6ing circuitr" is through a $i+i$e-b"-two flip-flop, but minimum an$ ma/imum +oltage high an$ low time specifications must be obser+e$*

!"le #o"e
3n i$le mo$e, the C&. puts itself to sleep while all the onchip peripherals remain acti+e* The mo$e is in+o6e$ b" software* The content of the on-chip (AM an$ all the special functions registers remain unchange$ $uring this mo$e* The i$le mo$e can be terminate$ b" an" enable$interrupt or b" a har$ware reset* 3t shoul$ be note$ that when i$le is terminate$ b" a har$ ware reset, the $e+ice normall" resumes program e/ecution, from where it left off, up to two machine c"cles before the internal reset algorithm ta6es control* On-chip har$ware inhibits access to internal (AM in this e+ent, but access to the port pins is not inhibite$* To eliminate the possibilit" of an une/pecte$ write to a port pin when 3$le is terminate$ b" reset, the instruction following the one that in+o6es 3$le shoul$ not be one that writes to a port pin or to e/ternal memor"*

Pro$ra%%in$ the &lash


The AT89C51 is normall" shippe$ with the on-chip #lash memor" arra" in the erase$ state %that is, contents C ##B) an$ rea$" to be programme$* The programming interface accepts either a high-+oltage %11-+olt) or a low-+oltage %=CC) program enable signal* The low-+oltage programming mo$e pro+i$es a con+enient wa" to program the AT89C51 insi$e the user,s s"stem, while the high-+oltage programming mo$e is compatible with con+entional thir$part" #lash or '&(OM programmers* The AT89C51 is shippe$ with either the high-+oltage or low-+oltage programming mo$e enable$* The AT89C51 co$e memor" arra" is programme$ b"te-b"b"te in either programming mo$e* To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode. Pro$ra%%in$ Al$orith% -efore programming the AT89C51, the a$$ress, $ata an$ control signals shoul$ be set up accor$ing to the #lash programming mo$e table* To program the AT89C51, ta6e the following steps* 1* 3nput the $esire$ memor" location on the a$$ress lines* 1* 3nput the appropriate $ata b"te on the $ata lines* 2* Acti+ate the correct combination of control signals*

* (aise 'A4=&& to 11= for the high-+oltage programming mo$e* 5* &ulse A;'4&(O9 once to program a b"te in the #lash arra" or the loc6 bits* The b"te-write c"cle is self-time$ an$ t"picall" ta6es no more than 1*5 ms* (epeat steps 1 through 5, changing the a$$ress an$ $ata for the entire arra" or until the en$ of the obDect file is reache$* Data Pollin$ The AT89C51 features @ata &olling to in$icate the en$ of a write c"cle* @uring a write c"cle, an attempte$ rea$ of the last b"te written will result in the complement of the written $atum on &O*E* Once the write c"cle has been complete$, true $ata are +ali$ on all outputs, an$ the ne/t c"cle ma" begin* @ata &olling ma" begin an" time after a write c"cle has been initiate$* 'ea"(/)*s( The progress of b"te programming can also be monitore$ b" the (@F4-SF output signal* &2* is pulle$ low after A;' goes high $uring programming to in$icate -.SF* &2* is pulle$ high again when programming is $one to in$icate ('A@F* Pro$ra% Veri+( 3f loc6 bits ;-1 an$ ;-1 ha+e not been programme$, the programme$ co$e $ata can be rea$ bac6 +ia the a$$ress an$ $ata lines for +erification* The loc6 bits cannot be +erifie$ $irectl"* =erification of the loc6 bits is achie+e$ b" obser+ing that their features are enable$* Chip Erase The entire #lash arra" is erase$ electricall" b" using the proper combination of control signals an$ b" hol$ing A;'4&(O9 low for 1: ms* The co$e arra" is written with all G1Hs* The chip erase operation must be e/ecute$ before the co$e memor" can be re-programme$* 'ea"in$ the Si$nat*re )(tes The signature b"tes are rea$ b" the same proce$ure as a normal +erification of locations :2:B, :21B, an$ :21B, e/cept that &2*5 an$ &2*E must be pulle$ to a logic low* The +alues returne$ are as follows* %:2:B) C 1'B in$icates manufacture$ b" Atmel %:21B) C 51B in$icates 89C51 %:21B) C ##B in$icates 11= programming %:21B) C :5B in$icates 5= programming

,ro2rammin2 The AT8!C51

AT89C52:
Features 4 Com(ati0le 5ith MCS6517 ,ro#ucts 4 88 -.tes o *n6S.stem 9e(ro2ramma0le Flash Memor. 4 En#urance3 1"000 :rite;Erase C.cles 4 Full. Static O(eration3 0 <= to 2$ M<= 4 Three6le)el ,ro2ram Memor. %oc> 4 25+ 1 860it *nternal 9AM 4 32 ,ro2ramma0le *;O %ines 4 Three 1+60it Timer;Counters 4 Ei2ht *nterru(t Sources 4 ,ro2ramma0le Serial Channel 4 %o56(o5er *#le an# ,o5er6#o5n Mo#es

Description
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 8! b"tes of #lash programmable an$ erasable rea$ onl" memor" %&'(OM)* The $e+ice is manufacture$ using Atmel,s high-$ensit" non+olatile memor" technolog" an$ is compatible with the in$ustr"stan$ar$ 8:C51 an$ 8:C51 instruction set an$ pinout* The on-chip #lash allows the program memor" to be reprogramme$ in-s"stem or b" a con+entional non+olatile memor" programmer* -" combining a +ersatile 8-bit C&. with #lash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which pro+i$es a highl"-fle/ible an$ cost-effecti+e solution to man" embe$$e$ control applications*

Pin Dia$ra%

The AT,-C.2 pro/i"es the +ollo0in$ stan"ar" +eat*res 8! b"tes of #lash, 155 b"tes of (AM, 21 34O lines, three 15-bit timer4counters, a si/-+ector twole+el interrupt architecture, a full-$uple/ serial port, on-chip oscillator, an$ cloc6 circuitr"* 3n a$$ition, the AT89C51 is $esigne$ with static logic for operation $own to 7ero fre8uenc" an$ supports two software selectable power sa+ing mo$es* The 3$le Mo$e stops the C&. while allowing the (AM, timer4counters, serial port, an$ interrupt s"stem to continue functioning* The &ower-$own mo$e sa+es the (AM contents but free7es the oscillator, $isabling all other chip functions until the ne/t har$ware reset* Special &*nction 'e$isters A map of the on-chip memor" area calle$ the Special #unction (egister %S#() space* Aote that not all of the a$$resses are occupie$, an$ unoccupie$ a$$resses ma" not be implemente$ on the chip* (ea$ accesses to these a$$resses will in general return ran$om $ata, an$ write accesses will ha+e an in$eterminate effect* .ser software shoul$ not write 1s to these unliste$ locations, since the" ma" be use$ in future pro$ucts to in+o6e*

Data #e%or(
The AT89C51 implements 155 b"tes of on-chip (AM* The upper 118 b"tes occup" a parallel a$$ress space to the Special #unction (egisters* That means the upper 118 b"tes ha+e the same a$$resses as the S#( space but are ph"sicall" separate from S#( space* <hen an instruction accesses an internal location abo+e a$$ress E#B, the a$$ress mo$e use$ in the instruction specifies whether the C&. accesses the upper 118 b"tes of (AM or the S#( space* 3nstructions that use $irect a$$ressing access S#( space* new features* 3n that case, the reset or inacti+e +alues of the new bits will alwa"s be :*
Ti%er 2 'e$isters

Control an$ status bits are containe$ in registers T1COA an$ for Timer 1* The register pair %(CA&1B, (CA&1;) are the Capture4(eloa$ registers for Timer 1 in 15-bit capture mo$e or 15bit auto-reloa$ mo$e*
!nterr*pt 'e$isters

The in$i+i$ual interrupt enable bits are in the 3' register* Two priorities can be set for each of the si/ interrupt sources in the 3& register*r* specifies whether the C&. accesses the upper 118 b"tes of (AM or the S#( space* 3nstructions that use $irect a$$ressing access S#( space* #or e/ample, the following $irect a$$ressing instruction accesses the S#( at location :A:B %which is &1)* 3nstructions that use in$irect a$$ressing access the upper 118 b"tes of (AM* #or e/ample, the following in$irect a$$ressing instruction, where (: contains :A:B, accesses the $ata b"te at a$$ress :A:B, rather than &1 %whose a$$ress is :A:B)* MO= ?(:, I$ata Aote that stac6 operations are e/amples of in$irect a$$ressing, so the upper 118 b"tes of $ata (AM are a+ailable as stac6 space*

Ti%er 0 an" 1
Timer : an$ Timer 1 in the AT89C51 operate the same wa" as Timer : an$ Timer 1 in the AT89C51*

Ti%er 2
Timer 1 is a 15-bit Timer4Counter that can operate as either a timer or an e+ent counter* The t"pe of operation is selecte$ b" bit C4T1 in the S#( T1COA* Timer 1 has three operating mo$es0 capture, auto-reloa$ %up or $own counting), an$ bau$ rate generator* The mo$es are selecte$ b" bits in T1COA* Timer 1 consists of two 8-bit registers, TB1 an$ T;1* 3n the Timer function, the T;1 register is incremente$ e+er" machine c"cle* Since a machine c"cle consists of 11 oscillator perio$s, the count rate is 1411 of the oscillator fre8uenc"* 3n the Counter function, the register is incremente$ in response to a 1-to-: transition at its correspon$ing e/ternal input pin, T1* 3n this function, the e/ternal input is sample$ $uring S5&1 of e+er" machine c"cle* <hen the samples show a high in one c"cle an$ a low in the ne/t c"cle, the count is incremente$* The new count +alue appears in the register $uring S2&1 of the c"cle following the one in which the transition was $etecte$* Since two machine c"cles %1 oscillator

perio$s) are re8uire$ to recogni7e a 1-to-: transition, the ma/imum count rate is 141 of the oscillator fre8uenc"* To ensure that a gi+en le+el is sample$ at least once before it changes, the le+el shoul$ be hel$ for at least one full machine c"cle*

Capt*re #o"e
3n the capture mo$e, two options are selecte$ b" bit '>'A1 in T1COA* 3f '>'A1 C :, Timer 1 is a 15-bit timer or counter which upon o+erflow sets bit T#1 in T1COA* This bit can then be use$ to generate an interrupt* 3f '>'A1 C 1, Timer 1 performs the same operation, but a 1- to-: transition at e/ternal input T1'> also causes the current +alue in TB1 an$ T;1 to be capture$ into CA&1B an$ (CA&1;, respecti+el"* 3n a$$ition, the transition at T1'> causes bit '>#1 in T1COA to be set* The '>#1 bit, li6e T#1, can generate an interrupt*

A*to1reloa" 23p or Do0n Co*nter4


Timer 1 can be programme$ to count up or $own when configure$ in its 15-bit auto-reloa$ mo$e* This feature is in+o6e$ b" the @C'A %@own Counter 'nable) bit locate$ in the S#( T1MO@* .pon reset, the @C'A bit is set to : so that timer 1 will $efault to count up* <hen @C'A is set, Timer 1 can count up or $own, $epen$ing on the +alue of the T1'> pin*

!nterr*pts
The AT89C51 has a total of si/ interrupt +ectors0 two e/ternal interrupts %3AT: an$ 3AT1), three timer interrupts %Timers :, 1, an$ 1), an$ the serial port interrupt* 'ach of these interrupt sources can be in$i+i$uall" enable$ or $isable$ b" setting or clearing a bit in Special #unction (egister 3'* 3' also contains a global $isable bit, 'A, which $isables all interrupts at once* Aote that bit position 3'*5 is unimplemente$* 3n the AT89C51, bit position 3'*5 is also unimplemente$* .ser software shoul$ not write 1s to these bit positions, since the" ma" be use$ in future AT89 pro$ucts* Timer 1 interrupt is generate$ b" the logical O( of bits T#1 an$ '>#1 in register T1COA* Aeither of these flags is cleare$ b" har$ware when the ser+ice routine is +ectore$ to* 3n fact, the ser+ice routine ma" ha+e to $etermine whether it was T#1 or '>#1 that generate$ the interrupt, an$ that bit will ha+e to be cleare$ in software* The Timer : an$ Timer 1 flags, T#: an$ T#1, are set at S5&1 of the c"cle in which the timers o+erflow* The +alues are then polle$ b" the circuitr" in the ne/t c"cle* Bowe+er, the Timer 1 flag, T#1, is set at S1&1 an$ is polle$ in the same c"cle in which the timer o+erflows*

AT89S510
The AT89;S51 is a low-+oltage, high-performance CMOS 8-bit microcontroller with ! b"tes of in-s"stem programmable #lash memor"* The $e+ice is manufacture$ using Atmel,s high-$ensit" non+olatile memor" technolog" an$ is compatible with the in$ustr"stan$ar$ 8:C51 instruction set an$ pinout* The on-chip #lash allows the program memor" to be reprogramme$ in-s"stem or b" a con+entional non+olatile memor" programmer* -" combining a +ersatile 8-bit C&. with in-s"stem programmable #lash on a monolithic chip, the Atmel AT89;S51 is a powerful microcontroller which pro+i$es a highl"-fle/ible an$ cost-effecti+e solution to man" embe$$e$ control applications* The AT89;S51 pro+i$es the following stan$ar$ features0 ! b"tes of #lash, 118 b"tes of (AM, 21 34O lines, <atch$og timer, two $ata pointers, two 15-bit timer4counters, a fi+e-+ector two-le+el interrupt architecture, a full $uple/ serial port, on-chip oscillator, an$ cloc6 circuitr"* 3n a$$ition, the AT89;S51 is $esigne$ with static logic for operation $own to 7ero fre8uenc" an$ supports two software selectable power sa+ing mo$es* The 3$le Mo$e stops the C&. while allowing the (AM, timer4counters, serial port, an$ interrupt s"stem to continue functioning* The &ower-$own mo$e sa+es the (AM contents but free7es the oscillator, $isabling all other chip functions until the ne/t e/ternal interrupt or har$ware reset* (est all function of this Atmel Series Microcontroller is same as its other members*

Architecture #eatures0
5 ,1)it CP3 Opti%i6e" +or Control Applications 5 E7tensi/e )oolean Processin$ Capa8ilities 2Sin$le1)it Lo$ic4 5 On1Chip &lash Pro$ra% #e%or( 5 On1Chip Data 'A# 5 )i"irectional an" !n"i/i"*all( A""ressa8le !/O Lines 5 #*ltiple 191)it Ti%er/Co*nters 5 &*ll D*ple7 3A'T 5 #*ltiple So*rce/Vector/Priorit( !nterr*pt Str*ct*re 5 On1Chip Cloc: Oscillator 5 On1chip EEP'O# 2AT,-S series4 5 SP! Serial )*s !nter+ace 2AT,-S Series4 5 ;atch"o$ Ti%er 2AT,-S Series4

#e%or( Or$ani6ation
Lo$ical Separation o+ Pro$ra% Data #e%or(
All Atmel #lash microcontrollers ha+e separate a$$ress spaces for program an$ $ata memor"* The logical separation of program an$ $ata memor" allows the $ata memor" to be accesse$ b" 8-bit a$$resses, which can be more 8uic6l" store$ an$ manipulate$ b" an 8- bit C&.* Ae+ertheless, 15-bit $ata memor" a$$resses can also be generate$ through the @&T( register* &rogram memor" can onl" be rea$* There can be up to 5 ! b"tes of $irectl" a$$ressable program memor"* The rea$ strobe for e/ternal program memor" is the &rogram Store 'nable signal %&S'A)* @ata memor" occupies a separate a$$ress space from program memor"* .p to 5 ! b"tes of e/ternal memor" can be $irectl" a$$resse$ in the e/ternal $ata memor" space* The C&. generates rea$ an$ write signals, (@ an$ <(, $uring e/ternal $ata memor" accesses* '/ternal program memor" an$ e/ternal $ata memor" can be combine$ b" appl"ing the (@ an$ &S'A signals to the input of an AA@ gate an$ using the output of the gate as the rea$ strobe to the e/ternal program4$ata memor"*

Pro$ra% #e%or(
After reset, the C&. begins e/ecution from location ::::B* each interrupt is assigne$ a fi/e$location in program memor"* The interrupt causes the C&. to Dump to that location, where it e/ecutes the ser+ice routine* '/ternal 3nterrupt :, for e/ample, is assigne$ to location :::2B* 3f '/ternal 3nterrupt : is use$, its ser+ice routine must begin at location :::2B* 3f the interrupt is not use$, its ser+ice location is a+ailable as general purpose program memor"* The interrupt ser+ice locations are space$ at 8-b"te inter+als0

:::2B for '/ternal 3nterrupt :, :::-B for Timer :, ::12B for '/ternal 3nterrupt 1, ::1-B for Timer 1, an$ so on* 3f an interrupt ser+ice routine is short enough %as is often the case in control applications), it can resi$e entirel" within that 8-b"te inter+al* ;onger ser+ice routines can use a Dump instruction to s6ip o+er subse8uent interrupt locations, if other interrupts are in use* The lowest a$$resses of program memor" can be either in the on-chip #lash or in an e/ternal memor"* To ma6e this selection, strap the '/ternal Access %'A) pin to either =CC or 9A@* #or e/ample, in the AT89C51 with ! b"tes of on-chip #lash, if the 'A pin is strappe$ to = CC, program fetches to a$$resses ::::B through :###B are $irecte$ to the internal #lash* &rogram fetches to a$$resses 1:::B through ####B are $irecte$ to e/ternal memor"* 3n the AT89C51 %8! b"tes #lash), 'A C = CC selects a$$resses ::::B through 1###B to be internal an$ a$$resses 1:::B through ####B to be e/ternal* 3f the 'A pin is strappe$ to 9A@, all program fetches are $irecte$ to e/ternal memor"* The rea$ strobe to e/ternal memor", &S'A, is use$ for all e/ternal program fetches* 3nternal program fetches $o not acti+ate &S'A* The har$ware configuration for e/ternal program e/ecution* Aote that 15 34O lines %&orts : an$ 1) are $e$icate$ to bus functions $uring e/ternal program memor" fetches* &ort : %&: in #igure 5) ser+es as a multiple/e$ a$$ress4$ata bus* 3t emits the low b"te of the &rogram Counter %&C;) as an a$$ress an$ then goes into a float state while waiting for the arri+al of the co$e b"te from the program memor"* @uring the time that the low b"te of the &rogram Counter is +ali$ on &:, the signal A;' %A$$ress ;atch 'nable) cloc6s this b"te into an a$$ress latch* Meanwhile, &ort 1 emits the high b"te of the &rogram Counter %&CB)* Then &S'A strobes the e/ternal memor", an$ the microcontroller rea$s the co$e b"te*

Pro$ra% #e%or(

&rogram memor" a$$resses are alwa"s 15 bits wi$e, e+en though the actual amount of program memor" use$ ma" be less than 5 ! b"tes* '/ternal program e/ecution sacrifices two of the 8-bit ports, &: an$ &1, to the function of a$$ressing the program memor"*

Data #e%or(
The right half of the internal an$ e/ternal $ata memor" spaces a+ailable on Atmel,s #lash microcontrollers* Bar$ware configuration for accessing up to 1! b"tes of e/ternal (AM* 3n this case, the C&. e/ecutes from internal #lash* &ort : ser+es as a multiple/e$ a$$ress4$ata bus to the (AM, an$ 2 lines of &ort 1 are use$ to page the (AM* The C&. generates (@ an$ <( signals as nee$e$ $uring e/ternal (AM accesses* Fou can assign up to 5 ! b"tes of e/ternal $ata memor"* '/ternal $ata memor" a$$resses can be either 1 or 1 b"tes wi$e* One-b"te a$$resses are often use$ in conDunction with one or more other 34O lines to page the (AM* Twob"te a$$resses can also be use$, in which case the high a$$ress b"te is emitte$ at &ort 1* 3nternal $ata memor" a$$resses are alwa"s 1 b"te wi$e, which implies an a$$ress space of onl" 155 b"tes* Bowe+er, the a$$ressing mo$es for internal (AM can in fact accommo$ate 28 b"tes* @irect a$$resses higher than E#B access one memor" space, an$ in$irect a$$resses higher than E#B access a $ifferent memor" space* Thus, the .pper 118 an$ S#( space occup"ing the same

bloc6 of a$$resses, 8:B through ##B, although the" are ph"sicall" separate entities* The lowest 21 b"tes are groupe$ into ban6s of 8 registers* &rogram instructions call out these registers as (: through (E* Two bits in the &rogram Status <or$ %&S<) select which register ban6 is in use* This architecture allows more efficient use of co$e space, since register instructions are shorter than instructions that use $irect a$$ressing*

Pro$ra%%in$ Stat*s ;or"

The !nstr*ction Set

All members of the Atmel microcontroller famil" e/ecute the same instruction set* This instruction set is optimi7e$ for 8- bit control applications an$ it pro+i$es a +ariet" of fast a$$ressing mo$es for accessing the internal (AM to facilitate b"te operations on small $ata structures* The instruction set pro+i$es e/tensi+e support for 1-bit +ariables as a separate $ata t"pe, allowing $irect bit manipulation in control an$ logic s"stems that re8uire -oolean processing* The following o+er+iew of the instruction set gi+es a brief $escription of how certain instructions can be use$*

Pro$ra% Stat*s ;or"


The &rogram Status <or$ %&S<) contains status bits that reflect the current state of the C&.* The &S<, shown in #igure 11, resi$es in S#( space* The &S< contains the Carr" bit, the Au/iliar" Carr" %for -C@ operations), the tworegister ban6 select bits, the O+erflow flag, a &arit" bit, an$ two user-$efinable status flags* The Carr" bit, in a$$ition to ser+ing as a Carr" bit in arithmetic operations, also ser+es as the GAccumulatorH for a number of -oolean operations* The bits (S: an$ (S1 select one of the four register ban6s shown in #igure 8* A number of instructions refer to these (AM locations as (: through (E* The status of the (S: an$ (S1 bits at e/ecution time $etermines which of the four ban6s is selecte$* The &arit" bit reflects the number of 1s in the Accumulator0 &C1 if the Accumulator contains an o$$ number of 1s, an$ &C: if the Accumulator contains an e+en number of 1s* Thus, the number of 1s in the Accumulator plus & is alwa"s e+en* Two bits in the &S< are uncommitte$ an$ can be use$ as general purpose status flags*

A""ressin$ #o"es
The a$$ressing mo$es in the #lash microcontroller instruction set are as follows*

Direct A""ressin$
3n $irect a$$ressing, the operan$ is specifie$ b" an 8-bit a$$ress fiel$ in the instruction* Onl" internal $ata (AM an$ S#(s can be $irectl" a$$resse$*

!n"irect A""ressin$
3n in$irect a$$ressing, the instruction specifies a register that contains the a$$ress of the operan$* -oth internal an$ e/ternal (AM can be in$irectl" a$$resse$* The a$$ress register for 8bit a$$resses can be either the Stac6 &ointer or (: or (1 of the selecte$ register ban6* The a$$ress register for 15-bit a$$resses can be onl" the 15-bit $ata pointer register, @&T(*

'e$ister !nstr*ctions
The register ban6s, which contain registers (: through (E, can be accesse$ b" instructions whose opco$es carr" a 2- bit register specification* 3nstructions that access the registers this wa" ma6e efficient use of co$e, since this mo$e eliminates an a$$ress b"te* <hen the instruction is e/ecute$, one of the eight registers in the selecte$ ban6 is accesse$* One of four ban6s is selecte$ at e/ecution time b" the two ban6 select bits in the &S<*

'e$ister1Speci+ic !nstr*ctions
Some instructions are specific to a certain register* #or e/ample, some instructions alwa"s operate on the Accumulator, so no a$$ress b"te is nee$e$ to point to it* 3n these cases, the opco$e itself points to the correct register* 3nstructions that refer to the Accumulator as A assemble as Accumulator-specific opco$es*

!n"e7e" A""ressin$
&rogram memor" can onl" be accesse$ +ia in$e/e$ a$$ressing* This a$$ressing mo$e is inten$e$ for rea$ing loo6-up tables in program memor"* A 15-bit base register %either @&T( or the &rogram Counter) points to the base of the table, an$ the Accumulator is set up with the table entr" number* The a$$ress of the table entr" in program memor" is forme$ b" a$$ing the Accumulator $ata to the base pointer* Another t"pe of in$e/e$ a$$ressing is use$ in the Gcase DumpH instruction* 3n this case the $est ination a$$ress of a Dump instruction is compute$ as the sum of the base pointer an$ the Accumulator $ata*

;i8ui$ Cr"stal @ispla" #un$amentals

A general $iscussion of how li8ui$ cr"stal $ispla"s wor6* A basic intro$uction to the chemistr", structure, an$ properties of li8ui$ cr"stals use$ in $ispla"s* An o+er+iew of $ispla" structure, assembl", an$ relate$ technolog" is summari7e$*

;i8ui$ Cr"stal @ispla"s %;C@s) are categori7e$ as nonemissi+e $ispla" $e+ices, in that respect, the" $o not pro$uce an" form of light li6e a Catho$e (a" Tube %C(T)* ;C@s either pass or bloc6 light that is reflecte$ from an e/ternal light source or pro+i$e$ b" a bac64si$e lighting s"stem* There are two mo$es of operation for ;C@s $uring the absence of an electric fiel$ %applie$ &ower)J a mo$e $escribes the transmittance state of the li8ui$ cr"stal elements* Aormal <hite mo$e0 the $ispla" is white or clear an$ allows light to pass through an$ Aormal -lac6 Mo$e0 the $ispla" is $ar6 an$ all light is $iffuse$* =irtuall" all $ispla"s in pro$uction for &C4<or6station use are normal white mo$e to optimi7e contrast an$ spee$* A simplifie$ $escription of how a $ot matri/ ;C@ $ispla" wor6s is as follows0 A twiste$ nematic %TA) ;C $ispla" consists of two polari7ers, two pieces of glass, some form of switching element or electro$e to $efine pi/els, an$ $ri+er 3ntegrate$ Circuits %3Cs) to a$$ress the rows an$ columns of pi/els* To $efine a pi/el %or subpi/el element for a color $ispla"), a rectangle is constructe$ out of 3n$ium Tin O/i$e -- a semi-transparent metal o/i$e %3TO) an$ charge is applie$ to this area in or$er to change the orientation of the ;C material % change from a white pi/el to a $ar6 pi/el)* The metho$ utili7e$ to form a pi/el in passi+e an$ acti+e matri/ $ispla"s $iffers an$ will be $escribe$ in later sections* #igure 1 illustrates a cross sectional +iew of a simple TA ;C $ispla"* #igure 1 $epicts a $ot matri/ $ispla" as +iewe$ without its metal mo$ule4case e/posing the 3C $ri+ers*

Looking dir !"#$ %" "& di'(#%$ "& g%" or ro) dri* r' %r #o!%" d i"& r on "& # +" or "& rig&" 'id o+ "& di'(#%$ )&i# "& d%"% or !o#,-n dri* r' %r #o!%" d on "& "o( .%nd or /o""o-0 o+ "& di'(#%$1 N ) "&in di'(#%$ -od,# " !&no#og$ -o,n"' "& IC' on !ond,!"i* "%( "&%" %##o)' "& "o / +o#d d / &ind "& di'(#%$ +,r"& r r d,!ing "& 'i2 o+ "& +ini'& d -od,# 1 An IC )i## %ddr '' % n,-/ r o+ ro)' or !o#,-n'1 Fig,r 3: Cro'' 4 !"ion o+ % 4i-(# LC Di'(#%$
viewer ///////////////////////////////////// Polarizer _____________________________________ glass ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Liquid Crystal _____________________________________ glass \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ Polarizer Backlight

Fig,r 2: LCD (%n # %nd IC dri* r #o!%"ion'

________________________________________ | | | IC IC | Source/Colu ! ICs

| | | | | | |IC"""""""""""""""""""""Pi#el | | | |IC $"""" %ate Li!e/&ow IC | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

5 An IC dri* r )i## %ddr '' % n,-/ r o+ ro)6!o#,-n #in ' %nd no" 7,'" "& 'ing# (i8 # in "& di%gr%- %/o* Po#%ri2 r' %r %n in" gr%# (%r" o+ % LCD di'(#%$9 (o'' ''ing "& ,ni:, (ro( r"$ o+ on#$ (%''ing #ig&" i+ i" i' ori n" d in % '( !i+i! .ori n" d0 dir !"ion1 To ,"i#i2 "&i' (& no- n% in TN LC di'(#%$'9 "& /o""o- (o#%ri2 r ori n"' in!o-ing #ig&" in on dir !"ion1 T& ori n" d #ig&" (%'' ' "&ro,g& "& LC -%" ri%# %nd i' i"& r ,n%#" r d or ;/ n"; 9< d gr '1 D ( nding on "& ori n"%"ion o+ "& "o( (o#%ri2 r9 "&i' #ig&" )i## i"& r (%'' "&ro,g& or / di++,' d1 I+ "& #ig&" i' di++,' d9 i" )i## %(( %r %' % d%rk %r %1 Fig,r = i' % 'i-(# i##,'"r%"ion o+ "& ' :, n! o+ * n"' "&%" o!!,r )& n #ig&" (%'' ' "&ro,g& % 'i-(# ")i'" d n -%"i! LC di'(#%$1

%i?ui# Cr.stal Material


T& #i:,id !r$'"%#' ,' d +or di'(#%$ " !&no#og$ %r "& r-o"ro(i! #i:,id !r$'"%#'> "& $ 8&i/i" d 'ir d !&%r%!" ri'"i!' o* r % '( !i+i! " -( r%",r r%ng 1 T&i' i' "& (ri-%r$ r %'on )&$ LCD' do no" o( r%" (ro( r#$ )& n "& $ %r "oo !o#d or "oo )%r-1 I+ #i:,id !r$'"%#' %r "oo !o#d9 "& $ )i## no" ")i'" %nd "& di'(#%$ )i## no" +or- %n i-%g 1 I+ "& di'(#%$ i' "oo )%r-9 "& r 'i'"%n! o+ "& #i:,id !r$'"%# -%" ri%# !&%ng ' %nd "&i' %#" r' "& (ro( r"i ' o+ "& di'(#%$ %nd ( r+or-%n! ',++ r'1 Li:,id !r$'"%# -%" ri%# +or di'(#%$ ,' i' nor-%##$ r + rr d "o %' TN .4TN9 D4TN9 M4TN9 %nd "!10 or T)i'" d N -%"i!??'o- "i- ' kno)n %' TNFE or T)i'" d N -%"i! Fi #d E++ !"1 I" i' !%## d T@I4TED 'in! "& !r$'"%#' %r ")i'" d 9< d gr ' .or -or +or 4TN0 +ro"& "o( (i ! o+ g#%'' "o "& /o""o- (i ! o+ g#%''1 .TN ,',%##$ r + r' on#$ "o % 9< d gr ")i'"10 Fi #d E++ !" .% dir !" !orr #%"ion i' "& ' -i!ond,!"or MO4FET09 r + r' "o "& LC -%" ri%#A' %/i#i"$ "o %#ign (%r%## # or ( r( ndi!,#%r "o %n %((#i d # !"ri! +i #d1 A' % r ',#"9 ,'ing ")i'" d or ,n")i'" d #i:,id !r$'"%# %nd ")o (o#%ri2 r'> %n %((#i d # !"ri! +i #d !%n +or! "& LC -%" ri%# in"o % (%r"i!,#%r %#ign- n" ++ !"i* #$ di++,'ing or (%''ing #ig&" "&ro,g& "& "o( (o#%ri2 r1 A' % no" o+ in" r '"9 (o#%ri2 r' %r %#'o on o+ "& -%7or r %'on' "&%" LC di'(#%$' r :,ir /rig&" /%!k #ig&"ing1 T& (o#%ri2 r' %nd #i:,id !r$'"%# -%" ri%#' %/'or/ -or "&%n 5<B o+ "& in!id n" #ig&"1 A' % r ',#"9 * n "&o,g& "& %!",%# di'(#%$ i' % * r$ #o) (o) r d *i! 9 "& (o) r &,ngr$ /%!k #ig&"ing -%k ' % LCD -od,# on o+ "& (ri-%r$ !%,' ' o+ '&or" /%"" r$ #i+ in no" /ook !o-(," r'1 D, "o "& +%!" "&%" "& LC -%" ri%# &%' o("i!%# (ro( r"i ' %nd ++ !"i* #$ / nd' #ig&"9 "& (ro/# - o+ *i )ing %ng# ++ !"' o!!,r1 @& n "& ,' r i' no" dir !"#$ in +ron" o+ "& di'(#%$ "& i-%g !%n di'%(( %r or ' - "o in* r" .d%rk i-%g ' / !o- #ig&" %nd #ig&" i-%g ' / !od%rk01 Ho) * r9 LC -%" ri%# %nd (o#%ri2 r " !&no#og$ i' r%(id#$ i-(ro*ing %nd "&%" i-(ro* - n" i' '&o)ing ,( in /rig&" r di'(#%$' )i"& gr %" r *i )ing %ng# '1

%i?ui# Cr.stal Ali2nment

Li:,id !r$'"%#' -,'" / %#ign d "o "& "o( %nd /o""o- (i ! ' o+ g#%'' in ord r "o o/"%in "& d 'ir d ")i'"1 In o"& r )ord'9 "& 9< d gr ")i'" i' +or- d /$ %n!&oring "& #i:,id !r$'"%# on on g#%'' (#%" %nd +or!ing i" "o ")i'" %!ro'' "& ! ## g%( ."& di'"%n! / ") n "& ")o g#%'' (#%" '0 )& n !on"%!"ing "& ' !ond (#%" 1 F,r"& r-or 9 T& %!",%# i-%g :,%#i"$ o+ "& di'(#%$ )i## / d ( nd n" on "& ',r+%! %#ign- n" o+ "& LC -%" ri%#1 T& - "&od !,rr n"#$ ,' d +or %#igning #i:,id !r$'"%#' )%' d * #o( d /$ "& D%i?Ni((on 4!r ning .Eng#i'&C Big J%(%n 4!r ning0 Co-(%n$1 T& (ro! '' !on'i'"' o+ !o%"ing "& "o( %nd /o""o- '& "' o+ g#%'' )i"& % Po#$i-id /%' d +i#-1 T& "o( (i ! o+ g#%'' i' !o%" d %nd r,// d in % (%r"i!,#%r ori n"%"ion> "& /o""o(%n #6(o#$i-id i' r,// d ( r( ndi!,#%r .9< d gr ' +or TN di'(#%$'0 )i"& r '( !" "o "& "o( (%n #1 I" )%' di'!o* r d "&%" /$ r,//ing "& (o#$i-id )i"& % !#o"&9 n%no- " r .3 D 3< ? 9 - " r'0 'i2 groo* ' %r +or- d %nd "& #i:,id !r$'"%#' %#ign )i"& "& dir !"ion o+ "& groo* '1 I" i' !o--on "&%" )& n %'' -/#ing % TN LC ! ##9 i" )i## / n ! ''%r$ "o #i-in%" (%"!& ' o+ non,ni+or- %r %'1 T& ")o (%r%- " r' r :,ir d "o #i-in%" "& non,ni+or-i"i ' %nd !o-(# " "& TN LC di'(#%$ %r (r "i#" %ng# %nd !&o# '" ri! i-(,ri"i '1 TN LC ! ##' !o--on#$ &%* ")o (ro/# -' "&%" %++ !" ,ni+or-i"$ +o##o)ing %'' -/#$: r * r' "i#" %nd r * r' ")i'"1 R * r' "i#" i' % +,n!"ion o+ "& %((#i d # !"ri!%# +i #d %nd r * r' ")i'" i' !o--on )& n no # !"ri!%# +i #d i' %((#i d1 R * r' ")i'" i' #i-in%" d /$ "& in"rod,!"ion o+ !&o# '" ri! %ddi"i* ' %nd r * r' "i#" i' #i-in%" d /$ in"rod,!ing % (r ?"i#" %ng# "o "& LC -%" ri%#1 T& (r ?"i#" %ng# %#'o d " r-in ' )&%" dir !"ion "& LC -o# !,# ' )i## ro"%" )& n %n # !"ri!%# +i #d i' %((#i d1 Pr ?"i#" %ng# !%n / *i',%#i2 d /$ !on'id ring "& nor-%# (o'i"ion o+ "& LC -o# !,# "o / +#%" %g%in'" "& g#%'' (#%" 9 /$ %n!&oring on dg %nd +or!ing "& o"& r ,()%rd /$ % '( !i+i! n,-/ r o+ d gr '9 % (r "i#" %ng# i' '"%/#i'& d1

Stepper Motor #un$amentals an$ @etails0


!ntro"*ction

Stepper motors are commonl" use$ in accurate motion control* The" allow to control an" motion with high precision b" counting the number of steps applie$ to the motor* Most of s"stems controlling stepper motors are embe$$e$ s"stems such as printer, scanner or flopp" $is6 $ri+e* This application note $escribes how to $ri+e a unipolar stepper motor with the &rogrammable Counter Arra" of an Atmel C514C151 microcontroller* There are two maDor t"pes of stepper motors0 &ermanent magnet stepper motors %unipolar stepper motors an$ bipolar stepper motors) an$ +ariable reluctance stepper motors %h"bri$ stepper motors)*

!"enti+ication o+ Stepper #otor


There are se+eral t"pes of stepper motors, these cannot be $ri+en in the same wa"* 3n this application note, we ha+e chosen to $ri+e a unipolar stepper motor #or more information "ou will fin$ schemes to i$entif" the other t"pes of stepper motors* .nipolar Stepper Motor .nipolar stepper motors are characterise$ b" their center-tappe$ win$ings* .nipolar Stepper Motor

-ipolar Stepper Motor -ipolar stepper motors are $esigne$ with separate coils* -ipolar Stepper Motor

=ariable (eluctance =ariable reluctance stepper motor %also calle$ h"bri$ motors) are characterise$ b" one common lea$*

=ariable (eluctance Stepper Motor

Dri/in$ 3nipolar Stepper #otors


There are three wa"s to $ri+e unipolar stepper motors %one phase on, two phase on or half step), each one has some a$+antages an$ $isa+antages*

T& r %r ")o '"%g ' "o 'or"ing o," )&i!& )ir i' )&i!& in % 5? or E?)ir ,ni(o#%r '" (( r -o"or: 31 *solate the Common ,o5er 5ire@sA /$ ,'ing %n o&-- " r "o !& !k "& r 'i'"%n! ' / ") n (%ir' o+ )ir '1 T& Co--on Po) r )ir )i## / "& on )i"& on#$ &%#+ %' -,!& r 'i'"%n! / ") n i" %nd %## "& o"& r'1 T&i' i' / !%,' "& Co--on Po) r )ir on#$ &%' on !oi# / ") n i" %nd %!& o"& r )ir 9 )& r %' %!& o+ "& o"& r )ir ' &%* ")o !oi#' / ") n "& -1 H n! &%#+ "& r 'i'"%n! 1 21 *#enti . the 5ires to the coils /$ ',((#$ing % *o#"%g on "& Co--on Po) r )ir .'0 %nd k (ing on o+ "& o"& r )ir ' gro,nd d )&i# gro,nding %!& o+ "& r -%ining "&r )ir ' in ",rn %nd o/' r*ing "& r ',#"'1 4 # !" on )ir %nd gro,nd i" A'',- i"A' !onn !" d "o !oi# F1 G (ing i" gro,nd d9 gro,nd %!& o+ "& o"& r "&r )ir ' on /$ on Hro,nding on )ir '&o,#d -%k "& ro"or ",rn % #i""# !#o!k)i' 1 T&%"A## / "& )ir !onn !" d "o Coi# =1 Hro,nding on )ir '&o,#d -%k "& ro"or ",rn % #i""# %n"i!#o!k)i' 1 T&%"A## / "& )ir !onn !" d "o Coi# 31 Hro,nding on )ir '&o,#d do no"&ing T&%"A## / "& )ir !onn !" d "o Coi# 21

Ste((er Motor &ri)er *C '%N2003

Pin Connection

Vo#"%g R g,#%"or IC .E# !"ri!%# C&%r%!" ri'"i!' o+ MCI8<50:


The MCE8>>4;ME8>>4MCE8>>A series of three terminal positi+e regulators are a+ailable in the TO-11:4@-&A! pac6age an$ with se+eral fi/e$ output +oltages, ma6ing them useful in a wi$e range of applications* 'ach t"pe emplo"s internal current limiting, thermal shut $own an$ safe operating area protection, ma6ing it essentiall" in$estructible* 3f a$e8uate heat sin6ing is pro+i$e$, the" can $eli+er o+er 1A output current* Although $esigne$ primaril" as fi/e$ +oltage regulators, these $e+ices can be use$ with e/ternal components to obtain a$Dustable +oltages an$ currents*

&eat*res
K Output Current up to 1A K Output =oltages of 5, 5, 8, 9, 1:, 11, 15, 18, 1 = K Thermal O+erloa$ &rotection K Short Circuit &rotection K Output Transistor Safe Operating Area &rotection

&in @iagram of the &ower 3C

T(pical Applications

Notes
%1) To specif" an output +oltage* substitute +oltage +alue for L>>*L A common groun$ is re8uire$ between the input an$ the Output +oltage* The input +oltage must remain t"picall" 1*:= abo+e the output +oltage e+en $uring the low point on the input ripple +oltage* %1) C3 is re8uire$ if regulator is locate$ an appreciable $istance from power Suppl" filter* %2) CO impro+es stabilit" an$ transient response*

S<CE#AT!C D!AG'A#

PCB Layout:

&(O9(AM in Assembl"0

Jprogram for a stepper ha+ing connecte$ at p1%form p1*: Jto p1*2)M to show message on the ;C@ $ata e8u p1 bus" e8u p1*E rs e8u p2*5 rw e8u p2* en e8u p2*2 b7r e8u p:*1 le$f e8u p:*: le$b e8u p:*1 org ::h show:0 $b N<elcome To AllN,N:N show10 $b NCurrent StationN,N:N show10 $b NAe/t StationN,N:N show20 $b Nsahibaba$N,N:N show 0 $b Nmohan nagarN,N:N Show50 $b NipecN,N:N org ::::h aDmp main org :::2h test0 mo+ c,p2*1 Dnc halt setb p:*1 reti halt0 clr b7r aDmp test main0 mo+ ie,I::h setb ea Jsetb e/:

Jtill 7ero blow on the b7r

here0 mo+ p1,I::h acall ini mo+ $ptr,Ishow: acall rea$ clr le$f Jp1*: acall $ela" mo+ a,I:1h acall comman$J Aow ma6e memor" clear cursor home mo+ $ptr,Ishow1 acall rea$ setb e/: JIIIIIIIIIIIII mo+ a,I:c:h acall comman$ mo+ $ptr,Ishow2 acall rea$ acall $ela" JStopage1 time 2 sec roo6ee acall $ela" clr b7r acall $ela" mo+ a,I:1h acall comman$ mo+ $ptr,Ishow1 acall rea$ mo+ a,I:c:h acall comman$ mo+ $ptr,Ishow acall rea$ setb b7r acall $ela"1: acall stepperf mo+ a,I:1h acall comman$ mo+ $ptr,Ishow1 acall rea$ mo+ a,I:c:h acall comman$ mo+ $ptr,Ishow acall rea$ acall $ela" JStopage1 time 2 sec shsar

acall $ela" clr b7r acall $ela" mo+ a,I:1h acall comman$ mo+ $ptr,Ishow1 J$ispla" ne acall rea$ mo+ a,I:c:h acall comman$ mo+ $ptr,Ishow5 acall rea$ setb b7r acall $ela"1: acall stepperf mo+ a,I:1h acall comman$ mo+ $ptr,Ishow1 acall rea$ mo+ a,I:c:h acall comman$ mo+ $ptr,Ishow5 acall rea$ acall $ela" JStopage1 time 2 sec Meerut acall $ela" clr b7r acall $ela" setb le$f clr le$b J J p1*: Joff le$ at p1*: for forwar$ Dourne" p1*1 J :n ;e$ for bac6 war$ Dourne"

mo+ a,I:1h acall comman$ mo+ $ptr,Ishow1 J$ispla" ne acall rea$ mo+ a,I:c:h acall comman$ mo+ $ptr,Ishow acall rea$ setb b7r acall $ela"1: acall stepperb

shar

mo+ a,I:1h acall comman$ mo+ $ptr,Ishow1 acall rea$ mo+ a,I:c:h acall comman$ mo+ $ptr,Ishow acall rea$ acall $ela" JStopage1 time 2 sec shsar acall $ela" clr b7r acall $ela" mo+ a,I:1h acall comman$ mo+ $ptr,Ishow1 J$ispla" ne acall rea$ mo+ a,I:c:h acall comman$ mo+ $ptr,Ishow2 acall rea$ setb b7r acall $ela"1: acall stepperb mo+ a,I:1h acall comman$ mo+ $ptr,Ishow1 acall rea$ mo+ a,I:c:h acall comman$ mo+ $ptr,Ishow2 acall rea$ setb le$b Jp1*1 lDmp here Jroutine for stepper motor J @ela" (outine Jone sec $ela" $ela"0

roor

push acc push ::h push :1h push p: push p1 mo+ r:,I:eh loopr0 mo+ a,I:ffh loopb0 mo+ b,I:ffh loopa0 $Dn7 b,loopa $Dn7 :e:h,loopb $Dn7 r:,loopr pop p1 pop p: pop :1h pop ::h pop acc ret J$la" stepper $ela"s0 push acc push ::h push :1h push p: push p1 mo+ a,I:ffh loopa10 mo+ b,I:fh loopb10 $Dn7 b,loopb1 $Dn7 :e:h,loopa1 pop p1 pop p: pop :1h pop ::h pop acc ret

$ela"1:0 mo+ tmo$,I:1h mo+ tcon,I::h mo+ tl:,I:f:h mo+ th:,I:f8h setb tr: no0 Dnb tf:,no clr tr: clr tf: ret JCCCCCCCCCCCCCCC (outine to rea$ $ata from prog mem rea$0 ne/0 clr a mo+c a,?aO$ptr cDne a,IN:N,aga sDmp $own aga0 acall $ispla" inc $ptr sDmp ne/ $own0 ret JCCCCCCCCCCCCCCCC stepper routine stepperf0 push acc push p1 mo+ a,I88h mo+ r1,I: h loop10 mo+ r:,I:e:h loop0 mo+ p1,a acall $ela"s rr a $Dn7 r:,loop $Dn7 r1,loop1 pop p1 pop acc ret stepperb0 push acc push p1

mo+ a,I88h mo+ r1,I: h loop110 mo+ r:,I:e:h loop:0 mo+ p1,a acall $ela"s rl a $Dn7 r:,loop: $Dn7 r1,loop11 pop p1 pop acc ret JPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP J;C@ strobe subroutines ini0 mo+ a,I28h acall comman$ mo+ a,I28h acall comman$ mo+ a,I28h acall comman$ mo+ a,I28h acall comman$ mo+ a,I:eh acall comman$ mo+ a,I:5h acall comman$ mo+ a,I:1h acall comman$ mo+ a,I8:h acall comman$ ret comman$0 acall rea$" mo+ $ata,a clr rs clr rw setb en clr en ret

$ispla"0 acall rea$" mo+ $ata,a setb rs clr rw setb en clr en ret rea$"0 clr en mo+ $ata,I:ffh clr rs setb rw wait0 clr en setb en Db bus",wait clr en ret en$

Co%ponent=s List +or Pro>ect


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