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You should now be familiar with the Binary, Decimal and Hexadecimal Number System. If we view single digit values for hex, the numbers 0 F, they represent the values 0 - 15 in decimal. Often, we wish to use a binary equivalent of the decimal system. This system is called Binary Coded Decimal or BCD. Each decimal digit 0~9 is represented by 4 binary bits 0000 to 1001. In BCD number system, the binary patterns 1010 through 1111 do not represent valid BCD numbers, and cannot be used. For example, a decimal number 26410 can be represented as BCD numbers 001001100100BCD.

To convert from BCD to decimal, simply reverse the process as an example below:

As you can see, BCD number system is designed for the convenience of showing decimal number using binary data.

We will design a combinational circuit to convert an 8-bit binary number to 12-bit BCD. Why 12-bit for the BCD? The 8-bit binary number can present an integer from 0 to 255. Therefore, we need 3 decimal digits. As we see from Section 1, each decimal digit is represented by a 4-bit BCD. Therefore, we need 3*4 = 12-bit BCD. The BCD number is particularly useful when we try to display numbers in decimal format. A binary to BCD converter will be used frequently in our future labs to display numbers. After all, people are so used to the decimal number format. We begin to design the binary to BCD convert by introducin g the shift and add-3 algorithm. 1. Shift the binary number left one bit. 2. If 8 shifts have taken place, the BCD number is in the Hundreds, Tens, and Units column. 3. If the binary value in any of the BCD columns is 5 or greater, add 3 to that value in that BCD column. 4. Go to 1. 1

For example, lets convert FF (11111111) into BCD format by using the above algorithm.

In Verilog, we can also simply list the truth table and the synthesis tool will analyze and implement it in an optimized form. Here is a Verilog module for this truth table.

module add3(in,out); input [3:0] in; output [3:0] out; reg [3:0] out; always @ (in) case (in) 4'b0000: out 4'b0001: out 4'b0010: out 4'b0011: out 4'b0100: out 4'b0101: out 4'b0110: out 4'b0111: out 4'b1000: out 4'b1001: out default: out endcase endmodule

<= <= <= <= <= <= <= <= <= <= <=

4'b0000; 4'b0001; 4'b0010; 4'b0011; 4'b0100; 4'b1000; 4'b1001; 4'b1010; 4'b1011; 4'b1100; 4'b0000;

It consists of 7 add-3 components. To skip all the details, here is a structural Verilog module corresponding to the logic diagram.

module binary_to_BCD(A,ONES,TENS,HUNDREDS); input [7:0] A; output [3:0] ONES, TENS; output [1:0] HUNDREDS; wire [3:0] c1,c2,c3,c4,c5,c6,c7; wire [3:0] d1,d2,d3,d4,d5,d6,d7; assign d1 = {1'b0,A[7:5]}; assign d2 = {c1[2:0],A[4]}; assign d3 = {c2[2:0],A[3]}; assign d4 = {c3[2:0],A[2]}; assign d5 = {c4[2:0],A[1]}; assign d6 = {1'b0,c1[3],c2[3],c3[3]}; assign d7 = {c6[2:0],c4[3]}; add3 m1(d1,c1); add3 m2(d2,c2); add3 m3(d3,c3); add3 m4(d4,c4); add3 m5(d5,c5); add3 m6(d6,c6); add3 m7(d7,c7); assign ONES = {c5[2:0],A[0]}; assign TENS = {c7[2:0],c5[3]}; assign HUNDREDS = {c6[3],c7[3]}; endmodule

module B_BCD ( ena, binary, bcd ); parameter B_SIZE = 11; input binary, ena; output bcd; wire ena; wire [B_SIZE-1 : 0] binary; reg [B_SIZE-1 : 0] bin; reg [B_SIZE+3 : 0] bcd; reg [B_SIZE+3: 0] result; always@( binary or ena ) begin bin = binary; result = 0; if ( ena == 0 ) bcd <= 0; else 4

begin repeat ( B_SIZE-1 ) begin result[0] = bin[B_SIZE-1]; if ( result[3 : 0] > 4 ) result[3 : 0] = result[3 : 0] + 4'd3; if ( result[7 : 4] > 4 ) result[7 : 4] = result[7 : 4] + 4'd3; if ( result[11 : 8] > 4 ) result[11 : 8] = result[11 : 8] + 4'd3; result = result << 1; bin = bin << 1; end result[0] = bin[B_SIZE-1]; bcd <= result; end end endmodule

4. The top level module also includes the LED display diver

module top ( input [7:0] A, input clk, output [3:0] an, output [6:0] disp, output dp ); wire [3:0] ones, tens; 5

wire [3:0] hundreds; wire [3:0] y; B_BCD fsm hex7seg bcd_inst (1'b1, {3'b0,A}, {hundreds, tens, ones}); fsm_inst (clk, ones, tens, hundreds, 4'b0, an, y, dp); hex_inst (y, disp);

endmodule

NET "clk" LOC = "V10" ;

NET "A[0]" LOC = "T10"; NET "A[1]" LOC = "T9"; NET "A[2]" LOC = "V9"; NET "A[3]" LOC = "M8"; NET "A[4]" LOC = "N8"; NET "A[5]" LOC = "U8"; NET "A[6]" LOC = "V8"; NET "A[7]" LOC = "T5";

NET "an[3]" LOC = "P17" ; NET "an[2]" LOC = "P18" ; NET "an[1]" LOC = "N15" ; NET "an[0]" LOC = "N16" ; NET "disp[6]" LOC = "T17" ; NET "disp[5]" LOC = "T18" ; NET "disp[4]" LOC = "U17" ; NET "disp[3]" LOC = "U18" ; NET "disp[2]" LOC = "M14" ; NET "disp[1]" LOC = "N14" ; NET "disp[0]" LOC = "L14" ; NET "dp" LOC = "M13";

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