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IBM SRDC

FINFET on SOI

Terence Hook IBM SRDC


FDSOI Workshop, San Francisco, California, 2012

IBM Semiconductor Research and Development Center

Outline
FinFet and FDSOI
Similarities Electrostatics Access resistance Threshold fluctuations Differences Physical Orientation Density Backgate effect Process sequence Structural results Similarities and Differences with PDSOI planar

Finfet on SOI substrates


Finfet on bulk
Similarities and differences with bulk planar Effects of doping

Feb 24, 2012

A decade of Finfets at IBM a representative survey


2001
D. Fried DRC J. Kedzierski IEDM

IBM Semiconductor Research and Development Center

2002 2003
E.Nowak IEDM

E.Nowak CICC

K.Maitra EDL

2009
V. Basker, VLSI H. Kawasaki IEDM

2010 2011
T. Yamashita VLSI

50nm

10nm

P. Oldiges EDL.

T. Yamashita, VLSI

J. Chang VLSI Looking ahead to 4nm!

Feb 24, 2012

IBM Semiconductor Research and Development Center

FINFET (ie, DG) electrostatics

Gate

Gate

/2

Gate D S Gate D

S BOX Substrate

= tdep +si/oxtox L ~ 1/N


Scaling requires increased doping loss, GIDL, high Cj, RDF
2004 IEEE SOI Short Course Huang & Nowak

= 2(tsi +si/oxtox) Lmin ~ 3tsi+9tox

= tsi +si/ox2tox Lmin ~ 1.5tsi+9tox

Finfet device of same minimum channel length has ~twice the body thickness of FDSOI device D. Frank, et al.

Feb 24, 2012

IBM Semiconductor Research and Development Center

Electrostatic Advantages of Fully-depleted (FD) device


Short channel effects controlled by geometry of device Use of fully-depleted (FD) device helps obtain DIBL <100 mV for L<25nm DIBL reduction on FD devices has been achieved on hardware

Sub-threshold slope improvement Mobility improvement due to lower electric field Lack of doping in body lower intrinsic variability
200 DIBL@0.9V

FinFET vs. PDSOI DIBL control

150 100 50 0 15

Dfin=10nm Tinv=1.8nm

45nm node PDSOI Dfin=15nm Tinv=1.8nm

Dfin=10nm Tinv=1.2nm
20 25 30 Lgate

FinFET
35 40 45

Feb 24, 2012

IBM Semiconductor Research and Development Center

Superior Vdd Scalability of AC Performance

PDSOI

SOI FINFET

Superior Vdd scalability of RO AC performance in FINFET due to much improved electrostatics.

Feb 24, 2012

IBM Semiconductor Research and Development Center

PDSOI FDSOI Finfet FDSOI


Gate
Drain

Gate
Drain

Source

Current flow

Gate

Current flow
Source

Current flow
Source

Drain

PDSOI
Drain

FDSOI

Source

Source

Current flow

Current flow

Gate

Gate
Fi n
Source

Gate

nt e r ur C flow

Drain

Drain

FinFET
Feb 24, 2012

IBM Semiconductor Research and Development Center

FINFET Cross-sections
BOX
BOX

W contact

Tfin = 40nm

Lgate = 140nm

Gate Fin
drain source

flo current

Cross-section parallel to fin


Feb 24, 2012

Cross-section perpendicular to fin

IBM Semiconductor Research and Development Center

Mobility on <110> surface


Electron Mobility (cm2V s )
-1 -1

500

Hole Mobility (cm2V -1s-1 )

400 300 200 100 0 0

Un

NFET
ive r sal (1 00 )c u rv e

180 160 140 120 100 80 60 40 20 0 0 2 4 6 8 10

PFET
Univ

ersa l (1

00) curv e

N inv

(X1012cm-2 )

10

15

12

14

16

Ninv

(X1012

cm-2 )

Channel is formed on <110> surface when fins are formed from (100) substrate PFET mobility improves significantly
~2x improvement as expected

(100)
10 1 < >

Measurements show NFET mobility not degraded significantly


NFET degradation is <20%

V. Basker, IBM, VLSI 2011

Feb 24, 2012

IBM Semiconductor Research and Development Center

Electrical vs. Physical FET Width - Fin-Effect FinFETs are like The Tardis Electrical WEFF ~ 1.5 x WPhysical possible. FET Specifications quoted per WEFF Physical Densities can be up to 1.5X higher (C and I)

t n i r p t o Fo

80nm 10nm
Ch an n

WPY=80nm
cu rre n t

af er

Representative calculation of reasonable dimensions

25nm

el

WEFF= 2 x (25nm + 10nm + 25nm) = 120nm

(gate not shown)


Feb 24, 2012

IBM Semiconductor Research and Development Center

Access resistance
FDSOI Finfet

Both thin-body devices use epitaxy to dope and fatten the body beyond the gate Modern bulk and SOI use epitaxial source/drains also
Feb 24, 2012

IBM Semiconductor Research and Development Center

Current flow from fin into contact is 3-dimensional

G
With the gate removed the active fins may be seen

S D

Feb 24, 2012

IBM Semiconductor Research and Development Center

Epitaxy engineering

Merged epitaxy

Yamashita et al, ECS 2011

Unmerged epitaxy
Engineering the connection to the thin body is the subject of much work in both FDSOI and Finfet

Feb 24, 2012

IBM Semiconductor Research and Development Center

Threshold Fluctuations

Liu et al., VLSI 2010

Endo et al., IEDM 2011

In the ideal case the bodies of both FDSOI and Finfet are undoped, which eliminates random dopant fluctuation as a component of threshold variation
Feb 24, 2012

Hook et al., IEDM 2011

IBM Semiconductor Research and Development Center

Substrate effect

Hook et al., SOI 2011

Backgate In FDSOI there are two (maybe 1 and ?) gates and the threshold voltage may be modulated (dynamically if desired) by the potential on the back gate
This is similar, but superior, to the bulk fet case This is similar to the PDSOI case but for a different reason In PDSOI the substrate is shielded from the device by body doping In Finfet only a small portion of the device is exposed to the substrate potential

In Finfet the substrate bias has little effect on the device

Feb 24, 2012

IBM Semiconductor Research and Development Center

Simplified Process:
SOI starting wafer

FinFET On SOI

Si3N4/SiO2

Conventional SOI

silicon Nitride/oxide Films, Etch silicon fins and source/drain regions. Conventional SOI, Only: Shallow Trench Sequence: Oxidize sidewall Dep SiO2 Plaraize Strip pad films.
Feb 24, 2012

Nitride/oxide Films, Etch silicon islands Oxide isolation planarization.

silicon Trench Fill (SiO2)

IBM Semiconductor Research and Development Center Process Flow 2

FinFET SOI

Conventional SOI
spacers

Gate

- Gate deposition (dummy gate), planarization, pattern & etch. - Spacers - Ion-Implant extensions and halos (optional in FinFET)

Feb 24, 2012

IBM Semiconductor Research and Development Center Process Flow 3

FinFET SOI

Conventional SOI
Selective Epitaxial Growth

-Merge Fins (Grows epi Si/SiGe/SiC) -Insitu-doped or I/I

-Etch S/D silicon regions -Grow S/D epi (strain regions) -Insitu-doped or I/I

Feb 24, 2012

IBM Semiconductor Research and Development Center Process Flow 4

FinFET SOI

Conventional SOI
Remove dummy gate, replace w/ metal

-Replacement Gate Sequence -Flow same in planar and Fin

Feb 24, 2012

IBM Semiconductor Research and Development Center Process Flow 5

FinFET SOI

Conventional SOI

-MOL Sequence -Flow same in planar and Fin -Vias, Silicide -Contacts to S/D -Contacts to gate (not illustrated)

Feb 24, 2012

IBM Semiconductor Research and Development Center

Finfet formation on SOI


Fin height is silicon thickness

Inter- and intradevice isolation is accomplished by removing unwanted fins


Feb 24, 2012

IBM Semiconductor Research and Development Center

FIN Uniformity is Critical for SCE/Variability Control


T. Yamashita, IBM, VLSI 2011 Process A
200
NFET Lgate=25nm

150

DIBL (mV)

Process A
Conventional SIT process

(a)

100

(b)

Process B

50

New SIT process

Process B
0 0 5 10 15 20 25 30 35

Fin number

Edge FIN profile is important; the challenge can be addressed by Cut-last (cut unwanted FIN post FIN definition).

Feb 24, 2012

IBM Semiconductor Research and Development Center

Fins and PDSOI


Like PDSOI:
No isolation wells No latchup concerns Low source/drain parasitic capacitance Floating-node antenna design rules apply

Unlike PDSOI:
No history effect No body contacted devices possible (or needed!) Device width is quantized

Feb 24, 2012

IBM Semiconductor Research and Development Center

SOI FINFET vs. Bulk FINFET

Active fin height set by SOI thickness


Feb 24, 2012

Active fin height set by oxide thickness and etched fin height

Bottom portion (at least) of the fin needs to be doped

IBM Semiconductor Research and Development Center

Punchthrough, or bulk-fet region

There must be enough doping to prevent this region from dominating the off-state conduction

Feb 24, 2012

IBM Semiconductor Research and Development Center

Suppressing Sub-Fin Leakage in Bulk MuGFETs


Ideal case s/d Pull Back Additional PC pull-down

(1)

(2)

(3)

1) In a perfect world.

1E-9 Imin/Weff (A/um)

2) Reduce RSD height relative to Hfin (deltaHsd) gate extends below S/D permits fin/substrate doping reduction, but requires same Hfin as #1. 3) Reduce Hfin and extend gate into local trench (deltaHg) to recover Wchannel from Hfin reduction similar effect as #2. In real world, we can pull back source/drain depth and pull-down PC to overcome device variability - this can impose a performance hit (both R and C penalty).

W10H30, deltaHsd=0 W13H24, deltaHsd=0 W10H30, deltaHsd=10 W13H24, deltaHsd=10

BTBT

1E-10
Reduced sub-fin thermal leakage

R. Vega, IBM
Feb 24, 2012

1E-11 1E+17 1E+18 Doping (cm-3) 1E+19

IBM Semiconductor Research and Development Center

FIN Doping Some Boundary Condition

C.H. Lin, IBM Similar to planar device, channel doping is an effective knob for Vt tuning (and multiVt solution). Due to the constraint on Vtmm and AVT, the maximum doping allowed in channel is ~1-2E18/cm3.
Feb 24, 2012

IBM Semiconductor Research and Development Center

FIN Doping Impact on Mobility


200 150
Mobility, arb units
High Field = 1MV/cm of Inversion charge 1015 1017 1018

Mob5

100 50
Esimate of 6e18

0 0.0 0.5 1.0 1.5 2.0 2.5

Edge, Linder, IBM

Eeff5Eeff (MV/cm)
Scaling BULK and PDSOI SCE beyond 32nm requires body doping in excess of 5e18/cm3 - Mobility significantly degraded. Undoped or Lightly doped FIN helps carrier mobility in addition, device is parked at lower vertical field at fixed Vdd, additional boost in mobility.
Feb 24, 2012

IBM Semiconductor Research and Development Center

Fins and bulk planar


Like bulk planar:
Use conventional nfet/pfet isolation wells Conventional latchup tap rules Conventional bulk antenna design rules apply

Unlike bulk planar:


No body contacted devices possible (or needed!) Device width is quantized Negligible body effect

Something like bulk planar:


Subsurface drain-source punchthrough suppression Junction area capacitance

Feb 24, 2012

IBM Semiconductor Research and Development Center

Finfets on SOI
Electrostatic benefits like FDSOI
Low voltage, high threshold operation Obviates need for tinv and Xj scaling

Low doping benefits like FDSOI


High mobility Low RDF

Some challenges similar to FDSOI


Epitaxial source/drain and access resistance

Some aspects entirely different than FDSOI


3D processing 3D density effect Width quantization

SOI is a convenience for Finfet while it is intrinsic to FDSOI


Bulk finfet is a viable option

Feb 24, 2012

IBM Semiconductor Research and Development Center

Acknowledgement
The talk is based on the work of, as well as discussions with: H. Bu E. Nowak A. Bryant J. Johnson C.H. Lin M. Fujiwara J. Cho R. Miller T. Yamashita R. Vega P. Zeitzoff V. Basker T. Standaert And many others in Albany, Burlington, and East Fishkill

Feb 24, 2012