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Semiconductor Materials

and Device Laboratory


J ong-Ho Lee
jhl@snu.ac.kr
School of EECS and ISRC, Seoul National University
Bulk FinFETs: Fundamentals,
Modeling, and Application
1
Introduction
Fundamentals of Bulk FinFETs
Modeling
Applications
Conclusions
Outline
The scaling of conventional planar MOSFETs has been facing
problems such as subthreshold swing degradation, significant
DIBL, fluctuation of device characteristics, and leakage.
To solve the problems, 3-D device structures could be a solution
and have been studied.
FinFETs (built on bulk silicon or SOI wafers) among 3-D devices
are very promising candidate for future nano-scale CMOS
technology and high-density memory application.
For the bulk FinFETs which is going to be applied to mass
production, we discuss about fundamental properties, modeling,
and application of the bulk FinFETs.
Introduction
2
Whats bulk FinFET?
FinFET
SOI FinFET Bulk FinFET
3-D view of
bulk FinFET
Si Sub
SiO
2
G
fin
Si Sub
SiO
2
G
fin
Low wafer cost
Low defect density
No floating body effect
High heat transfer rate
to substrate
Good process compatibility
S/D
S/D
H
Fin
x
j
0
W
Fin
T
FOX
Heat
- Korea/USA patent
Bulk FinFETs (Double- or Tri-gate MOSFETs)
I
D
-V
GS
Characteristics of 40 nm bulk N FinFET
3
S/D
S/D
HFin
xj
0
WFin
TFO
X
Heat
Comparison between Our Structure and Intels
Our Structure Intels Structure Conventional
Planar Structure
4
5
As
+
, 20 keV 3x10
15
/cm
2
, 2 Fin
25 nm
50 nm
40 nm
-0.5 0.0 0.5 1.0 1.5
10
-10
10
-9
10
-8
10
-7
V
DS
= 0.1 V


Vbs = 0 V
Vbs = -1 V
Vbs = -2 V
D
r
a
i
n

C
u
r
r
e
n
t

(
A
)
Gate Voltage (V)
I
D
-V
GS
Characteristics of 40 nm bulk N FinFET
Oxide
Si
CMP and
partial etch-back
Poly-Si
40 nm
Gate Poly-Si Etching
- T. Park et al., SNU/KNU, Physica E19, p.6, 2003
- T. Park et al., SNU/KNU, Nanomes03 2003
Top Si Width 25 nm
Bottom Si Width 100 nm
Si Fin Height 230 nm
First Bulk FinFET in the World
- T. Park et al., SNU/Samsung/KNU, p.135, Symp. on VLSI Tech. 2003
-0.5 0.0 0.5 1.0 1.5 2.0
10
-14
10
-13
10
-12
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
Conv. DRAM Cell Tr.
DIBL = 108 mV/V
Vds = 0.1 V
Vds = 0.6 V
Vds = 1.1 V
Vds = 1.6 V

D
r
a
i
n

C
u
r
r
e
n
t

(
A
)
Gate Voltage (V)
Vbs = 0 V
FinFET
DIBL = 24 mV/V

Fin Top Width = 30 nm
Fin Bottom Width = 61 nm
Fin Height = 99 nm
L
DRAWN
= 120 nm
W = 120 nm
L = 120 nm
181 nm
99 nm
61 nm
30 nm
82
Si Substrate
SiO
2
Poly-Si
fin body
SEM cross-section
G
a
t
e

E
l
e
c
t
r
o
d
e
S
i
O
2
S
i
N
S
i

S
u
b
s
t
r
a
t
e
F
i
n
S
iO
2
6
First Bulk FinFET at Industry
7
Introduction
Fundamentals of Bulk FinFETs
Modeling
Applications
Conclusions
Outline
Gate
Oxide
Fin
Gate
Fin
Gate
Fin
(a) (b) (c)
DG Structure TG Structure
90
o
Corner Half-circle Corner
8
Body Shape of FinFET
10 20 30 40 50
0.1
0.2
0.3
0.4
0.5
N
b
=1x10
19
cm
-3
T
ox
=1.5 nm
x
j,S/D
=66 nm
H
fin
=70 nm

Bulk
SOI
Fin Width (nm)
V
t
h

(
V
)
L
g
=25 nm
0
30
60
90
120
150
180
D
I
B
L

(
m
V
/
0
.
9
V
)
10 20 30 40 50
70
75
80
85
90
95
100
x
j,S/D
=66 nm
H
fin
=70 nm
N
b
=1x10
19
cm
-3
T
ox
=1.5 nm
L
g
=25 nm
V
DS
=0.9 V

S
u
b
t
h
r
e
s
h
o
l
d

S
w
i
n
g

(
m
V
/
d
e
c
)
Fin Width (nm)
Bulk
SOI
V
DS
=0.05 V

The bulk FinFETs (solid circles) have nearly the same V
th
, DIBL, and SS
characteristics as those of SOI FinFETs (open circles).
V
th
& DIBL SS
9
Equivalent FinFET on Bulk and SOI Wafers
Equivalent FinFET on Bulk and SOI Wafers
Tri-gate on bulk-silicon and SOI substrates have similar short channel
performance
- Source: Intel
Low body doping: x
j,SDE
>H
fin
DIBL & SS (due to bulk punch-through)
Medium body doping: x
j,SDE
~ H
fin
+ 10 nm
To prevent bulk punch-through : x
j,SDE
H
fin
and/or local doping
20 40 60 80 100
0
100
200
300
T
ox
=1.5 nm
u
m
=4.7 eV
H
fin
=70 nm

N
b
=1x10
16
cm
-3
N
b
=5x10
16
cm
-3
N
b
=5x10
16
cm
-3
N
b
=1x10
17
cm
-3
SDE J unction Depth (nm)
D
I
B
L

(
m
V
/
V
)
W
fin
=20 nm
V
DS
=0.05 V
L
g
=50 nm
+local doping
(x
p
=70 nm)
70
80
90
100
110
120
130
S
S

(
m
V
)
S/ D
S/ D
Fin body
Local doping
x
p S/ D
S/ D
Fin body
Local doping
x
p
Local doping
x
p
=70 nm
N
Local
=1x10
18
cm
-3
11
S/D Junction Depth Design of Bulk FinFET
Heat transfer rate : Bulk SOI
Bulk FinFET has a device temperature less by 130
o
C than SOI FinFET at a
fixed V
GS
of 0.9 V.
-0.2 0.0 0.2 0.4 0.6 0.8 1.0
300
325
350
375
400
425
450
475
130
o
C
Bulk
SOI

V
DS
=0.9 V
T
ox
=1.5 nm

D
e
v
i
c
e

T
e
m
p
e
r
a
t
u
r
e

(
K
)
Gate Voltage (V)
L
g
=30 nm

12
Device Temperature Characteristics
- Si Nanoelectronics, 102-103, 2003
-1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50
0.0
0.1
0.2
0.3
0.4
0.5
W
Fin
: 10, 15, 20, 30, 50 nm
W
Fin
: 10, 15, 20, 30, 50 nm
Body Bias (V)
V
T

(
V
)
70
80
90
100
110
120
S
u
b
t
h
r
e
s
h
o
l
d

S
w
i
n
g

(
m
V
/
d
e
c
)
L
G
=25 nm
No V
T
increase at
a given back bias
S B
G G
- Silicon Nanoelectronics workshop, p.102, 2003
Back-bias Effect
Properties of Bulk FinFETs
13
V
th
s of three devices are the same by using gate workfunction engineering.
Bulk and SOI FinFETs have an ignorable back bias effect.
-0.4 -0.2 0.0 0.2 0.4 0.6
0.1
0.2
0.3
0.4
0.5
V
DS
=0.05 V
@V
BS
=0 V
V
th0
=0.35 V
Width=200 nm
u
m
=4.33 eV
T
ox
=1.5 nm
H
g
=100 nm
L
g
=50 nm
Bulk FinFET
SOI FinFET
Planar MOSFET
V
t
h

(
V
)
V
BS
(V)
N
b
=2x10
18
cm
-3


W
fin
=20 nm
u
m
=4.51 eV
14
Back-Bias Effects
80 82 84 86 88 90 92
80
90
100
110
120
L
G
=30 nm
H
Fin
=70 nm W
Fin
=20 nm
Angle (u) (deg)
D
I
B
L

(
m
V
/
V
)
u
N
a
=1x10
19
cm
-3
n
+
poly gate
70
80
90
100
110
120
S
S

(
m
V
)
20 nm
Fin
-0.2 0.0 0.2 0.4 0.6 0.8 1.0
0.6
0.7
0.8
0.9
1.0
1.1
1.2
V
DS
=0.9 V
V
DS
=0.05 V







W
Fin
=20nm
H
Fin
=70nm
L
G
=30nm
90
o
83.3
o
81.6
o
Gate Bias (V)
N
o
r
m
a
l
i
z
e
d

D
r
a
i
n

C
u
r
r
e
n
t
Device Characteristics with Body Angle
Tapered fin widens degraded
SCEs
Closer to 90o of body angle, better
DIBL and drain current
Impact of Fin Profile
Rectangular Fin profile improves SCEs for L
G
scaling:
Lowers AS
SAT
Lowers DIBL
- Symp. on VLSI Tech, Intel, 2006
Gate
Fin
Si Substrate
Gate
Fin
BOX
(a) (b) (c) (d)
Bulk SOI
Gate
Fin
BOX
Gate
Fin
BOX
Process variation
17
Bottom Corner Effect
- Invited talk at ECS, ECS
Transactions, 19 (4) 101-112 (2009)
I
off
: (a) < (b) < (c) < (d)
-0.2 0.0 0.2 0.4 0.6 0.8 1.0
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
H
fin
=70 nm
V
DS
=0.05 V
V
DS
=0.9 V
n
+
poly gate
T
ox
=1.5 nm
W
fin
=20 nm
L
g
=100 nm
Bulk FinFET (a)
SOI FinFET (b)
SOI FinFET (d)


I
D

(
A
)
V
GS
(V)
N
b
=2x10
18
cm
-3
(a) (b) (c) (d)
0.01
0.02
0.03
0.04
0.05
0.06
SOI

T
h
r
e
s
h
o
l
d

V
o
l
t
a
g
e

(
V
)

Bulk
V
th
: (a) > (b) > (c) > (d)
I
D
vs V
GS
V
th
vs Structure
18
Bottom Corner Effect
W
fin
DIBL & V
th

Low doped bulk or SOI FinFETs narrow W
fin
for good characteristics
5 10 15 20
0.30
0.32
0.34
0.36
0.38
0.40
Simulation
Model
Fin Width (nm)
V
t
h

(
V
)
H
fin
=70 nm
L
g
=30 nm
N
b
=5X10
16
cm
-3
u
m
=4.71 V
0
50
100
150
200
250
300
350
body
Si substrate
W
Fin
Gate
T
OX
oxide
Local doping @ x
P
=80 nm
D
I
B
L

(
m
V
/
V
)
Rounded corner
corner effect
Low doped channel
N
b
=5x10
16
cm
-3
Local doping
x
p
=80 nm
N
Local
=3x10
18
cm
-3
19
Fin Body Width Effect of Bulk FinFET with Low N
b
Planar MOSFET : Delay Time (due to V
th
) with negatively increasing V
BS
SOI or Bulk FinFETs : nearly constant Delay Time with V
BS
more
effective devices for the full-down circuits
-0.50 -0.25 0.00 0.25
0.8
1.0
1.2
1.4
1.6
Planar MOSFET
Bulk FinFET
SOI FinFET

N
o
r
m
a
l
i
z
e
d

D
e
l
a
y

T
i
m
e


V
BS
(V)
N
b
=2x10
18
cm
-3
C=20 fF
T
ox
=1.5 nm L
g
=50 nm

-0.50 -0.25 0.00 0.25
0.8
1.0
1.2
1.4
1.6




V
1
C V
b
V
cc
V
in
Full-down delay time vs V
BS
Inverter circuit
Speed Characteristics
- ECS meeting (invited talk), May, 2008
20
(a) Small signal equivalent circuit for RF device modeling.
(b) Comparison of RF parameters extracted from bulk and SOI DG FinFETs.
C
gd
R
g
v
gs
Gate
Drain
Substrate
g
m
v
gs C
m
dt
dVgs
C
gs
g
mb
v
bs
g
ds
C
sd
v
bs
C
jd
C
js
R
sub
Source
P
O
R
T
1
P
O
R
T
2
Intrinsic Body
C
gd
R
g
v
gs
Gate
Drain
Substrate
g
m
v
gs C
m
dt
dVgs
C
m
dt
dVgs
C
gs
g
mb
v
bs
g
ds
C
sd
v
bs
C
jd
C
js
R
sub
Source
P
O
R
T
1
P
O
R
T
2
Intrinsic Body
177 GHz 170 GHz f
T
-0.0033 fF -0.0037 fF C
sd
-fF 0.0151 fF C
js
- 8200 R
sub
-fF 0.014 fF C
jd
472 461 R
g
0.038 fF 0.037 fF C
gd
0.073 fF 0.0713 fF C
dg
0.113 fF 0.116 fF C
gs
0.414 S 0.427 S g
ds
166 S 160 S g
m
0.286 V 0.31 V V
th
SOI DG
FinFET
Bulk DG
FinFET
177 GHz 170 GHz f
T
-0.0033 fF -0.0037 fF C
sd
-fF 0.0151 fF C
js
- 8200 R
sub
-fF 0.014 fF C
jd
472 461 R
g
0.038 fF 0.037 fF C
gd
0.073 fF 0.0713 fF C
dg
0.113 fF 0.116 fF C
gs
0.414 S 0.427 S g
ds
166 S 160 S g
m
0.286 V 0.31 V V
th
SOI DG
FinFET
Bulk DG
FinFET
(a) (b)
21
Speed Characteristics
20 30 40 50 60 70
0.1
0.2
0.3
0.4
0.5
L
g
=100 nm
T
ox
=1.5 nm

V
GS
=1.0 V, V
DS
=1.5 V
N
a
=3x10
18
cm
-3

c
=1x10
-7
O cm
2
n
+
poly gate
Solid : d=100 nm
Open : d=5 nm
Fin Width (nm)
V
d
r
o
p

(
V
)
2000
2200
2400
2600
2800
3000
3200
P
e
a
k

E
l
e
c
t
r
o
n

T
e
m
p
e
r
a
t
u
r
e

(
K
)
Effect of S/D Resistance with Fin Body Width
W
fin
electron temp.
: Ohmic drop across R
sd
(W
fin
less than 50 nm)
R
sd
=R
as
+R
sh
+R
c
22
3-D Spacer Formation
Epi grwoth blocked by the Fin
spacers
Spacers completely removed
allowing for epitaxial raised S/D
formation
- Source: Intel
23
Industry Leading Performance
NMOS
Integrated CMOS tri-gate with:
1.High-k dielectrics & metal gate
2.Strain engineering for NMOS & PMOS
3.Dual epitaxial raised source/drains
PMOS
- Source: Intel
24
25
Introduction
Fundamentals of Bulk FinFETs
Modeling
Applications
Conclusions
Outline
2-D schematic view of symmetric
double-gate MOSFET.
Gate

Gate

Source

(n+)

Drain

(n+)

Fin
Body

L
ov

T
ox

W
fin

L


L
g

V
GS

V
GS
V
DS

Oxide

y


x


0


Bulk FinFET or SOI
FinFET (not shown)
Side-channel
S/D
S/D
T
FOX
A
A
Side-channel of bulk or SOI FinFETs :
DG structure key point
26
Schematic View of DG MOSFETs
27
Short-channel effect
x
m
x
m
S
D
x
ls x
ld
L
c
=L-2x
m
x
rs
=x
cs
x
rd
=x
cd
S
(a) (b)
x
cs
x
hs
G
G
T
ox
W
fin
SiO
2
SiO
2
( )
b dep hs hd
th ,SCE
ox c
qN x x x / 2
V
C L
A
(
+
=
(
(

b dep
th ,SCE FB B
ox
h
c
qN x
V V 2 1
C
x
L

| |
= + +
|
|
\ .
-
-
Charge-sharing length
hs hd
h
x x
x
2
+
=
: V
th
model of the conventional
planar MOSFETs
:DG MOSFETs
fin
0.5W
V
th
Modeling of Side-Channel (1)
28
Narrow-width effect
-
-
S
D
G
x
hs
x
hd
L
g
H
g
L
c
x
df
(a)
SiO2 SiO2
Fin
Body
xdf
H
g
G G
T
gate
T
ox
W
fin
(b)
b dep df
th ,NWE
ox g
qN x x
V
C 4 H
t
A
| |
= |
|
\ .
gate
ox
th ,s
2
dep b
d
ox
f
T
8
V ln 1
x qN
x
T
c
t
| |
= +
|
|
\ .
: an effective width
depleted by gate fringing
field
V
th
Modeling of Side-Channel (2)
V
th
Modeling of Bulk FinFETs
g
MS B
E
2e
u
| |
= +
|
\ .
b dep df
th ,NWE
ox g
qN x x
V
C 4 H
t
A
| |
= |
|
\ .
gate
ox
of
ox
T
2
C ln 1
T
c
t
| |
= +
|
|
\ .
gate
ox
df th ,woc
2
dep b ox
T
8
x V ln 1
x qN T
c
t
| |
= +
|
|
\ .
( )
b dep df
h
th ,woc FB B w
ox m g
qN x x
x
V V 2 1
C L 2 x 4 H
t
o
| |
= + + + + |
|

\ .
( )
b dep
hs hd
th ,SCE
ox m
qN x
x x
V
C 2 L 2 x
A
| |
+
= |
|

\ .
V
th
equations of bulk FinFETs based on 3-D charge sharing
SCE
NWE
: in NMOSFET with n
+
poly gate
The x
df
and the
V
th,woc
are
obtained by
solving these
equations
b dep
h
th ,SCE FB B
ox m
qN x
x
V V 2 1
C L 2 x

| |
= + +
|
|

\ .
- IEEE Trans on Electron Devices, p. 537, 2007
29
0.0 0.2 0.4 0.6 0.8 1.0
0.08
0.12
0.16
0.20
W
B
=15 nm
L=60 nm
g
m,max
Method
Proposed Model
CC Method
L=30 nm
L=190 nm

V
t
h

(
V
)
V
DS
(V)
T
ox
=1.5 nm
N
b
=5x10
18
cm
-3
n
+
poly gate
V
th0
0.0 0.2 0.4 0.6 0.8
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Simulation
Proposed Model
CC Method


I
D

(
m
A
/

m
)
V
DS
(V)

n
=200 cm
2
/V-sec n
+
poly gate
W
B
=15 nm
T
ox
=1.5 nm
V
GS
=0.4 V
L=30 nm
N
b
=2x10
18
cm
-3
V
DS,sat
=0.426 V
N
b
=5x10
18
cm
-3
V
DS,sat
=0.271 V
V
th
Model Considering Drain Bias
- Jpn. Journal of Applied Physics
Verification in Double-Gate MOSFETs
30
10 100 1000
-0.25
-0.20
-0.15
-0.10
-0.05


Simulation
Model
V
t
h

(
V
)
L
g
(nm)
x
h
=20 nm N
b
=8x10
17
cm
-3
n
+
poly gate
V
DS
=0.05 V
W
fin
=10 nm
T
ox
=1.5 nm
o
W
=-0.04274 V
o
B
=-0.045 V
20 40 60 80 100 120 140 160 180 200
50
60
70
80
90
100
ideal subthreshold slop
n
+
poly gate


Simulation
Model
S
S

(
m
V
/
d
e
c
.
)
Channel Length (nm)
N
b
=5x10
18
cm
-3
W
fin
=15 nm
V
DS
=0.05 V
T
ox
=1.5 nm
N
b
=8x10
17
cm
-3
, W
fin
=10 nm
V
th
vs L
g
SS vs L
Models show a good agreement with simulation data.
N
b
=5x10
18
cm
-3
, W
fin
=15 nm
31
DC Models of Doped DG MOSFETs (2)
0.0 0.2 0.4 0.6 0.8 1.0
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3

V
GS
(V)
I
D

(
A
/

m
)
N
b
=5x10
18
cm
-3
W
fin
=15 nm
T
ox
=1.5 nm
V
DS
=0.05 V

n
=200 cm
2
/V-sec
n
+
poly gate
0.0
0.2
0.4
0.6
0.8
1.0
Simulation
Model
I
D

(
m
A
/

m
)
V
th
=0.1297 V
L=30 nm
L=190 nm
V
th
=0.1899 V
0.0 0.2 0.4 0.6 0.8
0
2
4
6
Simulation
Model


I
D
,
d
r
i
f
t

(
m
A
/

m
)
V
DS
(V)
N
b
=5x10
18
cm
-3
n
+
poly gate
W
fin
=15 nm
V
GS
=0.4 V
T
ox
=1.5 nm

n
=200 cm
2
/V-sec
L=30 nm
V
DS,sat
=0.274 V
V
DS,sat
=0.679 V
V
GS
=0.8 V
N
b
=5x10
18
cm
-3
, W
fin
=15 nm, T
ox
=1.5 nm,
n
=200 cm
2
V
-1
s
-1
I
D
vs V
GS
I
D
vs V
DS
Models show a good agreement with simulation data.
32
DC Models of Doped DG MOSFETs (3)
33


oxide




Si substrate

Gate
Body
Wsc

Ws

Wtc




Wtc


channel
Wsc
Ws
Hg
xh
body
Wfin
Gate

Tox
r
xdep
Wc
(a) (b) (c)
(a) Schematic 3-D view for considering the
corner effect
(b) Cross-sectional view of the fin body
with 90
o
corner
(c) Cross-sectional view of the fin body
with half-circle corner
Schematic Views for Considering Top Corner
Effect
33
h
2 x
1
3 L

( )
,
'
0.5
2
2 1
3
c b fin
h
FB B
ox
th c
q N W
x
V
C
V
L
o

| |
= + +
|
\ .
V
th,s
model for side-channel with a fully depleted fin body
V
th,c
model for corner-channel with a fully depleted fin body

: SCE term in the corner region regardless of the corner shape


: Corner V
th
model
Corner factor(=0.4)
: Fitting parameter
Corner-channel
( )
b fin
df
h
FB B
ox g
th ,s
qN 0.5W
x
x
V 2 1
C L 4 H
V
t

| |
= + + + |
|
\ .
SCE & NWE
Side-channel
SCE NWE

bulk FinFET only


34
V
th
Model of FinFET with Top Corner (1)
20 30 40 50 60 70 80 90 100
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
o
c
=0.4

V
DS
=0.05 V
n
+
poly gate
N
b
=5x10
18
cm
-3

u
MS
=-1.0683 V
W
fin
=20 nm
H
fin
=70 nm
T
ox
=1.5 nm
N
b
=10
19
cm
-3

u
MS
=-1.0862 V
oxide
Si substrate
body
WFin
Gate
TOX
Si substrate
oxide
Simuation
Model
V
t
h


(
V
)
Gate Length (nm)


5 10 15 20
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Gate
T ox
body
Si substrate
oxide
W fin H g
o
c
=0.4
N
b
=5x10
18
cm
-3

u
MS
=-1.0683 V
N
b
=10
19
cm
-3

u
MS
=-1.0862 V
L
g
=100 nm
Simuation
Model
V
t
h


(
V
)
W
fin
(nm)
n
+
poly gate
T
ox
=1.5 nm
V
DS
=0.05 V
H
fin
=70 nm


V
th
vs L
g
V
th
vs W
fin
Models show a good agreement with simulation data.
H
fin
=70 nm, V
DS
=0.05 nm, T
ox
=1.5 nm, n
+
poly gate
35
V
th
Model of FinFET with Top Corner (3)
V
th
Modeling of Bulk FinFETs
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Mod.
o
c
=0.25
L
g
=100 nm
u
m
=4.71 V
u
m
=4.17 V
1 0.6 0.3
Radius Ratio [=r/0.5Wfin]
r
0.5Wfin
Body
N
b
=1x10
19
cm
-3
, H
g
=70 nm
N
b
=5x10
18
cm
-3
, H
g
=70 nm
N
b
=5x10
18
cm
-3
, H
g
=40 nm
N
b
=2x10
18
cm
-3
, H
g
=70 nm
V
t
h

(
V
)
0
V
DS
=0.05 V
W
fin
=20 nm
Sim.
30 40 50 60 70 80 90 100
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
o
c
=0.25

V
DS
=0.05 V
n
+
poly gate
N
b
=5x10
18
cm
-3

u
MS
=-1.0683 V
W
fin
=20 nm
H
g
=70 nm
T
ox
=1.5 nm
N
b
=10
19
cm
-3

u
MS
=-1.0862 V
oxide
Si substrate
body
WFin
Gate
TOX
Si substrate
oxide
Simuation
Model
V
t
h


(
V
)
Gate Length (nm)


Verification of the Model
- IEEE Trans on Electron Devices, p. 537, 2007
36
3-D schematic view
2-D schematic view
Bulk FinFET
as an example
S/D
S/D
H
g
XjSDE
0
Wfin
T
FOX
A
A
body
Gate
Si substrate
oxide
Top-
channel
region
Field
penetration
region
from top-
gate

Electric
field

The electric field penetration region


(hatched triangle) from the top-gate into
the side-channel region.
37
Current Model of FinFET (1)
I
D
vs V
GS
With V
th,s
& V
th,c
Before considering field penetration
effect
With V
th0,s
& V
th0,t
After considering field penetration
effect
-0.2 0.0 0.2 0.4 0.6 0.8 1.0
10
-14
10
-13
10
-12
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
H
g
=70 nm
V
DS
=0.05 V
W
fin
=20 nm
L
g
=100 nm
Simulation
Side-channel (model)
Top-channel (model)
Total (model)


I
D

(
A
)
V
GS
(V)
N
b
=5x10
18
cm
-3
-0.2 0.0 0.2 0.4 0.6 0.8 1.0
0.0
1.0x10
-5
2.0x10
-5
3.0x10
-5
Simulation
Side-channel (model)
Top-channel (model)
Total (model)

I
D

(
A
)
N
b
=5x10
18
cm
-3
L
g
=100 nm
W
fin
=20 nm
V
DS
=0.05 V
H
g
=70 nm
10
-14
10
-13
10
-12
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
I
D

(
A
)
V
GS
(V)
38
Current Model of FinFET (5): An Example
I
D
vs V
GS
39
Continuous Current Model of DG MOSFET
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
1.0x10
-5
2.0x10
-5
3.0x10
-5
4.0x10
-5
5.0x10
-5
6.0x10
-5
7.0x10
-5
8.0x10
-5
9.0x10
-5
1.0x10
-4
0.0 0.2 0.4 0.6 0.8 1.0
10
-14
10
-13
10
-12
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
Simulation
N
b
=2x10
18
cm
-3
N
b
=10
18
cm
-3
N
b
=10
17
cm
-3
N
b
=0 cm
-3
Model


I
d

(
A
)
V
gs
(V)
V
ds
=1V
t
ox
=1.5nm
t
b
=10nm
L
g
=1m
W =1m


Lines: Model
Symbols: Simulation
|
g
=|
b
|
g
= midgap when N
b
=0
No source/drain resistances
Good agreement
From intrinsic to ~10
17
cm
-3
:
nearly the same
( ) | |

(
(

|
|
.
|

\
|
+

=
b si
b b
t
x
q
kT t x qN
x
|
|
c

2
cos ln cos ln
2
8
) 4 (
) (
2 2
( ). tan
4
2
|
c
|c
c
ox b
ox si
ox
ox b b
fb gs
q t
kT t t t qN
V V +
. 2
2 /
0
) (
} }

c
c
=
d
s
b
f
t
kT
q
i
f
g
n d
e qn d
L
W
I
|
|

|

|
40
Introduction
Fundamentals of Bulk FinFETs
Modeling
Applications
Conclusions
Outline
First SRAM Application of Bulk FinFET
41
Bulk FinFET Control planar FET Nano width planar FET
Inverter
schematic
SNM Comparison
- IEDM, p.27, 2003
SEM
Top
view
- IEEE Trans on Electron Devices, p.481, 2006
Si
SiO
2
S
i
N
G
a
t
e

P
o
l
y
-
S
i
S
i

F
i
n
-1.00 -0.75 -0.50 -0.25 0.00 0.25
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1

D
r
a
i
n

C
u
r
r
e
n
t

(
A
)
Gate Voltage (V)
Triple Gate PMOSFET, Vds =-0.1 V
Triple Gate PMOSFET, Vds =-1.1 V
Planar PMOSFET, Vds =-0.1 V
Planar PMOSFET, Vds =-1.1 V
V
BS
= 0 V
-2.5 -2.0 -1.5 -1.0 -0.5 0.0
0.0
-1.0x10
-5
-2.0x10
-5
-3.0x10
-5
-4.0x10
-5
-5.0x10
-5
-6.0x10
-5
-7.0x10
-5

D
r
a
i
n

C
u
r
r
e
n
t

(
A
)
Drain Voltage (V)
V
BS
=0 V
Solid : Triple Gate PMOSFET
Dashed : Planar PMOSFET
- IEEE Electron Device Letters, p. 798, 2004
Bulk pFinFET in a SRAM Cell
SEM View and I-V Curves of pMOSFET
SEM view
I
D
-V
GS
curves
I
D
-V
DS
curves
42
World 1
st
Saddle MOSFET for DRAM Cells
Si sub.
S/D
SiO
2
Fin body
Gate A`
A
B
B`
- IEEE Electron Device Letters, p. 690, 2005
A A`
B B`
x
j S /D
Gate
insulator
G
a
t
e

S /D
L
g
Gate
insulator
Gate
S iO
2
S i sub.
W
fin
L
ov_ s ide
Local
doping
-0.3 0.0 0.3 0.6 0.9 1.2 1.5
10
-16
10
-14
10
-12
10
-10
10
-8
10
-6
10
-4
Saddle u
m
= 4.71 V
Recess u
m
= 4.17 V
V
DS
=
0.05 V 1.5 V
Saddle
Recess
D
r
a
i
n

C
u
r
r
e
n
t

(
A
)
Gate Voltage (V)
L
g
=12 nm W
fin
=20 nm T
ox
=3.5 nm
Recess depth=50 nm
x
jS/D,LDD
=21 nm
x
jS/D,HDD
=33 nm
Schematic View and Comparison of I-V Curves
Saddle Recess
SS 69.5 132
DIBL 21 170
Schematic view
- Korea/USA patents
43
Summary
Brief introduction
Fundamentals of Bulk FinFET
- Nearly the same scalability and performance as those of SOI
FinFET, and has several advantages
- Body shape, temperature, back-bias, S/D resistance, and speed
- Design guideline on body doping and width
Model explains very well the behavior of V
th
, internal physics, and
I-V of double/tri-gate bulk FinFETs
Bulk FinFETs could be applied to SRAM, low-power logics, and be
modified to DRAM cell
44