Contents: 1. Abstract 2. Introduction 3. eSi-RISC Configurable Embedded Processor IPVirus Detection By OS 4. ABOUT EnSilica 5. Benefits Of EnSilica 6.

. Features Of EnSilica 7. Scalability 8. Development Kit Of EnSilica 9. Toolchain 10. IP Delivery 11. EnSilica updates eSi-RISC development suite 12. Conclusion 13. References

ABSTRACT
Microprocessors have evolved dramatically in the twelve years of their development by the implementation of large numbers of devices on single chips. Word widths have increased along with microprogramming capabilities, addressing capabilities, and trends toward single-chip computers. Only a year after the introduction of 4-bit processors came the 8-bit processor. Three years later, in 1974, 16-bit processors became the leading technology. The article compares architectures and operations of the TI 9900, Intel 8086, Zilog Z8000, Motorola 68000, and NSC 16032 16bit microprocessors. The 32-bit processor was realized in 1981. General trends in architecture, technology, principles of operation, register organization, instruction set, memory organization, and performance are examined in the Bellmac32A chip, the HP 32-bit processor, and the iAPX 432 processor chip set. With the development of advanced

processors have come improvements and evolution of operating systems and processor communications. Multiprocessing and specialpurpose processors have also improved computing technology. The processor technologies are illustrated by diagrams and compared in tables. A glossary of microprocessor terms is included.

INTRODUCTION
eSi-RISC is a highly configurable microprocessor architecture for embedded systems, that scales across a wide range of applications. The core has been silicon proven in anumber of A EnSilica provides a substantial catalogue of configurable embedded processor cores and communications IP, said Daniel Platzker, Product Line Director for FPGA synthesis at Mentor Graphics. By validating its IP for use with Precision, EnSilica broadens the Precise-IP catalogue of advanced partner cores, allowing our

mutual customers to benefit from Mentor Graphics comprehensive, vendorindependent FPGA design flow.SIC and FPGA technologies.

processor cores and eSi-Comms library of communications IP has been fully validated for use in Mentor Graphics Precision Synthesis FPGA design flow, enabling design engineers to easily implement them on any FPGA device. EnSilica provides a substantial catalogue of configurable embedded processor cores and communications IP, said Daniel Platzker, Product Line Director for FPGA synthesis at Mentor Graphics. By validating its IP for use with Precision, EnSilica broadens the Precise-IP catalogue of advanced partner cores, allowing our mutual customers to benefit from Mentor Graphics comprehensive, vendorindependent FPGA design flow. EnSilica's eSi-RISC is a family of highly configurable and lowpower soft processor cores for embedded systems that scales across a wide range of applications. It is unique in being the only processor

eSi-RISC Configurable Embedded Processor IP

EnSilica's eSi-RISC embedded processors validated for Mentor Graphics' Precision Synthesis FPGA design flow

Mentor Graphics partners with EnSilica for its Precise-IP vendor-independent FPGA IP platform
EnSilica, a leading independent provider of front-end IC design services, has announced that it has become a partner for Mentor Graphics Precise-IP vendor-independent FPGA IP platform. As a result, EnSilicas range of eSi-RISC embedded

architecture scalable from 16 bits to 32 bits, and encompassing optional DSP extensions, floating point and custom instructions. Furthermore, the memory architecture can be configured for Harvard or Von Neumann, or to include data and program caches. Using a mix of 16-bit and 32-bit instructions, it gives exceptional code density, reducing the program code size by up to 40% compared to leading FPGA vendor processors such as NIOSII and MicroBlaze while the minimum configuration can be implemented in as little as 8K gates, providing class leading overall silicon area and very low power. System clock speeds of over 200MHz can be achieved in Altera Stratix IV and Xilinx Virtex-6 FPGAs and all processors use the industry standard AMBA APB and AXI buses. EnSilica also has a library of APB-based peripherals, including UART, SPI, I2C, Timers and a 10/100 Ethernet MAC.

EnSilicas eSi-Comms library of highly parameterised communications IP is suitable for many of the current air interface standards including WLAN, WiMAX, DVB and DAB. Precise-IP is Mentor Graphics vendor-independent FPGA IP platform. It is part of the Precision Synthesis product family that includes RTL, physical and rad-tolerant synthesis tools. Precision Synthesis is the centre-piece of the industry's most comprehensive vendorindependent solution for FPGA design. The tool uses the same design source and constraints to target all major device vendors, enabling designers to synthesize eSi-RISC processors and eSiComms IP for optimal performance on any FPGA technology. Our eSi-RISC embedded processor cores and eSi-Comms IP library will give Mentor Graphics Precision Synthesis users an additional, distinctive

edge to their FPGA designs, said Ian Lankshear, Managing Director of EnSilica. Siliconproven, eSi-RISCs single architecture is scalable over a range of embedded applications enabling companies to secure their software investment while addressing a wide range of needs. A high level of configurability enables hardware resources to be optimised to application requirements, minimising area and power to a level not possible with a general purpose processor architecture. The highly pipelined nature of the design gives customers a solution that can be easily migrated between FPGA types or even to ASIC technologies. All the eSi-RISC embedded processor cores and eSi-Comms communications IP are available direct from EnSilica. For more information visit: http://www.ensilica.com.

ABOUT EnSilica
EnSilica is an established company with many years experience providing high quality IC design services to customers undertaking FPGA and ASIC designs. EnSilica has an impressive record of success working across many market segments with particular expertise in multimedia and communications applications. Customers range from start-ups to blue-chip companies. EnSilica can provide the full range of front-end IC design services, from System Level Design, RTL coding and Verification through to either a FPGA device or the physical design interface (synthesis, STA, DFT) for ASIC designs. EnSilica also offers a portfolio of IP, including a highly configurable 16/32 bit embedded processor called eSiRISC and the eSi-Comms range of communications IP.

 Backed up by the EnSilica reputation for quality design services.

Features Of EnSilica
Configurable 16 or 32-bit, 5stage pipelined RISC, load-store architecture. Implemented in as little as 8k ASIC gates for minimum 16bit configuration. Intermixed 16 and 32-bit instructions gives exceptional code density. Uses industry standard bus architecture for IPinterconnection (AMBA AXI/AHB/APB). Configurability and custom instructions will deliver a solution Choice of von Neumann or Harvard memory architecture.

Benefits Of EnSilica
Highly configurable, allowing the processor to be tailored to fit a wide range of applications, on both FPGA and ASIC technology. Performance and code density amongst the very best available. Silicon proven. License-free SW development using GNU tools. Competitive licensing terms.

 Supports user and supervisor modes. JTAG or serial hardware debug. Applications include sensors, medical, power management, metering, wireless or mobile products with exceptionally lowlower.

EnSilicas eSi-1600 16-bit CPU core is a low-cost, low-power processor. It offers similar performance to more expensive 32-bit CPUs while having a system. cost comparable to that of 8bit CPUs. eSi-3200 EnSilica's eSi-3200 32-bit CPU core is particularly suited to embedded control applications. eSi-3250 EnSilica's eSi-3250 32-bit CPU core is a high-performance processor ideal for integration into ASIC and/or FPGA designs with off-chip memories. The eSi-3250 is suited to a wide range of applications including running complex operating systems such Linux and uClinux.

Scalability

. EnSilica have defined a family

of processor cores that demonstrates the versatility of the eSi-RISC configurable. architecture to cover a wide range of applications.

eSi-1600

Development Kit Of EnSilica

A hardware development kit is available for evaluating these cores. This board provides a range of memory and external interfaces to suit most applications.

The toolchain is available for both Windows and Linux hosts and is available to use at no additional cost.

IP Delivery
The eSi-RISC is implemented as a soft IP core, based on synthesisable Verilog RTL and can be easily ported to a wide range of ASIC processes and FPGAs. The design is DFT ready, supporting full scan insertion for all flip flops and memory BIST. A selection of AMBA peripherals are supplied with the core, including: UART, SPI, I2C, Timer, PWM, Watchdog, GPIO, PS/2, Ethernet MAC as well as a static memory interface and DMA engine. By using an industry standard bus, a wide range of 3rd party IP

Toolchain

The toolchain is based upon the industry standard GNU toolchain, which includes an optimising C and C++ compiler, assembler, linker, debugger, simulator and binary utilities. All these tools can be driven by the customisable Eclipse IDE (Integrated Development Environment).

cores can also be used.

facilitated through the Eclipse integrated development environment and GNU GCC 4.4.0 toolchain, which now features native support for the eSi-RISC architectural features. FPGA configurations are supplied for the eSi-RISC processor family, along with application examples demonstrating how the systemon-chip peripherals can be used, including a full port of the open source FreeRTOS with lwIP TCP/IP network stack. Documentation and a range of interactive tutorials are also included. Debug facilities in the eSiRISC Development Suite v2.1 also enhance development productivity. Non-intrusive debugging for FPGAs is provided through the JTAG hardware debugger, which provides the ability to examine data, insert break and watchpoints and control program execution, giving developers full read/write access to all variables, registers, memory and attached peripherals, while supporting single-step and step-over execution of the C code and views of the disassembly.

EnSilica updates eSi-RISC development suite

EnSilica (Wokingham, UK), a provider of front-end IC design services, has launched a updated version of its eSi-RISC Development Suite. Version 2.1 provides a platform for evaluating the companys family of eSi-RISC configurable and low-power soft processor cores, along with a complete development environment for the creation, implementation and test of eSi-RISC processor embedded application designs.

Version 2.1 includes a new hardware evaluation platform based on Alteras Cyclone III FPGA with rapid software development and debugging

 Debugging is seamless with communication over a USB interface to a host PC with GDB, the GNU project debugger, running inside Eclipse.

Conclusion
Microcomputers and other advances in hardware such as semiconductor sensors and analog/digital converters have made a wide variety of simple, intelligent instruments available to us to simplify patient care and medical testing. Often, however, the cost of a new instrument is high.

References
http://en.wikipedia.org/wiki/Co mputeren.wikipedia.org/wiki/Mi crocomputeren.wikipedia.org/wi ki/Microprocessor www.angelfire.com/ultra/muzir/ microp/microcomputer.pdf http://www.faqs.org/ http://books.google.co.in/books http://www.ncbi.nlm.nih.gov