Fazel Seyed

Technische Universitt Berlin
Investigation and Comparison of Multi-Level Converters for Medium Voltage Applications
Seyed Saeed Fazel
von der Fakultt IV- Elektrotechnik und Informatik der Technischen Universitt Berlin Institut fr Energie- und Automatisierungstechnik
Zur Erlangung des akademischen Grades eines
Doktoringenieurs (Dr.-Ing.)
genehmigte Dissertation
Vorsitzender: Gutachter:
Prof. Dr.-Ing. C. Boit Prof. Dr.-Ing. S. Bernet Prof. Dr.-Ing. U. Schfer Prof. Dr.-Ing. M. Michel Tag der Verteidigung: 23.08.2007
Tag der Einreichung: 11.07.2007
Berlin 2007 D 83
Seyed Saeed Fazel
Investigation and Comparison of Multi-Level Converters for Medium Voltage Applications
Preface
I would like to express my sincere gratitude to my supervisor, Professor Dr.-Ing. Steffen Bernet for his professional guidance, interesting discussion and encouragement throughout the period of this research. I would also like to thank my friends and colleagues in the Power Electronics Group of Berlin University. In particular, I would like to acknowledge Dietmar Krug and Kamran Jalili. The author wishes to acknowledge the financial support of Iran Ministry of Science, Research and Technology scholarship. Finally, my personal thanks are extended to my family and friends for their support.
Seyed Saeed Fazel Berlin, July 2007
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TABLE OF CONTENTS
Glossary of Symbols and Acronyms ....................................................................... List of Figures .......................................................................................................... List of Tables ............................................................................................................ 1. Introduction......................................................................................................... 2. Overview of Medium Voltage Converter Topologies ....................................... 2.1. State of the Art in Medium Voltage Converters ............................................. 2.2. State of the Art in Medium Voltage Power Semiconductors........................... 3. Basic Structure and Function of Multi-Level Voltage Source Converter Topologies ..... 3.1. Two-Level Voltage Source Converter (2L-VSC) ............................................. 3.1.1. Structure of Two-Level Voltage Source Converter (2L-VSC).................... 3.1.2. Switch States and Commutations ................................................................ 3.1.3. Sine-Triangle Modulation ............................................................................ 3.1.4. Output Waveforms and Spectrum ............................................................... 3.2. Diode Clamped Voltage Source Converter (DC VSC) .................................... 3.2.1. Structure ....................................................................................................... 3.2.1.1. Three-Level Neutral Point Clamped Voltage Source Converter (3LNPC VSC)................................................................................................ 3.2.1.1.1. Switch States and Commutations ....................................................... 3.2.1.1.2. Sine-Triangle Modulation .................................................................. 3.3. Flying Capacitor Voltage Source Converter (FLC VSC) ................................ 3.3.1. Flying Capacitor Converter Structure ......................................................... 3.3.1.1. Three-Level Flying Capacitor Voltage Source Converter (3L-FLC VSC).. 3.3.1.1.1. Switch States and Commutations....................................................... 3.3.1.1.2. Sine-Triangle Modulation................................................................... 3.3.1.2. Four-Level Flying Capacitor Voltage Source Converter (4L-FLC VSC)......................................................................................................... 3.4. Series Connected H-Bridge Voltage Source Converter (SCHB VSC) ... 3.4.1. Single-Phase Full-Bridge (H-Bridge) Topology ........................................ 3.4.1.1. Circuit Configuration ............................................................................... 3.4.1.2. Switch States and Commutations ............................................................ 3.4.1.3. Sine-Triangle Modulation........................................................................ 3.4.2. Three-Phase Two-Level H-Bridge (2L-H-Bridge) Topology ................... 3.4.2.1. Circuit Configuration ............................................................................... 3.4.2.2. Switch States and Commutations............................................................. 3.4.2.3. Sine-Triangle Modulation........................................................................
iv x xvii 1 3 3 6 9 9 9 9 11 12 14 14 15 16 19 22 22 23 23 25 28 32 32 32 33 36 38 38 39 39
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3.4.3. Introduction to the Series Connected Two-Level H-Bridge Voltage Source Converter (SC2LHB VSC).......................................... 3.4.3.1. Series Connected Two-Level H-Bridge Voltage Source Converter with Two Power Cells per Phase Leg (5L-SC2LHB VSC).................... 3.4.3.1.1. Circuit Configuration.......................................................................... 3.4.3.1.2. Switch States and Commutations........................................................ 3.4.3.1.3. Sine-Triangle Modulation................................................................... 3.4.3.2. Series Connected Two-Level H-Bridge Voltage Source Converter with Three Power Cells per Phase Leg (7L-SC2LHB VSC).................. 3.4.3.2.1. Circuit Configuration.......................................................................... 3.4.3.2.2. Switch States and Commutations....................................................... 3.4.3.2.3. Sine-Triangle Modulation................................................................... 3.4.3.3. Series Connected Two-Level H-Bridge Voltage Source Converter with Four Power Cells per Phase Leg (9L-SC2LHB VSC).................... 3.4.4. N-Level Series Connected Three-Level H-Bridge Voltage Source Converter (NL- SC3LHB VSC) ............................................................... 3.4.4.1. Circuit Configuration of Five-Level Series Connected 3-Level HBridge Voltage Source Converter (5L-SC3LHB VSC).......................... 3.4.4.2. Switch States and Commutations............................................................. 3.4.4.3. Sine-Triangle Modulation........................................................................ 3.4.5. Conclusion ................................................................................................ 4. Modelling and Simulation.................................................................. 4.1. Load and Grid Models.................................................................................... 4.1.1. Load Model................................................... 4.1.2. Grid Model................................................................................................ 4.2. Converter Model.......................................................................... 4.2.1. Inverter.. 4.2.1.1. Modulation Method.. 4.2.1.2. Compact Power Semiconductor Model 4.2.1.2.1. Power Semiconductor Losses.. 4.2.1.2.2. Loss Approximation based on Datasheets 4.2.1.2.3. Description of the Loss Simulation Model.. 4.2.1.2.4. Agreement Calculation Measurement... 4.2.2. DC Link Capacitor Models... 4.2.2.1. Capacitor................................................................................................ 4.2.2.1.1. Aluminium Electrolytic Capacitors .... 4.2.2.1.2. Film Capacitors ... 4.2.3. Rectifier Model. 4.3. Isolation Transformer Modelling and Simulation....................................... 4.3.1. Transformer Model................................................................................... 4.3.1.1. Transformer Winding Model................................................................ 4.3.1.2. MATLAB/PELECS Implementation....................................................
41 44 44 44 46 50 50 50 52 54 59 60 61 62 65 67 67 67 68 68 68 69 69 69 70 72 72 73 74 74 74 75 76 76 79 84
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4.3.1.3. Medium Voltage Converter Application............................................... 4.3.1.3.1. Three-Level Neutral Point Clamped Voltage Source Converter..... 4.3.1.3.1.1. Simulation Results................................................................. 4.3.1.3.2. Nine-Level Series Connected H-Bridge Voltage Source Converter 4.3.1.3.2.1. Simulation Results................................................................. 5. Design Criteria and Converter Data........................................................... 5.1. Design Criteria 5.1.1. Power Semiconductor Devices..... 5.1.2. DC Link Capacitor 5.1.2.1. DC Link Voltage Ripples.. 5.1.2.2. DC Link Capacitor Stored Energy 5.1.2.3. Design of the Flying Capacitors 5.2. Definition of the Converter Data..................................................................... 5.2.1. Power Semiconductor Devices................................................................. 5.2.2. Switching Frequency................................................................................. 5.2.3. DC Link Voltage.......................................................................................... 5.2.4. Rectifier.......................... 5.2.5. General Data for the Selective Medium Voltage Converter...................... 6. Converter Comparison........................................................................................ 6.1. Comparison of Power Semiconductor Utilization and Loss Distribution......... 6.1.1. Comparison at Constant Installed Switch Power and Constant Carrier Frequency..................................................................................................... 6.1.2. Comparison of Maximum Carrier Frequency at Constant Installed Switch Power and Constant Apparent Converter Output Power............................................................................................................ 6.1.3. Comparison of Converter Power and Loss Distribution at for Constant Installed Switch Power and Constant Frequency of the First Carrier Band 6.1.4. Comparison of 4.16kV, 4.32MVA Multi-Level Converters at Constant Efficiency.. 6.2. Comparison of Power Semiconductor Utilization and Power Loss Distribution for 2.3kV-6kV Multi-Level Converters (3L-NPC VSC and SC2LHB VSCs).................................................................................................. 6.3. Comparison of the DC Link Capacitor for a 24-pulse, 4.16kV, 4.32MVA, 3L-NPC VSC and 9L-SC2LHB VSC 7. Conclusion and Discussion Appendix A.. Bibliography .............................................................................................................
87 88 89 91 93 95 95 95 100 100 100 101 102 102 103 103 103 103 107 107 107
112 118 123
127 130 143 147 151
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GLOSSARY OF SYMBOLS AND ACRONYMS

Variable a, b, c Aon,x Asw,off,x, Bsw,off,x Asw,on,x, Bsw,on,x Bcon,x Cjx Cmin,NPC Cmin,SCHB Cx cos Djkx, D jkx Djx Meaning AC terminals of the converter On state resistance for device x Turn-off curve-fitting constants for device x Turn-on curve-fitting constants for device x Curve-fitted constant for device x Flying capacitor (j = 1, .., N-1), (x = a, b, c) Minimum size of the dc link capacitance for NPC converter Minimum size of the dc link capacitance for SCHB converter DC link capacitance (x = 1, .., N-1) Load power factor H-bridge diodes (j = 1, 2, ... p), (k = L, R), (x = a, b, c) NPC diodes (j = 1, .., N-1), (x = a, b, c) Series connected three-level H-bridge NPC diodes (j = 1, 2), (x = a, b, c), (i = 1, 2) 3L-H-Bridge freewheeling diodes (j = 1, 2, ... p), (k = 1, 2), (x = a, b, c), (i = 1, 2), freewheeling diodes (x = a, b, c), (j = 1, .., N-1) Stored energy in the dc link capacitor Turn-on, turn-off energy in IGBT and recovery energy in diode Switching energy loss for device x Load electromotive force (x = a, b, c) Fundamental output frequency Carrier frequency Maximum carrier frequency Frequency of the first harmonics carrier band Frequency of harmonics order Converter output frequency Rectifier output frequency Frequency of triangle carrier signal H-bridge negative dc rail Gate signal Ordinal number of harmonic Instantaneous value of current Transformer secondary windings current referred to the primary side (x = 1,.., 4) Collector current Collector current in IGBT Forward current in diode Amplitude of the harmonic current Maximum value of the output phase current Effective value of the output phase current Peak value of the output phase current Transformer primary winding current (x = 1, 2) Transformer secondary winding current (x = 1, 2, 3, 4) Rating capacitor current
D jxi ,D jxi DTjkxi ,DTjkxi

DTjx, DTjx EC Eon, Eoff, Erec Esw,x ex f1 fC fC,max fC1b fh fo frec ftri g gs h i(t) Isx IC IC,n IF,n Ih Iph,max Iph,rms,1 I ph ,rms ,1 Ipx Isx iC
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iC,j iC,rip iC,rms iCj,x idc,j idcjx iLx io i ph iph iph,a isx k11, k21, k22 L1 LESR LL Lm LmY, LmD Ls Lx1jY, Lx1jD Lx2jY, Lx2jD M, Mj N ma mf n n n11 n2jx nc nC nj1YD nsw nT, nD ntr PC Pcon,x PconD PconT Ploss Ploss,D Ploss,T PoffD PoffT PonT Psw,x p ph R1
DC link capacitor current (j = 0, .., N-1) Effective ripple current in the capacitor Effective current of flying capacitor cells Flying capacitor current (j = 1, 2, ..), (x = a, b, c), Current at any node of the capacitor bank (j = 0, .., N-1) Capacitor current at each H-bridge (j = 1, 2, ... p), (x = a, b, c) Load current (x = a, b, c) Transformer no-load primary current Peak value of the phase current Output phase current a-phase current Utility grid phase current (x = A, B, C) Transformer turn ratio between secondary windings Transformer primary inductance Equivalent series inductance Load inductance Transformer magnetization inductance Transformer equivalent inductance with star and delta connections Utility grid inductance Transformer primary leakage inductance (x = U, V, W), (j = 1, 2) Transformer secondary leakage inductance (x = U, V, W), (j = 1, 2, 3, 4) Converter midpoint (j = 0, .., N-1) Number of level voltage per phase leg Amplitude modulation ratio Frequency modulation ratio Load star point Converter star point Number of primary turn winding Number of secondary turn windings (j = 1, 2), (x = Y, D) Number of series capacitors Number of series connected flying capacitor cells Transformer secondary windings turn ratio between delta and star connections (j = 1, 2) Number of switch states Number of semiconductors and diodes in the converter Transformer open circuit turns ratio Converter output active power Conduction losses in device x Conduction losses of diodes Conduction losses of IGBT Power dissipation loss Power dissipation loss in a freewheeling diode Power dissipation loss in an IGBT Turn-off losses of diode Turn-off losses of IGBT Turn-on losses of IGBT Average switching loss in device x Number of single-phase H-bridge cell per phase leg Number of phase Transformer primary resistance
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R1jD R2jx REPR RESR RL Rm Rs RT Rth Rth,ch Rth,ch,T, Rth,ch,D Rth,ha Rth,jc Rth,jc,T, Rth,jc,D SC SC,max SCR Sin Sjkx, S jkx
S jkxi ,S jkxi
Sjx, S jx Skx, S kx SN1 Sout SS SSR T1 Ta tan TC Th Tj, Tj(x) Tj,max Tj,sp Tjkx, T jkx
Transformer primary winding resistance (j = 1, 2) Transformer secondary winding resistance (j = 1, 2), (x = Y, D) Bypass resistance Equivalent series resistance Load resistance Transformer magnetization resistance Utility grid resistance Transformer resistance Thermal resistances Thermal resistances from junction to case Thermal resistances of the IGBT and diode from junction to case Thermal resistances from heat sink to ambient Thermal resistances from case to heat sink Thermal resistances case to heat sink of IGBT and diode Converter three-phase apparent power Maximum apparent converter output power Relative apparent converter output power Inner switches Two-level H-bridge switches (i = 1,...p), (k = L, R), (x = a, b, c) Three-level H-bridge switches (j = 1,...p), (k = 1, 2), (x = a, b, c), (i = 1, 2) Switches (j = 1, .., N-1), (x = a, b, c) Series connected H-bridge switches (k = L, R), (x = a, b, c) Transformer apparent rated power Outer switches Installed switch power Relative installed switch power Fundamental period Ambient temperature Dissipation factor of capacitor Period of carrier frequency Heat sink temperature Junction temperature (x = T, D) Maximum junction temperature Specified junction temperature Two-level H-bridge transistor (j = 1,...p), (k = L, R), (x = a, b, c) Three-level H-bridge transistors (j = 1,...p), (k = 1, 2), (x = a, b, c), (i = 1, 2) Transistors (j = 1, .., N-1), (x = a, b, c) H-bridge transistor (k = L, R), (x = a, b, c) Time Specific line-to-line voltages Specific output leg voltages (x = g, M1) Capacitor operating voltage Collector-emitter voltage On-state saturation voltage in IGBT Flying capacitor voltage (j = 1, 2), (x = a, b, c) Commutation voltage
T jkxi ,T jkxi
Tjx, T jx Tkx, Tkx , Tk, Tk t Uab, Ubc, Uca Uax, Unx UC UCE UCE,n UCjx Ucom
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Ucom@100FIT Ucon, Ucon,x con,1 UCx Udc Udc,3L-HB Udc,HB Udc,min Udc,n Udc,tv Udcjx UF,n Ujxn Ujxn Uk Uk12Y, Uk12D Uk2YD Ull,rms,1 UnM Uo,x URRM Usx tri Utri,cell,j, Utri,kj Utri,Utri,j,Utri,j,x Utri,i Ux UxM Uxn Uxn VgTj ,VgT j ,VgTj,x ,VgTj,x ,
Commutation voltage for a device reliability of 100FIT Reference voltage per phase (x = a, b, c) Peak value of the desired fundamental component of the reference voltage DC link capacitor voltage (x = 1, 2, ...) DC link voltage for 2L-VSC, 3L-VSCs, and 4L-FLC VSC DC link voltage of one H-bridge in SC3LHB VSC DC link voltage of one H-bridge in SC2LHB VSC Minimum dc link voltage Nominal dc link voltage Total virtual dc link voltage for SC2LHBVSCs, and SC3LHBVSCs H-bridge dc link voltage (j = 1, .., p), (x = a, b, c) On-state voltage in diode H-bridge output voltage (j = 1, .., p), (x = a, b, c) Specific line-to-ground x-phase voltage for H-bridge (j = 1, .., p) Transformer short-circuit voltage Transformer short-circuit voltage between primary and secondary windings Transformer short-circuit voltage between secondary star and delta windings Effective value of line-to-line output voltage Specific common-mode voltage Threshold voltage in device x Rated repetitive peak reverse voltage of diodes Utility grid phase voltage (x = A, B, C) Peak value of triangular wave Amplitude of triangle carrier signal (j = 1, 2, ), (k = L, R) Amplitude of triangle carrier signal (j = up, low), (x = a, b), (i = 1, 2) x-phase line-to-ground voltage (x = a, b, c) Specific phase-midpoint output voltage (x = a, b, c) Specific line-to-neutral voltages (x = a, b, c) Specific H-bridge output voltage (x = a, b, c) Gate signals (j = 1, 2, ), (x = a, b, c), (k = L, R), (i = 1, 2) Transformer primary voltage (X = U, V, W), (j = 1, 2) Transformer secondary voltage (X = U, V, W), (j = 1, 2, 3, 4), (k = Y, D) Transformer primary rated voltage (X = U, V, W) Transformer primary no-load voltages with star and delta connections (X = U, V, W) Transformer secondary no-load voltages with star and delta connections (X = U, V, W) Transformer secondary rated voltages (X = U, V, W), (j = 1, 2, 3, 4) Transformer reactance Transformer secondary winding impedance (j = 1, 2), (x = Y, D) Primary equal impedance of 24-pulse transformer Primary equal impedance of each 12-pulse transformer Transformer primary winding no-load impedance Transformer primary winding impedance with delta connection (j = 1, 2) Transformer secondary equal impedance (j = 1, 2) Transformer secondary winding impedance (j = 1, 2), (x = Y, D) Transformer equivalent short-circuit impedance (j = 1, ... 4)
VgTk,x ,VgTk,x ,VgT1j,xi ,VgT1j,xi

X1j X2jk XN1 XN10Y, XN10D XN20Y, XN20D XN2j XT Z2jx Z1 Z11, Z11 Z11Yo Z1jD Z2j Z2jx Zkj
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ZN11Y ZT p UC UC,max 1
Transformer primary winding rated impedance Transformer impedance Transformer phase displacement between primary and secondary Transformer phase displacement DC link capacitor voltage ripples Maximum dc link capacitor voltage ripples Load current angle Fundamental angular frequency Efficiency
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Acronyms and Abbreviations

Acronym/Name ANSI BJT CD CSC CSI D DC VSC Dd Dy Dzz EMF EMI FIT FLC GCT GTO H HV-IGBT IEEE IGBT IGCT LV-IGBT MCT ML MLC MOSFET MPC MTO MV MVD N NEMA NPC OP PD POD PS PWM SC2LHB SC3LHB SCHB SVM T THD VSC VSI WTHD Zdy Meaning American National Standard Bipolar Junction Transistor Carrier Disposition Modulation Current Source Converter Current Source Inverter Diode Diode Clamped Voltage Source Converter Delta-delta Configuration Delta-star Configuration Delta-zigzag-zigzag Configuration Electromotive force Electromagnetic Interference One failure in 109 operation hours Flying Capacitor Gate-commutated Thyristor Gate Turn-Off Thyristor Hybrid Modulation High Voltage Insulated Gate Bipolar Transistor Institute of Electrical and Electronics Engineers Insulated Gate Bipolar Transistor Integrated Gate Commutated Thyristor Low Voltage Insulated Gate Bipolar Transistor MOS-controlled Thyristor Multi-Level Multi-Level Converter Metal Oxide Semiconductor Field Effect Transistor Multiple Point Clamped MOS Turn-Off Thyristor Medium Voltage Medium Voltage Drive Number of Voltage Level National Electrical Manufacturers Association Neutral Point Clamped Operating Point Phase Disposition Phase Opposition Disposition Phase Shifted Modulation Pulse-Width-Modulated Series Connected Two-Level H-Bridge Series Connected Three-Level H-Bridge Series Connected H-Bridge Space Vector Modulation Transistor Total Harmonic Distortion Voltage Source Converter Voltage Source Inverter Weighted Total Harmonic Distortion Zigzag-delta-star Configuration
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List of Figures
Figure 2-1: Figure 2-2: Figure 2-3: Figure 2-4: Figure 2-5: Application ranges of commercially available power semiconductors IGBT-based inverter fed medium voltage drives: (a) 3L-NPC, (b) SCHB Classification of state-of-the-art power semiconductors Power range of commercially available power semiconductors Application ranges of IGBTs and IGCTs
Figure 3-1: Two-Level Voltage Source Configuration Figure 3-2: Switch states: (a) conduction paths, (b) commutations and switching losses for each phase of the 2L-VSC Figure 3-3: Voltage waveforms of the 2L-VSC: (a) control signals Ucon, x and triangular signal Utri, (b) gating signals in phase a, (c) phase-midpoint output voltage, (d) line-toline output voltage, (e) common mode voltage Figure 3-4: Harmonic spectrum of the 2L-VSC: (a) phase-midpoint output voltage, (b) line-toline output voltage Figure 3-5: One-phase N-Level Neutral Point Clamped Converter Figure 3-6: Three-phase Three-Level Neutral Point Clamped Converter Figure 3-7: Conduction path of the Three-Level Neutral Point Clamped Converter Figure 3-8: Commutations and switching losses in the 3L-NPC VSC: (a) and (b) for positive load current, (c) and (d) for negative load current Figure 3-9: Voltage waveforms of the 3L-NPC VSC: (a) control signals Ucon, x and triangular signals Utri,up and Utri,low, (b) gating signals in phase a, (c) phase-midpoint output voltage, (d) line-to-line output voltage, (e) common mode voltage Figure 3-10: Harmonic spectrum of the 3L-NPC VSC: (a) phase-neutral point output voltage, (b) line-to-line output voltage Figure 3-11: The generalized N-Level Flying Capacitor Converter Figure 3-12: Three-phase Three-Level Flying Capacitor Converter Figure 3-13: Conduction path of the Three-Level Flying Capacitor Converter Figure 3-14: Commutations and switching losses in the 3L-FLC Converter (a-d) for positive load current, (e-h) for negative load current Figure 3-15: Voltage waveforms of the 3L-FLC VSC: (a) control signals and triangular signals, (b) gating signals in phase a, (c) phase-midpoint output voltage, (d) line-to-line output voltage, (e) common mode voltage Figure 3-16: Harmonic spectrum of the 3L-FLC VSC: (a) phase-neutral point output voltage, (b) line-to-line output voltage Figure 3-17: Three-phase Four-Level Flying Capacitor Converter Figure 3-18: Voltage waveforms of the 4L-FLC VSC: (a) control signals and triangular signals, (b) phase-midpoint output voltage, (c) line-to-line output voltage, (d) common mode voltage Figure 3-19: Harmonic spectrum of the 4L-FLC VSC: (a) phase-neutral point output voltage, (b) line-to-line output voltage
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Figure 3-20: Transitions between voltage levels for the Four-Level Flying Capacitor Figure 3-21: Three-phase configuration for the N-Level H-Bridges VSC Figure 3-22: Typical power cell (H-bridge) converter Figure 3-23: Conduction path of the single-phase H-bridge cell: (a) positive, (b, c) zero, and (d) negative states Figure 3-24: Commutations and switching losses in the H-bridge cell: (a) and (b) for positive load current, (c) and (d) for negative load current Figure 3-25: Voltage waveforms of the H-bridge cell: (a) control signals Ucon and triangular signals Utri,1 and Utri,2, (b) output voltage of leg a, (c) output voltage of leg n, (d) load voltage Figure 3-26: Harmonic spectrum of the H-bridge output voltage Figure 3-27: Three-phase configuration for the 2L-H-Bridges Voltage Source Converter Figure 3-28: Voltage waveforms of the three-phase 2L-H-Bridge cell: (a) control signals Ucon,x and triangular signals Utri,1 and Utri,2, (b) gate signals, (c) output phase voltage, (d) output line-to-line voltage Figure 3-29: Harmonic spectrum of the three-phase 2L-H-Bridge cell: (a) phase output voltage, (b) line-to-line output voltage Figure 3-30: Series Connected Two-Level H-Bridge Voltage Source Converter with p series Hbridge cells per phase Figure 3-31: 5L-SC2LHB Voltage Source Converter Figure 3-32: Transitions between voltage levels for the 5L-SC2LHB VS Figure 3-33: Conduction path of the 5L-SC2LHB VSC Figure 3-34: Voltage waveforms of the 5L-SC2LHB VSC: (a) control signals Ucon,x and triangular signals Utri,L1, Utri,L2, Utri,R1 and Utri,R2, (b) gate signals, (c) output phaseto-ground voltage Uan, (d) output line-to-line voltage Uab, (e) output load-phase voltage Uan Figure 3-35: Harmonic spectrum of the 5L-SC2LHB VSC Figure 3-36: Pulse width modulation for the 7L-SC2LHB VSC: (a) control signals Ucon,a and triangular signals Utri,Li and Utri,Ri, (b) gate signals (mf = 3) Figure 3-37: Voltage waveforms of the 7L-SC2LHB VSC: (a) reference and triangular signals, (b) output phase voltage Uan, (c) output line-to-line voltage Uab, (d) output loadphase voltage Uan (mf = 15) Figure 3-38: Harmonic spectrum of the phase voltage (a) and line-to-line voltage (b) of the 7LSC2LHB VSC Figure 3-39: The 9L-SC2LHB Voltage Source Converter Figure 3-40: Pulse width modulation for the 9L-SC2LHB VSC: (a) control signals Ucon,a and triangular signals Utri,Li and Utri,Ri, (b) gate signals (mf = 3) Figure 3-41: Voltage waveforms of the 9L-SC2LHB VSC: (a) reference and triangular signals, (b) output phase voltage Uan, (c) output line-to-line voltage Uab, (d) output loadphase voltage Uan (mf = 15) Figure 3-42: Harmonic spectrum of the phase voltage Uan (a) and the line-to-line voltage Uab
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(b) of the 9L-SC2LHB VSC Figure 3-43: NL-SC3LHB VSC with p series 3L-H-Bridge cells per phase Figure 3-44: Five-level SC3LHB diode clamped topology (5L-SC3LHB) Figure 3-45: Voltage waveforms of the 5L-SC3LHB VSC: (a) control signal Ucon and triangular signals, (b) a1-leg gate signals, (c) a1-leg phase voltage, (d) a2-leg gate signals, (e) a2-leg phase voltage, (f) converter output voltage Figure 3-46: Harmonic spectrum of the 5L-SC3LHB VSC Figure 3-47: Number of total components required in the multi-level converter as a function of the number of phase voltage levels Figure 4-1: Block diagram of Medium Voltage Drives: (a) NPC and FLC VSCs, (b) SCHB VSC Figure 4-2: Standard load model for one-phase and three-phase Figure 4-3: Standard three-phase utility grid model Figure 4-4: The ideal circuit symbol of the IGBT Figure 4-5: The steady state equivalent thermal circuit diagram: (a) general model, (b) Infineon model Figure 4-6: Characteristics of current sharing for two connected modules in parallel Figure 4-7: Approximation characteristics based on the curve-fitting method: (a) IGBT/Diode on-state characteristics, (b) IGBT turn-on and IGBT/Diode turn-off switching energy (FZ800R33KF2C IGBT-module from Eupec, UCE = 1800V, Tj,max = 125C) Figure 4-8: Equivalent circuit of a capacitor Figure 4-9: Circuit diagram of the standard six-pulse diode rectifier Figure 4-10: Multi-pulse phase-shift transformer Figure 4-11: 24-pulse phase-shift transformer models: (a) Zdy, (b) Dzz Figure 4-12: Investigated zigzag coupling configurations: (a) Delta-zigzag-zigzag configuration (Dzz), (b) Zigzag-delta-star configuration (Zdy) used by the industry Figure 4-13: Windings position for positive (a), and negative (b) phase shift of Dzz configuration Figure 4-14: Windings position for positive (a), and negative (b) phase shift of Zdy configuration Figure 4-15: Equivalent electrical circuit of a linear 3-winding transformer Figure 4-16: The model of a 12-pulse transformer Figure 4-17: 24-Pulse-Diode-Rectifier with serial connections and Dzz configuration Figure 4-18: 24-Pulse-Diode-Rectifier with serial connections and Zdy configuration Figure 4-19: Utility grid current and its harmonic spectrum for the 24-pulse transformer (a, b), primary winding currents and their harmonic spectrum for the 12-pulse transformer (c, d), and secondary winding currents and their harmonic spectrum for the 12-pulse transformer (e, f)
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Figure 4-20: Primary and secondary winding currents of the 24-pulse transformer Figure 4-21: DC link voltage and its harmonic spectrum (a, b), and dc link current and its harmonic spectrum, Idc = 710A, fC = 750Hz Figure 4-22: 24-Pulse-Diode-Rectifier with independent connections: (a) Dzz configuration, and (b) Zdy configuration Figure 4-23: Utility grid current and its harmonic spectrum for the 24-pulse transformer (a, b), primary winding currents and their harmonic spectrum for the 12-pulse transformer (c, d), and secondary winding currents and their harmonic spectrum for the 12-pulse transformer (e, f) Figure 4-24: Primary and secondary winding currents of the 24-pulse transformer Figure 4-25: DC link voltage and its harmonic spectrum, fC= 750Hz Figure 4-26: DC link current and its harmonic spectrum, Idc = 471A, fC = 750Hz Figure 5-1: Iterative design approach to the power semiconductor design Figure 5-2: Iterative design approach to calculate the maximum converter output power SC,max and the semiconductor utilization (Tj = Tj,max, SS = const., fC = const.) Figure 5-3: Iterative design approach to calculate the maximum carrier frequency (Tj = Tj,max, SS = const., SC = const.) Figure 5-4: Iterative design approach to calculate the converter output power and losses (Tj = Tj,max, SS = const., f1Cb = const.) Figure 5-5: Iterative design approach to calculate the maximum carrier frequency (Tj = Tj,max, SC = const., = ref const.) Figure 5-6: The dc link voltage ripple UC and the dc link stored energy EC as functions of the dc link capacitance for the 3L-NPC VSC (Ull,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9, Udc = 6118V) Figure 5-7: 24-pulse diode rectifier configurations (a) series configuration uses for the 3L-NPC VSC, (b) separate configuration uses for the9L-SCHB VSC Figure 5-8: Voltage and power ranges of the selective medium voltage drives (Iph,rms,1 = 600A), (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3) Figure 6-1: Converter semiconductor losses and efficiencies as functions of the phase current for the investigated output voltage classes (fC = 450Hz, ma = 1.15, cos = 0.9): (a) Ull,rms,1 = 2.3kV, (b) Ull,rms,1 = 3.3kV, and (c) Ull,rms,1 = 4.16kV (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3) Figure 6-2: Converter semiconductor loss distribution at constant carrier frequency (fC = 450Hz, ma = 1.15, cos = 0.9, Iph,rms,1 = 600A) (a) Ull,rms,1 = 2.3kV, (b) Ull,rms,1 = 3.3kV, (c) Ull,rms,1 = 4.16kV (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3) Figure 6-3: Harmonic spectrum of line-to-line output voltage at constant carrier frequency (fC = 450Hz, fo = 50Hz, ma = 1.15, f1Cb,3L-NPC = 450Hz, f1Cb,3L-FLC = 900Hz, f1Cb,4L-FLC = 1350Hz, f1Cb,5L-SC2LHB = 1800Hz, f1Cb,7L-SC2LHB = 2700Hz, f1Cb,9L-SC2LHB = 3600Hz) (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A:
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FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3) Figure 6-4: Converter semiconductor losses and efficiencies as functions of the carrier frequency for the investigated output voltage classes: (a) Ull,rms,1 = 2.3kV, (b) Ull,rms,1 = 3.3kV, and (c) Ull,rms,1 = 4.16kV (fC = 450Hz, Iph,rms,1 = 600A, ma = 1.15, cos = 0.9) (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3) Figure 6-5: Converter semiconductor loss distribution at maximum carrier frequency (fo = 50Hz, ma = 1.15, cos = 0.9, Iph,rms,1 = 600A, fC = 450Hz), (fC,3L-NPC = 450Hz, fC,3LFLC,2.3kV = 880Hz, fC,3L-FLC,3.3kV = 635Hz, fC,3L-FLC,4.16kV = 595Hz, fC,4L-FLC,2.3kV = 250Hz, fC,4L-FLC,3.3kV = 790Hz, fC,4L-FLC,4.16kV = 850Hz, fC,5L-SC2LHB = 1585Hz, fC,7L= 1300Hz, fC,9L-SC2LHB =3450Hz) (6.5kV/600A: FZ600R65KF1, SC2LHB 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3) Figure 6-6: Harmonic spectrum of line-to-line voltage at maximum carrier frequency (f1Cb,3L-NPC = 450Hz, f1Cb,3L-FLC,2.3kV = 1760Hz f1Cb,4L-FLC,2.3kV = 750Hz f1Cb,5L-SC2LHB = 6340Hz, fo = 50Hz, fC = 450Hz, ma = 1.15, cos = 0.9, Iph,rms,1 = 600A) (3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3) Figure 6-7: Harmonic spectrum of line-to-line voltage at maximum carrier frequency (f1Cb,3L-NPC = 450Hz, f1Cb,3L-FLC,3.3kV = 1270Hz, f1Cb,4L-FLC,3.3kV = 2370Hz, f1Cb,7L-SC2LHB = 7800Hz, fo = 50Hz, fC = 450Hz, ma = 1.15, cos = 0.9, Iph,rms,1 = 600A) (4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 1.7kV/600A: FZ600R17KE3) Figure 6-8: Harmonic spectrum of line-to-line voltage at maximum carrier frequency (f1Cb,3L-NPC = 450Hz, f1Cb,3L-FLC,4.16kV = 1190Hz, f1Cb,4L-FLC,4.16kV = 2550Hz, f1Cb,9L-SC2LHB = 27600Hz, fo = 50Hz, fC = 450Hz, ma = 1.15, cos = 0.9, Iph,rms,1 = 600A) (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 1.7kV/600A: FZ600R17KE3) Figure 6-9: Converter semiconductor losses as functions of the phase current for the investigated output voltage classes: (a) Ull,rms,1 = 2.3kV, (b) Ull,rms,1 = 3.3kV, and (c) Ull,rms,1 = 4.16kV (fC,3L-NPC = 450Hz, fC,3L-FLC = 225Hz, fC,4L-FLC = 150Hz, fC,5LSC2LHB = 112.5Hz, fC,7L-SC2LHB = 75Hz, fC,9L-SC2LHB = 56.25Hz, fo = 50Hz, f1Cb = 450Hz, ma = 1.15, cos = 0.9, Iph,rms,1 = 600A), (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3) Figure 6-10: Converter semiconductor loss distribution at constant frequency of the first carrier band (fC = f1Cb = 450Hz, ma = 1.15, cos = 0.9, Iph,rms,1 = 600A): (a) Ull,rms,1 = 2.3kV, (b) Ull,rms,1 = 3.3kV, (c) Ull,rms,1 = 4.16kV (fC,3L-NPC = 450Hz, fC,3L-FLC = 225Hz, fC,4L-FLC = 150Hz, fC,5L-SC2LHB = 112.5Hz, fC,7L-SC2LHB = 75Hz, fC,9L-SC2LHB = 56.25Hz, fo = 50Hz, f1Cb = 450Hz, ma = 1.15, cos = 0.9, Iph,rms,1 = 600A), (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3) Figure 6-11: Harmonic spectrum of line-to-line voltage at constant frequency of the first carrier band (fC,3L-NPC = 450Hz, fC,3L-FLC = 225Hz, fC,4L-FLC = 150Hz, fC,5L-SC2LHB = 112.5Hz, fC,7L-SC2LHB = 75Hz, fC,9L-SC2LHB = 56.25Hz, fo = 50Hz, f1Cb = 450Hz, ma = 1.15, cos = 0.9, Iph,rms,1 = 600A), (6.5kV/600A: FZ600R65KF1, 4.5kV/600A:
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CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3) Figure 6-12: Average junction temperature of IGBTs and diodes (Udc,n = 6118V, ma = 1.15, cos = 1, Th = 80C) (a) 3L-NPC VSC (Eupec 6.5kV/740.4A IGBT, Iph,max = 600A, SC = 4.32MVA, fC = 450Hz) (b) 3L-FLC VSC (Eupec 6.5kV/863.4A IGBT, Iph,max = 919A, SC = 6.62MVA, fC = 225Hz) (c) 4L-FLC VSC (Mitsubishi 4.5kV/832A IGBT, Iph,max = 1061A, SC = 7.64MVA, fC = 150Hz) (d) 9L-SCHB VSC (Eupec 1.7kV/825.8A IGBT, Iph,max = 891A, SC = 6.42MVA, fC = 56.25Hz) Figure 6-13: Loss distribution (a), efficiency (b), and relative installed switch power (c), (Sc = 4.32MVA, Iph,rms,1 = 600A, fo = 50Hz, ma = 1.15, cos = 0.9, Tjmax = 125C, fC,3LNPC-6.5kV = 450Hz, fC,3L-NPC-3.3kV = 1250Hz, fC,3L-FLC-6.5kV = 475Hz, fC,3L-FLC-3.3kV = 650Hz, fC,4L-FLC-4.5kV = 610Hz, fC,9LSC2LHB-1.7kV = 1125Hz), (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3) Figure 6-14: Flying capacitor current (a) and voltage ripple (b) of a 3L-FLC VSC as functions of the modulation index and phase shift (Iph,rms,1 = 600A, fC,3L-FLC = 1200Hz, C = 770F) Figure 6-15: Flying capacitor current (a) and voltage ripple (b) of a 4L-FLC VSC as functions of the modulation index and phase shift (Iph,rms,1 = 600A, fC,4L-FLC = 1200Hz, C1,2 = 518F) Figure 6-16: Harmonic spectrum of line-to-line voltage at constant efficiency (Iph,rms,1 = 600A, fo = 50Hz, ma = 1.15, cos = 0.9, Tjmax = 125C, fC,3L-NPC-6.5kV = 450Hz, fC,3L-NPC3.3kV = 1250Hz, fC,3L-FLC-6.5kV = 475Hz, fC,3L-FLC-3.3kV = 650Hz, fC,4L-FLC-4.5kV = 610Hz, fC,9LSC2LHB-1.7kV = 1125Hz) Figure 6-17: Semiconductor loss distribution and relative installed switch power occurring at line-to-line output voltages of 2.3kV, 3.3kV, 4.16kV, and 6kV at different switching frequencies of 450Hz, 750Hz, and 1050Hz (Iph,rms,1 = 600A, fo = 50Hz, ma = 1.15, cos = 0.9, Tjmax = 125C), (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3) Figure 6-18: The effective, average, and ripple capacitor current as a function of the modulation index and load angle in the 3L-NPC VSC according to Figure 3-6: (a-c) (idc2,eff,max/iph,peak = 85.6% at = 180, 0 and ma = 1.15), (idc2,avg,max/iph,peak = 80.3% at = 0 and ma = 1.15), (idc2,rip,max/iph,peak = 45.8% at = 180, 0 and ma = 0.6), and in the 9L-SC2LHB VSC according to Figure 3-39 (df).(idc21,eff,max/iph,peak = 68.7% at = 180, 0 and ma = 1.15), (idc21,avg,max/iph,peak = 57.5% at = 0 and ma = 1.15), (idc21,rip,max/iph,peak = 54.3% at = 90, and ma = 1.15), (iph,rms,1 = 600A, fC = 750Hz, fo = 50Hz) Figure 6-19: (a, b): Utility grid phase current and its harmonic spectra in the 3L-NPC VSC, (c, d): transformer primary phase currents of the 12-pulse transformer and their harmonic spectra in the 3L-NPC VSC, (e, f): transformer secondary phase currents of the 12-pulse transformer and their harmonic spectra in the 3L-NPC VSC (E = 6J/kVA, C1 = C2 = 2.77mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9) Figure 6-20: (a, b): Utility grid phase current and its harmonic spectra in the 3L-NPC VSC, (c, d): transformer primary phase currents of the 12-pulse transformer and their
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harmonic spectra in the 3L-NPC VSC, (e, f): transformer secondary phase currents of the 12-pulse transformer and their harmonic spectra in the 3L-NPC VSC (E = 12J/kVA, C1 = C2 = 5.54mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9) Figure 6-21: (a, b): Utility grid phase current and its harmonic spectra in the 9L-SC2LHB VSC, (c, d): transformer primary phase currents of the 12-pulse transformer and their harmonic spectra in the 9L-SC2LHB VSC, (e, f): transformer secondary phase currents of the 12-pulse transformer and their harmonic spectra in the 9L-SC2LHB VSC (E = 12J/kVA, C1 = C2 = 14.8mF, fC = 750Hz, fo = 50Hz, ma = 1.15, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9) Figure 6-22: (a, b): Utility grid phase current and its harmonic spectra in the 9L-SC2LHB VSC, (c, d): transformer primary phase currents of the 12-pulse transformer and their harmonic spectra in the 9L-SC2LHB VSC, (e, f): transformer secondary phase currents of the 12-pulse transformer and their harmonic spectra in the 9L-SC2LHB VSC (E = 34J/kVA, C1 = C2 = 44mF, fC = 750Hz, fo = 50Hz, ma = 1.15, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9) Figure 6-23: (a, b): DC link voltage ripple and its harmonic spectra in the 3L-NPC VSC, (c, d): dc link current and its harmonic spectra, (e, f): capacitor voltage ripples and their harmonic spectra in the 3L-NPC VSC (E = 6J/kVA, C1 = C2 = 2.77mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9) Figure 6-24: (a, b): DC link voltage ripple and its harmonic spectra in the 3L-NPC VSC, (c, d): dc link current and its harmonic spectra in the 3L-NPC VSC, (e, f): capacitor voltage ripples and their harmonic spectra in the 3L-NPC VSC (E = 12J/kVA, C1 = C2 = 5.54mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9) Figure 6-25: (a, b): DC link voltage ripple and its harmonic spectra in the 9L-SC2LHB VSC, (c, d): dc link current and its harmonic spectra in the 9L-SC2LHB VSC, (e, f): phase output voltage and its harmonic spectra in the 9L-SC2LHB VSC (E = 12J/kVA, C1 = C2 = 14.8mF, fC = 750Hz, fo = 50Hz, ma = 1.15, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9) Figure 6-26: (a, b): DC link voltage ripple and its harmonic spectra in the 9L-SC2LHB VSC, (c, d): dc link current and its harmonic spectra in the 9L-SC2LHB VSC, (e, f): phase output voltage and its harmonic spectra in the 9L-SC2LHB VSC (E = 34J/kVA, C1 = C2 = 44mF, fC = 750Hz, fo = 50Hz, ma = 1.15, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9) Figure 6-27: (a, b): Capacitor current ripples and their harmonic spectra in the 3L-NPC VSC, (c, d): phase-midpoint output voltage and its harmonic spectra in the 3L-NPC VSC, (e, f): phase output load currents and their harmonic spectra in the 3L-NPC VSC (E = 6J/kVA, C1 = C2 = 2.77mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9) Figure 6-28: (a, b): Capacitor current ripples and their harmonic spectra in the 3L-NPC VSC, (c, d): phase-midpoint output voltage and its harmonic spectra in the 3L-NPC VSC, (e, f): phase output load currents and their harmonic spectra in the 3L-NPC VSC (E = 12J/kVA, C1 = C2 = 5.54mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9)
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List of Tables
Table 2-1: Overview of available industrial medium voltage drives on the market Table 2-2: Device rating and package types of typical MV power semiconductors Table 3-1: Switch positions for each phase of the two-level VSC Table 3-2: Conduction losses in the two-level VSC Table 3-3: Switching losses in the two-level VSC Table 3-4: Switch positions for one phase of the three-level NPC VSC Table 3-5: Conduction losses in the 3L-NPC VSC Table 3-6: Switching losses in the 3L-NPC VSC Table 3-7: Switch positions for one phase of the three-level FLC VSC Table 3-8: Conduction losses in the three -level FLC VSC Table 3-9: Switching losses in the three-level FLC VSC Table 3-10: Switch positions for the one phase of the four-level FLC VSC Table 3-11: Switch positions for single-phase H-bridge cell Table 3-12: Conduction losses in the single-phase full-Bridge converter Table 3-13: Switching losses in the single-phase full-Bridge converter Table 3-14: Quantities comparison of the SC2LHB VSC Table 3-15: Switch positions for the 5L-SC2LHB VSC Table 3-16: The output voltage levels of the 5L-SC2LHB VSC Table 3-17: Number of redundancies in each phase voltage level of the 7L-SC2LHB VSC Table 3-18: The output voltages and their corresponding levels of the 7L-SC2LHB VSC Table 3-19: The output voltages and their corresponding levels of the 9L-SC2LHB VSC Table 3-20: Switch positions for the 3L-H-Bridge converter Table 3-21: Conduction losses in the 3L-H-Bridge converter Table 3-22: Switching losses in the 3L-H-Bridge converter Table 3-23: Comparison of power component requirements for multi-level topologies Table 4-1: Fitting parameters and thermal resistances of medium voltage IGBTs/Diodes Table 4-2: Thermal resistance of the IGBT module: FZ600R65KF1 Table 4-3: Harmonic current and their phase angles in 24-pulse transformers Table 4-4: The necessary input data of the 12-pulse phase-shift transformer Table 4-5: The secondary quantity parameters for the 24-pulse transformer with Zdy connection Table 4-6: The designing parameters for the 24-pulse transformer with Zdy connection Table 5-1: Critical operating points for the determination of the power semiconductor current ratings (stationary thermal design) for all considered topologies Table 5-2: Converter data (Output phase current Iph,rms,1 = 600A)
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Table 5-3: Power semiconductor devices Table 5-4: The converter specifications for medium voltage converters Table 6-1: Power semiconductor design for Iph,rms,1 = 600A, fC = 450Hz / 1000Hz Table 6-2: Maximum phase current and apparent converter output power for constant carrier frequency (Iph,rms,1 = 600A, ma = 1.15, cos = 0.9) Table 6-3: Maximum carrier frequency for constant apparent converter output power and constant installed switch power (Iph,rms,1 = 600A, ma = 1.15, cos = 0.9) Table 6-4: Maximum phase current and apparent converter output power for constant carrier frequency of the first carrier band and installed switch power (Iph,rms,1 = 600A, f1Cb = 450Hz / 1000Hz, ma = 1.15, cos = 0.9) Table 6-5: Converter voltage and semiconductor specifications for a constant converter power and carrier frequency (Ull,rms,1 = 4.16kV, Iph,rms,1 = 600A, SC = 4.32MVA, fC = 450Hz, Tj,max = 125C) Table 6-6: Carrier and harmonic carrier band frequencies, capacity of flying capacitors and installed switch power for a converter efficiency of about 99% (Ull,rms,1 = 4.16kV, Iph,rms,1 = 600A, SC = 4.32MVA) Table 6-7: Power semiconductor design (Iph,rms,1 = 600A, ma = 1.15, cos = 0.9)
1. INTRODUCTION
The development of new high power semiconductors such as 3.3kV, 4.5kV, and 6.5kV Insulated Gate Bipolar Transistors (IGBTs), and 4.5kV to 5.5kV Integrated Gate Commutated Thyristors (IGCTs), and improved converter designs have led to a drastic increase of the market share of Pulse-Width-Modulated (PWM) controlled Voltage Source Converters (VSC) [21]. Despite a price reduction of Gate Turn-Off Thyristors (GTOs) by a factor of two to three over the last five years, also conventional GTO Voltage Source Converters and Current Source Converters (CSC) are increasingly replaced by PWM Voltage Source Converters with IGCTs or IGBTs in traction and industry applications [21]. Today the two-level Voltage Source Converter (2L-VSC) applying IGBTs is clearly the dominating converter topology in traction applications (low, medium, and high power propulsion) and the three-level Neutral Point Clamped Voltage Source Converter (3L-NPC VSC) is mostly applied in industrial medium voltage converters. The 2L-VSC and the 3L-NPC VSC offer technical advantages like a simple power part, a low component count, and straightforward protection and modulation schemes. On the other hand, the hard-switching transients of the power semiconductors at high commutation voltage cause high switching losses and a poor harmonic spectrum which produces additional losses in the machine. Further problems are created by over-voltages in cables and machines as well as bearing currents due to the steep-switching transients [5], [21], [121]. Multi-level converters (MLCs) have been receiving attention in the recent years and have been proposed as the best choice in a wide variety of medium voltage (MV) applications [47]. They enable a commutation at substantially reduced voltages and an improved harmonic spectrum without a series connection of devices, which is the main advantage of a multi-level structure. Other advantages of these topologies are better output voltage quality, reduced electromagnetic interference (EMI) problems, and lower overall losses in some cases. However, today they have a limited commercial impact due to their disadvantages such as high control complexity and increased power semiconductor count compared to the 2L-VSC and the 3L-NPC VSC. There is a large variety of power semiconductors (e.g. IGBTs, GTOs, IGCTs) and converter topologies (e.g. 2L-VSC, 3L-NPC VSC, 3L-FLC VSC, 4L-FLC VSC, and SCHB VSCs). However, today there is no comparative analysis of the different converter topologies. Therefore, the objective of this thesis is a detailed comparison of state-of-the-art 2L-VSC, 3LNPC VSC, and different multi-level VSCs (e.g. 3L-FLC VSC, 4L-FLC VSC, 5L-, 7L-, and 9LSC2LHB VSCs) for medium voltage converters. On the basis of the application requirements, different ML converter structures are designed, simulated, and evaluated. The development of design tools based on state-of-the-art converters and semiconductors, which enable the dimensioning of power semiconductors, dc link capacitors, and transformers; are one major part of this thesis. Finally, the amount of active and passive components, the modulation, losses, and efficiency of aforementioned converters are calculated and compared. The thesis is arranged in seven main chapters: This introduction is followed by an overview of medium voltage converter topologies, including medium voltage power semiconductors and modulations in chapter 2.
INTRODUCTION
Chapter 3 presents the basic structure and function of voltage source converter topologies. Based on the requirements for MV applications, advantages and disadvantages of the topologies are discussed. One of the main parts of this thesis is the modelling and simulation of the different multi-level converters. The dimensioning and design of power semiconductors, dc link capacitors, and isolation transformers are developed in chapter 4. The basic converter data for a converter comparison, including the IGBTs, modulation, switching frequency, and state of the art are described in chapter 5. The comparison of the different converter topologies is performed in chapter 6 for 3L-NPC VSC, 3L-FLC VSC, 4L-FLC VSC, and 5L-, 7L-, 9L-, and 11L-SCHB VSCs on the basis of the state-of-the-art 1.7kV, 2.5kV, 3.3kV, 4.5kV, and 6.5kV IGBTs for 2.3kV, 3.3kV, 4.16kV, and 6kV medium voltage converters. As a result, the converter losses, the semiconductor loss distribution, the converter efficiency, harmonic spectrum analysis, and the installed switch power of the different converter topologies are compared in this chapter. Finally, the conclusion and discussion are presented in chapter 7.
2. OVERVIEW OF MEDIUM VOLTAGE CONVERTER TOPOLOGIES

2.1. State of the Art in Medium Voltage Converters Multi-level voltage source converters have been studied intensively for high-power applications [44], [53], [87], [88]. Standard drives for medium voltage industrial applications have become available since the mid-1980s [27], [82], [83], [129]. These converters synthesize higher output voltage levels with a better harmonic spectrum and less motor winding insulation stress. However, the reliability and efficiency of the converter are reduced due to an increasing number of devices. Today there is a large variety of converter topologies for Medium Voltage Drives (MVD). For low and medium power industrial applications (e.g. S = 300kVA - 30MVA) the majority of the drive manufacturers offer different topologies of Voltage Source Converters: Two-Level Voltage Source Converters (2L-VSC) (e.g. Alstom), Three-Level Neutral Point Clamped Voltage Source Converters (3L-NPC VSC) (e.g. ABB, Alstom, Siemens), Four-Level Flying Capacitor Voltage Source Converters (4L-FLC VSC) (e.g. Alstom: SYMPHONY [80]) and Series Connected H-Bridge Voltage Source Converters (SCHB VSC) (Robicon [81], [139]). One manufacturer (Allen Bradley) still offers self-commutated current source inverters (CSI). While 4.5kV, 6kV and 6.5kV IGCTs are mainly used in 3L-NPC VSCs and CSIs respectively; 2.5kV, 3.3kV, 4.5kV and 6.5kV High Voltage IGBTs (HV-IGBTs) are applied in 2L-VSCs, 3LNPC VSCs and 4L-FLC VSCs. In contrast, 1.2kV and 1.7kV Low Voltage IGBTs (LV-IGBTs) are usually applied in SCHB VSCs [94]. Among the high-power multi-level converters, three topologies have been successfully implemented as standard products for medium voltage industrial drives: the Three-Level Neutral Point Clamped Voltage Source Converter (3L-NPC VSC) [82], [83], the Four-Level Flying Capacitor Voltage Source Converters (4L-FLC VSC) [80], and the Series Connected HBridge Voltage Source Converters (SCHB VSC) [27], [129]. In medium voltage applications, the 3L-NPC topology has been accepted by several large manufacturers. ABB is using this topology in both their ACS 1000 [83] and ACS 6000 series, in a voltage and power range of 2.3kV-4.16kV and 315kVA-27MVA [154]. Siemens SIMOVERT MV [155] is also utilising this topology with output voltages from 2.3kV to 6.6kV and a power range from 660kVA to 9MVA. Not only European but also Asian vendors, such as Mitsubishi, employ the 3L-NPC converter [48]. The NPC topology uses high-voltage blocking devices with a relatively low switching frequency capability. This topology has a simple circuit but it needs a large inductivecapacitive (LC) output filter to operate standard motors. The 4L-FLC VSC is attractive if a very high switching frequency, a low harmonic distortion, and a small output filter or a high output voltage is required [25]. The SCHB topology uses low-voltage blocking devices (e.g. 1700V IGBTs) with a high switching frequency capability. It typically consists of three to six equal H-bridge cells per phase, which results in a seven- to thirteen-level output voltage waveform. An input isolation transformer feeds each of the H-bridges via its own three-phase winding and full-bridge diode-
OVERVIEW OF MEDIUM VOLTAGE CONVERTER TOPOLOGIES
rectifier. To obtain a high pulse number at the primary side, secondary transformer windings in star, delta, zigzag, and combinations are used. This topology has excellent utility grid current and output voltage waveforms. However, the cost of the complex input transformer and the high number of semiconductor devices with their control equipment are its drawbacks. The disadvantages of both topologies can be limited by using a hybrid asymmetric multi-level converter which is constructed by combining the SCHB with the NPC topologies [133], [134]. This combination produces more output voltage levels with the same number of components than a symmetric multi-level converter. The first H-bridge cells of each phase in the SCHB topology are replaced by a leg of the NPC converter. Although an H-bridge cell and a leg of the NPC converter provide the same output voltage level, the hybrid asymmetric multi-level topology requires a smaller number of separate dc sources and H-bridge cells for the same output voltage levels [85], [86]. This leads to a further simplification of the feeding transformer and rectifiers [84]. This topology can be operated with a low or high switching frequency for high- or low-voltage applications. However, the need for a complex input transformer remains and its control would be complicated due to its structure, so that it is not commercially offered on the market. Table 2-1 summarizes the available industrial medium voltage drive applications offered by drive manufactures [28]. The voltage source converter topology applying IGBTs and IGCTs are offered by the majority of manufactures. The medium voltage drives cover power ratings from 0.2MW to 40MW at the medium voltage level of 2.3kV to 13.8kV [9], [28]. These drives are used in various applications such as traction [21], electric power, and other industries [35]. The medium voltage traction converters are mostly fed by a single-phase ac line using a lowfrequency transformer (e.g. 15kV 16 2 Hz or 25kV 50Hz) [21], [38], [39]. The feeding of 3 some traction converters by dc mains is also possible, but due to the large variations of the dc voltages of -30% to +40%, such applications are complicated [21]. Figure 2-1 represents the most important power converters on the market and their rated voltages and powers today [14], [28].
Table 2-1 Manufacturer Robicon Allen Bradley Siemens Overview of available industrial medium voltage drives on the market [28], [75] Type Perfect Harmony Power Flex 7000 Masterdrive MV Masterdrive ML2 ACS 1000 ACS 5000 ACS 6000 VDM 5000 Alstom General Electric VDM 6000 VDM 7000 Dura-Bilt5 MV MV-GP Type H Power (MVA) 0.3-31 0.15-6.7 0.66-9.1 5-30 0.3-5 5.2-24 3-27 1.4-7.2 0.3-8 7-9.5 0.3-2.4 0.45-7.5 Voltage (kV) 2.3-13.8 2.3, 3.3, 4.16, 6.6 2.3, 3.3, 4.16, 6, 6.6 3.3 2.3, 3.3, 4 6, 6.6, 6.9 3, 3.3 2.3, 3.3, 4.2 2.3, 3.3, 4.2 3.3 4.16 3.3, 4.16 Topology ML-SCHB-VSC CSI 3L-NPC-VSC 3L-NPC-VSC 3L-NPC-VSC ML-SCHB-VSC 3L-NPC-VSC 2L-VSC 4L-FLC-VSC 3L-NPC-VSC 3L-NPC-VSC ML-SCHB-VSC Semiconductor LV IGBT IGCT HV IGBT IGCT IGCT IGCT IGCT IGBT IGBT GTO IGBT IGBT
ABB
Figure 2-2 illustrates two examples of medium voltage drives: Figure 2-2a shows a medium voltage drive using an IGBT-based 3L-NPC inverter (SIMOVERT [9]). The standardized output power range extends for motors from about 0.2MW up to more than 7MW [150]. Figure 2-2b shows a 4.16kV, 7.5MW SCHB inverter with five identical IGBT power cells which generate 21 levels at the line-to-line output voltage (ASI Robicon [9]).
Figure 2-1 Application ranges of commercially available power semiconductors [14], [28]
(a) Cabinet of Siemens (SIMOVERT MV)
(b) Cabinet of ASI Robicon (Perfect Harmony)
Figure 2-2 IGBT-based inverter fed medium voltage drives: (a) 3L-NPC, (b) SCHB [9], [75]
2.2. State of the Art in Medium Voltage Power Semiconductors Recent technology advances in power electronics have been made by improvements in controllable power semiconductor devices. Figure 2-3 and Figure 2-4 summarize the most important power semiconductors on the market and their rated voltages and currents today [14], [21]. The device characteristics for medium voltage power semiconductors are shown in Table 2-2 [28]. Metal Oxide Semiconductor Field Effect Transistors (MOSFET) and IGBTs have replaced Bipolar Junction Transistors (BJT) almost completely. A remarkable development in MOSFETs took place during the last years. Nowadays MOSFETs are available up to a maximum switch power of about 100kVA [21]. Various new concepts of MOS-controlled thyristors such as the MOS-controlled thyristor (MCT) and the MOS turn-off thyristor (MTO) have been presented but they do not have any commercial applications. Conventional GTOs are available with a maximum device voltage of 6kV in traction and industrial converters (Table 2-2) [21], [28]. The high on state current density, the high blocking voltages, and the possibilities to integrate an inverse diode are considerable advantages of these devices. However, the requiring of bulky and expensive snubber circuits [92], [93] as well as the complex gate drive are the reasons that GTOs are being replaced by IGCTs and Gifts [21], [28]. Like GTOs, IGCTs are offered only as a presspack device. The symmetrcial IGCT is offered by Mitsubishi with a maximum device voltage of 6.5kV (Table 2-2) [21], [28]. An increase of the blocking voltage of IGCTs and inverse diodes to 10kV is technically possible today [21]. Due to the thyristor latching, a GTO structure offers lower conduction losses than an IGBT of the same voltage class. To improve the switching performance of classical GTOs, gatecommutated thyristors (GCTs) with a very little turn-off delay (about 1.5s) have been developed [90], [91]. New asymmetric GCT devices up to 10kV with peak controllable currents up to 1kA have been manufactured but only those devices with 6kV and 6kA are commercially available. IGBTs were introduced on the market in 1988. IGBTs from 1.7kV up to 6.5kV with dc current ratings up to 3kA are commercially available today (Table 2-2) [21], [28]. They have been optimized to satisfy the specifications of the high-power motor drives for industrial and traction applications. They are mainly applied in a module package due to the complex and expensive structure of an IGBT presspack [28]. In IGBT modules, multiple IGBT chips are connected in parallel and bonded to ceramic substrates to provide isolation. Both IGCTs and IGBTs have the potential to decrease the cost of systems and to increase the number of economically valuable applications as well as the performance of high-power converters, compared to GTOs, due to a snubberless operation at higher switching frequencies (e.g. 500-1000Hz). Figure 2-5 represents the typical converter voltage as a function of power ratings for both IGBT and IGCT applications [28], [30], [31]. It can be seen that LV-IGBT modules are commercially available with a maximum device voltage of 1700V on the entire low-voltage drive market (i.e. up to 690V). On the other hand, MV-IGBT modules enable converter designs in a voltage range from 1kV up to 7.2kV with a power range from 200kVA up to 7MVA (Figure 2-4) [28]. MVIGBT modules have replaced GTOs in recent traction applications. IGBT presspacks are applied mainly in self-commutated High Voltage Direct Current (HVDC) converters (e.g. HVDC light) where a redundant converter design is a main
requirement and each converter switch position consists of a series connection of many IGBTs (e.g. n 10) [28].
Table 2-2 Device rating and package types of typical MV power semiconductors [28] Voltage Ratings Current Ratings 6kV 6000A* MITSUBISHI 4.5kV 1000-4000A* 4.5kV 600-4000A* ABB 6kV 3000A* 3.3kV 400-1200A EUPEC 6kV 200-600A 3.3kV 800-1200A 400-900A MITSUBISHI 4.5kV 6kV 600A HITACHI 3.3kV 400-1200A 3.3kV 400-1200A TOSHIBA 4.5kV 1200-2100A 3.3kV 1200A ABB 4.5kV 600-3000A 6kV 600A 4.5kV 3800-4000A* 4.5kV 340-2200A** ABB 5.5kV 280-1800A** 6kV 3000A* 4.5kV 4000A* 3500-6000A* MITSUBISHI 6kV 6.5kV 400-1500A*** Manufacturer Case Presspack Presspack Presspack Presspack Module Module Module Module Module Module Presspack Module Module Presspack Module Presspack Presspack Presspack Presspack Presspack Presspack Presspack
Power Semiconductors GTO
IGBT
IGCT
*: Asymetric blocking device
**: Reverse conducting device ***: Symetric blocking device
Power Semiconductors Silicon Diodes Transistors Thyristors Silicon Carbide Diodes Transistors
Schottky PIN Double (PIN)
BJT MOSFET IGBT
GTO IGCT GCT MCT MTO
Schottky JBS PIN
MOSFET
Low importance on the market today
Figure 2-3 Classification of state-of-the-art power semiconductors [21]
IGCTs enable converter designs in the high power range from 5MVA up to 100MVA in a voltage range of 2.3kV to 15kV. The majority of applications are industrial converters and drives as well as interties, dynamic voltage restorers, and energy storage systems [28].
Figure 2-4 Power range of commercially available power semiconductors [14], [21]
Ull
Figure 2-5 Application ranges of IGBTs and IGCTs [28], [30], [31]
3. BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
MULTI-LEVEL
This chapter describes the basic structure and function of Multi-level VSC topologies. The principle of operation that includes the structure, switching states, and modulation methods are discussed for the 2L-VSC, 3L-NPC VSC, 3L-FLC VSC, 4L-FLC VSC, 9L-SC2LHB VSC, and the hybrid VSC. 3.1. Two-Level Voltage Source Converter (2L-VSC) 3.1.1. Structure of Two-Level Voltage Source Converter The three-phase 2L-VSC consists of three legs, one for each phase, as shown in Figure 3-1. Each converter leg consists of two active switches and two freewheeling diodes in parallel with each switch. The output of each leg of the three-phase converter depends only on the dc link voltage Udc and the switch state. The output voltage is independent of the output load current since one of the two active switches or freewheeling diodes in a leg is always on at any instant. Therefore, the converter output voltage is independent of the direction of the load current.
+ C2 Udc M C1 iph,a idc Uc2 T1a UaM Uc1 T 2a DT1a T1b a DT2a T2b Uab n
Figure 3-1 Two-Level Voltage Source Configuration
DT1b b DT2b
T1c
DT1c S1c c
T2c Ubc
DT2c
3.1.2. Switch States and Commutations As shown in Figure 3-1, the three-phase two-level VSC contains six unidirectional active switches having inverse diodes. Each ac terminal of the converter (a, b, or c) can be connected to the positive dc rail "+" or the negative dc rail "-". Thus, the number of different converter switch states calculates to
nsw = N ph = 23 = 8
(3-1)
with N being the number of voltage levels in the dc link and ph being the number of phases.
10
BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES
The switch positions for two possible states of each phase leg are given in Table 3-1, where 1 and 0 denote the on- and off state of the switch. Figure 3-2a depicts the eight active inverter voltage vectors for the three-phase two-level VSC, where [0 0 1] means that S1a, S1b are switched off and S1c is switched on.
[0 0 1]
[0 1 0]
[0 1 1]
[1 0 1]
[1 0 0]
[1 1 0]
[1 1 1]
[0 0 0]
(a)
+ U dc 2
M C2 T1a DT1a a C1 T2a DT2a
+ U dc 2
M C2 T 1a DT1a a C1 T2a DT2a
U dc 2 -
U dc 2 -
(b)
+
U dc 2
M C2 T1a DT1a
+
U dc 2
M C1 T2a DT2a C2 T1a DT1a
U dc 2
U dc 2
C1
T2a
DT2a
(c)
Figure 3-2 Switch states: (a) conduction paths, (b) commutations and switching losses of the 2L-VSC
11
Table 3-1
Switch positions for each phase of the two-level VSC
State Positive + (UxM = +Udc/2) Negative - (UxM = -Udc/2)
S1x
1 0
S2x
0 1
The current paths for positive and negative phase currents iph are depicted in Figure 3-2b. In any switch state, one semiconductor lies within the current path. It should be noted that all switches and diodes of the two-level VSC are stressed by Udc. Assuming a sinusoidal phase current, the maximum switch/diode current is the maximum phase current i ph . These parameters determine the rating of the main semiconductors. Switching losses are created by the commutation processes between the different switch states. Only turn-on and turn-off losses of active switches and recovery losses of diodes are considered. Turn-on losses of diodes are usually small so that they can be neglected [1]. The distribution of the switching losses and the conduction losses are summarized in Table 3-2 and Table 3-3 respectively. For a positive phase current iph > 0, the commutation (+ ) is initiated by the turn-off of T1x and the current forced from T1x to DT2x (x = a, b, c). The situation is visualized in Figure 3-8c, where the current path of the switching active device is marked bold and the current path of the switching passive device is marked with a dashed line. The loss devices are encircled. In contrast, the commutation ( +) is initiated by the turn-off of D2x and the current forced from DT2x to T1x. For a negative phase current iph < 0, the commutation (+ ) is initiated by the turn-off of DT1x and the current forced from DT1x to T2x. In contrast, the commutation ( +) is initiated by the turn-off of T2x and the current forced from T2x to DT1x, as shown in Figure 3-8c.
Table 3-2 State + - + - Table 3-3 State T1x Negative phase current T1x Negative phase current Switching losses in the two-level VSC T2x DT1x Positive phase current DT2x Conduction losses in the two-level VSC T2x DT1x Positive phase current DT2x
+ +
3.1.3. Sine-Triangle Modulation
The purpose of PWM three-phase converters is to shape and to control the three-phase output voltages in magnitude and frequency with an essentially constant input voltage Udc. To obtain balanced three-phase output voltages in a three-phase PWM, the same triangular voltage
12
waveform U tri is compared with three control voltage waveforms (U con,a , U con,b , U con ,c ) that are 120 out of phase. In order to generate the switching signals, three control signals are compared with a repetitive switching frequency triangular waveform, as shown in Figure 3-3a. The frequency modulation ratio mf and the amplitude modulation ratio ma of a PWM are defined as
mf =
ma =
f tri fn
U con ,1 U
tri
(3-2) (3-3)
where U con,1 denotes the peak value of the fundamental component of the reference voltage.
For a sine-triangle modulation the linear modulation range is limited to values of m a 1 . By adding a third harmonic with one-sixth of the fundamental amplitude, it can be expanded to its theoretical maximum of ma = 1.155 [73]. Thus, the reference control voltage per phase is
1 U con,x ( t ) = U sin ( 3w1t ) con ,1 sin ( w1t ) + 6 In order to trigger the switches, the following algorithm can be used:
U con,x > U tri S1x = on U con,x < U tri S1x = off U dc 2 U dc 2
(3-4)
( S2 x = off ) ( S2 x = on )
U xm =
( x = a,b,c ) ( x = a,b,c )
(3-5) (3-6)
U xm =
Since the two switches are never off simultaneously, the output voltage UxM fluctuates between two values (Udc/2 and Udc/2). The gating signals (Vg1,x and Vg2,x) and switching sequence according to Figure 3-1 are depicted in Figure 3-3b (for m f = 15 ).
3.1.4. Output Waveforms and Spectrum
The following equations will be very helpful to obtain the line-to-line voltages (Uab, Ubc and Uca) and line-to-neutral voltages (Uan, Ubn and Ucn) respectively. For all investigations in this thesis, a load with a floating star point is assumed.
U ab = U aM - U bM U an = U aM - U nM
where the common mode voltage UnM is calculated as
(3-7) (3-8)
U nM =
1 (U aM + U bM + U cM ) 3
(3-9)
It should be noted that the same value of the average dc component exists in the output voltages of any one of the legs, which are measured with respect to the negative dc rail "-". These dc components are suppressed in the line-to-line voltages, as shown in Figure 3-3d. The phasemidpoint output voltage waveform (UaM, UbM, and UcM) and the common mode voltage are depicted in Figure 3-3c and Figure 3-3e respectively. The common mode voltage can assume the voltage levels of Udc/2 and Udc/6.
13
Utri Udc
Ucon, a
Ucon, b
Ucon, c (a)
-Udc 1 Vg1, a 0 1 Vg2, a 0 Udc / 2 UaM 0 (b)
(c)
-Udc / 2 Udc Uab (d)
-Udc Udc / 2 Udc / 6 0 -Udc / 6 -Udc / 2 0 90 180 270 360 (e)
UnM
Figure 3-3 Voltage waveforms of the 2L-VSC: (a) control signals Ucon, x and triangular signal Utri, (b) gating signals in phase a, (c) phase-midpoint output voltage UaM, (d) line-toline output voltage Uab, (e) common mode voltage UnM
14
In order to eliminate even harmonics, the frequency modulation ratio mf should be odd. The odd harmonics in the phase-midpoint voltages are the same as the output of any one of the legs, centred around the switching frequency and its multiples (mf, 2mf, ...), as shown in Figure 3-4a. Various harmonics in the line-to-line voltage (Uab, Ubc and Uca) are suppressed due to the phase difference between the mf harmonic in the output voltage of any one of the legs, as shown in Figure 3-4b.
0.6 Harmonic Magnitude (p.u.)
(U aM )h
U dc
mf = 15, ma = 1.15
(a)
0.4
0.2
0 1 Harmonic Magnitude (p.u.) 0.8 0.6 0.4 0.2 0
1 3
mf
2m f
mf = 15, ma = 1.15
3m f
(U ab )h
U dc
(b)
mf
Harmonic Order
2m f
3m f
Figure 3-4 Harmonic spectrum of the 2L-VSC: (a) phase-midpoint output voltage, (b) line-toline output voltage
3.2. Diode Clamped Voltage Source Converter (DC VSC) 3.2.1. Structure
A type of a voltage source converter configuration, which is important for high-power applications, is the so-called diode clamped (DC) converter. The diode-clamped converter provides multiple voltage levels through the connection of the phases to a series bank of capacitors. According to the original invention [127], the concept can be extended to any number of levels by increasing the number of capacitors. Early descriptions of this topology were limited to three levels [37], where two capacitors were connected across the dc bus resulting in one additional level. The additional level was the neutral point of the dc bus; hence, the terminology NPC converter was introduced [37]. However, with an even number of voltage levels, the neutral point is not accessible, and the term multiple point clamped (MPC) is sometimes applied [41]. Due to capacitor voltage balancing and also high voltage stress on the clamping diodes with a number of levels larger than three, the diode-clamped converter implementation has been mostly limited to three levels [17], [122], [123]. In this case the converter is usually called Three-Level Neutal Point Clamped Voltage Source Converter (3L-
15
NPC VSC). One phase leg consists of 2(N-1) active switches and (N-1) (N-2) clamping diodes, where N is the number of voltage levels shown in Figure 3-5 [122]. The total dc bus voltage Udc is distributed across the dc capacitors C1, C2, ..., C(N-1). Hence, an output voltage of Udc / (N-1), ..., Udc / (N-1) is possible at the output [47].
M(N-1) idc(N-1) ic(N-1) C(N-1) M(N-2) idc(N-2) ic(N-2) C(N-2) M(N-3) idc(N-3) ic(N-3) C(N-3) M(N-4) idc(N-4) ic(N-4) S( N -1 )a S( N -2 )a
S( N -3 )a
D(N-1)a
S(N-1)a
D(N-2)a S(N-2)a D(N-3)a S(N-3)a D2a S2a S1a iph,a a
Udc
M1
idc1 ic1 C1
S2 a S1a
Mo
Figure 3-5 One-phase N-Level Neutral Point Clamped Converter [122]
3.2.1.1. Three-Level Neutral Point Clamped Voltage Source Converter (3L-NPC VSC)
The topology of the three-level neutral point clamped (diode-clamped) converter is presented in Figure 3-6. It contains 12 unidirectional active switches having inverse diodes and 6 neutral point clamp diodes. The switches S1x ,S2 x are named outer switches ( Sout ) and the remaining switches S1x ,S 2 x are designated inner switches ( Sin ). The group of NPC-diodes is referred to as D2 x ,D1x . This converter has a zero dc voltage centre point "M1", which is switchable to the phase outputs, thereby creating the possibility of switching each converter phase leg to one of three voltage levels. The major benefit of this configuration is that, while there are twice as many switches as in the two-level converter, each of the switches must block only one-half of the dc link voltage "Udc/2" [7]. However, one problem that does not occur in a two-level converter is the need to ensure voltage balance across the two series-connected capacitors making up the dc link. One solution is to simply connect each of the capacitors to its own
16
isolated dc source (for example, the output of a diode bridge fed from a secondary transformer) [7], [124]. The other method is to balance the two capacitor voltages by feedback control [7], [124], [125].
M2 idc2 T2a T1a DT2a DT1a a Uc1 T2a D1a T1a D1b T2b T1b D1c T2b T1b DT2b DT1b b T2c T1c T2c T1c DT2c DT1c c S2c
D2a C2 Udc M1 C1 Uc2 idc1
D2b
D12
M0
idco iph,a
Uab n
Ubc
Figure 3-6 Three-phase Three-Level Neutral Point Clamped Converter
3.2.1.1.1. Switch States and Commutations
In order to produce three levels, the switches are controlled so that only two of the four switches in each phase leg are turned on at any time [37]. In summary, each phase node (a, b, or c) can be connected to any node in the capacitor bank (M0, M1, and M2). Thus, the number of different converter switch states calculates to nsw = N ph = 33 = 27 (3-10)
with N being the number of voltage levels in the dc link and ph being the number of phases. Connection of the a-phase to junctions M0 and M2 can be accomplished by switching both transistors T1a and T2a either off or on. These states are the same as the two-level inverter, yielding a phase voltage of UxM1 = Udc/2 or UxM1 = -Udc/2 assuming UC2 = UC1 = Udc/2. The connection to the junction M1 is accomplished by gating T1a on and T2a off. In this representation, the labels T1a and T2a are used to identify the transistors as well as the transistor logic (1 = on and 0 = off). Since the transistors are always switched in pairs, the complement transistors are labelled T 1a and T 2 a accordingly. In a practical implementation, some dead time is inserted between the transistor signals and their complements meaning that both transistors in a complementary pair may be switched off for a small amount of time during a transition. However, for this discussion here the dead time will be ignored. From Figure 3-6 it can be seen that, with this switching state, the a-phase current iph,a will flow into the junction through diode D1a if it is negative, or out of the junction through diode D2a if the current is positive. According to this description, the switch positions for three possible states of each phase leg are given in Table 3-4. The current paths for positive and negative phase currents iph are depicted in Figure 3-7. In zero state, the direction of iph determines whether the upper or lower path of the neutral tap is
17
utilized. Therefore, both S1x and S 2 x have to be turned on in zero state "0" to provide an open path in case the phase current reverses. In any switch state, two semiconductors in series lie within the current path, either two active switches or two diodes for the states positive "+" and negative "-". It should be noted that each of the switches must block only one-half of the dc link voltage Udc/2 assuming sinusoidal currents. The maximum switch/diode current is the maximum phase current i ph . These parameters condition the rating of the main semiconductors. The distribution of the conduction losses is summarized in Table 3-5.
Table 3-4 State Positive + (UxM1 = +Udc/2) Zero 0 (UxM1 = 0) Negative - (UxM1 = -Udc/2) Switch positions for one phase of the three-level NPC VSC
S1x
1 1 0
S2 x
1 0 0
S1x 0 0 1
S2 x 0 1 1
S2x U dc 2 D2 x S1x U dc 2 D2 x
S2x S1x U dc 2 D2 x
S2x S1x
U dc 2
D1x
S2 x S1x
U dc 2
D1x
S2 x S1x
U dc 2
D1x
S2 x S1x
Figure 3-7 Conduction path of the Three-Level Neutral Point Clamped Converter Table 3-5 State + 0 - + 0 - Conduction losses in the 3L-NPC VSC
T1x

DT 1x
T2 x
DT 2 x
T1x
DT 1x
T2 x
DT 2 x
D1x
D2 x
Positive phase current
Negative phase current
Switching losses are created by the commutation processes between the different switch states. For a positive phase current iph > 0, the commutation from "+" towards "-" (+ 0 ) is named forced commutation. The contrary natural commutation ( 0 +) realizes a positive output power gradient. They are initiated by an active turn-on transient. For the following discussion of commutations, a positive phase current iph > 0 is assumed. Only turn-on and turn-off losses of active switches and recovery losses of diodes are
18
considered. For a positive phase current iph > 0, the commutation (+ 0) is initiated by the turn-off of T2x and the current is forced from T2x to D2x. After a dead time (to ensure that T2x has completely turned off), T2 x is turned on. The switches T1x and T1x stay on and off respectively. Only two switches and diodes are involved in this commutation: T2x and D2x. Essential turn-off losses occur in T2x. Though the switch T2 x is turned on, it does not experience losses since it does not take over any current after the commutation. For the reverse commutation (0 +), all switching transitions take place in the reverse order. T2 x is turned off first, followed by turning on T2x after the dead time. Turning off T2 x does not affect the phase current. It only returns to the positive rail after the turn-on of T2x. Recovery losses occur in D2x, and T2x experiences turn-on losses. The situation for this pair of commutations is visualized in Figure 3-8a, where the current path of the switching active device is marked bold and the current path of the switching passive device is marked with a dashed line. The loss devices are encircled. Four devices are involved in the commutation (0 ) (Figure 3-8b). It is started by the active turn-off of the switch T1x, forcing the current from its path through D2x and T1x to DT 1x and DT 2 x . T2 x has already been in the on state before; T1x is turned on after a dead time. T1x faces turn-off losses.
S 2x U dc 2 D2 x E rec D1 x S2x S1 x S1x
E on E off U dc 2
S 2x D2 x S1x
E on E off
U dc 2
U dc 2
D1 x
S2x
S1 x
E rec
(a)
S 2x U dc 2 D2 x S1x E rec
(b)
S 2x U dc 2 D2 x E rec U dc 2 D1 x S2x S1 x S1x
U dc 2
D1 x
S2x S1 x
E on E off
E on E off
(c)
(d)
Figure 3-8 Commutations and switching losses in the 3L-NPC VSC: (a) and (b) for positive load current, (c) and (d) for negative load current
19
Although the diode D2x in series with T1x is turned off too, it does not experience notable recovery losses since it does not take over voltage after the commutation. Again, for the reverse commutation ( 0), all switching transitions take place in the reverse order. T1x is turned off, and T1x is turned on after a dead time. After triggering T1x, the phase current commutates from DT 1x and DT 2 x back to D2x and T1x. Both diodes in series DT 1x and DT 2 x are turned off, but only DT 1x takes over blocking voltage. Thus, only DT 1x experiences recovery losses. T1x faces turn-on losses. This situation is depicted in Figure 3-8b. The commutations at negative phase current are illustrated in Figure 3-8c and Figure 3-8d. The distribution of the switching losses is summarized in Table 3-6. It is important to note that all commutations in the NPC VSC can be explained by the basic commutation cell, comprising one active switch and one diode.
Table 3-6 State Switching losses in the 3L-NPC VSC
T1x
DT 1x
T2 x
DT 2 x
T1x
DT 1x
T2 x
DT 2 x
D1x
D2 x
+0 0
+0 0
3.2.1.1.2. Sine-Triangle Modulation
To obtain balanced three-phase output voltages, the converter is controlled by a PWM technique. The reference control voltage per phase is
1 U con,x ( t ) = U sin ( 3w1t ) con,1 sin ( w1t ) + 6 (3-11)
where U con,1 denotes the peak value of the desired fundamental component of the reference voltage.
In order to generate the switching signals, two triangular voltage waveforms U tri ,up and U tri ,low are compared with three control voltage waveforms that are 120 out of phase (which is drawn for m f = 15 ), as shown in Figure 3-9a. In order to trigger the switches, the following algorithm can be used
U dc U con ,x > U tri ,up ( S 2 x = on , S1x = on ) U xM1 = 2 U dc U con ,x < U tri ,low ( S 2 x = on , S1x = on ) U xM1 = 2 else U xM1 = 0 ( x = a,b,c )
(3-12)
The positive half wave of the desired sinusoid is generated by switching the respective phase leg
20
between the positive "+" and zero "0" states, and the negative half wave is generated by switching between the zero "0" and negative "-" states. The average switching frequency per device equals half the carrier frequency visible at the output.
Utri,up Udc Ucon, a Ucon, b Utri,low Ucon, c (a)
-Udc 1 Vg2, a 0 1 Vg1, a 0 Udc / 2 UaM1 0 (c) (b)
-Udc / 2 Udc Udc / 2 0 -Udc / 2 -Udc Udc / 2 UnM1 (e) Uab (d)
-Udc / 2
90
180
270
360
Figure 3-9 Voltage waveforms of the 3L-NPC VSC: (a) control signals Ucon, x and triangular signals Utri,up and Utri,low, (b) gating signals in phase a, (c) phase-midpoint output voltage UaM1, (d) line-to-line output voltage Uab, (e) common mode voltage UnM1
21
The output voltage fluctuates between three values (Udc/2, 0, and Udc/2). The gating signals and switching sequence according to Figure 3-6 are depicted in Figure 3-9b. The output voltage waveforms of the three-phase 3L-NPC VSC according to Figure 3-6 are depicted in Figure 3-9. The line-to-line voltages of the three-level converter, e.g. U ab = U aM1 - U bM1 comprise five voltage levels, viz. +Udc, +Udc/2, 0, -Udc/2, -Udc (see Figure 3-9d). The connection of two considered phases to the opposite dc rails gives rise to the maximum lineto-line voltage of Udc. The intermediate voltage levels are generated by connecting one phase to neutral point M1, whereas both phases switched to the same dc terminal create a zero voltage. The comparison of the line-to-line voltage waveform of Figure 3-9d with that of a two-level converter clearly reveals the superior output voltage quality of the 3L-NPC VSC. The steps in the line-to-line voltage are reduced to Udc/2, compared to Udc for the two-level converter. Moreover, the reduction of the commutation voltage to Udc/2 yields lower switching losses for every single commutation [3]. The common mode part of the phase voltages drops between load star point "n" and converter neutral point "M1". The common mode voltage depicted in Figure 3-9e is calculated as (3-13)
U nM1 =
1 U aM1 + U bM1 + U cM1 3
(3-14)
and the line-to-neutral voltage shown in Figure 3-9c is as follows U an = U aM1 - U nM1 (3-15)
The line to neutral voltage consists of nine voltage levels, viz. 2Udc/3, Udc/2, Udc/3, Udc/6, and 0.
100 Harmonic Magnitude (p.u.)
(U )
U dc
(a)
mf = 15, ma = 1.15
aM 1 h
10-3 100 Harmonic Magnitude (p.u.)
1 3
mf
2m f
3m f
(U ab )h
U dc
(b)
mf = 15, ma = 1.15
10-3
mf
2m f Harmonic Order
3m f
Figure 3-10 Harmonic spectrum of the 3L-NPC VSC: (a) phase-neutral point output voltage, (b) line-to-line output voltage
22
The common mode voltage can assume the voltage levels of Udc/2, Udc/3, Udc/6, and 0. However, the maximum common mode voltage arises from the connection of all three phases to either the positive or the negative dc link. The odd harmonics in the line-to-neutral voltages are centred around a switching frequency and its multiples ( mf ,2mf ,3mf ,... ), as shown in Figure 3-10a. Some dominant harmonics are suppressed in the line-to-line voltage (Uab, Ubc and Uca), as shown in Figure 3-10b.
3.3. Flying Capacitor Voltage Source Converter (FLC VSC) 3.3.1. Flying Capacitor Converter Structure
Another fundamental multi-level topology, the flying capacitor converter, involves a series connection of capacitor switching cells [44]. This topology has several unique and attractive features when compared to the diode-clamped converter. One feature is that added clamping diodes are not needed. Furthermore, the flying capacitor converter has a switching redundancy within the phase, which can be used to balance the flying capacitors so that only one dc source is needed. Traction converters (e.g. T13 locomotive [45]) and industrial medium voltage converters (e.g. SYMPHONY [45], [80]) are typical applications of this topology. One phase leg consists of 2(N-1) active switches and (N-2) flying capacitors, with N being the number of level voltage waveforms UxM shown in Figure 3-11 [47].
ic(N-2),a
S(N-1)a S(N-2)a
U dc 2
ic2,a ic1,a
S3a S2a S1a Cell 1 iph,a a
Udc
C(N-2)a
C2a
C1a
S1a S2a S3 a
U dc 2
S( N 2 )a S( N 1 )a
Figure 3-11 The generalized N-Level Flying Capacitor Converter [122]
23
3.3.1.1. Three-Level Flying Capacitor Voltage Source Converter (3L-FLC VSC)
The topology of the three-level flying capacitor converter is presented in Figure 3-12. It contains 12 unidirectional active switches having inverse diodes and 3 flying capacitors. The general concept of operation is that each flying capacitor is charged to one-half of the dc voltage. It can be connected in series with the phase to add or subtract this voltage.
ic1,a T2a T1a M U dc 2 UC1a C1a T1a T2 a DT2a DT1a a C1b S1b S2b S2b S1b b C1c S1c S2c S2c S1c c
U dc 2 Udc
ic1,b
ic1,c
iph,a
Uab
Ubc
Figure 3-12 Three-phase Three-Level Flying Capacitor Converter
In order to produce three levels, the switches are controlled so that only two of the four switches in each phase leg are turned on at any time. In this representation, the labels T1a and T2a are used to identify the transistors as well as the transistor logic (1 = on and 0 = off). Since the transistors are always switched in pairs, the complement transistors are labelled T1a and T2 a accordingly. Table 3-7 shows the switch positions for each phase leg. In comparison to the three-level diode clamped converter, an extra switching state is possible. In particular, there are two transistor states which make up the zero state. Considering the direction of the a-phase flying capacitor current ic1,a for the redundant states, a decision can be made to charge or discharge the capacitor, and the capacitor voltage can therefore be regulated to its desired value by operating the switches within the phase. Due to two switch states that produce the same output voltage but different current directions through the flying capacitor, the capacitors can be balanced regardless of the load current.
Table 3-7 Switch positions for one phase of the three-level FLC VSC
State + 0 -
S1x
1 1 0 0
S2 x
1 0 1 0
S1x 0 0 1 1
S2 x 0 1 0 1
U xM
Udc /2 0 0 -Udc /2
ic1,x
0 - iph iph 0
24
The current paths for positive and negative phase currents iph are depicted in Figure 3-13. For positive and negative phase currents, either both S1x ,S2 x or both S1x ,S2 x , have to be turned on in state "0". In any switch state, two semiconductors in series lie within the current path, either two active switches or two diodes for the states "+" and "-". Like the 3L-NPC, each switch must block only one-half of the dc link voltage Udc/2. The distribution of the conduction losses is summarized in Table 3-8. Switching losses are created by the commutation processes between the different switch states.
U dc 2
T2x T1x M C1x T1x
DT2x DT1x
U dc 2
T2x T1x M C1x T1x
DT2x DT1x
U dc 2
T2 x (a)
U dc 2
T2 x (b)
U dc 2 M U dc 2 (c) C1x
T2x T1x T1x T2x
DT2x DT1x
U dc 2
T2x T1x M C1x T1x T2 x (d)
DT2x DT1x
U dc 2
Figure 3-13 Conduction path of the Three-Level Flying Capacitor Converter Table 3-8 State + 0 - + 0 - Conduction losses in the three-level FLC VSC
T1x

DT 1x
T2 x
DT 2 x
T1x
DT 1x
T2 x
DT 2 x

25
For a positive phase current iph > 0, the commutation (+ 0) is initiated by the turn-off of T1x. After a dead time (to ensure that T1x has completely turned off), T1x is turned on and the current is forced from T1x to D1x . The switches T2x and T2 x stay on and off respectively. Essential turnoff losses occur in T1x. For the reverse commutation (0 +), all switching transitions take place in the reverse order. T1x is turned off first, followed by the turn-on of T1x after the dead time. The situation for this pair of commutations is visualized in Figure 3-14a, where the commutation (+ 0) is marked bold and the reverse commutation (0 +) is marked with a dashed line. The loss devices are encircled. The commutation (0 ) is started by the active turn-off of the switch T2x, forcing the current to DT 2 x . T1x has already been in the on state and T2x faces turn-off losses. Again, for the reverse commutation ( 0), all switching transitions take place in the reverse order. T2 x is turned off and T2x turned on after a dead time. After triggering T2x, the phase current commutates from DT 2 x back to T2x. The diode DT 2 x is turned off and thus experiences recovery losses while T2x faces turn-on losses. This situation is depicted in Figure 3-14c. The commutations at negative phase current are illustrated in Figure 3-14e and Figure 3-14f. The distribution of the switching losses is summarized in Table 3-9.
Table 3-9 State Switching losses in the three-level FLC VSC
T1x
DT 1x
T2 x
DT 2 x
T1x
DT 1x
T2 x
DT 2 x
+0 0
+0 0
The 3L-FLC VSC is modulated by a sine-triangle modulation with an addition of 1/6 of the third harmonics according to equation (3-7). The modulation of this converter can be seen in Figure 315a. In the FLC VSCs, there is one carrier signal per commutation cell and the commutations of one commutation cell are determined by the comparison of the carrier and the reference signals. Two carrier signals are shifted by TC/2, resulting in four commutations per phase during one period TC. In order to generate the switching signals, two triangular voltage waveforms Utri,cell,1 and Utri,cell,2 are compared with three control voltage waveforms that are 120 out of phase (which is drawn for m f = 15 ). In order to trigger the switches, the following algorithm can be used. The gating signals and switching sequence according to Figure 3-12 are depicted in Figure 3-15b.
U con,x > U tri ,cell ,1 S 2 x = on ( S 2 x = off ) U xM = U dc 2 U con,x > U tri ,cell ,2 S1x = on ( S1x = off ) U con,x < U tri ,cell ,1 S 2 x = off U con,x < U tri ,cell ,2 S1x = off else
( x = a,b,c ) ( x = a,b,c )
(3-25)
(S (S
2x
1x
= on ) U xM = U dc 2 = on )
U xM = 0 ( x = a,b,c )
26
U dc 2
M C1x
S2x S1x
(a)
Eon Eoff
U dc 2
M C1x
S2x S1x
Eon Eoff
(b)
U dc 2
S1x S2x
i ph > 0 , commutation (+ 0 )
S2x S1x M C1x
Erec
U dc 2
S1x S2x
i ph > 0 , commutation (+ 0 )
Erec
Eon Eoff
(c)
(d)
U dc 2
U dc 2
M C1x
S2x S1x
Eon Eoff
Erec
U dc 2
S1x S2x
i ph > 0 , commutation ( 0 )
S2x S1x M C1x (e)
Erec
U dc 2
S1x S2x
i ph > 0 , commutation ( 0 )
S2x S1x M C1x
U dc 2
Erec Eon Eoff
U dc 2
Erec
(f)
U dc 2
S1x
S2x
i ph < 0 , commutation (+ 0)
S2x S1x M C1x
U dc 2
S1x S2x
i ph < 0 , commutation (+ 0)
Eon Eoff
(g)
U dc 2
Erec
U dc 2
M C1x
S2x S1x
(h)
Erec
U dc 2
S1x S2x
Eon Eoff
U dc 2
S1x S2x
i ph < 0 , commutation ( 0 )
Eon Eoff
i ph < 0 , commutation ( 0 )
Figure 3-14 Commutations and switching losses in the 3L-FLC Converter (a-d) for positive load current, (e-h) for negative load current
27
Utri,cell,1 Utri,cell,2 Udc
Ucon, a
Ucon, b
Ucon, c (a)
-Udc 1 Vg2, a (b)
0 1 Vg1, a 0 Udc / 2 UaM (c)
-Udc / 2 Udc Udc / 2 0 -Udc / 2 -Udc Udc Udc / 2 0 -Udc / 2 -Udc 0 90 180 270 360 UnM (e) Uab (d)
Figure 3-15 Voltage waveforms of the 3L-FLC VSC: (a) control signals and triangular signals, (b) gating signals in phase a, (c) phase-midpoint output voltage UaM, (d) line-to-line output voltage Uab, (e) common mode voltage UnM
28
The output voltage waveform of the three-phase 3L-FLC VSC according to Figure 3-12 is depicted in Figure 3-15c to Figure 3-15e. The phase-to-midpoint voltages of the 3L-FLC VSC, e.g. UaM, comprise three voltage levels, viz. +Udc/2, 0, -Udc/2 (see Figure 3-15c) and the line-toline voltages, e.g. Uab, comprise five voltage levels, viz. +Udc, +Udc/2, 0, -Udc/2, -Udc (see Figure 3-15d). The connection of two considered phases to the opposite dc rails gives rise to the maximum line-to-line voltage of Udc. The common mode part of the phase voltages drops between load star point "n" and converter midpoint "M". The common mode voltage depicted in Figure 3-15e is calculated according to equation (3-9). The common mode voltage can consist of the voltage levels of 2Udc/3, Udc/2, Udc/3, Udc/6, and 0. For a constant carrier frequency, the 3L-NPC VSC generates half of the switching losses than the 3L-FLC VSC, where two commutation cells switch during one period of the carrier frequency (TC = 1/fC). However, whereas the first carrier band of the line-to-line voltage of the 3L-NPC VSC occurs around the carrier frequency, the first carrier band is centred around two times the carrier frequency in the 3L-FLC VSC (f1Cb = 2fC), as shown in Figure 3-16.
(U aM )h
U dc
mf = 15, ma = 1.15
(a)

0
1 3
mf
2m f
mf = 15, ma = 1.15
3m f
(b)
(U ab )h
U dc
10-3
mf
Harmonic Order
2m f
3m f
Figure 3-16 Harmonic spectrum of the 3L-FLC VSC: (a) phase-neutral point output voltage, (b) line-to-line output voltage
3.3.1.2. Four-Level Flying Capacitor Voltage Source Converter (4L-FLC VSC)
Figure 3-17 shows the structure of the three-phase 4L-FLC VSC. For this converter, the capacitors C1x and C2x are ideally charged to one-third and two-thirds of the dc voltage respectively. The four voltage levels are obtained by the relationships shown in Table 3-10. As with the three-level flying capacitor converter, the highest and lowest switching states do not change the charge of the capacitors. The two intermediate voltage levels contain redundant states so that both capacitors can be regulated to their ideal voltages. In order to generate the switching signals, three triangular voltage waveforms U tri ,cell ,i ( i = 1, 2 ,3) are compared with three control voltage waveforms that are 120 out of phase. The three carrier
29
signals are shifted by TC/3, resulting in six commutations per phase during one period TC. The modulation of the 4L-FLC converter topology can be seen in Figure 3-18a for mf = 15.
ic2,a U dc 2 UC2a UC1a ic1,a
T3a T2a T1a C1a T1a
DT3a DT2a DT1a a
ic2,b ic1,b
S3b S2b S1b
ic2,c ic1,c
S3c S2c S1c
Udc
C2a
C2b
C1b S1b S 2b S 3b
C2c
C1c S1c S2c S3 c
U dc 2
T2 a T3 a
iph,a
Uab
Ubc
Figure 3-17 Three-phase Four-Level Flying Capacitor Converter
In order to trigger the switches, the following algorithm can be used U con,x > U tri ,cell ,1 S3 x = on ( S3 x = off ) U con,x > U tri ,cell ,2 S 2 x = on ( S2 x = off ) U xM = U dc 2 U con,x > U tri ,cell ,3 S1x = on ( S1x = off )
( x = a,b,c )
(U con,x (U con,x (U con,x (U con,x (U con,x (U con,x
U con,x U tri ,cell ,1 , U con ,x > U tri ,cell ,2 , U con ,x U tri ,cell ,1 , U con ,x U tri ,cell ,3 ) or U xM = dc 6 U tri ,cell ,2 , U con ,x > U tri ,cell ,3 ) > U tri ,cell ,1 , U con ,x U tri ,cell ,2 , U con ,x U tri ,cell ,3 )
(3-26)
The output voltage waveforms of the three-phase 4L-FLC VSC according to Figure 3-17 are depicted in Figure 3-18b to Figure 3-18d.
30
Table 3-10 Switch positions for one phase of the four-level FLC VSC
State 0 1 2 3
S1x
0 1 0 0 1 0 1 1
S2 x
0 0 1 0 1 1 0 1
S3 x
0 0 0 1 0 1 1 1
S1x 1 0 1 1 0 1 0 0
S2 x 1 1 0 1 0 0 1 0
S3 x 1 1 1 0 1 0 0 0
U xM
-Udc/2 -Udc/6 -Udc/6 -Udc/6 Udc/6 Udc/6 Udc/6 Udc/2
Ucon, b
ic1,x
0 -iph iph 0 0 iph - iph 0
ic 2 ,x
0 0 -iph iph -iph 0 iph 0
Ucon, c (a)
Utri,cell,3 Utri,cell,2 Utri,cell,1 Ucon, a Udc
-Udc
Udc / 2
UaM
(b)
-Udc / 2 Udc Udc / 2 0 -Udc / 2 -Udc Udc Udc / 2 0 -Udc / 2 -Udc 0 90 180 270 360 (d) (c)
Uab
UnM
Figure 3-18 Voltage waveforms of the 4L-FLC VSC: (a) control signals and triangular signals, (b) phase-midpoint output voltage UaM, (c) line-to-line output voltage Uab, (d) common mode voltage UnM
31
The phase-to-midpoint voltages of the 4L-FLC VSC, e.g. uaM, comprise four voltage levels, viz. Udc/2 and Udc/6 (see Figure 3-18b) and the line-to-line voltages, e.g. Uab, comprise seven voltage levels, viz. Udc, 2Udc/3, Udc/3, 0 (see Figure 3-18c). The common mode voltage UnM can assume the voltage levels of 2Udc/3, 5Udc/9, 4Udc/9, Udc/3, 2Udc/9, and Udc/9 (see Figure 3-18d). The harmonic spectrum of phase voltage and line-to-line voltage are depicted in Figure 3-19. The first carrier band harmonics of the 4L-FLC VSC occurs at three times the corresponding carrier frequency (f1Cb = 3fC). Figure 3-20 shows the transitions between two voltage levels in the 4L-FLC VSC. Some of these transitions (dashed lines) force all switches of the leg to switch. Nevertheless, these critical transitions can be used to achieve the full control of the voltages of the floating capacitors.
100
Harmonic Magnitude (p.u.)
(U aM )h
U dc
mf = 15, ma = 1.15
(a)
10-3 10
0
1 3
mf
2m f
3m f
mf = 15, ma = 1.15 (b)
(U ab )h
U dc
10-3
mf
Harmonic Order
2m f
3m f
Figure 3-19 Harmonic spectrum of the 4L-FLC VSC: (a) phase-neutral point output voltage, (b) line-to-line output voltage
U dc 2 S2x S1x U dc 6 S2x S1x U dc 6 U dc 2
U xM = S3x
U xM = S3x
U xM =
U xM =
S3x S2x S1x off on on
S3x S2x S1x
off off on off off off off on off
on off on on on off
on on on
on off off
Figure 3-20 Transitions between voltage levels for the Four-Level Flying Capacitor
32
3.4. Series Connected H-Bridge Voltage Source Converter (SCHB VSC)
This class of multi-level converters is based on a series connection of single-phase converters (Figure 3-21), and the earliest reference to them appeared in 1975 [128] but several recent patents have been obtained for this topology as well [129], [130], [131]. This converter topology has several advantages that have made it attractive to medium and high power drive applications [86]. Since this topology consists of series power conversion cells, the voltage and power level may be easily scaled. The dc link supply for each H-bridge converter element must be provided separately. The ability to synthesize higher number of output voltage levels with an excellent harmonic spectrum utilizing low-cost low-voltage power semiconductors and capacitors are important advantages of this topology [86]. However, drawbacks of this topology are the large number of power devices and of voltages required to supply each cell with a complex and expensive isolated transformer, as well as control the complexity [126], [129].
iph,a a
idcpa idcpb
c
idcpc
Udcpa
TpRa
TpLa
U pan
Udcpb
TpRb
TpLb
U pbn
Udcpc
TpRc TpRc
TpLc
TpLc
U pcn
TpRa
TpLa
TpRb
TpLb
idc2a
idc2b
idc2c
Udc2a
T2 Ra
T2 Ra
idc1a
T2 La
T2 La
U 2 an
Udc2b
T2 Rb T2 Rb
idc1b
T2 Lb T2 Lb
U 2bn
Udc2c
T2 Rc T2 Rc
idc1c
T2 Lc T2 Lc
U 2 cn
Udc1a
T1Ra T1Ra
T1La
U 1an
Udc1b
T1 Rb T1Rb
T1Lb T1Lb
U1bn
Udc1c
T1Rc
T1Lc
U1cn
T1La
T1Rc
T1Lc
Figure 3-21 Three-phase configuration for the N-Level H-Bridges VSC
3.4.1. Single-Phase Full-Bridge (H-Bridge) Topology 3.4.1.1. Circuit Configuration
The circuit of Figure 3-22 shows the basic topology of an H-bridge converter used for the implementation of SCHB VSCs. It is based on the simple, four switches converter, which is usually used for single-phase applications. A three-phase diode rectifier, fed by an isolated transformer, charges the dc capacitor. The dc voltage feeds a single-phase IGBT bridge, which generates the PWM output of the power cell.
33
idc TL DL a iph
n
SR
TR
DR
U an = U ag U ng
U dc 2
TL
DL g
TR
DR
Figure 3-22 Typical power cell (H-bridge) converter
3.4.1.2. Switch States and Commutations
Each cell consists of two half-bridge configurations. The labels TL and TR are used to identify the transistors as well as the transistor logic (1 = on and 0 = off). Since the transistors are always switched in pairs, the complement transistors are labelled TL and TR accordingly. In order to prevent a short circuit, the complementary leg switches are not switched simultaneously. In other words, whatever state the top switch is in (either on or off) the bottom switch must be in the opposite. The switch positions for the three possible states of each phase leg are given in Table 3-11. The current paths for positive and negative phase currents iph are depicted in Figure 3-23. The zero state "0" can be generated in two ways, depending on the direction of iph. Therefore, if either top switches (TL, TR) or bottom switches ( TL ,TR ) are turned on, the output voltage will lead to zero. In positive "+" and negative "-" states, two diagonally opposite semiconductors, (TL, TR ) or (TR, TL ), lie within the current path, either two active switches or two diodes. Therefore, each typical H-bridge cell can only produce three distinct voltage levels. It should be noted that each of the switches must block the dc link voltage Udc/2. The maximum switch/diode current is the maximum phase current i ph . These parameters determine the basic requirements for rating the main semiconductors. The distribution of the conduction losses is summarized in Table 3-12. Switching losses are created by the commutation processes between the different switch states. Two complement switches in each leg, (TR, TR ) or (TL, TL ), are involved in (+ 0) and (0 ) commutations. For a positive phase current iph > 0, the commutation (+ 0) is initiated by the turn-off of TL in the first leg and the current is forced from TL to DL The switch TR stays turned on. Only two complement switches in the first leg are involved in this commutation. Essential turn-off losses occur in TL. In the second leg, the commutation (+ 0) is initiated by the turn-off of TR and the current is forced from TR to DR. The switch TL stays turned on. Only two complement switches in the second leg are involved in this commutation (TR, TR ). Essential turn-off losses occur in TR . For the reverse commutation (0 +), all switching transitions take place in the reverse order.
34
For example, in the second leg, TR is turned off first, followed by the turn-on of TR after the dead time. Recovery losses occur in DR while TR experiences turn-on losses.
Table 3-11 Switch positions for the single-phase H-bridge cell
State Positive + Zero 0 Negative -
SL
1 1 0 0
SR
0 1 0 1
SL 0 0 1 1
SR 1 0 1 0
Uag
Udc/2 Udc/2 0 0
Ung
0 Udc/2 0 Udc/2
Uan
Udc/2 0 0 -Udc/2
TL
U dc 2
DL
a
TR
n
DR
U dc 2
TL
DL
a
TR
n
DR
TL
DL
(a)
TR
DR
TL
DL
(b)
TR
DR
TL
U dc 2
DL
a
TR
n
DR
U dc 2
TL
DL
a
TR
n
DR
TL
DL
(c)
TR
DR
TL
DL
(d)
TR
DR
Figure 3-23 Conduction path of the single-phase H-bridge cell: (a) positive, (b, c) zero, and (d) negative states Table 3-12 Conduction losses in the single-phase full-bridge converter State + (Uag = Udc/2) 0 (Uag = 0) -(Uag = -Udc/2) + (Uag = Udc/2) 0 (Uag = 0) -(Uag = -Udc/2)
TL

DL
TR
DR
TL
DL
TR
DR
35
The situation for these commutations is visualized in Figure 3-24a, where the current path of the switching active device is marked bold and the current path of the switching passive device is marked with a dashed line. The loss devices are encircled. The commutation (0 ) in the first leg is started by the active turn-off of the switch TL, forcing the current from its path through DL . DR has already been in the on state. TL faces turnoff losses. Again, for the reverse commutation ( 0), all switching transitions take place in the reverse order. TL is turned off and TL turned on after a dead time.
TL
U dc 2
DL
a
TR
n
DR
U dc 2
TL
DL
a
TR
n
DR
TL TL
U dc 2
DL
TR TR
n
DR
TL TL
U dc 2
DL
TR TR
n
DR
DL
a
DR
DL
a
DR
TL
DL
TR
DR
TL
DL
TR
DR
(a)
i ph > 0 , commutation (+ 0)
(b) i ph > 0 , commutation ( 0 )

DR
U dc 2
TL
U dc 2
DL
a
TR
n
TL
DL
a
TR
n
DR
TL
DL
TR
DR
TL
DL
TR
DR
TL
U dc 2
DL
a
TR
n
DR
U dc 2
TL
DL
a
TR
n
DR
TL
DL
TR
DR
TL
DL
TR
DR
(c) i ph < 0 , commutation (+ 0)
(d) i ph < 0 , commutation ( 0 )
Figure 3-24 Commutations and switching losses in the H-bridge cell: (a) and (b) for positive load current, (c) and (d) for negative load current
36
After triggering TL, the phase current commutates from DL back to TL. Diode DL is turned off and thus takes over blocking voltage and experiences recovery losses. TL faces turn-on losses. In the second leg, the commutation (0 ) is started by the active turn-off of the switch TR , forcing the current from its path through DR. DL has already been in the on state. TR faces turnoff losses. Again, for the reverse commutation ( 0), all switching transitions take place in the reverse order. TR is turned off and TR turned on after a dead time. After triggering TR , the phase current commutates from DR back to TR . Diode DR is turned off and thus takes over blocking voltage and experiences recovery losses. TR faces turn-on losses. These situations are depicted in Figure 3-24b. The commutations at the negative phase current are illustrated in Figure 3-24c and Figure 3-24d. The distribution of the switching losses is summarized in Table 3-13.
Table 3-13 Switching losses in the single-phase full-bridge converter State
TLx

DLx
TRx
DRx
TLx
DLx

TRx
DRx
+0 0
+0 0
3.4.1.3. Sine-Triangle Modulation
Each cell is modulated by a sine-triangle modulation with an addition of 1/6 of the third harmonic, as shown in Figure 3-25a. There are two carrier signals U tri1 , U tri 2 and the commutations of one commutation cell (half bridge) are determined by the comparison of the corresponding carrier signal and the reference signal Ucon. The two carrier signals are shifted by TC/2 (180 phase difference with respect to each other). Thus, there are four commutations during one period of the carrier signal. As shown in Figure 3-25a, the comparison of Ucon with U tri1 results in the following logic signals to control the switches in the first leg
U ag U dc if : U con > U tri1 = 2 0 if : U con < U tri1
(T : on,T : off ) (T : off ,T : on )

L L L L
(3-27)
For controlling the second leg switches, U tri 2 is compared with the same control signal, which yields the following
U ng 0 = U dc 2 if : U con > U tri 2 if : U con < U tri 2
(T
: off ,TR : on )
(TR : on,TR : off )
(3-28)
37
Utri,1 Utri,2
Udc
Ucon (a)
-Udc
U dc 2
(b) Uag
0
U dc 2
(c) Ung
0
U dc 2
(d)
Uan,1
Uan
U dc 2
90
180
270
360
Figure 3-25 Voltage waveforms of the H-bridge cell: (a) control signals Ucon and triangular signals Utri,1 and Utri,2, (b) a-leg output voltage Uag, (c) n-leg output voltage Ung, (d) load voltage Uan
Because of the diodes in anti-parallel with the switches, the foregoing voltage given by equations (3-31) and (3-32) are independent of the direction of the output current iph. The output voltages of leg a and leg n with respect to the negative dc rail g are shown in Figure 3-25b and Figure 3-25c respectively. The H-bridge output voltage waveform Uan according to Figure 3-22 is depicted in Figure 325d. This voltage comprises three voltage levels, viz. Udc/2 and 0. Because two legs of the H-bridge are controlled separately, as mentioned in the previous section, the first carrier band harmonics of the output voltage occur at twice the corresponding carrier
38
frequency (f1Cb = 2fC). This advantage appears in the harmonic spectrum of the output voltage waveform, as shown in Figure 3-26. If we choose the frequency modulation ratio mf to be even, the output voltage waveforms of any one of the legs Uag and Ung are displaced by 180 of the fundamental frequency, with respect to each other. Therefore, the harmonic components at the switching frequency in any one of the legs have the same phase, since the output voltage waveforms are 180 displaced and mf is assumed to be even [4]. This results in the cancellation of the harmonic component at the sidebands of the switching frequency in the output voltage. Moreover, the use of this PWM voltage switching causes a smaller ripple on the dc current side. We notice that when both the upper switches are on, the output voltage is zero. The output current circulates in a loop through (TL, DR) or (DL, TR), depending on the direction of iph. During this interval, the current idc is zero. A similar condition occurs when both bottom switches TL and TR are turned on.
(U ab )h
U dc 2
mf = 15, ma = 1.15
10-3
1 3
mf
2m f
Harmonic Order
3m f
Figure 3-26 Harmonic spectrum of the H-bridge output voltage
3.4.2. Three-Phase Two-Level H-Bridge (2L-H-Bridge) Topology 3.4.2.1. Circuit Configuration
Converters having additional phases can be realized by simply adding multiple numbers of Hbridge converter legs (Figure 3-22). A simplified diagram of a three-phase two-level H-bridge converter is shown in Figure 3-27. It contains 12 unidirectional active switches with inverse diodes.
iph,a
U ab
n
U bc
idc,a U dc,a
U an U dc,b
idc,b
U bn U dc,c
idc,c
U cn
S La
S La
S Ra
S Ra
S Lb
S Lb
S Rb
S Rb
n
S Lc
S Lc
S Rc
S Rc
Figure 3-27 Three-phase configuration for the 2L-H-Bridges Voltage Source Converter
39
In order to produce three levels in each phase leg, the switches are controlled so that only two of the four switches in each phase leg are turned on at any time. The labels SLx and SRx are used to identify the transistors in each phase (x = a, b, c). Since the transistors are always switched in pairs, the complement transistors are labelled S Lx and S Rx accordingly. The switch positions for three possible states of each phase leg remain the same as for a single-phase Hbridge (see Table 3-11). The distribution of the conduction and switching losses are the same as for a single-phase H-bridge (see Table 3-12 and Table 3-13).
The fundamental modulation concept remains the same as for a single-phase H-bridge. The modulation method for a three-phase 2L-H-Bridge is shown in Figure 3-28a. It demonstrates that the difference between the three-phase 2L-H-Bridge and a single-phase H-bridge are the two-phase legs which were added to the first. Furthermore, the reference signals for each phase leg are now displaced by 120. Therefore, each phase leg is controlled separately by comparing a reference signal U con , x (x=a, b, c) with the triangular waveforms U tri1 , U tri 2 . The commutations are determined by the comparison of the corresponding carrier signal and the reference signal. The two carrier signals are shifted by TC/2. Thus, there are four commutations per phase during one period of the carrier signal. In order to generate the gate signals, the same algorithm as for a single-phase H-bridge can be used U dc U con ,x > U tri1 (TLx : on,TLx : off ) ,U con ,x > U tri 2 (TRx : off ,TRx : on ) U xn = 2 U dc U con ,x < U tri1 (TLx : off ,TLx : on ) ,U con ,x < U tri 2 (TRx : on,TRx : off ) U xn = 2 U xn = 0 else
(3-29)
Because of the inverse diodes in anti-parallel to the switches, the voltage given by equation (329) is independent of the direction of the output current iph. The output voltage waveforms of the three-phase 2L-H-Bridge according to Figure 3-27 are depicted in Figure 3-28. The phase voltages (e.g. Uan) comprise three voltage levels, viz. Udc/2 and 0 [see Figure 3-28c], and the line-to-line voltages (e.g. Uab) comprise five voltage levels, viz. Udc, Udc/2, and 0 (see Figure 3-28d). The harmonic spectrum of the phase voltage and the line-to-line voltage are illustrated in Figure 3-29a and Figure 3-29b respectively (which is drawn for m f = 15 ). Like in a single-phase Hbridge, the first carrier band harmonics of the 2L-H-Bridge occurs at twice the corresponding switching frequency (f1Cb = 2fC).
40
Utri,1 Utri,2 Udc
Ucon, a
Ucon, b
Ucon, c (a)
-Udc 1 VgL, a 0 1 VgR, a 0

U dc 2
(b)
(c) Uan,1
0 Uan
U dc 2
Udc
U dc 2
(d) Uab
0
U dc 2
-Udc 0 90 180 270 360
Figure 3-28 Voltage waveforms of the three-phase 2L-H-Bridge cell: (a) control signals Ucon,x and triangular signals Utri,1 and Utri,2, (b) gate signals, (c) output phase voltage, (d) output line-to-line voltage
41
(U an )h
U dc 2
mf = 15, ma = 1.15
(a)
1 3
mf
2m f
mf = 15, ma = 1.15
3m f
(b)
(U ab )h
U dc 2
10-3
mf
Harmonic Order
2m f
3m f
Figure 3-29 Harmonic spectrum of the three-phase 2L-H-Bridge cell: (a) phase output voltage, (b) line-to-line output voltage
3.4.3. Introduction to the Series Connected Two-Level H-Bridge Voltage Source Converter (SC2LHB VSC)
In traditional converter topologies such as the 2L-VSC or 3L-NPC VSC, the device with the maximum available voltages (e.g. 6.5kV IGBT) is connected in series to reach the required lineto-line output voltage (Ull > 3.3kV and Ull > 4.16kV). The concept of the generalized Series Connected Two-Level H-Bridge Voltage Source Converter (SC2LHB VSC) is shown in Figure 3-30. It is based on series connected isolated H-bridge cells rather than series connected devices. The patent for the series connected isolated H-bridge cell was originally obtained by Robicon [129]. The SC2LHB VSC is a popular power converter for motor drives [42], [46], [129], [130], power supplies [49], [132], and ac power systems [52], [54], [57], [58]. The SC2LHB VSCs will be designated according to the voltage levels of the individual Hbridge cells. The step of the output voltage is comparatively small and equal to the dc bus voltage of one H-bridge cell (order of 600 volts for a 460-volt input). To attain the rated medium output voltage, all single-phase low-voltage H-bridge cells are connected in series, only using low-cost low-voltage devices (e.g. 1.7kV IGBT). The total virtual dc link voltage Udc,tv differs according to the necessary line-to-line output voltage of the converter. This voltage depends on the number of series connected H-bridges p and is determined by
U dc ,tv = 2 p U dc ,HB
(3-30)
Using the same dc link voltage Udc,HB for each H-bridge cell, the converter synthesizes an output phase voltage (e.g. Uan, Ubn , Ucn) U xn = U1xn + U 2 xn + ... + U pxn (3-31)
42
U an
i ph ,a
a
U pan
S pRa
S pRa
U ab
p
3
S pLa
S pLa
b
S pLb
S pLb
p
3
S pRb
S pRb
U pbn
c
S pLc S pLc S pRc S pRc
p
3
U pcn
S 2 La
S 2 Ra
U 2 an
0 3
S 2 La
S 2 Ra
S 2 Lb S 2 Rb
2
3
U 2 bn
S 2 Lb
S 2 Rb
S 2 Lc S 2 Rc
2
3
U 2 cn
S 2 Lc
S 2 Rc
1
3
S1La S1 La
S1 Ra S1 Ra
U 1an U 1bn
S1Lb S1Lb S1 Rb S1 Rb
S1Lc S1Lc S1Rc S1 Rc
1
3
1
3
U 1cn
Figure 3-30 Series Connected Two-Level H-Bridge Voltage Source Converter with p series Hbridge cells per phase
with a number of output phase voltage levels

N=2p+1
(3-32) (3-33)
and a number of output line-to-line voltage levels

Nll = 2 N 1
The number of series H-bridge cells is chosen typically from 2 to 5, for the worldwide standard machine voltages of 2.3 to 7.2kV. With two power cells per phase (p = 2), the circuit of Figure 3-30 can produce five distinct phase voltage levels (N = 5). With three, four, and five cells per phase; 7, 9, and 11 distinct phase voltage levels are available. There are several families of Hbridge cells with the same input voltage (460, 630, and 690) that are capable to produce (800,
43
1100, and 1200) line-to-line output voltages (per cell) for rated currents ranging from 70 to 1000 amperes [35]. For the modulation, two triangular carrier signals are needed for each cell, which is the same as in the single-phase H-bridge. It should be noted that the pair of triangular carrier signals applied in each cell have a phase shift of 180/p, in contrast to the triangular carrier of the previous Hbridge cell, with the first H-bridge cell as reference cell. With this modulation, the frequency of the first harmonics carrier band of the output voltage is equal to
f1Cb =2 p f C
(3-34)
where fC denotes the carrier frequency. Due to many different output voltage levels and the high frequency f1Cb, the output voltage and current harmonics are low; and therefore, the filtering processes are easier. Each additional level is another "degree of freedom" in reducing the output harmonics. It is possible to add an extra tier of H-bridge cells that enables the drive to operate with an increased output voltage (p+1)/p capability. Since the output voltage is distributed uniformly between the H-bridge cells, there is some redundancy which allows the drive to operate with one shortened H-bridge. If an H-bridge fails, its output is shortened by the controller without any user intervention. The drive remains at work and operates with nominal output voltage. The maximum input and output voltages of each H-bridge cell are equal to the instantaneous dc link voltage, according to Figure 3-22. Therefore, the dc link capacitor acts as a large snubber for all the devices. All H-bridge cells carry the same current at the output fundamental voltage. This results in an equal power among all H-bridge cells, a simple control structure, and modularity of the control. Although the H-bridge could be constructed with a variety of low voltage semiconductor devices, the LV-IGBT is an excellent choice due to its extremely low gate power and fast switching behaviour. Robicon utilizes low-cost low-voltage IGBTs, e.g. 1700V, for its medium voltage drives [36]. The drive can produce 2.3kV, 3.3kV, 4.16kV, and 6kV line-to-line voltages with two, three, four, and five H-bridge cells in series per phase. Other important advantages of this drive are a minimal common mode voltage and a potentially low dv/dt in the output voltages. However, the dc link supply for each H-bridge cell must be provided separately. This is accomplished by multiple isolated secondary windings of an integral isolation transformer. The transformer is more complex and expensive than customary, but it performs several very important functions. First, it ensures that any common mode voltage does not have to be supported by the motor insulation. Second, by the phase shift
p=
360 6p
(3-35)
between the secondary windings, it is possible to cancel most of the harmonic currents drawn by the individual power cells so that the primary currents are nearly sinusoidal (the pulse number at the primary is equal to 6p). The transformer impedance is consciously made larger than normal to limit the inrush current and to reduce the harmonics. Due to the excellent harmonic performance of the grid side, the reduced input filter compensates the extra cost of the transformer. The transformer efficiency is typically 98.5%. Table 3-14 summarizes the quantities comparison for this topology with different H-bridge cells per phase.
44
Table 3-14 Quantities comparison of the SC2LHB VSC Number of series connected H-Bridges p Number of phase output voltage level N Number of line-to-line output voltage level Nll Number of dc-link capacitors Transformer phase displacement p Number of the carrier signals Carrier phase shift displacement 2 5 9 6 30 4 90 3 7 13 9 20 6 60 4 9 17 12 15 8 45 5 11 21 15 12 10 36
p 2p+1 4p+1 3p 60/p 2p 180/p
3.4.3.1. Series Connected Two-Level H-Bridge Voltage Source Converter with Two Power Cells per Phase Leg (5L-SC2LHB VSC) 3.4.3.1.1. Circuit Configuration
Figure 3-31 shows the 5L-SC2LHB VSC utilizing two three-level H-bridge cells in series per phase. This structure may be related to Figure 3-30 regarding the points labelled a and n. It contains 24 unidirectional active switches with inverse diodes, 6 separated dc link capacitors, and a 12-pulse transformer with two secondary windings which are shifted 30 with respect to each other. If the dc voltage of each H-bridge cell is set to the same value of Udc,HB, the resulting converter can operate with five output phase voltage levels (e.g. Uxn).
a
30
3
S 2 La
S 2 Ra
U 2 an
S 2 La
S 2 Ra
S 2 Lb S 2 Rb
30
3
U 2bn
c
U 2 cn
S 2 Lb
S 2 Rb
S 2 Lc S 2 Rc
30
0 3
S 2 Lc
S 2 Rc
0
3
S1La S1La
S1Ra S1Ra
U1an U1bn
0
3
S1Lb S1Lb
S1Rb S1Rb
0
3
U1cn
S1Lc S1Lc S1Rc S1Rc
Figure 3-31 5L-SC2LHB Voltage Source Converter
In order to produce five levels, the switches are controlled so that only two of the four switches in each H-bridge cell are turned on at any time. The labels SpLx and SpRx are used to identify the switches as well as the switches logic (1 = on and 0 = off, p = 1, 2). Since the
45
switches are always switched in pairs, the complement switches are labelled S pLx and S pRx accordingly. In order to prevent a short circuit, the complementary leg switches are not switched simultaneously. In other words, in whatever state that the top switch is, the bottom switch must be in the opposite. The switch positions for five possible states of each phase leg as well as the individual H-bridge voltage are given in Table 3-15. It shows that there are six and four redundant possibilities for switching Uxn = 0 and Uxn = Udc,HB. Figure 3-32 illustrates the transitions between the output voltage steps. The number of commutations between each two adjacent voltage levels are marked in grey. These critical transitions can be used to achieve the full control of the voltages. As can be seen from this Figure, some of these transitions force three switches to switch. For the following discussion of commutations, only one of the transition states is assumed, as indicated in bold line in Figure 3-32. The current paths for positive and negative phase currents iph are depicted in Figure 3-33. If either the diagonally opposite semiconductors ( S1Lx ,S1Rx ,S 2 Lx ,S2 Rx ) or ( S1Lx ,S1Rx ,S 2 Lx ,S2 Rx ) are turned on, i.e. either two active switches or two diodes, then the phase-to-ground output voltage will lead to 2Udc,HB or -2Udc,HB (Table 3-15). The positive and the negative states Udc,HB and Udc,HB can be generated, if either for example, the switches ( S1Lx ,S1Rx ,S 2 Lx ,S2 Rx ) or ( S1Lx ,S1Rx ,S2 Lx ,S2 Rx ) are turned on (Table 3-15). The zero state can be generated if the upper switches ( S1Lx ,S1Rx ,S 2 Lx ,S 2 Rx ) in both H-bridges lie within the current path. Therefore, each phase-to-ground can produce five distinct voltage levels. It should be noted that each of the switches must block the dc link voltage Udc,HB (e.g. Udc/4), compared to Udc/2 in the 3L-NPC and 3L-FLC converters, to achieve the same output voltage. The distribution of the conduction and switching losses are the same as for a single-phase Hbridge converter (refer to section 3.4.1.2).
Table 3-15 Switch positions for the 5L-SC2LHB VSC State 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
S1Lx 1 1 1 1 0 1 1 0 0 0 1 0 0 1 0 0
S1Rx 0 0 0 1 0 1 1 0 0 1 0 1 1 1 0 1
S 2 Lx 1 1 0 1 1 0 1 1 0 1 0 1 0 0 0 0
S 2 Rx 0 1 0 0 0 0 1 1 0 0 1 1 0 1 1 1
U1xn Udc,HB Udc,HB Udc,HB 0 0 0 0 0 0 -Udc,HB Udc,HB -Udc,HB -Udc,HB 0 0 -Udc,HB
U 2 xn Udc,HB 0 0 Udc,HB Udc,HB 0 0 0 0 Udc,HB -Udc,HB 0 0 -Udc,HB -Udc,HB -Udc,HB
U xn 2Udc,HB = Udc/2
Udc,HB = Udc/4
-Udc,HB = -Udc/4 -2Udc,HB = -Udc/2
46
U xn = 0
U xn = U dc ,HB State
1 3 1 1 3 3 1
State
3 1 1 3 1 1
U xn = U dc ,HB
U xn = 2U dc ,HB State 1
6 State 7 8 12 9 10 11 1 1 6 3 3 7 3 3 8 1 1 13 9 1 3 10 3 1 11 1 1 6 1 1 7 3 3 8 3 3 14 9 1 3 10 3 1 11 3 3 6 3 3 7 1 1 8 1 1 15 9 1 3 10 3 1 11 Number of the commutations between states
U xn = 2U dc ,HB State 16
Figure 3-32 Transitions between voltage levels for the 5L-SC2LHB VSC
There are different PWM methods which have been extended for the use in an H-bridge converter by applying multiple carriers. These methods are described in many publications in the technical literature [28], [43], [50], [55], [59], [60], [61]. They can be categorized into three groups: Phase Shifted (PS), Carrier Disposition (CD), and Hybrid (H) method. These methods are described in Appendix in detail. The following subsection only discusses the PS method due to its balanced switch utilization and simple implementation. This PWM method uses four carrier signals of the same amplitude and frequency, which are phase shifted by TC/4 with respect to each other, where TC is the period of the carrier signal. The modulation method for the 5L-SC2LHB VSC is shown in Figure 3-34a. The triangular carriers Utri,L1, Utri,R1 for the first H-bridge cell and the triangular carriers Utri,L2, Utri,R2 for the second H-bridge cell are considered (one carrier signal for each column). The commutations are determined by the comparison of the corresponding carrier signal and the reference signal Ucon,x (x = a, b, c). There are eight commutations per phase during one period of carrier signal TC. The gate signals can be produced by the following algorithm
U con, x > U tri , Lp ( S pLx : on , S pLx : off ) or U con , x U tri , Rp ( S pRx : on , S pRx : off ) or U con, x < U tri , Rp ( S pRx : off , S pRx : on ) p = 1, 2
(3-36)
47
S 2 Lx
S 2 Rx
S 2 Lx
S 2 Rx
U dc ,HB = U dc / 4
S 2 Lx S 2 Rx
U dc ,HB
S 2 Lx S 2 Rx
S1Lx
U dc ,HB = U dc / 4 S1Lx
S1Rx
U dc ,HB
S1Lx
S1Rx
S1Rx State 1
S1Lx State 4
S 2 Lx
S1Rx
S 2 Lx
S 2 Rx
S 2 Rx
U dc,HB
S 2 Lx S 2 Rx
U dc ,HB
S 2 Lx S 2 Rx
S1Lx
U dc ,HB
S1Rx
U dc ,HB
S1Lx
S1Rx
S1Lx
S1Rx State 7
S 2 Lx S 2 Rx
S1Lx
S1Rx State 14
U dc,HB
S 2 Lx S 2 Rx
S1Lx U dc,HB
S1Rx
S1Lx
S1Rx
State 16
Figure 3-33 Conduction path of the 5L-SC2LHB VSC (according to Figure 3-32)
48
The resulting gate signals for the 5L-SC2LHB VSC are shown in Figure 3-34b, which directly yields the switch states of S1Lx , S1Rx , S 2 Lx and S 2 Rx . The output voltage waveforms of the 5L-SC2LHB VSC according to Figure 3-31 are depicted in Figure 3-34c to Figure 3-34e. The converter ground n is isolated from the load neutral point n and each phase voltage Uan, Ubn, and Ucn is directly controlled by the ac output of the individual multi-level H-bridge cells. Due to the same dc voltage value of each cell (i.e. Udc,HB = Udc/4), the phase output voltage of the 5L-SC2LHB converter, e.g. U dc if 2 U dc if 4 if = 0 U dc if 4 U dc if 2
(U
con , x
> U tri , L1 , U con , x > U tri , R1 ,U con , x > U tri , L 2 , U con, x > U tri , R 2 ) > U tri , L1 , U con , x U tri , L 2 , U con , x > U tri , R 2 ) (3-37)
U xn
(U (U (U
con , x
con , x
> U tri , L1 , U con , x U tri , L 2 , U con , x U tri , L1 , U con , x < U tri , R1 , U con , x < U tri , L 2 , U con , x < U tri , R 2 )
(U
con , x
con , x
< U tri , L1 , U con , x < U tri , R1 ,U con , x < U tri , L 2 , U con , x < U tri , R 2 )
comprises five voltage levels, viz. Udc/2, Udc/4, and 0 (see Figure 3-34c). The line-to-line output voltages of the 5L-SC2LHB converter, e.g
U ab = U an U bn
comprise nine voltage levels, viz. Udc, 3Udc/4, Udc/2, Udc/4, and 0 (see Figure 3-34d).
(3-38)
The load phase voltages Uan, Ubn, and Ucn, as depicted in Figure 3-34e, may be expressed in terms of the phase voltages by [11]
U an 2 1 1 U an U = 1 1 2 1 U bn 3 bn U cn 1 1 2 U cn
(3-39)
The load phase voltages comprise thirteen voltage levels, viz. 7Udc/12, Udc/2, 5Udc/12, Udc/3, Udc/4, Udc/6, and 0. Table 3-16 summarizes the output voltages and their corresponding voltage levels. The spectrum of the phase voltage and line-to-line output voltage waveforms are depicted in Figure 3-35a and Figure 3-35b respectively (at ma = 1.15 and m f = 15 ). As can be seen in these Figures, the first carrier band of the output voltages is centred around four times the carrier frequency (f1Cb = 4fC) (equation 3-33). Hence, an output filter of the 5L-SC2LHB VSC would be smaller than the corresponding filters of conventional converters such as the 3L-NPC VSC [25].
Table 3-16 The output voltage levels of the 5L-SC2LHB VSC Output Voltage Uxn Uab Uxn
Udc
3Udc/4
2Udc/3
7Udc/12 Udc/2

5Udc/12 Udc/3
Udc/4

Udc/6
0
0 0 0
49
Ucon, a
Utri,L2
Utri,R2
Utri,L1
Utri,R1
Udc Udc / 2 0 -Udc / 2 -Udc 1 0 1 0 1 0 1 0 Udc / 2 Udc / 4 0 -Udc / 4 -Udc / 2 Udc Udc /2 0 -Udc /2 -Udc 3Udc/5 2Udc/5 Udc/5 0 -Udc/5 -2Udc/5 -3Udc/5 0 90 180 270
Uan Uab Uan,1 Uan Vg , L 2 Vg , R 2
(a)
(b)
Vg , L1
Vg , R1
(c)
(d)
(e)
360
Figure 3-34 Voltage waveforms of the 5L-SC2LHB VSC: (a) control signals Ucon,x and triangular signals Utri,L1, Utri,L2, Utri,R1 and Utri,R2, (b) gate signals, (c) output phase-toground voltage Uan, (d) output line-to-line voltage Uab, (e) output load-phase voltage Uan
50
100
(U an )h
10-1
(a)
mf = 15, ma = 1.15
U dc
10-2
10-3 100
1 3
mf
2m f
3m f
4m f (b)
(U ab )h
U dc
mf = 15, ma = 1.15
10-1
10-2
10-3
mf
Harmonic Order
2m f
3m f
4m f
Figure 3-35 Harmonic spectrum of the 5L-SC2LHB VSC
3.4.3.2. Series Connected Two-Level H-Bridge Voltage Source Converter with Three Power Cells per Phase Leg (7L-SC2LHB VSC) 3.4.3.2.1. Circuit Configuration
The structure of the 7L-SC2LHB VSC utilizing three H-bridge cells in series per phase leg is similar to Figure 3-30, but with p = 3. It contains 36 unidirectional active switches with inverse diodes and 9 separated dc link capacitors as well as an 18-pulse transformer with three secondary windings which are shifted 20 with respect to each other. If the dc voltage of each H-bridge cell is set to the same value of Udc,HB, the resulting converter can operate with seven output voltage levels (e.g. Uxn) by using the combinations of the three H-bridge converter voltages.
The fundamental concepts for the 7L-SC2LHB VSC remain the same as for the 5L-SC2LHB VSC. The total number of switch states, which includes all redundancies, calculates to nsw = 22 p = 26 = 64 with p being the number of H-bridge cells per phase. The phase output voltages (e.g. Uxn) 2Udc,HB (Udc/3 according to equation (3-30)), Udc,HB (Udc/6), and 0 can be generated with more than one combination, as given in Table 3-17. It shows that there are different redundant possibilities to achieve the same output voltages. For a positive phase current, if either all diagonally opposite switches ( S pLx ,S pRx : p = 1, 2,3) or (3-40)
(S
pLx
,S pRx : p = 1, 2,3) are turned on, then the phase output voltage will lead to +3Udc,HB =
51
+Udc/2 or -3Udc,HB = +Udc/2. The positive and negative states +2Udc,HB and 2Udc,HB can be generated, if either only one pair of switches ( S pLx ,S pRx :p = 1 or 2 or 3) or
(S
pLx
,S pRx :p = 1 or 2 or 3) is turned off. In order to produce the positive state +Udc,HB and the
negative state Udc,HB, only one out of three diagonally arranged switches must be turned on. The zero state can be created if all upper or lower switches in the three H-bridges lie within the current path. Therefore, each phase can produce seven distinct voltage levels, viz. Udc/2, Udc/3, Udc/6, and 0 (Table 3-17). There are some redundancies to produce the output voltage levels +Udc/3, +Udc/6, and 0. Although the same output voltages are generated, the output current iph flows in different paths. This means that a different current flows in different dc link capacitors. Consequently, the dc link capacitors have different voltage profiles. The redundancies can be used to adjust the individual capacitor voltages and to balance these voltages. To achieve minimal operating losses and power balancing, the most suitable redundancy should be selected. Regarding the optimization concern, the selected operation modes used to generate the positive and zero output voltages for a 7L-SC2LHB VSC.
Ucon,a Udc Utri,L1 Utri,L2 Utri,L3 (a)
-Udc 1 0 1 0 1 0 1 0 1 0 1 0
Utri,R1
Utri,R2
Utri,R3
Vg , L1
(b)
Vg , R1 Vg , L 2 Vg , R 2
Vg , L 3
Vg , R 3
90
180
270
360
Figure 3-36 Pulse width modulation for the 7L-SC2LHB VSC: (a) control signals Ucon,a and triangular signals Utri,Lp and Utri,Rp, (b) gate signals (mf = 3) Table 3-17 Number of redundancies in each phase voltage level of the 7L-SC2LHB VSC Phase output voltage level Number of redundancies at level
Udc/2 1
Udc/3 6
Udc/6 15
0 20
-Udc/6 15
-Udc/3 6
-Udc/2 1
52
The redundancy combination used to produce the output voltages of +3Udc,HB, +2Udc,HB, +Udc,HB, and 0 are one, three, three, and one respectively (Table 3-17). This also applies to negative output voltages. Therefore, the total number of switch states for the 7L-SC2LHB VSC is 15, which breaks down to seven for the positive voltage, seven for the negative voltage, and one for the zero voltage. It should be noted that each switch of the H-bridge cells must block the dc link voltage Udc/6, compared to the Udc/4 in the 5L-SC2LHB VSC, to achieve the same output voltage. Switching losses are caused by the commutation processes between the different switch states. Only the two complement switches in each H-bridge cell are involved in the commutations.
The fundamental concept is the same as the 5L-SC2LHB converter. The PS modulation method uses six carrier signals of the same amplitude and frequency, which are phase shifted by TC/6 with respect to each other, where TC is the period of the carrier signal. The modulation method for the 7L-SC2LHB VSC is shown in Figure 3-36a. Triangular carriers (U tri,L1 ,U tri,R1 ) , (U tri,L 2 ,U tri,R 2 ) , and (U tri,L3 ,U tri,R3 ) are considered for the first, second, and third H-bridge cell respectively (one carrier signal for each leg). The commutations are determined by the comparison of the corresponding carrier signal and the reference signal U con , x ( x = a, b, c ) . There are twelve commutations per phase during one period of the carrier signal TC. Gate signals can be produced by U con ,x > U tri ,Lp ( S pLx : on , S pLx : off ) or U con ,x U tri ,Ri ( S pRx : on , S pRx : off ) or U con,x < U tri ,Rp ( S pRx : off , S pRx : on ) p = 1, 2,3
(3-41)
The resulting gate signals for the 7L-SC2LHB VSC are shown in Figure 3-36b, which directly yield the switch states of S1Lx , S1Rx , S 2 Lx , S 2 Rx , S3 Lx and S3 Rx respectively.
U dc 2 U 3 dc U 6 dc = 0 U dc 6 U dc 3 U dc 2 if if if if if if if
U xn
(U (U (U (U (U (U (U
con , x con , x con , x
> U tri , L1 ,U tri , L 2 ,U tri , L 3 , U tri , R1 ,U tri , R 2 ,U tri , R 3
> U tri , L1 ,U tri , L 2 ,U tri , L 3 ,U tri , R1 ,U tri , R 2 , U con , x U tri , L1 ,U tri , L 2 ,U tri , L 3 , U tri , R1 , U con , x U tri , L1 ,U tri , L 2 ,U tri , L 3 , U con , x 
con , x
con , x con , x
 U tri , R 3 < U tri , L1 ,U tri , L 2 ,U tri , L 3 ,U tri , R1 ,U tri , R 2 ,U tri , R 3
) ) )
(3-42)
The output voltage waveform of the 7L-SC2LHB VSC is depicted in Figure 3-37. Similar to the 5L-SC2LHB VSC, the converter ground n is isolated from the load neutral point n and each phase-to-ground voltage Uan, Ubn, and Ucn is directly controlled by the ac output of the individual multi-level H-bridge cells. Considering the same dc voltage value Udc,HB = Udc/6 for each cell (according to equation 3-30), the phase output voltage of the 7L-SC2LHB VSC
53
comprises seven voltage levels, viz. Udc/2, Udc/3, Udc/6, and 0 (see Figure 3-37b and Table 3-18). The line-to-line output voltages of the 7L-SC2LHB VSC comprise thirteen voltage levels, viz. Udc, 5Udc/6, 2Udc/3, Udc/2 Udc/3, Udc/6, and 0 (see Figure 3-37c and Table 3-18). The load phase voltage Uan is depicted in Figure 3-37d. It comprises 25 voltage levels, viz. 2Udc/3, 11Udc/18, 5Udc/9, Udc/2, 4Udc/9, 7Udc/18, Udc/3, 5Udc/18, 2Udc/9, Udc/6, Udc/9, Udc/18, and 0 (Table 3-18).
Udc Udc/2 0 -Udc/2 -Udc Udc/2 Udc/4
(a)
Uan
(b)
0
-Udc/4 -Udc/2 Udc Udc/2
Uan,1
Uab
(c)
0
-Udc/2 -Udc
3Udc/5 2Udc/5 Udc/5 0 -Udc/5 -2Udc/5 -3Udc/5 0 90 180
Uan
(d)
270
360
Figure 3-37 Voltage waveforms of the 7L-SC2LHB VSC: (a) reference and triangular signals, (b) output phase voltage Uan, (c) output line-to-line voltage Uab, (d) output loadphase voltage Uan (mf = 15)
54
Table 3-18 The output voltages and their corresponding levels of the 7L-SC2LHB VSC output voltage levels Udc 5Udc/6 2Udc/3 11Udc/18 5Udc/9 Udc/2 4Udc/9 7Udc/18 Udc/3 5Udc/18 2Udc/9 Udc/6 Udc/9 Udc/18 0
Uxn
Uab
0
Uxn
0
The spectrum of the phase-to-ground and the line-to-line output voltage waveforms are depicted in Figure 3-38a and Figure 3-38b respectively (at ma =1.15 and mf = 15). It becomes apparent that the first carrier band of the output voltages is centred around six times the carrier frequency (f1Cb = 6fC), according to equation 3-33.
100
(U an )h
U dc
(a)
mf = 15, ma = 1.15
10-1 10-2 10-3 100
1 3
mf
2mf
3mf
4mf
5mf
6mf (b)
(U ab )h
U dc
10-1 10-2 10-3
mf = 15, ma = 1.15
mf
2mf
3mf 4mf Harmonic order
5mf
6mf
Figure 3-38 Harmonic spectrum of the phase voltage (a) and line-to-line voltage (b) of the 7LSC2LHB VSC
3.4.3.3. Series Connected Two-Level H-Bridge Voltage Source Converter with four Power Cells per Phase Leg (9L-SC2LHB VSC)
Figure 3-39 represents the structure of the 9L-SC2LHB VSC utilizing four H-bridge cells in
55
series per phase leg p = 4. It contains 48 unidirectional active switches with inverse diodes, 12 separated dc link capacitors as well as a 24-pulse transformer with three secondary windings which are shifted 15 with respect to each other. If the dc voltage of each H-bridge cell is set to the same value of Udc,HB, the resulting converter can operate with nine voltage levels by using the combinations of the four H-bridge converter voltages.
i ph ,a
U an U 4 an
4
3
S 4 La
S 4 La
S 4 Ra
S 4 Ra
U ab
b
4
3
S 4 Lb S 4 Lb
S 4 Rb S 4 Rb
U 4 bn c
S 4 Lc S 4 Lc S 4 Rc S 4 Rc
4
3
U 4 cn
3
3
S 3 La S 3 La
S 3 Ra S 3 Ra
U 3 an
3
3
S 3 Lb
S 3 Rb
U 3bn
S 3 Lb
S 3 Rb
S 3 Lc S 3 Rc
U 3 cn
0 3
S 2 Lc
S 2 La S 2 La S 2 Ra S 2 Ra
S 2 Rc
2
3
U 2 an
2
3
S 2 Lb S 2 Lb
S 2 Rb S 2 Rb
U 2 bn
2
3
S 2 Lc S 2 Lc
S 2 Rc S 2 Rc
U 2 cn
1
3
id21a
S1La
S1La
S1 Ra
S1 Ra
U 1an U 1bn
1
3
S1Lb
S1Lb
S1Rb
S1Rb
1
3
U 1cn
S1Lc S1Lc S1 Rc S1 Rc
Figure 3-39 The 9L-SC2LHB Voltage Source Converter
56
The fundamental concepts of commutations are the same as for the 7L-SC2LHB VSC. There are different redundant possibilities to generate the phase output voltage, (e.g. Uxn), 3Udc,HB, 2Udc,HB, Udc,HB, and 0. The redundancies can be used to adjust the individual capacitor voltages and to balance cell power. Considering the optimal redundancies, the total number of switch states can be calculated by
2 p +1 1 = 25 1 = 31
(3-43)
In order to generate the gate signals, the PS modulation method is used. The commutations are determined by the comparison of the eight carrier signals, one carrier signal for each leg, and the reference signal U con , x ( x = a, b, c ) . The carrier signals are phase shifted by TC/8 with respect to each other. The modulation method for the 9L-SC2LHB VSC is shown in Figure 3-40a. There are sixteen commutations per phase (four commutations per cell) during one period of carrier signal TC. The gate signals can be produced by U con ,x > U tri ,Lp ( S pLx : on , S pLx : off ) or U con ,x U tri ,Ri ( S pRx : on , S pRx : off ) or U con,x < U tri ,Rp ( S pRx : off , S pRx : on ) p = 1, 2,3, 4
(3-44)
The resulting gate signals for the 9L-SC2LHB VSC are depicted in Figure 3-40b, which directly yield the switch states of S1Lx , S1Rx , S 2 Lx , S 2 Rx , S3 Lx , S3 Rx , S 4 Lx and S 4 Rx respectively. The output voltage waveform of the 9L-SC2LHB VSC is illustrated in Figure 3-41. Each phase voltage Uan, Ubn, and Ucn is directly controlled by the ac output of the individual multi-level H-bridge cells. Considering the same dc voltage value Udc,HB = Udc/8 for each cell, according to equation 3-30, the phase output voltage Uxn of the 9L-SC2LHB VSC, e.g.
U dc 2 3U 8 dc U 4 dc U dc 8 = 0 U dc 8 U dc 4 3U dc 8 U 2 dc
U xn
(U if (U if (U if (U if (U if (U if (U if (U if (U
if
con , x
> U tri , L1 ,U tri , L 2 ,U tri , L 3 ,U tri , L 4 ,U tri , R1 ,U tri , R 2 ,U tri , R 3 , U tri , R 4
con , x
> U tri , L1 ,U tri , L 2 ,U tri , L 3 ,U tri , L 4 ,U tri , R1 ,U tri , R 2 , U tri , R 3 , U con, x U tri , L1 ,U tri , L 2 ,U tri , L 3 ,U tri , L 4 , U tri , R1 ,U tri , R 2 , U con , x U tri , L1 ,U tri , L 2 ,U tri , L 3 ,U tri , L 4 , U tri , R1 , U con , x U tri , L1 ,U tri , L 2 ,U tri , L 3 ,U tri , L 4 , U con, x U tri , R 2 ,U tri , R 3 , U tri , R 4
con , x
con , x
 U tri , R 3 , U tri , R 4 U tri , L1 ,U tri , L 2 ,U tri , L 3 ,U tri , L 4 ,U tri , R1 ,U tri , R 2 , U tri , R 3 , U con , x > U tri , R 4 < < U tri , L1 ,U tri , L 2 ,U tri , L 3 ,U tri , L 4 ,U tri , R1 ,U tri , R 2 , U tri , R 3 ,U tri , R 4
con , x
con , x
) ) ) ) ) )
(3-45) comprises nine voltage levels, viz. Udc/2, 3Udc/8, Udc/4, Udc/8, and 0 (see Figure 3-41b and Table 3-19). The line-to-line output voltages of the 9L-SC2LHB VSC comprise seventeen voltage levels, viz. Udc, 7Udc/8, 3Udc/4, 5Udc/8, Udc/2, 3Udc/8, Udc/4, Udc/8, and 0 (see Figure 3-41c and Table 3-19). The load phase voltage Uan of the 9L-SC2LHB VSC comprises 29 voltage levels (see Figure 3-41d and Table 3-19).
57
U con,a U dc
U tri,L1 U tri,L2 U tri,L3
U tri,L4 U tri,R1 U tri,R2 U tri,R3 U tri,R4 (a)
-U dc
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 V g , L1 Vg , R 1 Vg , L 2 Vg , R 2 Vg , L 3 Vg , R 3 Vg , L 4 Vg , R 4
(b)
90
180
270
360
Figure 3-40 Pulse width modulation for the 9L-SC2LHB VSC: (a) control signals Ucon,a and triangular signals Utri,Lp and Utri,Rp, (b) gate signals (mf = 3) Table 3-19 The output voltages and their corresponding levels of the 9L-SC2LHB VSC output voltage levels Udc 7Udc/8 3Udc/4 5Udc/8 7Udc/12 13Udc/24 Udc/2 11Udc/24 5Udc/12 3Udc/8 Udc/3 7Udc/24 Udc/4 5Udc/24 Udc/6 Udc/8 Udc/12 0
Uxn
Uab
0
Uxn
58
Udc
(a)
-Udc Udc/2 Uan Udc/4 0 -Udc/4 -Udc/2 Udc Udc/2 0 -Udc/2 -Udc 3Udc/5 2Udc/5 Udc/5 0 -Udc/5 -2Udc/5 -3Udc/5 0 90 180 270 360 Uan (d) Uab (c) (b)
Uan ,1
Figure 3-41 Voltage waveforms of the 9L-SC2LHB VSC: (a) reference and triangular signals, (b) output phase voltage Uan, (c) output line-to-line voltage Uab, (d) output loadphase voltage Uan (mf = 15)
The spectrum of the phase and line-to-line output voltage waveforms are depicted in Figure 342a and Figure 3-42b respectively (at ma = 1.15 and m f = 15 ). As can be seen in these Figures, the first carrier band of the output voltages is centred around eight times the carrier frequency (f1Cb = 8fC), according to equation 3-33.
59
100
-1
(U an )h
U dc
mf = 15, ma = 1.15
10
10-2 10-3 10
0
13
mf
2mf
3mf
4mf
5mf
6mf
7mf
8mf
(U ab )h
10-1
U dc
mf = 15, ma = 1.15
10-2 10-3
mf
2mf
3mf
4mf 5mf Harmonic order
6mf
7mf
8mf
Figure 3-42 Harmonic spectrum of the phase voltage Uan (a) and the line-to-line voltage Uab (b) of the 9L-SC2LHB VSC
3.4.4. N-Level Series Connected 3-Level H-Bridge Voltage Source Converter (NLSC3LHB VSC) [47], [120]
The topologies summarized above constitute the basic structures of the multi-level converters. To reduce the number of separate dc sources for high-voltage high-power applications, the SC2LHB VSC can be modified by replacing its conventional two-level converters (2L-HBridge) with combinations of multi-level converters (3L-H-Bridge). These combinations can be considered as having NL-SC3LHB VSC because this includes multi-level cells as the building block of the cascaded converter. Figure 3-43 represents the structure of the NLSC3LHB VSC, utilizing p 3L-H-Bridge cells in series per phase leg. The dc link voltage depends on the number of the series connected 3L-H-Bridges and is determined by U dc = p U dc ,3 L HB (3-46)
Using the same dc link voltage for each H-bridge cells Udc,3L-HB, the converter synthesizes an output phase voltage (e.g. Uan, Ubn, Ucn) U xn = U1xn + ... + U pxn with a number of output phase voltage levels N = 4 p +1 (3-48) Due to a higher number of voltage levels, compared to the SC2LHB VSC, this converter generates an output voltage with improved harmonic performance. The advantage of the topology is that it needs less separate dc sources. However, the modulation is more complicated due to the 3L-H-Bridge structure. (3-47)
60
i ph ,a
a
U an
p
3
S p 2 a1 S p1a1 S p 2 a1 S p1a1
S p 2 a2 S p1a2
U pan
U ab b
S p 2 a2
S p1a2 S p 2b1 S p1b1 S p 2b1 S p1b1 S p 2b2 S p1b2
U pbn
p
3
S p 2b2
S p1b2 S p 2c1 S p1c1 S p 2c1 S p1c1 S p 2c2 S p1c2
U pcn
p
3
S p 2 c2
S p1c2
0 3
1
3
S12 a1 S11a1 S12 a1 S11a1
S12 a2 S11a2 S12 a2 S11a2
U1an
U1bn
S12b1 S11b1 S12b1 S11b1 S12b2 S11b2 S12b2 S11b2 S12 c1 S11c S12 c1 S11c1 S12c2 S 21c2 S12 c2 S11c2
1
3
U1cn
1
3
Figure 3-43 NL-SC3LHB VSC with p series 3L-H-Bridge cells per phase
3.4.4.1. Circuit Configuration of Five-Level Series Connected 3-Level H-Bridge Voltage Source Converter (5L-SC3LHB VSC)
The circuit of Figure 3-44 shows the basic topology of a single-phase 5L-SC3LHB VSC [46], [47], [120]. This converter was constructed from two halves of a three-level diode-clamped converter connected to the same bank of series capacitors to form a five-level converter. This topology is presently being produced by ABB and General Electric in their medium voltage (4160V) drive product [12], [46]. It contains 8 unidirectional active switches with inverse
61
diodes and 4 neutral point clamp diodes per phase. If a NPC single-phase (3L-H-Bridge) replaces the conventional full-bridge cell (2L-H-Bridge), the voltage level is effectively doubled for each cell. Thus, to achieve the same voltage levels N for each phase, only (N-1)/4 separate dc sources are needed for one phase leg converter, whereas (N-1)/2 separate dc sources are needed for the NL-SC2LHB converter. Although the converter in Figure 3-44 is a five-level structure, the concept may be expanded to any odd number of voltage levels [33]. Using the same philosophy, a full-bridge five-level phase leg can be built, based on the three-level flying capacitor topology, but in this section only the 5L-SC3LHB diode-clamped converter will be discussed.
M2 idc2 a
S12 a D2 a
C2 Udc,3L-HB Uc2 idc1
S12 a D2 a
2
Uan
2
S11a
S11a
M1 C1
Uc1
S12 a
1
S12 a
2
D1a S11a
M0 idco
D1a S11a
Figure 3-44 Five-level SC3LHB diode clamped topology (5L-SC3LHB)
By suitably switching the converter transistors, the points a and n in Figure 3-44 may be connected to any of the points M0, M1, and M2 [33]. In order to produce five levels in each cell, the switches are controlled like in the conventional 3L-NPC VSC, which was explained in section 3.2.1.1.1. Four of the eight switches in each cell are turned on at any time. The switch positions for five possible states of each cell are given in Table 3-20, where 1 and 0 designate the on- and off state of the respective switch. Assuming that the dc voltage is set to Udc and each capacitor remains charged to half of the dc voltage, the converter output voltage Uan, according to equation (3-46), may be set to the five distance levels Udc, Udc/2, and 0 (Table 3-20). Capacitor voltage balancing in this topology may be accomplished in a straightforward way through redundant state selection [41]. As can be seen in Figure 3-44, switching to output voltages of Udc and 0 will not result in a current draw from the neutral point M1 and therefore will not affect the capacitor voltage balance. However, when a voltage of Udc/2 is required, the neutral junction will be utilized. As an example of how the redundant state switching is accomplished, consider the case where an output voltage of Udc/2 is desired and the phase current is positive. One possibility is to switch point a to junction M2 and point n to M1. This choice will tend to charge the lower capacitor since the current is flowing into the neutral junction. The other possibility is to switch point a to junction M1 and point n to junction M0. This will result in a current out of the neutral junction which will discharge the lower capacitor. The choice can then be readily made, depending on whether the lower capacitor is under- or over-charged relative to the upper one.
62
The commutation processes between the different switch states are the same as in the conventional 3L-NPC VSC, which was explained in section 3.2.1.1.1. The distribution of the conduction and switching losses are summarized in Table 3-21 and Table 3-22 respectively. It is remarkable that four semiconductors lie within the current path in any switch state, either four active switches or four diodes.
Table 3-20 Switch positions for the 3L-H-Bridge converter
State
S11a1 S12 a1
1
1 1 1 1 1 1 1 0 1 1 0 1
2
1 0 1 1 0 1 1 1 1 1 0 0 1 0 1 0 0 1 1 0
3
1 0 0 1 0 1 0 1 0 0 1 1 1 0 0 0 0 1 0 0
4
0 0 1 0 0 0 0 1
5
0 0 0 0
S11a2 S12 a2 U aM1 U nM1 U ab
Udc/2 -Udc/2 Udc
Udc/2 0 Udc/2
0 -Udc/2
Udc/2 Udc/2
0 0 0
-Udc/2 -Udc/2
0 Udc/2
-Udc/2 0 -Udc/2
-Udc/2 Udc/2 -Udc
Table 3-21 Conduction losses in the 3L-H-Bridge converter
State
+ (Uan = Udc) 0 (Uan = 0) - (Uan = -Udc)
Switches Half-Bridge a1 Half-Bridge a2 Positive phase current T12 a1 ,T11a1 T12 a2 ,T11a2
D2 a1 ,T11a1
DT 12 a1 ,DT 11a1 T12 a2 ,D1a2
Switches Half-Bridge a1 Half-Bridge a2 Negative phase current DT 12 a1 ,DT 11a1 DT 12 a2 ,DT 11a2
T12 a1 ,D1a1 T12 a1 ,T11a1
D2 a2 ,T11a2 T12 a2 ,T11a2
DT 12 a2 ,DT 11a2
Table 3-22 Switching losses in the 3L-H-Bridge converter
State +0
0
Switches Switches Half-Bridge a Half-Bridge b Half-Bridge a Half-Bridge b Positive phase current Negative phase current T12 a1 ,D2 a1 T11a2 ,D1a2 DT 11a1 ,T12 a1 DT 12 a2 ,T11a2
T11a1 ,DT 11a1 T12 a2 ,DT 12 a2 D1a1 ,T11a1
D2 a2 ,T12 a2
Gate signals for one half-bridge are produced by comparing one control voltage waveform with two triangular voltage waveforms U tri ,up and U tri ,low (which is drawn for m f = 15 ), as shown in Figure 3-45a. The upper and lower carrier band are in phase but displaced vertically. However, the triangular signals in each carrier band are shifted by TC/2 with respect to each other. In order to trigger the switches, the following algorithm can be used. The comparison of Ucon with Utri,up,a and Utri,low,a results in the following logic signals to control the switches in the first leg
63
if if if if
(U (U
(U
con
> 0 and U con > U tri ,up ,a ) S11a1 ,S12 a1 : on ,S11a1 ,S12 a1 : off U aM 1 = > 0 and U con U tri ,low,a

con
< 0 and U con < U tri ,low,a
( ) (S ) (S ) (S
,S12 a1 : on ,S11a1 ,S12 a1
11a1 ,S12 a1 : on ,S11a1 ,S12 a1
11a1
,S12 a1 : on ,S11a1 ,S12 a1
) : off ) U : off ) U : off ) U
U dc 2 aM 1 = 0
aM 1 = 0
(3-49)
aM 1
U dc 2
For controlling the second leg switches, Utri,up,b and Utri,low,b are compared with the same control signal, which yields the following if if if if
(U (U
(U (U
con
> 0 and U con > U tri ,up ,b ) S11a2 ,S12 a2 : on ,S11a2 ,S12 a2 : off U nM 1 = > 0 and U con U tri ,low,b < 0 and U con < U tri ,low,b
con
( ) (S ) (S ) (S
,S12 a2 : on ,S11a2 ,S12 a2 ,S12 a2 : on ,S11a2 ,S12 a2 ,S12 a2 : on ,S11a2 ,S12 a2
11a2
11a2
) : off ) U : off ) U : off ) U
U dc 2
nM 1 nM 1
=0 =0 =
U dc 2
(3-50)
nM 1
Therefore, the leg voltages (e.g. UaM1 and UnM1) comprise three voltage levels, viz. Udc/2 and 0 (see Figure 3-45c and Figure 3-45e). The output voltage of the 5L-SC3LHB VSC, e.g.
U ab = U aM 1 U nM 1
(3-51)
if if if if if
(U (U (U (U
con
> 0 and U con > U tri ,up ,a and U con > U tri ,up ,b ) U ab = U dc > 0 and U con > U tri ,up ,a and U con 0 and U con U tri ,up ,b )
con con con
> 0 and U con > con tri ,low,a con tri ,low,b ) ( con (U con < 0 and U con > U tri ,up ,a and U con U tri ,low,b ) (U con < 0 and U con U tri ,low,b ) U ab = U dc
(3-52)
comprise five voltage levels, viz. Udc, Udc/2, and 0 (see Figure 3-45f). The output voltage waveforms of the 5L-SC3LHB VSC according to Figure 3-44 are depicted in Figure 3-45. The harmonic spectrum of the output voltage Uab is illustrated in Figure 3-46 (which is drawn for m f = 15 ). It can be seen in this Figure that the first carrier band of the output voltage is centred around two times the carrier frequency (f1Cb = 2fC), according to equation 3-33.
64
Utri,up,a Udc
Ucon
Utri,up,b
Utri,low,a
Utri,low,b (a)
-Udc 1
Vg ,T12 a
(b)
0 1
Vg ,T11a
0 Udc / 2 0 -Udc / 2 1
U aM1
(c)
Vg ,T11a
(d)
0 1
Vg ,T12 a
0 Udc / 2 0 -Udc / 2 Udc Udc / 2 0 -Udc / 2 -Udc
0 90
U nM1
(e)
U an
(f)
180
270
360
Figure 3-45 Voltage waveforms of the 5L-SC3LHB VSC: (a) control signal Ucon and triangular signals, (b) a-leg gate signals, (c) a-leg phase voltage, (d) n-leg gate signals, (e) n-leg phase voltage, (f) converter output voltage uan
65
(U ab )h
U dc
mf = 15, ma = 1.15
10-3
1 3
mf
Harmonic Order
2m f
3m f
Figure 3-46 Harmonic spectrum of the 5L-SC3LHB VSC
3.4.5. Conclusion
Multi-level converters are becoming more attractive in high voltage and high efficiency applications. Because of their multi-step output voltage waveforms, the total harmonic distortion (THD) of the multi-level converter voltages is relatively low compared to the 2LVSC. Moreover, the effective switching frequency of the multi-level converters is a function of its number of voltage levels. In other words, to achieve the same voltage THD, a higherlevel converter can operate at a lower switching frequency. Obviously, the theoretical superiority of a multi-level converter is proportional to its number of voltage levels assuming ideal switches. However, the number of voltage levels is limited by its control complexity, complication of the system structure, cost and conduction losses. Four multi-level VSCs have been considered: Neutral Point Clamp (NPC), Flying Capacitor (FLC), Series Connected Two-Level H-Bridge (SC2LHB), and Series Connected Three-Level H-Bridge (ML-SC3LHB). These converter topologies are compared in terms of the structure, function and basic characteristics in medium voltage applications. The number of components needed in each system is compared in Table 3-23, where N is the number of voltage levels. Clamping diodes are not required in the FLC and SC2LHB, while balancing capacitors are not needed in the NPC and FLC. In the FLC topology, a high amount of capacitances are required for high voltage levels. In the 7L-FLC VSC, for example, 15 clamping capacitors plus 6 dc link capacitors are necessary to achieve the same voltage rating yielded by utilizing 9 capacitors in the SC2LHB topology. Not only do these many capacitors make the system less cost-effective, but they also induce the necessity to balance the capacitor voltages. Figure 3-47 shows the total required components of Table 3-23 in four investigated multi-level converters as a function of the number of voltage levels. Although the same number of modules (IGBTs/diodes) is needed in the four considered topologies, the total number of components necessary in these four topologies is different at higher voltage levels. In the same voltage range, the NPC requires substantially more components than the others do; therefore, it does not qualify for the use with a high number of voltage levels. Moreover, for more than three-level configuration, the NPC voltage imbalance problem cannot be overcome by utilizing modulation techniques. Complex balance circuits would be necessary. This makes the NPC unattractive for levels larger than three. As shown in Figure 3-47, to synthesize the same number of voltage levels, the SC2LHB
66
requires the least number of total main components. However, the SC2LHB needs more capacitors as compared to those needed in the NPC. Another major advantage of the SC2LHB is its circuit layout flexibility, because each level has the same structure and there are no extra clamping diodes or voltage balancing capacitors, which are required in the NPC and the FLC topologies. The number of output voltage levels can then be easily adjusted by changing the number of H-bridge cells. Moreover, redundancy can be easily applied to enhance the reliability of the entire system. However, the control complexity is directly proportional to the number of H-bridge cells. As the number of voltage levels increases, the voltage imbalance problem becomes more of a concern. To achieve stable system, a well-defined model and an effective dc link balancing method are necessary. Each cell of the SC3LHB VSC generates a number of output voltage levels higher than the SC2LHB VSC with fewer harmonic. To achieve the same number of voltage levels N for each phase, the SC3LHB requires a 3(N-1)/2 pulse-transformer, whereas a 3(N-1) pulse-transformer is needed for the SC2LHB VSC. In conclusion, among the considered multi-level converter topologies, the Series Connected HBridge Converter is an attractive topology for multi-level converters.
240 210 Number of total componenets 180 150 120 90 60 30 0 3 4 5 6 7 Number of phase voltage levels 8 9 NPC FLC SC2LHB SC3LHB
Figure 3-47 Number of total components required in the multi-level converter as a function of the number of phase voltage levels Table 3-23 Comparison of power component requirements for multi-level topologies
Topology Number of module (IGBT/Diode) Number of clamping diodes Number of dc link capacitors Number of balancing capacitors Total
NPC
6(N-1) 3(N-1)(N-2) (N-1) 0 3N2-2N-1 N = 3, 4,
FLC
6(N-1) 0 (N-1) 3(N-2) 10N-13 N = 3, 4,
SC2LHB
6(N-1) 0 3(N-1)/2 0 15(N-1)/2 N = 5, 7, 9,..
SC3LHB
6(N-1) 3(N-1) 3(N-1)/2 0 21(N-1)/2 N = 5, 9,
4. MODELLING AND SIMULATION

This chapter introduces the modelling of the medium voltage drive components, including utility grid, load, multi-pulse transformer, rectifier, dc link capacitor, power semiconductor devices, and inverter, as shown in Figure 4-1.
Grid Multi-Pulse Transformer Converter
Rectifier DC-link Capacitor Inverter
Load
is
3
iL
(a)
is
3
3
3
iL
(b)
Figure 4-1 Block diagram of Medium Voltage Drives: (a) NPC and FLC VSCs, (b) SCHB VSC
4.1. Load and Grid Models 4.1.1. Load Model The electric load component has different characteristics according to the variation of voltage and frequency. Thus, for proper operation, it is essential to model it. Figure 4-2 depicts a standard load model for a one-phase and a three-phase form [5]. The simplified circuit diagram is based on the following conditions and simplifications: The three-phase equivalent circuit is assumed to be symmetric. It is accepted that the electromotive force (EMF) delivers sinusoidal voltages with variable amplitude and frequency.
68
MODELLING AND SIMULATION
iLa RL iLa RL Ua
LL
LL LL LL
ea eb ec
ea
Ua
iLb RL
Ub i Lc RL Uc
Figure 4-2 Standard load model for one-phase and three-phase
Resistance RL is assumed to be zero. According to this assumption, the inductive portion LL of the load impedance is dominant.
Generally, this simplification is permissible for middle and large power drives, since the amount of the relationship between the inductive and resistive portion of impedance can be 10 and more for the nominal frequency of the converter. However, the simplification is invalid if the control of the converter is concerned. In particular, within very low fundamental frequency, for example, in the starting range of a drive, resistance RL is dominant in relation to inductor LL. If the standard load is used with a star connection, the load voltages are equal to the phase voltages and the load currents are equal to the phase currents. However, it is not relevant to the converter which kind of load connection is used. These general load models are often used to simulate an induction motor or a synchronous motor, which are the most important class of the three-phase loads. Although for simulation purposes, other simple load models are also considered such as an ideal current source or a series resistive-inductive load. 4.1.2. Grid Models The three-phase utility grid is modelled by an electrical generator that implements a symmetrical voltage of three different phases (e.g. UsA, UsB, UsC) with internal resistive-inductive impedance. In contrast to the load model, the currents are defined to be positive in the inverse direction according to Figure 4-3. The three voltage sources are connected in star with a neutral connection that can be internally grounded or made accessible. The source-internal resistance Rs is assumed to be zero.
UsA
Ls Rs Rs
isA isB
UsB L s UsC
Ls
Rs isC
Figure 4-3 Standard three-phase utility grid model
4.2. Converter Model 4.2.1. Inverter The inverter consists of the power semiconductor devices which are triggered by sine-triangle modulation scheme.
69
4.2.1.1. Modulation method The modulation is one of the important factors in optimizing the performance of the converter. The modulation process determines the spectral content of the output waveforms as well as the distribution of losses within the converter. Many different modulation approaches have been proposed in the literature [43], [53], [56], [68], [69], [70], [71]. The converter model in this thesis is based on the sine-wave modulation strategy with a third harmonic added, as explained in detail in chapter 3 and Appendix. 4.2.1.2. Compact Power Semiconductor Model In this thesis, IGBT modules are considered due to the modularity. For analysis purposes, the IGBTs and diodes are usually considered ideal, i.e. lossless, featuring infinite current and voltage handling capability according to Figure 4-4. The ideal IGBT is simulated as being controlled by a logical gate signal (gs 0). It conducts an arbitrary current with zero on-state voltage when the switch is on (gs > 0) and blocks any forward or reversely applied voltage with zero current when the switch is off (gs = 0) [4]. The device can be switched instantaneously between on and off states or vice versa by triggering it.
IC UCE
Figure 4-4 The ideal circuit symbol of the IGBT
4.2.1.2.1. Power Semiconductor Losses For the calculations, the load current is assumed to be an ideal sinusoid. Then, a symple calculation of the power semiconductor losses for medium voltage converters is presented. The losses of an IGBT can be classified as switching losses and on state (conduction) losses. The power loss dissipation in an IGBT (Ploss,T) and diode (Ploss,D) can be calculated as t f C ( Eon + Eoff ) Ploss ,T = U CE ,n I C ,n + TC turn-on and turn off losses
on-state loss
(4-1)
t Ploss ,D = 1 U F I F ,n + [ f C Erec ] TC Reverse recov ery loss

on-state loss
(4-2)
with UCE,n is the on state saturation voltage and IC,n is the collector current of the IGBT UF,n is the on state voltage and IF,n is the forward current in the diode fC is the carrier frequency and TC is the one period of the carrier frequency Eon is the turn-on and energy and Eoff is the and turn-off energy of the IGBT and Erec is the recovery energy in the diode. These parameters may be deviated from the data sheets.
70
4.2.1.2.2. Loss Approximation based on Datasheets A loss model of the device is developed based on an experimental determination of the power losses. The total power losses in the converter are estimated to determine the junction temperature. A. Conduction Losses The conduction losses Pcon,x of an IGBT or a diode can be expressed by the well-known approximation as [29], [66], [143]
Pcon ,x = with
1 T1 B U o ,x + Acon,x i ( t ) con ,x i ( t ) dt T1 0
(4-3)
Pcon,x are the conduction losses in device x T1 is the fundamental period Uo,x and Aon,x are on state voltage parameters for device x Bcon,x is the curve-fitted constant for device x and i is the instantaneous value of the device current.
B. Switching Losses
Switching losses are created by the commutation processes between different switch states. These commutation processes can be classified into (1) natural or inductive commutations, which are characterized by turn-on losses of active switches and recovery losses of diodes, and (2) forced or capacitive commutations, which are contrarily characterized by turn-off losses of active switches. Turn-on losses of diodes are usually small and can be neglected [1], [3]. It is possible to calculate the switching losses on the basis of the collector-emitter voltage and the collector current. However, this is not a very accurate method due to the need of rough approximations. Therefore, it is more effective and more accurate to measure the switching energy directly as a function of the load current and then describe the relationship by a simple equation. The equation Esw,x = Asw,on,x i ( t )
Bsw ,on ,x
+ Asw,off ,x i ( t )
Bsw ,off ,x
)U U
com CE
(4-4)
can be found in [3], [66], [143]. Esw,x is the switching energy loss for device x, Asw,on,x, Bsw,on,x and Asw,off,x, Bsw,off,x are turn-on and turn-off curve-fitting constants for device x, Ucom is the commutation voltage, and UCE denotes the voltage at which the losses where measured. This equation is useful for turn-on and turn-off losses of the IGBT as well as for the diode. The constant parameters are determined by applying a first-order curve-fitting of the measured on state voltage characteristics and the switching energy losses which are dependent on the load current. The fitting parameters and thermal resistances of the semiconductors examined in this thesis are given in Table 4-1 [29], where the abbreviations T (IGBT) and D (Diode) are used for a device x. Therefore, the average switching losses Psw,x are written as
Psw,x = 1 T1 Esw,x dt T1 0 (4-5)
71
The total converter losses are dependent on the conduction ratio of the diode and the IGBT (modulation index ma and power factor cos) on the modulation method, the junction temperature Tj, dc link voltage Udc, gate drive conditions, load current, and switching frequency fC [66].
Table 4-1 Fitting parameters and thermal resistances of medium voltage IGBTs/Diodes
FZ600R17KE3 FZ1000R25KF1 FZ800R33KF2C CM600HB90H FZ600R65KF1 EUPEC EUPEC EUPEC POWEREX EUPEC 1.7kV/600A 2.5kV/1000A 3.3kV/800A 4.5kV/600A 6.5kV/600A UCE Uo,T Uo,D Aon,T Bon,T Aoff,T Boff,T Aoff,D Boff,D Acond,T Bcond,T Acond,D Bcond,D Rth-jc,T Rth-jc,D Rth-ch
900V 0.7 0.5 0.00057942 0.9351 0.00066378 0.88671 0.0088387 0.43627 0.010357 0.79806 0.050265 0.52041 0.04 0.065 0.01 1200V 1 0.6 0.000233997 1.284617945 0.00177838 0.919017928 0.046509042 0.38569705 0.016146867 0.744225321 0.007117244 0.767030918 0.012 0.024 0.008 1800V 1 0.8 0.000959466 1.115444805 0.003771589 0.841860719 0.059062305 0.422711861 0.033603338 0.687596711 0.015314298 0.725344373 0.013 0.026 0.006 2250V 1 0.5 0.006213403 0.950072933 0.06854911 0.511257394 0.019676069 0.47047145 0.031681013 0.664827161 0.045008694 0.660487133 0.0135 0.027 0.01 3600V 1 0.5 0.010908105 1.001643596 0.00437628 1.044655002 0.039192228 0.574254248 0.098574252 0.591830287 0.086990881 0.573661926 0.011 0.021 0.006
C. Selection of Heat Sinks
For safe operation, the power losses generated by each module must be dissipated. The heat transfer of a semiconductor can be simulated in an electric circuit. Figure 4-5a shows the general equivalent circuit for an IGBT module. At steady state the junction temperature Tj can be calculated using the following thermal equation T j ( x ) = Ploss { Rth,ch + Rth ,ha } + Ploss ,x Rth, jcx + Ta with Rth,jc denotes the thermal resistance of the IGBT/diode from junction to case Rth,ch is the thermal resistance of the IGBT/diode from case to heat sink Rth,ha is the thermal resistance from heat sink to ambient, and Ta is the ambient temperature. Infineon/Eupec published a new datasheet software for IGBT modules in 2003 [147] which states that Rth,ch can be supplemented by the therein included values for Rth,chT and Rth,chD, as shown in Figure 4-5b. However, homogeneous heat distribution to the base plate is not guaranteed under all operation conditions [147] due to the distribution of separate chips for the IGBT and diode across the modules surface. Hence, a separate thermal calculation for the IGBT as well as the diode part is necessary. The values of Rth,chT and Rth,chD can already be derived from the previous specification but have now been added for more simplicity, as shown in Table 4-2 taken from [147]. (4-6)
72
Junction Ploss,T Tj(T) Ploss,D Tj(D) Rth,jcD Rth,jcT
Case
Heat sink Rth,ch Rth,ha
Ambient
Ta
(a)
Junction Ploss,T Tj(T) Ploss,D Tj(D) Rth,jcD Rth,chD Rth,jcT Case Rth,chT Rth,ha Heat sink Ambient
Ta
(b)
Figure 4-5 The steady state equivalent thermal circuit diagram: (a) general model, (b) Infineon model Table 4-2 Thermal resistance of the IGBT module: FZ600R65KF1 [147] Rth,ch Rth,ch Rth,chT Rth,chD
6K/kW 6K/kW 9K/kW 18K/kW
Previous specifications Thermal resistance, case to heat sink per module New specifications Thermal resistance, case to heat sink per module Thermal resistance, case to heat sink per IGBT Thermal resistance, case to heat sink per Diode
4.2.1.2.3. Description of the Loss Simulation Model [66], [143]
An accurate loss simulation model, which is described in detail in [3], [22], [66], enables the determination of the semiconductor losses and junction temperatures. The accuracy of the loss and junction temperature calculation and the thermal model being applied is evaluated in [3], [29], [66]. To calculate the ideal current rating IC,n (IF,n), an ideal parallel connection of commercially available IGBT or diode modules is assumed. It is obvious that on state and switching losses are adapted to the ideally rated current and the corresponding silicon area, as shown in Figure 4-6. Furthermore, the thermal resistances Rth,jc and Rth,ch are adjusted to the rational number of ideally parallel connected modules according to the silicon area and the module size.
4.2.1.2.4. Agreement Calculation Measurement
An agreement calculation of the power semiconductor on-state voltage and switching losses is represented at this stage. It is necessary to use computer simulations in order to realize detailed
73
power loss calculations of different converter topologies. The output characteristics of the IGBT/diode modules have been approximated based on data contained in the module specification sheets. Figure 4-7 depicts the simulation results for the FZ800R33KF2C IGBT-module from Eupec.
IC cf UCE
Parallel current factor
IC
IC
IC cf UCE
cf cf Ploss (UCE , IC cf )
Ploss (UCE , IC) Ploss Rth
Ploss
Parallel current factor
Rth cf
cf Rth = Rth,jc + Rth,ch Rth =
Rth,jc + Rth,ch cf
Figure 4-6 Characteristics of current sharing for two connected modules in parallel
1600 1400 1200 IC / IF [A] 1000 800 600 400 200 0 0 1 2 4 UCE / UF [V] 3 5
Acon,T = roT = 0.033603 Bcon,T = 0.6876 Uo,T = 1 Acon,D = roD = 0.015314 Bcon,D = 0.72534 Uo,D = 0.8
5 4 3 E [J]
Eon Eon
fitting
data sheet
Eoff Eoff
fitting data sheet
Aon,T = 0.00095947 Bon,T = 1.1154 Aoff,T = 0.0037716 Boff,T = 0.84186 Aoff,D = 0.059062 Boff,D = 0.42271
UCE UCE UF UF
fitting
2 1 0 0
Erec Erec
fitting
data sheet
data sheet
fitting
data sheet
200
400
600
800 1000 1200 1400 1600 IC [A]
(a)
(b)
Figure 4-7 Approximation characteristics based on the curve-fitting method: (a) IGBT/Diode on-state characteristics, (b) IGBT turn-on and IGBT/Diode turn-off switching energy (FZ800R33KF2C IGBT-module from Eupec, UCE = 1800V, Tj,max = 125C)
4.2.2. DC Link Capacitor Models
The instantaneous dc link current values of the grid side and the machine side converter are generally different. The dc link capacitor serves for the decoupling of both sides from each other. This section discusses the modelling process of a dc link capacitor.
74
4.2.2.1. Capacitor [63-65], [135-142] 4.2.2.1.1. Aluminium Electrolytic Capacitors [135], [138]
Aluminium electrolytic or foil capacitors are generally used in converters to smooth the dc link voltage. Among the various types of capacitors, aluminium electrolytic capacitors offer a large volume at low cost. It can also provide a large capacitance, compared with other types. Hence, it is mostly used in low voltage converters. The principle structure of an aluminium electrolytic capacitor is represented in [13], [135] in detail. The equivalent circuit of an aluminium electrolytic capacitor is shown in Figure 4-8 [135]. It forms a capacitance, a series resistance, a series inductance, and a parallel resistance. Equivalent Series Resistance (RESR) is the series resistance consisting of the aluminium oxide layer, electrolyte/separator combination, and other resistance-related factors, foil length, foil surface area, among others. It depends upon the temperature and represents the di-electric losses and the resistance of the electrolytes and the connections. The series capacitance Cx represents the actual capacity of the capacitor and depends upon frequency and temperature. The capacitance of an aluminium electrolytic capacitor becomes smaller with increasing frequency. As the temperature decreases, the capacitance also becomes smaller. The Equivalent Series Inductance (LESL) consists of the inductive resistance of the connecting cables. The bypass resistor REPR is due to a leakage current and can be neglected. The capacitor is designed for an operating voltage UC. This may be exceeded only briefly by a peak voltage of 10 percent. All aluminium electrolytic capacitors are polarized for dc applications. Therefore, the alternating voltage may be located only within the range UC [135]. Each capacitor has a rating current which is effective at the maximal permissible alternating current. Typical values for an acceptable rating current range from 3mA to 22mA per F [13], [136]. The capacity is indicated for a certain operating point. Typical tolerance values for the capacity are 10% and 20% for operating voltages of UC > 150V. Aluminium electrolytic capacitors have a higher dissipation factor tan than any other types of capacitors. Therefore, the ripple current causes in aluminium electrolytic capacitors a higher internal heat. This leads to an increase in temperature.
REPR
RESR
Cx
LESL
Figure 4-8 Equivalent circuit of a capacitor [135]
4.2.2.1.2. Film Capacitors [139], [140]
Since 1980, great improvements have been made on dc film capacitors. Their volume and weight have been reduced by a factor of 3 or 4 over the last years. By now, film manufacturers [140] have developed thinner films and improved the segmentation techniques. Today film capacitors are attractive in a voltage ranges between 600V DC and 1200V DC. Depending on the application, over 1200VDC, oil-filled versions are recommended [139]. Consequently, the
75
trend of industrial and traction power conversion is to replace electrolytic capacitors with film technology. This trend is supported by the many advantages that film technology offers [140]. These include: high effective current capabilities up to 1ARMS per F, over-voltage withstanding up to 2 times the rated voltage, capability of voltage reversal and high peak current, no acid inside, long lifetime, and no storage problems. The principle structure of film capacitors is represented in [139] in detail. Film capacitors have the same simplified equivalent circuit as aluminium electrolytic capacitors, as depicted in Figure 4-8. However, the magnitude of the parameters differs strongly from that of the aluminium electrolytic capacitors. The serial inductance LESL and the serial resistance RESR are clearly smaller. Thus, the dissipation factor tan is also clearly smaller. It is typically in the range of 10-4...10-3, whereas for aluminium electrolytic capacitors it is in the range of 10-2...100. The capacitance of the film capacitors remains virtually unaffected by the frequency up to 1MHz [139]. The frequencies of film capacitors are increased by 100 times, compared to the aluminium electrolytic capacitors, due to their structure. The capacity of film capacitors depends on the temperature and exhibits a small tolerance compared to aluminium electrolytic capacitors [139]. The capacitance fluctuation as a function of temperature is smaller than that in the aluminium electrolytic capacitors. The temperature range is typically from -55C ... 85C with a variable capacity of -4% ... +2%. The maximum continuous voltage of film capacitors is equal to the rated dc voltage, and their maximum permissible current rating depends on the energy dissipation. The film capacitors are outstandingly suitable for high alternating current applications because of their small dissipation factor and self-heating. Typical values for film capacitors are from 150 to 250mA per F rated current, up to 1000V rated voltage, and 1mF nominal capacity. However, film capacitors are relatively expensive compared to aluminium electrolytic capacitors. For simulation purposes, two simplified capacitor models have been used. In the first model, the effect of REPR, LESL, and RESR is neglected. The second model which was applied is an ideal voltage source.
4.2.3. Rectifier Models
In medium voltage drives, a diode rectifier is often used as a front-end converter due to its simple structure and low manufacturing cost. The simplified circuit diagram of the standard six-pulse rectifier is represented in Figure 4-9. To simplify the simulations, all the diodes are considered to be ideal, i.e. without any on state voltage drops, reverse recovery behaviour or power losses.
idc
Uu Uv Uw
Udc
Figure 4-9 Circuit diagram of the standard six-pulse diode rectifier
76
4.3. Isolation Transformer Modelling and Simulation [6], [7], [9], [67]
The dc power supplies are made of rectifiers which inject harmonics into the grid. Increasing the pulse number of the rectifiers (e.g. 12-, 18-, 24-pulse rectifier) is attractive, since the grid current harmonics decrease. Corresponding circuit configurations are shown in Figure 4-10. This requires phase-shifting transformers with multi-windings. The 15-degree phase shift can not be obtained by classical transformers with delta, star, or zigzag winding connections. The only means is using an unbalanced zigzag winding with two different numbers of turns. The most complex part of modelling such special transformers is the determination of all the needed parameters: inductance and resistance values for each winding and coupling coefficients between all considered windings. These parameters must be determinated by using the measurements obtained from the typical tests under no-load and short-circuit conditions. Unfortunately, perfect transformers cannot be built in practice. The output voltage of the secondary windings cannot be perfectly balanced because this depends on turn ratios, which are limited to plus or minus one turn. Leakage reactance is another function of the coil position and volume. Therefore, the perfect balance between the groups of secondary windings cannot be achieved. However, to simplify the analysis the simulations are performed under the assumption of balanced three-phase line voltages.
0 0 30 0 -20 0 20
(a) 12-pulse diode rectifier 22.5
(b) 18-pulse diode rectifier 22.5 -7.5 -7.5 7.5 7.5 -22.5
-7.5 7.5 -22.5
(c) 24-pulse diode rectifier
Figure 4-10 Multi-pulse phase-shift transformer
4.3.1. Transformer Model
The 24-pulse isolation transformer is designed to provide one-fourth of the nominal input voltage to each of the four rectifiers at a 15-degree phase displacement from each other. The 15-degree phase shift is obtained by phase shifting the transformers secondary windings. Some transformer connections can be used to achieve the 15-degree phase displacement between the input voltages and the four rectifiers. Figure 4-11 depicts two typical diagrams of 24-pulse
77
transformers constructed from two 12-pulse transformers. Each model has six windings overall, two windings in the primary sides and four windings in the secondary sides. Figure 4-11b shows the model which is used by the industry with zigzag primary connections and a delta-star connection in the secondary sides; whileFigure 4-11a simply uses an isolation transformer with a delta-primary connection and four zigzag secondary winding connections, one shifted +22.5 degrees, one shifted -7.5 degrees, one shifted +7.5 degrees, and one shifted 22.5 degrees in relation to the primary connection. The transformer has a turn ratio that ensures the total dc voltage produced by the four rectifiers being the same as that of a single unit of the three-phase diode rectifier directly connected to the utility grid. Due to the use of diode rectifiers, the secondary currents are distorted, but they do not contain even or triple harmonics if a constant dc link current is assumed. The secondary currents can be expressed as I s1 = I1 sin (t + 22.5 ) + I 5 sin 5 (t + 22.5 ) + I 7 sin 7 (t + 22.5 ) + I11 sin11(t + 22.5 ) + ... + I h sin ( h (t + 22.5 ) ) + ...
I s1 =
h =1,5 ,7 ,11,13 ,...
I h sin ( h (t + 22.5 ) )
(4-7)
POWER TRANSFORMER WITH ISOLATED SECONDARY WINDING
POWER TRANSFORMER WITH ISOLATED SECONDRAY WINDING
22.5 U11 V11 W11 -7.5 7.5 Ip1
Is1
22.5 U11 -7.5 Ip1 Is2 Is1
Is2
V11 W11 -7.5
Is3 U11 V11 W11 Is4 Ip2
7.5 U11 V11 Is4 W11 7.5 Ip2 Is3
-22.5
-22.5
(a)
(b)
Figure 4-11 24-pulse phase-shift transformer models: (a) 2(Dzz), (b) 2(Zdy)
78
Is2 = I s3 =
Is4 =
h =1,5 ,7 ,11,13 ,...
I h sin ( h (t 7.5 ) ) I h sin ( h (t + 7.5 ) )

I h sin ( h (t 22.5 ) )
(4-8) (4-9) (4-10)
h =1,5 ,7 ,11,13 ,...
h =1,5 ,7 ,11,13 ,...
where Ih is the amplitude of hth harmonic. The utility grid phase current isA (Figure 4-17) can be calculated by
isA = I p1 + I p 2 = I s1' + I s 2' + I s 3' + I s 4'
(4-11)
where I s1' ,I s 2' ,I s 3' ,I s 4' are the secondary currents referring to the primary side. For the referred current I s1' , all the positive-sequence current components (h = 1, 7, 13, 19 ) are 22.5 ahead of their corresponding positive-sequence currents whereas all the negative-sequence components (h = 5, 11, 17, 23) are -22.5 behind their counterparts in the secondary winding. The magnitude of this current is reduced by the turn ratio of the transformer ntr ; therefore
I s1' =
1 + + 22 5 22 5 I sin h t h . . I h sin ( ht + h 22.5 + 22.5 ) (4-12) ( ) h ntr h =1,7 ,13,19 ,... h = 5 ,11,17 ,23 ,...
In a similar method, the other referred currents I s 2' ,I s 3' ,I s 4' can be expressed as
I s 2' =
I s 3'
1 7 5 7 5 I sin h t h . . I h sin ( ht h 7.5 7.5 ) + + ( ) h ntr h =1,7 ,13 ,19 ,... h = 5 ,11,17 ,23 ,... 1 = I h sin ( ht + h 7.5 7.5 ) + I h sin ( ht + h 7.5 + 7.5 ) ntr h =1,7 ,13 ,19 ,... h = 5 ,11,17 ,23 ,...
(4-13) (4-14)
I s 4' =
1 + + 22 5 22 5 I sin h t h . . I h sin ( ht h 22.5 22.5 ) (4-15) ( ) h ntr h =1,7 ,13,19 ,... h = 5 ,11,17 ,23 ,...
in which the first term represents all the positive-sequence harmonic currents while the second term denotes the negative-sequence harmonic currents. Substituting equations (4-12) through (4-15) with (4-11) and using an appropriate turn ratio yields
isA = I s1' + I s 2' + I s 3' + I s 4' = [ I1 sin t + I 23 sin 23t + I 25 sin 25t + ...]
(4-16)
Equation (4-16) shows that the low-order current harmonics, 5th, 7th, 11th, 13th, 17th, and 19th are eliminated due to the transformer connection, and they do not appear in the utility grid current. The other harmonic components (up to the 49th) and their corresponding phase angles are also calculated and listed in Table 4-3. As a result, the utility line current is close to sinusoidal with little distortion, which is recommended by the IEEE standard 519-1992 [151] and C57.135-2001 [152].
79
Table 4-3
Harmonic current and their phase angles in 24-pulse transformers

I
' s1
h
1 5 7 11 13 17 19 23 25 29 31 35 37 41 43 47 49
' s2
' s3
' s4
isA = I si'
i =1
t 5 t + 135 7 t + 135 11 t + 270 13 t + 270 17 t + 405 19 t + 405 23 t + 540 25 t + 540 29 t + 675 31 t + 675 35 t + 810 37 t + 810 41 t + 945 43 t + 945 47t + 1080 47t + 1080
t 5 t 45 7 t 45 11 t 90 13 t 90 17 t 135 19 t 135 23 t 180 25 t 180 29 t 225 31 t 225 35 t 270 37 t 270 41 t 315 43 t 315 47 t 360 49 t 360
t 5 t + 45 7 t + 45 11 t + 90 13 t + 90 17 t + 135 19 t + 135 23 t + 180 25 t + 180 29 t + 225 31 t + 225 35 t + 270 37 t + 270 41 t + 315 43 t + 315 47 t + 360 49 t + 360
t 5 t 135 7 t 135 11 t 270 13 t 270 17 t 405 19 t 405 23 t 540 25 t 540 29 t 675 31 t 675 35 t 810 37 t 810 41 t 945 43 t 945 47t 1080 49t 1080
I1 sin t 0 0 0 0 0 0 I23 sin 23t I25 sin 25t 0 0 0 0 0 0 I47 sin 47t I49 sin 49t
4.3.1.1. Transformer Winding Model
Generally, in high power applications, using two transformers is more favourable and the mechanical construction is simpler, compared to one transformer with four secondary windings. In this section, two different configurations are modelled and investigated, according to Figure 4-11a and Figure 4-11b, applying the transformer component in MATLAB/PLECS. It should be noted that the kind of winding connections is the basic difference between these configurations. In the first model Dzz, two basic zigzag couplings are used for negative and positive phase shifts, as shown in the left part of Figure 4-12a. In the second model Zdy, which is used by the industry, the zigzag primary connections and delta-star secondary connections are used for the desired phase-shift angle, as shown in the left part of Figure 4-12b. This means that the Zdy configuration needs thinner conductors due to more windings than the Dzz configuration. Therefore, the fluctuations on the primary windings are realized simpler in the Zdy configuration. In the following sections, both configurations are investigated separately and finally the results are compared. Table 4-4 shows the necessary input data that corresponds to the data plate of the transformer used for both models.
Table 4-4 The necessary input data of the 12-pulse phase-shift transformer 2.25[MVA] 10[kV] 0.741Udc,n[V] 50[Hz] 0.005[p.u.]
Apparent rated power, SN1 Primary side line voltage, UN1 Secondary line voltage (no-load), UN20 Frequency, f1 No-load primary side current, io @
@ The no-load current of transformers with a range of 1 to 10MVA is assumed to about 0.9% of the rated current [6].
80
U11
U21
U22
U11
V11
W11
LU11D
LV11D
LW11D
W11 U11 V11
V11 W11
W21 U21 V21
V21 W21
W22 V22 W22 U22
V22
U21
LU21Y LU21D
V21
LV21Y LV21D
W21
LW21Y LW21D
U21
V21
W21
V22
W22
U22 LV22Y
V22
W22
LW22Y LW22D
U22
LU22Y LU22D
LV22D
Primary 1,2
Secondary 1, 3
Secondary 2, 4
(a)
7.5 -22.5 7.5
U11
U11
LU11Y LU11D
V11
LV11Y
W11
LW11Y
U21D V21D
U22Y
LV11D
LW11D
W11
U11 V11 W11
V11
W21D
U21D V21D W21D
W22Y
V22Y
V22Y W22Y
U21D
LU21D
V21D
W21D
U22Y
LV21D
LW21D
U11
V11
W11
U22Y
LU22Y
V22Y
LV22Y
W22Y
LW22Y
Primary 1
-7.5
Secondary 1
22.5
Secondary 2
-7.5
U12
LU12Y LU12D
V12
LV12Y LV12D
W12
LW12Y LW12D
U12
U24D
U23Y
W12
U12 V12 W12
V12
W24D
V24D
V24D W24D
W23Y
U23Y V23Y W23Y
V23Y
U24D
LU24D
V24D
LV24D
W24D
LW24D
U24D U12 V12 W12
U23Y
LU23Y
V23Y
LV23Y
W23Y
LW23Y
Primary 2
Secondary 4
Secondary 3
Figure 4-12 Investigated zigzag coupling configurations: (a) Delta-zigzag-zigzag configuration (Dzz), (b) Zigzag-delta-star configuration (Zdy) used by the industry
81
I. Delta-zigzag-zigzag (Dzz) configuration
This configuration is represented in Figure 4-12a. For the secondary 1 winding, the desired phase-shift angle is equal to -22.5. This means that this secondary winding has to be a combination of Dy11 (-30) and Dd0 (0) [67]. The secondary phase voltage is shown in Figure 4-13. For the negative or positive phase shift, the zigzag winding of each phase consists of three parts.
U21
LU21Y
U22 U21
LU21D
U22
LW22Y
LV22D
O W21 W21 (a)
LV21Y
V21
V21
W22
W22
O
LV22Y
V22
(b)
V22
Figure 4-13 Windings position for positive (a), and negative (b) phase shift of Dzz configuration
Based on Figure 4-13a, the following equation can be written for the negative phase shift
) + (U 21 V21 ) + (V21 V21 ) U 21V21 = (U 21 U 21
(4-17) (4-18)
+ U 21 V21 + V21 V21 U 21V21 = U 21U 21
The turn ratios between the secondary windings n21YD can be calculated as
n21YD = U n21Y U 21U 21 V V tan 21 = = 21 21 = N 20Y = V21 V21 n21D U 21 U 21 U N 20 D 0.866 + 1.5 tan 21
(4-19)
where UN20Y, UN20D are secondary no-load voltages with star and delta connections in each three-phase transformer. Now equation (4-18) can be rewritten as below by applying equation (4-19) V21 U 21V21 = U 21 (1 + n21YD + n21YD cos 60 ) j ( n21YD sin 60 )
V21 U 21V21 = U 21
(4-20) (4-21) (4-22)
(1 + 1.5 n21YD )2 + ( 0.866 n21YD )2 arctg 0.866 n21YD 1 + 1.5 n21YD
V21 21 U 21V21 = k21 U 21

where k21 is a constant and calculated as
82
k21 =
U U 21V21 n = N 20 = 21 = ' ' U 21 V21 U N 20 D n21D
(1 + 1.5 n21YD )2 + ( 0.866 n21YD )2
(4-23)
The next step is to define the similar open-circuit turn ratio ntr between the primary and each secondary winding of the transformer.
ntr = U n11 U11V11 = = N1 n21 U 21V21 U N 20
(4-24)
According to Figure 4-14, the equivalent short-circuit impedance for secondary winding j can be calculated as follows
Z kj = Z1 jD + Z 2 jD Z 2 jY
' '
'
'
' Z' Z 2 jY 2 jD = Z1 jD 1 + Z1 jD Z1 jD
where j = 1,.., 4
(4-25)
where Z 2 jD and Z 2 jY denote the secondary winding impedance with star and delta connections referred to the primary side, and Z1jD is the primary winding impedance.
Z11
Z 21
j L11
U N1
R11
j Lm Rm n11
n21
j L21
Z 22
R21
U N 21
n22
j L22
R22
U N 22
Figure 4-14 Equivalent electrical circuit of a linear 3-winding transformer
With due attention to the winding impedance, which is proportional to the square number of windings turns, it can be written as
n2 jY n2 jD = Z 2 jY Z 2 jD
' '
n2 jD n11
Z 2 jD Z1 jD
'
n2 jY n11
Z 2 jY Z1 jD
'
(4-26)
By substituting equations (4-24) and (4-26) in equation (4-25), the equation

n2 jYD 2 Z kj = Z1 jD 1 + 2 k21 (1 + n2 jYD 2 )
(4-27)
results. Moreover, by suggesting a value for the transformer short-circuit voltage Uk = 10% [146], the equal short-circuit impedance can be calculated according to equation (4-28).
Z kj = U k Z N = 0.1 Z N
(4-28)
The absolute value is taken account of since a phase shift will be introduced in the zigzag
83
winding. By replacing equation (4-27) in equation (4-28), the primary winding impedance can be calculated as
Z1 jD =
0.1 Z N 1 j 1+
k2 j 2 (1 + n2 jYD 2 ) n2 jYD 2
(4-29)
Now the equivalent circuit parameters include the winding resistance, the leakage inductance and the magnetizing impedance of the zigzag winding can be determined. These parameters are strongly dependent on the rated output current of the transformer. At large units in a range of 1MVA to 10MVA, the leakage inductance can be considered to be 20 to 30 times the resistance [6]. In order to determine the shares of the winding resistance and the leakage inductance in each transformer, a ratio of 25 is considered between the leakage inductance and the winding resistance (XT = 25RT). Then, the following equation can be used to determine the winding resistance and the leakage inductance in each transformer.
RT = ZT 2
X 1+ T RT
XT
(4-30)
LT =
20 RT 2 f1
(4-31)
II. Zigzag-delta-star (Zdy) configuration
This configuration is represented in Figure 4-12b. Two primary windings with the desired phase-shift angle of 7.5 are considered. This means that the primary windings have to be a combination of Delta-star DY and Delta-delta DD connections. The primary phase voltage is shown in Figure 4-15. Similar to the secondary windings in the Dzz configuration, the primary zigzag winding of each phase consists of three parts for the negative or positive phase shift.
U11 U11
LU11Y
U12
LU12Y
U12
LU12D
LV11D
W11
W11
O
LV11Y
O V11 W12 W12
LV12Y
V12
V12
(a)
V11
(b)
Figure 4-15 Windings position for positive (a), and negative (b) phase shift of Zdy configuration
84
Therefore, equations (4-19) and (4-23) can be rewritten for the positive phase shift, according to Figure 4-15a,
n11YD = U n11Y U11U11' V11V11' tan 11 = = = N 10Y = ' ' ' ' n11D U11 V11 U11 V11 U N 10 D 0.866 1.5 tan 11
(4-32) (4-33)
k11 =
1
n11D
(1 + 1.5 n11YD )2 + ( 0.866 n11YD )2
where UN10Y, UN10D are primary no-load voltages with star and delta connections in each threephase transformer. The same equations can be applied to the negative phase shift case, according to Figure 4-15b.
4.3.1.2. MATLAB/PLECS Implementation
The MATLAB simulation software is used to simulate these multi-winding transformers in detail. Both Dzz and Zdy configurations are modelled, examined, and compared. The linear three-winding transformer in the PLECS models three coupled windings on the same core, which is a toolbax for the fast simulation of electrical and power electronics circuits, according to Figure 4-14. The magnetization inductance Lm and the core losses Rm are modelled as linear elements. The magnetization resistance Rm represents the core losses and is negligible in this part. Instead, the values of the core losses are referred to the primary side. For the following discussion, this equivalent electrical circuit is assumed for both Dzz and Zdy configurations. The following computation shows how to model a three-winding transformer with a zigzag connection in detail.
I. Dzz configuration
By setting UN1 = 10kV and UN21 = 1200V as well as using equation (4-24), the open-circuit turn ratio between the primary and secondary windings can be calculated as
ntr = n11 10000 = = 8.33 1200 n2 j where j = 1,.., 4
(4-34)
By setting SN1 = 2.25MVA, the rated impedance ZN11Y of the primary winding is calculated according to equation (4-35)
Z N 11Y
3 V2 U N 12 (10 10 ) = 44.44 = = SN1 2250 103 [VA] 2
(4-35)
The star-connected equivalent no-load impedance Z11Yo is calculated by taking into account the no-load current io (Table 4-4) [67]
Z11Yo =
1 1 Z N 11Y = 44.44 = 8.88k 0.005 io

Z11Yo
(4-36)
Using the angular frequency, the equivalent star-connected inductance LmY is calculated as
LmY =
2 50 Hz
= 28.29 H
(4-37)
To obtain the delta-connected inductance LmD, the previous value has to be multiplied by 3; thus
85
LmD = 3 28.29 H = 84.88 H
(4-38)
Considering a negative phase-shift angle of 22.5 and using equation (4-23), the ratio between the turn number of the star and delta connection of this secondary winding is equal to
n21YD =
tan ( 22.5 ) n21Y = = 1.693 n21D 0.866 + 1.5 tan ( 22.5 )
(4-39)
Introducing (4-39) in (4-23), we obtain k21 = (1 + 1.5 1.693)2 + ( 0.866 1.693)2 = 3.83 1 = 0.261 , n21Y = n21D n21YD = 0.442 k21 (4-40)
Then, the turn number of the star and delta connections of this secondary is equal to n21D = (4-41)
Now the equal short-circuit impedance Zk1 can be calculated as Z k1 = 0.1 Z N 11Y = 4.44 Further, by using equation (4-29), the primary winding impedance is calculated as
Z11D = 4.44 = 4.23 (1 + 0.05)
(4-42)
(4-42)
Now by applying equations (4-30) and (4-31), the primary winding resistance, the primary leakage inductance, and the primary impedance are calculated as R11D = 4.232 1 + ( 20 )
2
= 0.211 , L11D =
20 0.211 = 0.0134 H 2 ( 50 )
(4-44) (4-45)
Z11D = R11D + jX 11D = ( 0.211 + j 4.22 )
Afterwards, the secondary winding resistance, the secondary leakage inductance, and the secondary impedance can be determined on the basis of equation (4-26), yielding the following equations
R21D n 0.261 = R11D 21D = 0.211 = 207 8.33 n11 n 0.261 = L11D 21D = 0.0134 H = 13.2 H 8.33 n11
2 2 2 2
(4-46)
L21D
(4-47) (4-48)
Z 21D = R21D + jX 21D = ( 0.207 + j 4.1) m
R21Y
n 0.442 = R11D 21Y = 0.211 = 594 8.33 n11

n 0.442 = L11D 21Y = 0.0134 H = 37.7 H 8.33 n11
2 2
(4-49)
L21Y
(4-50)
86
Z 21Y = R21Y + jX 21Y = ( 0.594 + j11.85 ) m
(4-51)
Thus, the secondary equivalent impedance is equal to

Z 21 = 3 Z 21Y + Z 21D = (1.98 + j 39.6 ) m
(4-52)
The same equations can be applied to the positive phase-shift case, according to Figure 4-13b. To achieve this aim, a similar method is employed for the positive phase-shift angle of 7.5. The ratio between the turn number of the star and delta connections of this secondary winding is equal to n22YD = k22 = tan ( 7.5 ) n22Y = = 0.197 n22 D 0.866 1.5 tan ( 7.5 ) (1 + 1.5 0.197 )2 + ( 0.866 0.197 )2 = 1.306 1 = 0.765 , n22Y = n22 D n22YD = 0.151 k22
4.44 = 4.34 (1 + 0.0219 )
(4-53) (4-54)
Then, the turn number of the star and delta connections of this secondary winding is equal to n22 D = (4-55)
Thus, by using equation (4-29), the primary winding impedance is calculated as

Z12 D =
(4-56)
Now by using equations (4-30) and (4-31), the primary winding resistance, the primary leakage inductance, and the primary impedance are calculated as R12 D = 0.217 , L12 D = 0.0138H
Z12 D = R12 D + jX 12 D = ( 0.217 + j 4.33)
(4-57) (4-58)
Then, the secondary winding resistance, the secondary leakage inductance, and the secondary impedance can be determined as follows, based on equation (4-26), R22 D n 0.765 = R12 D 22 D = 0.217 = 1.83m 8.33 n11 n 0.765 = L12 D 22 D = 0.0138 H = 116.4 H 8.33 n11
2 2 2 2
(4-59)
L22 D
(4-60) (4-61)
Z 22 D = R22 D + jX 22 D = (1.83 + j 36.5 ) m
R22Y
n 0.151 = R12 D 22Y = 0.217 = 71.3 8.33 n11 n 0.151 = L12 D 22Y = 0.0138H = 4.5 H 8.33 n11
2 2
(4-62)
L22Y
(4-63) (4-64)
Z 22Y = R22Y + jX 22Y = ( 0.0713 + j1.42 ) m
Thus, the secondary equivalent impedance is equal to
87
Z 22 = 3 Z 22Y + Z 22 D = ( 2 + j 40.7 ) m
(4-65)
Now the primary equal impedance of parallel transformers (-22.5 and 7.5) can be calculated by
Z11 = Z11D Z12 D =
( 0.211 + j 4.22 ) ( 0.217 + j 4.33) = 0.108 + j 2.14 ( ) ( 0.211 + j 4.22 ) + ( 0.217 + j 4.33)
(4-66)
Thereby, the magnetization inductance Lm is equal to Lm = 2 LmD = 2 84.88 H = 169.7 H (4-67) Similar methods can be used to obtain the winding resistances, the leakage inductances, and winding impedances for the parallel operation of the negative phase-shift angle 7.5 and positive phase-shift angle 22.5. Table 4-5 depicts the quantity results for all secondary windings in detail. These values are used directly in the PLECS model component of MATLAB. As seen in Table 4-5, similar results are obtained for the secondary windings with a phase-shift angle of 22.5 and a phase-shift angle of 7.5 too. Therefore, the primary equivalent impedance of the parallel transformers -22.5 and 7.5 is equal to the primary equivalent impedance of the parallel transformers 22.5 and -7.5
' Z11 = Z11 = ( 0.108 + j 2.14 )
(4-68)
Then, the primary equivalent impedance of transformer Z1 is equal to

' Z1 = Z11 Z11 =
1 Z11 = ( 0.54 + j1.07 ) 2
(4-69)
Table 4-5
The secondary quantity parameters for the 24-pulse transformer with Zdy connection
n21YD
1.693
n21D
0.261
n21Y
0.442
k21
3.83
L21D [H]
13.2
= 22.5 L21Y [H] R21D []

37.7 207
R21Y []
594
Z 21 [m]
1.98+j39.6
Z11D [m]
0.211+j4.22
n22YD
0.197
n22 D
0.765
n22Y
0.151
k22
1.31
L22 D [H]
116.4
= 7.5 L22Y [H] R22 D []

4.5 1830
R22Y []
71.3
Z 22 [m]
1.83+j36.5
Z12 D [m]
0.211+j4.33
II. Zdy configuration
The Zdy configuration parameters can be determined like the Dzz configuration. For this purpose, the following model is assumed for each 12-pulse transformer, according to Figure 416. The calculations are accomplished on the basis of equations (4-19) to (4-31) and the input data of the Table 4-4. The computation results are summarized in Table 4-6.
4.3.1.3. Medium Voltage Converter Application
The effect of a multi-winding transformer on two medium power converters, i.e. the 3L-NPC VSC and 9L-SC2LHB VSC, is investigated. The steady state at 100% load with symmetrical
88
transformers, as calculated above, is assumed. Each 24-pulse transformer consists of two 12pulse transformers. The model of one 12-pulse transformer is illustrated in Figure 4-16. To validate the obtained simulation results, MATLAB and Simplorer programs are used.
Table 4-6 The designing parameters for the 24-pulse transformer with Zdy connection L1 R1 L2Y = L2D R2Y = R2D Lm Uk12Y = Uk12D Uk2YD io 1.41[mH] 22.2[m] 130[H] 2[] 85[H] 8[%] 14[%] 0.005[p.u.]
U N1
j L1
R1
j L2Y j L2 D j L2Y
j L2 D
R2Y
U N 2Y
j Lm j L1 R1
j Lm
R2 D
U N 2D
VN 2Y VN 2 D
VN 1
R2Y
R2 D
j Lm
WN 1
j L1
R1
j L2Y
j L2 D
R2Y
R2 D
WN 2Y
WN 2 D
Figure 4-16 The model of a 12-pulse transformer
4.3.1.3.1. Three-Level Neutral Point Clamped Voltage Source Converter
The first application example deals with the 24-pulse rectifier with serial diode-bridge-rectifier connections, which is used for the 3L-NPC VSC. The corresponding circuit is represented in Figure 4-17 and Figure 4-18 for the two aforementioned configurations. The structure consists of the ac three-phase input source, four diode-bridge circuits, and two 12-pulse phase-shift transformers. The dc output is made of four 6-pulse rectifiers with a serial connection. The three-phase voltages of the rectifier input terminals are set to have a 15-degree phase difference. This connection allows supplying the four-diode rectifiers with 15-degree phase-shifted their phase voltage systems. This leads to a 24-pulse rectifier system.
89
RECTIFIER
Is1 Ip1
INPUT POWER THREE-PHASE AC SOURCE
22.5
Is2 -7.5
UsA UsB UsC isA
Ls Ls Ls
Rs Rs
Is3 Rs Ip2 7.5
Udc
idc
Is4 -22.5
Figure 4-17 24-Pulse-Diode-Rectifier with serial connections and Dzz configuration
RECTIFIER
Is1 22.5
Ip1
-7.5 Is2 -7.5
UsA UsB UsC isA
Ls Ls Ls
Rs Rs Rs Ip2
Udc Is3 -22.5 7.5 Is4 7.5
idc
Figure 4-18 24-Pulse-Diode-Rectifier with serial connections and Zdy configuration
4.3.1.3.1.1.
Simulation Results
Figure 4-19 to Figure 4-21 represent the simulation results assuming an ideal current source as load. As expected, the first dominant ac supply phase current harmonics are the 23rd and the 25th ones, according to Figure 4-19b. The first dominant primary and secondary current
90
harmonics are the 11th, 13th and 5th, 7th ones, according to Figure 4-19c and Figure 4-19e respectively. The harmonics analysis results confirm the proposed 24-pulse modelling.
500
10
isA isB isC
(a)
Amplitude isA 10
2
(b)
is,x [A]
10
10
-500 0.04 0.045 0.05 Time [sec.] 0.055 0.06
10
20 30 Harmonics order
40
50
200 100 Ip1,x [A] Ip1U 0 -100 -200 0.04 0.045 0.05 Time [sec.] 0.055 Ip1V Ip1W
(c)
Amplitude I p1U
10
(d)
10
10
0.06
10
40
50
800 600 400 200 Is1,x 0 -200 -400 -600 -800 0.04 0.045 0.05 Time [sec.] 0.055 Is1U Is1V Is
1W
10
(e)
Amplitude Is1U 10
2
(f)
10
0.06
10
10
40
50
Figure 4-19 Utility grid current and its harmonic spectrum for the 24-pulse transformer (a, b), primary winding currents and their harmonic spectrum for the 12-pulse transformer (c, d), and secondary winding currents and their harmonic spectrum for the 12-pulse transformer (e, f) (see Figure 4-17)
91
200
Ip1 Ip2
500
Is1 Is2 Is3 Isx [A] Is4 0
100 Ipx [A]
-100
-500
-200 0.04
0.045
0.05 Time [sec.]
0.055
0.06
0.04
0.045
0.05 Time [sec.]
0.055
0.06
Figure 4-20 Primary and secondary winding currents of the 24-pulse transformer
6300 6250 6200 Udc [V] 6150 6100 6050 6000 5950 0.04 0.045 0.05 Time [sec.] 0.055 0.06
(a)
10 Amplitude U dc
3
(b)
10
10
10
40
50
720
(c)
719 718 717 716 715 0.04
(d)
10
2
Amplitude i dc
idc [A]
10
0.045
0.05 Time [sec.]
0.055
0.06
10
-2
10
40
50
Figure 4-21 DC link voltage and its harmonic spectrum (a, b), and dc link current and its harmonic spectrum (c, d), idc = 710A, fC = 750Hz (see Figure 4-17)
92
4.3.1.3.2. Nine-Level Series Connected H-Bridge Voltage Source Converter
The second application example deals with the 24-pulse dc supply with independent diodebridge-rectifier connections, which is used for the 9L-SC2LHB VSC. The corresponding circuits are represented in Figure 4-22 only for one motor phase. The dc supply is made of four separate 6-pulse transformers, each one leading to a 6-pulse rectifier system. The three-phase voltages of the rectifier input terminals are set to have a 15-phase difference, which generates a 24-pulse rectifier system.
POWER TRANSFORMER WITH ISOLATED SECONDARY WINDING RECTIFIER
Is1 Ip1
22.5
idc1
Udc,1
Is2 -7.5 idc2 Udc,2
UsA UsB UsC isA
Ls Ls Ls
Rs Rs Rs Ip2
Is3 7.5 idc3 Udc,3
Is4 -22.5 idc4 Udc,4
(a)
POWER TRANSFORMER WITH ISOLATED SECONDARY WINDING RECTIFIER
Is1 22.5
idc1
Udc,1
Ip1
-7.5
Is2 -7.5 idc2 Udc,2
UsA
Ls isA Ls Ls
Rs Rs Rs Ip2
UsB UsC
Is3 -22.5 7.5 Is4 7.5
idc3
Udc,3
idc4
Udc,4
(b)
Figure 4-22 24-Pulse-Diode-Rectifier with independent connections: (a) Dzz configuration, and (b) Zdy configuration
93
4.3.1.3.2.1.
Simulation Results
Figure 4-23 to Figure 4-26 represent the simulation results in the steady state at 100% load, which are the equivalent to that of the 3L-NPC VSC. As expected, the first dominant ac supply phase current harmonics are the 23rd and the 25th ones, according to Figure 4-23b. The harmonics analysis results confirm the proposed 24-pulse modelling. The first dominant primary and secondary current harmonics are the 11th, 13th and 5th, 7th ones, according to Figure 4-23d and Figure 4-23e respectively.
150 100 50 is,x [A] 0 -50 -100 -150 0.04 0.045 0.05 Time [sec.] 0.055 0.06 10
-1
isA isB isC
(a)
Amplitude isA
10
(b)
10
10
10
40
50
80 60 40
Amplitude I p1U
10
(c)
Ip1U Ip1V Ip1W
10
1
(d)
Ip1,x [A]
20 0 -20 -40 -60 -80 0.04 600 400 200 0.045 0.05 Time [sec.] 0.055
10
0.06
10
-1
0
3
10
40
50
10
(e)
Is1U Is1V Is1W
Amplitude I s1U 10
2
(f)
Is1,x [A]
0 -200 -400
10
10
-600 0.04
0.045
0.05 Time [sec.]
0.055
0.06
10
40
50
Figure 4-23 Utility grid current and its harmonic spectrum for the 24-pulse transformer (a, b), primary winding currents and their harmonic spectrum for the 12-pulse transformer (c, d), and secondary winding currents and their harmonic spectrum for the 12-pulse transformer (e,f) (see Figure 4-18)
94
80 60 40 20 Ipx [A] 0 -20 -40 -60 -80 0.04 0.045 0.05 Time [sec.] 0.055
Ip1 Ip2
600 400 200 Isx [A] 0 -200 -400
Is1 Is2 Is3 Is4
0.06
-600 0.04
0.045
0.05 Time [sec.]
0.055
0.06
Figure 4-24 Primary and secondary winding currents of the 24-pulse transformer
900 850 Udc,x [V] 800 750 700
Udc1 Udc2 Amplitude Udc1 Udc3 Udc4
10
10
10 650 0.06 0.065 0.07 Time [sec.] 0.075 0.08
10
40
50
Figure 4-25 DC link voltage and its harmonic spectrum, fC= 750Hz (see Figure 4-18)
472 471.9 471.8 471.7 471.6 471.5 0.06 idc1 idc2 idc3 idc4 0.065 0.07 Time [sec.] 0.075 0.08
10 Amplitude idc,x
idc,x [A]
10
10
-2
10
40
50
Figure 4-26 DC link current and its harmonic spectrum, idc = 471A, fC = 750Hz (see Figure 4-18)
5. DESIGN CRITERIA AND CONVERTER DATA

This chapter defines the design criteria and technical data of the typical available industrial medium voltage drives (the 3L-NPC VSC, 3L-FLC VSC, 4L-FLC VSC, and 9L-SC2LHB VSC) which will be compared in detail in chapter 6. 5.1. Design Criteria The design process of a power converter depends on the topology and the converter specifications including line-to-line voltage Ull,rms,1, phase current Iph,rms,1, and the apparent converter output power SC, which have a critical influence on the overall characteristics, performance, and cost of any design. 5.1.1. Power Semiconductor Devices The selection of power semiconductors fundamentally determines the design and the performance as well as the investment and operating costs of power converters. IGBTs are usually used as power semiconductors in medium and high power applications [18], [78] due to their technical advantages. When designing an IGBT/diode, important technical characteristics are: UCE : Rated collector-emitter voltage. IC,n / IF,n : Rated IGBT/Diode current. URRM : Repetitive peak reverses voltage of diodes. Tj,max : Maximum junction temperature range within the IGBT/Diode may be operated. Rth,jc, Rth,ch : Thermal resistances of the IGBT/diode from junction to case and case to heat sink. Th : Temperature of the heat sink. Eon /Eoff : Turn-on / turn-off dissipation energy in the IGBT. Erec : Recovery dissipation energy in the Diode. Ucom@100FIT : The voltage Ucom@100FIT characterizes the device commutation voltage for a device reliability of 100FIT (where 1FIT corresponds to one failure in 109 operation hours) due to cosmic radiation. For a steady state operation, this voltage should be higher than the dc link voltage (Ucom@100FIT > Udc,n). The installed switch power SS is a measureof the semiconductor cost and can be defined as S S = U CE I C ,n nT + 0.5 U RRM I F ,n nD where nT and nD denote the number of semiconductors and diodes in the converter. Considering that the diode area is typically only about 50% of that of the IGBTs in IGBT modules, the diodes are weighted with 50% compared to the IGBTs (equation 5-1), [29], [147]. (5-1)
96
DESIGN CRITERIA AND CONVERTER DATA
The relative installed switch power is calculated by normalizing the installed switch power of a certain converter topology to the installed switch power of the reference topology (e.g. the 3LNPC VSC) [29].
S SR = SS S S ,3 L NPC VSC 100
(5-2)
This definition enables a comparison of the installed switch powers as a measure for the expense of semiconductors of the different converter topologies with respect to the 3L-NPC VSC. The dimensioning of the semiconductor devices is based on the electrical and thermal data given in module specification datasheets. The switching frequency and output power of the MV converters are limited by the junction temperature Tj of the semiconductor devices. For a safe operation, the junction temperature must never exceed the maximum value Tj,max, whereby the average power losses in frequency ranges of 5Hz to 50Hz are considered (operating range). Therefore, the cooling of power semiconductors and thus the power dissipation in the semiconductors are criteria for the dimensioning of these devices. However, the operating range of fo < 5Hz, failure conditions, and dynamic procedures (e.g. overload, connection, and disconnection of the converter) are not examined in this thesis. Figure 5-1 depicts the suggested iterative approach to the power semiconductor design. By using this chart, it is possible to determine the installed switch power, the semiconductor losses, and the necessary silicon area. To select the suitable device, an iterative MATLAB program is used, which allows to select the calculation of the required switch ratings. Essentially, it starts by providing a screen with different critical operation points related to the topology. The number of ideal parallel connections is selected so that the mostly stressed device never exceeds the maximum junction temperature Tj,max in all critical operating points (Table 51) of a four-quadrant operation [20], [25]. A maximum junction temperature greater than 125C is an indication that the number of ideal parallel connections should be changed and more silicon area is necessary. Furthermore, to evaluate the converter topologies for a variety of applications, four different categories are discussed and simulated in chapter 6. In a first step, a constant carrier frequency and a constant installed switch power SS are assumed. This approach allows a comparison between the maximum converter output power SC,max and the semiconductor utilization of the considered converter topologies. Figure 5-2 shows the applied calculation method. In the second comparison, a constant installed switch power SS (which is a measure for the cost of semiconductors) as well as an equal output current and a constant converter output power SC are assumed to calculate the maximum carrier frequency of the considered converter topologies, as shown in Figure 5-3.
Table 5-1 Critical operating points for the determination of the power semiconductor current ratings (stationary thermal design) for all considered topologies [20], [25] Operating Point OP1 OP2 OP3 OP4 OP5 OP6 Udc,n
+10% -10% +10% -10% -10% -10%
Iph,rms,1
-10% +10% -10% + 10% +10% +10%
cos
1 1 -1 -1 1 -1
ma
1.15 1.15 1.15 1.15 0 0
97
Converter specifications Ull,rms,1, Iph,rms,1, SC Calculation of the nominal dc link voltage Udc,n = f (Ull,rms,1)
Calculation of the commutation voltage and the rated device voltage (Ucom, UCE) = f (Udc,n)
Calculation of the power semiconductor losses and the junction temperature in 4Q-operation (Ploss, Tj)
0.99T j ,sp T j T j ,sp

No Adaption of the rated device current IC,n (IF,n ) and thermal resistance Rth by cf to provide the condition
Yes
Calculation of the installed switch power SS for all considered topologies
Adaption of the current factor cf to provide the constant installed switch power SS for all considered topologies
1
Figure 5-1 Iterative design approach to the power semiconductor design
98
1 fC = constant
Results

No Variation of the output converter current Iph
Yes
I ph,max ,SC ,max ,Ploss ,
Figure 5-2 Iterative design approach to calculate the maximum converter output power SC,max and the semiconductor utilization (Tj = Tj,max, SS = const., fC = const.)
Iph = constant
Results

No Variation of the carrier frequency fC to provide the condition
Yes
fC ,max ,Ploss ,
Figure 5-3 Iterative design approach to calculate the maximum carrier frequency (Tj = Tj,max, SS = const., SC = const.)
The third condition for a converter comparison is the constant installed switch power SS and a constant frequency of the first harmonic carrier band f1Cb, according to Figure 5-4. This approach allows a comparison between the converter output power and losses of the considered converter topologies. If the first harmonic carrier band occurs at around the same frequency, the design of an output filter with about the same size and weight is enabled. The constant converter power SC and a constant converter efficiency are assumed for a fourth condition to calculate the carrier frequency, achieving a maximum junction temperature of Tj,max in one worst case operating point of the converter (see Figure 5-5). The chosen efficiency is typical for state-of-the-art medium voltage converters.
99
1 f1Cb = constant
Calculation of the switching frequency fC for all topologies
Results

No Variation of the output converter current Iph
Yes
I ph,max ,SC ,max ,Ploss ,
Figure 5-4 Iterative design approach to calculate the converter output power and losses (Tj = Tj,max, SS = const., f1Cb = const.)
= constant
ref
Variation of the carrier frequency fC to provide the condition Results
Yes
Ploss , ,...
No Adaption of the rated device current IC,n (IF,n ) and thermal resistance Rth to provide the condition
Figure 5-5 Iterative design approach to calculate the maximum carrier frequency (Tj = Tj,max, SC = const., = ref const.)
100
5.1.2. DC Link Capacitor Different criteria are given in the literature for the dimensioning of the dc link capacitor [10], [65], [77], [138], and [141]. Design criteria like dc link voltage ripples and dc link capacitor storage energy play important roles in sizing the dc link capacitor and they are therefore examined in this thesis in order to choose the most suitable amount and size of dc link capacitors. 5.1.2.1. DC Link Voltage Ripples The primary function of the dc link capacitor is to filter the dc link voltage and to provide a stable dc voltage link for the inverter section. The impermissible dc link voltage ripples may have unfavourable effects on the operation of the drive. They increase the current harmonics and the electromagnetic interference (EMI) of the drive and negatively affect the electric machine. Other possible consequences are an increase of electric losses, higher supply current harmonics, an excessive rise of motor temperature, appearance of torque pulsations on the machine side, noise problems, and a higher risk of semiconductor failure. A solution to these problems is an appropriate design of the dc link capacitor. For this purpose, this section first presents an equation to determine the minimum size of the dc link capacitor for the NPC and SCHB topologies as a function of the voltage ripple UC, which is derived in [140], [144].
Cmin,NPC =
PC U C U C 1 2
2 U dc f rec
(5-3)
Cmin,SCHB =
PC ma 1 sin arccos U C 2 4 U C 1 U dc f rec 2
(5-4)
where PC denotes the converter output active power in watts, ma is the modulation index and frec is the rectifier output frequency in hertz.
5.1.2.2. DC Link Capacitor Stored Energy
Stored energy is a measure to compare the different converter topologies with each other and/or to compare the different applications of a topology with each other. This size is also a measure for ride-through capability. Power disturbance ride-through capability can be defined as the ability of a drive to maintain the motor output power with a power line disturbance or drop voltage at the drive input. If there is an input power disturbance, the dc link voltage will drop and the drive will stop the motor after a short time. During a power ride-through capability, the input power is removed and the stored energy in the dc link capacitor bank is the only source of power available to run the motor. Then, the stored energy per kVA is a measure of the ridethrough capability as well as a measure of the cost and volume of the dc link capacitor. The equation for the stored energy in a dc link capacitor is
1 EC = C U dc 2 2 (5-5)
It can be observed that the stored energy in a drive is directly proportional to the dc link capacitance and proportional to the square of the dc link voltage. However, not the entire stored energy is available for the drive to provide output power to the motor. If the ride-through capability time is under one second, it is very likely that the energy requirement is supplied by the internal dc link capacitor. If, however, the required energy is only
101
slightly more than the stored energy of the dc link capacitor, an increase in the dc link capacitor and a recalculation of the available energy should be considered. Figure 5-6 illustrates the relations between the dc link voltage ripple and the stored energy for the 3L-NPC VSC as a function of the dc link capacitance, using equations (5-3) and (5-5). An increase of the dc link capacitance increases the stored energy and decreases the dc link voltage ripple. It is to remark that the application of the dc link capacitance C = 2.77mF enables a reduction of the dc link voltage ripple by 51% at twice the stored energy, compared to the use of the dc link capacitance C = 1.39mF at a stored energy of 6J/kVA.
20
15
UC [%]
5 2 4 6 8 EC [J/kVA] 10
C = 2.77 [mF]
10
C = 1.39 [mF]
12
14
Figure 5-6 The dc link voltage ripple UC and the dc link stored energy EC as functions of the dc link capacitance for the 3L-NPC VSC (Ull,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9, Udc = 6118V)
5.1.2.3. Design of the Flying Capacitors
Assuming sinusoidal converter output voltages and currents, equation (5-5) can be used as an approximation to determine the capacitance of the flying capacitors of a 3L-FLC VSC and a 4LFLC VSC
C= I ph ,rms ,1 nC U C f C
(5-6)
where I ph,rms ,1 denotes the amplitude of the phase current, nC is the number of series connected flying capacitor cells, fC is the carrier frequency, and UC denotes the maximum voltage ripple across the flying capacitors. For the design being realized the maximum capacitor voltage ripple UC,max was specified to 15% of the rated flying capacitor voltage of the 3L-FLC VSC for both flying capacitor converters (UC,max = 0.15Udc,n/2). [29] To verify the approximation according to (5-5), the voltage ripple UC and current iC,rms of the flying capacitors of a 3L-FLC VSC and a 4L-FLC VSC are studied in section 6.1.4.
102
5.2. Definition of the Converter Data
Table 5-2 depicts the characteristic converter data for the output phase current Iph,rms,1 = 600A, which is used for the comparison of the investigated converter topologies in chapter 6. Today, the line-to-line voltages of 2.3kV, 3.3kV, and 4.16kV are usually used for MVDs. However, due to the development of 6kV-7.2kV MVDs in the last years, rated voltages of 6.2kV and 6.9kV are also selected.
Table 5-2 Converter data (Output phase current Iph,rms,1 = 600A) 2.3kV, 3.3kV, 4.16kV, 6.2kV, and 6.9kV 2.4MVA, 3.4MVA, 4.3MVA, 6.4MVA, and 7.2MVA 3383V, 4853V, 6118V, 9119V, and 10148V 600A 50Hz
Converter line-to-line voltage Ull,rms,1 Apparent converter output power Sc Nominal dc link voltage Udc,n Phase current Iph,rms,1 Converter output frequency fo
Converter efficiency 99% Output voltage THD according to IEEE 5% 519-1999 Natural sampled sine-triangle modulation with 1/6 Modulation added third harmonics Carrier frequency fC 450Hz 1050Hz Maximum junction temperature Tj,max 125C (IGBT, diode) Heat sink temperature Th 80C
5.2.1. Power Semiconductor Devices
Table 5-3 summarizes the power semiconductor devices in the voltage classes of 1.7kV, 2.5kV, 3.3kV, 4.5kV, and 6.5kV from several manufacturers, which are used in this thesis.
Table 5-3 Manufacturer Eupec (Infineon) Power semiconductor devices [156], [158], [160] Device FZ600R65KF1 FZ800R33KF2 FZ800R33KF2C FZ1000R25KF1 FZ600R17KE3 CM900HB-90H CM600HB-90H CM800HA-66H CM800HA-50H CM600DY-34H DIM800NSM33-A DIM600DDM17-A
UCE,n
6.5kV 3.3kV 3.3kV 2.5kV 1.7kV 4.5kV 4.5kV 3.3kV 2.5kV 1.7kV 3.3kV 1.7kV
IC,n (IF,n)
600A 800A 800A 1000A 600A 900A 600A 800A 800A 600A 800A 600A
Ucom@100FIT
3600V 1800V 1800V 1200V 900V 2250V 2250V 1650V 1250V 850V 1800V 900V
Mitsubishi (Powerex)
Dynex
103
5.2.2. Switching Frequency

The considered converter topologies are modulated by a sine-triangle modulation with an addition of 1/6th of third harmonics. To evaluate the converter topologies for a variety of applications, carrier
frequencies of fC = 450Hz ... 1050Hz are assumed for all investigated converter topologies. This range is typical for available industrial medium voltage drives.
5.2.3. DC Link Voltage
The minimum dc link voltage Udc,min to achieve a certain line-to-line output voltage by using a sine-triangle modulation with 1/6 added third harmonics for all topologies is calculated by
U dc ,min = 2 U ll ,rms ,1
(5-6)
To determine the nominal dc link voltage of the converter Udc,n, a control voltage reserve of 4% is assumed, which is needed for dynamic processes and filter voltage drops. U dc ,n = 1.04 U dc ,min (5-7)
Due to the circuit structure of the SC2LHB VSCs, the minimum dc link voltage of one H-bridge Udc,HB depends on the number of series connected H-bridges p. It is determined by equation (330) and can be rewritten as
U dc ,HB = U dc ,n 2p (5-8)
To evaluate the harmonic spectrum of the line-to-line output voltage, the total harmonic distortion (THD) and the weighted total harmonic distortion (WTHD) are being considered (based on equation 5-9).
THD =
(U )
h=2 ll ,h
U ll ,1
U ll ,h h=2 h WTHD = U ll ,1
(5-9)
where h denotes the order of harmonics. The weighted total harmonic distortion is a measure of the harmonic content for the output current and the harmonic losses in the load.
5.2.4. Rectifier
Depending on the inverter configuration, two types of diode rectifiers are used: (1) series-type, where the dc sides of the standard six-pulse diode rectifiers are connected in series which uses for the 3L-NPC VSC and (2) separate-type, where each dc side is connected directly which uses for the 9L-SCHB VSC. The block diagrams of a 24-pulse-diode-bridge configuration for both applications are depicted in Figure 5-7.
5.2.5. General Data for the Selective Medium Voltage Converters
Figure 5-8 illustrates the selected medium voltage drives in the 2.4MVA to 7.2MVA range with voltage ratings from 2.3KV to 6.9KV at a phase current rating of 600A. The technical data of the selected medium voltage topologies (e.g. the 2L-VSC, 3L-NPC VSC, 3L-FLC VSC, 4LFLC VSC, and SC2LHB VSCs), which are analyzed in this thesis, are also summarized in Table 5-4. State-of-the-art 1.7kV, 2.5kV, 3.3kV, 4.5kV, and 6.5kV IGBTs are examined. The converter ratings were chosen so that they are comparable with the ratings of commercially
104
available topologies. It is interesting to note that the same technical data are utilizable for both 3L-VSCs due to the same voltage utilization of the semiconductors. However, the required current rating to achieve a certain output current is different because of the different circuit structures and modulation schemes. In SC2LHB VSCs, the number of series connected H-bridges differs according to the required line-to-line output voltage and if 1.7kV IGBT moduls are applied. Today, the use of the 1.7kV IGBT moduls is state-of-the-art for all considered output voltage classes of the SC2LHB VSCs.
22.5 -7.5 -7.5 7.5 7.5 -22.5 7.5 -7.5
22.5 -7.5 7.5 -22.5 (b) Seperate configuration
(a) Series configuration
Figure 5-7 24-pulse diode rectifier configurations: (a) series configuration uses for the 3L-NPC VSC, (b) separate configuration uses for the9L-SCHB VSC
Power range
2.4MVA 3.4MVA 4.3MVA 6.4MVA 7.2MVA
Voltage range
2.3kV 3.3kV 24.5kV IGBT 4.5kV IGBT 6.5kV IGBT 23.3kV IGBT 4.5kV IGBT 6.5kV IGBT 6.5kV IGBT 4.16kV 6.6kV 6.9kV
2L-VSC
6.5kV IGBT
3L-VSCs
3.3kV IGBT
4L-FLC VSC
2.5kV IGBT 3.3kV IGBT
SC2LHB VSC
Number of cells per phase/Number of levels per phase

2/5 3/7 4/9 5/11 6/13
1.7kV IGBT
Figure 5-8 Voltage and power ranges of the selective medium voltage drives (Iph,rms,1 = 600A), (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
105
Table 5-4
The converter specifications for medium voltage converters
Converter specifications for the 2L-VSC Converter line-to-line voltage Ull,rms,1 Apparent converter output power Sc Nominal dc link voltage Udc,n Commutation voltage Ucom = Udc,n Rated device voltage UCE,n 2.3kV 2.4MVA 3383V 3383V 6.5kV IGBT 3600V 0.94 Converter specifications for the 3L-VSCs Converter line-to-line voltage Ull,rms,1 Apparent converter output power Sc Nominal dc link voltage Udc,n Commutation voltage Ucom = Udc,n/2 Rated device voltage UCE,n 2.3kV 2.4MVA 3383V 1691.5V 3.3kV IGBT 1800V 0.94 2.3kV 3383V 1128V 2.5kV IGBT 1200V 0.94 2.3kV 3383V 2 846V 846V 5 9 3.3kV 4853V 1618V 3.3kV IGBT 1800V 0.9 3.3kV 4853V 3 809V 809V 7 13 3.3kV 3.4MVA 4853V 2426.5V 4.5kV IGBT 2250V 1.08 4.16kV 6118V 2039V 4.5kV IGBT 2250V 0.91 4.16kV 6118V 4 765V 765V 9 17 1.7kV IGBT 900V 0.94 0.9 0.85 1.01 0.94 4.16kV 4.3MVA 6118V 3059V 6.5kV IGBT or 23.3kV IGBT 3600V 0.85 6.2kV 9119V 3040V 6.5kV IGBT 3600V 0.84 6.2kV 9119V 5 912V 912V 11 21 6.9kV 10148V 3383V 6.5kV IGBT 3600V 0.94 6.9kV 10148V 6 846V 846V 13 25 3.3kV 3.4MVA 4853V 4853V 24.5kV IGBT 2250V 1.08
Ucom@100FIT Ucom/Ucom@100FIT
Converter line-to-line voltage Ull,rms,1 Apparent converter output power Sc Nominal dc link voltage Udc,n Commutation voltage Ucom = Udc,n/3 Rated device voltage UCE,n
Converter specifications for the 4L-FLC VSC 2.4MVA 3.4MVA 4.3MVA 6.4MVA 7.2MVA
Converter line-to-line voltage Ull,rms,1 Apparent converter output power Sc Nominal dc link voltage Udc,n Number of series connected H-bridges p Dc link voltage of one H-bridge Udc,HB Commutation voltage Ucom = Udc,HB Number of phase voltage level (2p + 1) Number of line-to-line voltage level (4p + 1) Rated device voltage UCE,n
Converter specifications for the SC2LHB VSC 2.4MVA 3.4MVA 4.3MVA 6.4MVA 7.2MVA
6. CONVERTER COMPARISON
This chapter compares 2.3kV, 3.3kV, 4.16kV, and 6kV medium voltage converters on the basis of the 3L-NPC VSC, 3L-FLC VSC, 4L-FLC VSC and 5L-, 7L-, 9L-, and 11L-SC2LHB VSCs topologies applying state-of-the-art 1.7kV, 2.5kV, 3.3kV, 4.5kV, and 6.5kV IGBTs. The design of semiconductors and passive components, the semiconductor loss distribution, converter losses, the installed switch power, and the harmonic spectrum will be compared in detail. 6.1. Comparison of Power Semiconductor Utilization and Loss Distribution Table 6-1 summarizes the design of the power semiconductors for the two carrier frequencies of fC = 450Hz and fC = 1000Hz at a phase current of Iph,rms,1 = 600A and a maximum junction temperature of Tj,max = 125C for converter voltages of 2.3kV, 3.3kV, and 4.16kV in all investigated topologies. The calculated ideal rated IGBT/diode currents IC,n/IF,n (Figure 6-1) guarantee that the junction temperature of the mostly stressed IGBT or diode reaches a value of Tj,max = 125C in one worst case operating point of a four-quadrant operation [20], [25]. To evaluate the converter topologies for a variety of applications, four different comparison cases are discussed in this section. 6.1.1. Comparison at Constant Installed Switch Power and Constant Carrier Frequency In a first step, a constant carrier frequency (fC = 450Hz / 1000Hz) is assumed for all considered converter topologies. The installed switch power SS of the 3L-, 4L-FLC VSCs, and SC2LHB VSCs are equal to that of the 3L-NPC VSC, achieving an output current of 600A in the corresponding output voltage class. This approach allows a comparison of the maximum converter output power SC,max and the semiconductor utilization of the considered converter topologies (Table 6-2). For line-to-line output voltages of 2.3kV, 3.3kV, and 4.16kV, the SC2LHB VSCs enable a maximum converter output power SC,max, which is increased by 12.3%, 8.5%, and 36% in comparison to the corresponding 3L-NPC VSCs (Table 6-2 at fC = 450Hz). The total converter losses, efficiencies, the loss distribution, and the harmonic spectrum of the investigated converter topologies are shown in Figure 6-1 to Figure 6-3, where the installed switch power and the carrier frequency (fC = 450Hz) are constant. Figure 6-1 depicts the total converter losses (on the left) and efficiencies (on the right) as a function of the phase current in the three investigated output voltage classes. These figures show that the 3L-NPC VSCs feature less losses and therefore superior efficiencies, compared to other topologies in the three investigated output voltage classes. The losses of the 5L-SC2LHB VSC are smaller in the entire current range than those of the 3L- and 4L-FLC VSCs, assuming a lineto-line voltage of 2.3kV. The 7L- and 9L-SC2LHB VSCs feature fewer losses up to a phase current 400A for a line-to-line voltage of 3.3kV and 600A for a line-to-line voltage of 4.16kV, compared to the corresponding 3L- and 4L-FLC VSCs. Figure 6-2 shows the loss distribution and the switch utilization of the considered converter topologies if a constant phase current of Iph,rms,1 = 600A and a constant carrier frequency of fC =
108
CONVERTER COMPARISON
450Hz are assumed. It is interesting to note that the converter losses (in the left part of Figure 62) of the 5L-SC2LHB VSC, 4L-FLC VSC, and 3L-FLC VSC are increased by 2.6%, 46.8%, and 12.8%, compared to the 3L-NPC VSC (Ull,rms,1 = 2.3kV, SC = 2.39MVA). Furthermore, the 7L-SC2LHB VSC, 4L-FLC VSC, and 3L-FLC VSC generate 61.5%, 77.7%, and 41.36% more semiconductor losses, compared to the 3L-NPC VSC (SC = 3.43MVA), if a line-to-line output voltage of 3.3kV is applied. For a line-to-line output voltage of 4.16kV the converter losses of the 9L-SC2LHB VSC, 4L-, and 3L-FLC VSCs produce 18.9%, 19.8%, and 42.4% more semiconductor losses, compared to the 3L-NPC VSC (SC = 4.32MVA).
Table 6-1 Power semiconductor design for Iph,rms,1 = 600A, fC = 450Hz / 1000Hz
Converter line-to-line voltage Ull,rms,1 = 2.3kV Dc link voltage Udc,n 3382.8V 3L-NPC 3L-FLC 4L-FLC Converter topology Commutation voltage Ucom = Udc,n Udc,n / 2 Udc,n / 2 Udc,n / 3 / (N-1) 1691.4V 1691.4V 1127.6V Rated device voltage UCE,n Device commutation Ucom@100FIT Ucom/Ucom@100FIT voltage
3.3kV IGBT FZ800R33KF2 1800V 450 [Hz] 0.939 1000 [Hz] 722.8 450 [Hz] 3.3kV IGBT FZ800R33KF2 1800V 0.939 1000 [Hz] 736 450 [Hz] 664 2.5kV IGBT FZ1000R25KF1 1200V 0.939 1000 [Hz] 792
5L-SC2LHB
Udc,n / 4
845.7V 1.7kV IGBT FZ600R17KE3 900V 450 [Hz] 0.939 1000 [Hz] 645 39.47
Rated IGBT current IC,n (IF,n) [A] @ Tj,max = 125C, Iph,rms,1 = 600A
604.8
610.4
609.6 37.31
41.91 50.06 36.26 43.72 44.82 53.46 Installed switch power SS [MVA] Converter line-to-line voltage Ull,rms,1 = 3.3kV Dc link voltage Udc,n 4853.6V 3L-NPC 3L-FLC 4L-FLC Converter topology Commutation voltage Ucom = Udc,n Udc,n / 2 Udc,n / 2 Udc,n / 3 2426.8V 2426.8V 1617.8V / (N-1)
7L-SC2LHB
Udc,n / 6
809V 1.7kV IGBT FZ600R17KE3 900V 0.9 450 1000 [Hz] [Hz] 609 55.91 642 58.93
Rated device voltage UCE,n Ucom@100FIT Ucom/Ucom@100FIT Rated IGBT current IC,n (IF,n) [A]
4.5kV IGBT CM600HB-90H 2250V 1.078 450 1000 [Hz] [Hz]
4.5kV IGBT CM600HB-90H 2250V 1.078 450 1000 [Hz] [Hz]
3.3kV IGBT FZ800R33KF2 1800V 0.9 450 1000 [Hz] [Hz]
1039.2 614.4 642 1014.6 690.6 732 @ Tj,max = 125C, Iph,rms,1 = 600A 60.67 95.88 55.94 84.17 54.74 65.22 Installed switch power SS [MVA] Converter line-to-line voltage Ull,rms,1 = 4.16kV Dc link voltage Udc,n 6118.4V 3L-NPC 3L-FLC 4L-FLC Converter topology Commutation voltage Ucom = Udc,n Udc,n / 2 Udc,n / 2 Udc,n / 3 3059.2V 3059.2V 2039.4V / (N-1)
9L-SC2LHB
Udc,n / 8
765V 1.7kV IGBT FZ600R17KE3 900V 0.85 450 1000 [Hz] [Hz] 607.2 638.4 74.32 78.14
Rated device voltage UCE,n Ucom@100FIT Ucom/Ucom@100FIT Rated IGBT current IC,n (IF,n) [A] @ Tj,max = 125C, Iph,rms,1 = 600A Installed switch power SS [MVA]
6.5kV IGBT FZ600R65KF1 3600V 0.85 450 1000 [Hz] [Hz] 740.4 1152 101.1 157.2
6.5kV IGBT FZ600R65KF1 3600V 0.85 450 1000 [Hz] [Hz] 750.6 1194 87.82 139.7
4.5kV IGBT CM600HB-90H 2250V 0.906 450 1000 [Hz] [Hz] 681 932.4 82.74 113.3
109
Table 6-2
Maximum phase current and apparent converter output power for constant carrier frequency (Iph,rms,1 = 600A, ma = 1.15, cos = 0.9) Converter line-to-line voltage Ull,rms,1 = 2.3kV
3L-NPC
FZ800R33KF2
Converter topology Device part number Carrier frequency fC [Hz] Installed switch power SS [MVA] Rated IGBT current IC,n (IF,n) [A]
3L-FLC
FZ800R33KF2
4L-FLC
FZ1000R25KF1
5L-SC2LHB
FZ600R17KE3
450 41.91 604.8
1000 50.06 722.4
450 41.91 705.5
1000 50.06 842.8
450 41.91 620.8
1000 50.06 845.8
450 41.9 1 684. 8 1800 674 2.68 112. 3 20.1 0.44
1000 50.06 818 4000 761 3.03 126.8 20.3 0.19
Frequency of the first harmonics 450 1000 900 2000 1350 3000 carrier band f1Cb [Hz] Maximum phase current Iph,max [A] 600 600 693.5 687 561 561.8 @ Tj,max = 125C Maximum apparent converter 2.39 2.39 2.76 2.73 2.23 2.24 output power SC,max [MVA] Relative apparent converter output 100 100 115.5 114.5 93.3 93.6 power SCR [%] 26.86 29.5 28.9 20.4 20.4 Total harmonic distortion THD [%] 22.5 Weighted total harmonic 1.49 1.02 1.48 0.46 0.47 0.22 distortion WTHD [%] Converter line-to-line voltage Ull,rms,1 = 3.3kV 3L-NPC 3L-FLC 4L-FLC Converter topology CM600HB-90H CM600HB-90H FZ800R33KF2 Device part number 450 1000 450 1000 450 1000 Carrier frequency fC [Hz] 60.67 95.88 60.67 95.88 60.67 95.88 Installed switch power SS [MVA] 642 1014.6 749 1183.7 681 1076 Rated IGBT current IC,n (IF,n) [A] Frequency of the first harmonics 450 1000 900 2000 1350 3000 carrier band f1Cb [Hz] Maximum phase current Iph,max [A] 600 600 650.7 683.4 665 882 @ Tj,max = 125C Maximum apparent converter 3.43 3.43 3.72 3.91 3.8 5.04 output power SC,max [MVA] Relative apparent converter output 100 100 108.5 113.8 110.8 147 power SCR [%] 22.5 26.86 29.5 28.9 20.4 20.4 THD [%] 1.49 1.02 1.48 0.46 0.47 0.22 WTHD [%] Converter line-to-line voltage Ull,rms,1 = 4.16kV 3L-NPC 3L-FLC 4L-FLC Converter topology CM600HB-90H FZ600R65KF1 FZ600R65KF1 Device part number 450 1000 450 1000 450 1000 Carrier frequency fC [Hz] 101.1 157.2 101.1 157.2 101.1 157.2 Installed switch power SS [MVA] 740.4 1152 863.7 1344 832 1294 Rated IGBT current IC,n (IF,n) [A] Frequency of the first harmonics 450 1000 900 2000 1350 3000 carrier band f1Cb [Hz] Maximum phase current Iph,max [A] 600 600 690.5 675.4 732.8 832.8 @ Tj,max = 125C Maximum apparent converter 4.32 4.32 4.97 4.86 5.28 6 output power SC,max [MVA] Relative apparent converter output 100 100 115 112.6 122.2 138.8 power SCR [%] 22.5 26.86 29.5 28.9 20.4 20.4 THD [%] 1.49 1.02 1.48 0.46 0.47 0.22 WTHD [%]
7L-SC2LHB
FZ600R17KE3
450 60.67 660.8 2700 651 3.72 108.5 15.3 0.23
1000 95.88 1044 6000 976.1 5.57 162.4 15.3 0.1
9L-SC2LHB
FZ600R17KE3
450 101.1 825.8 3600 815.8 5.88 136 9.5 0.1
1000 157.2 1285 8000 1207 8.69 201.2 9.5 0.05
110
Converter semiconductor losses [kW]
60 50 40 30 20 10 0 200 400 600 Phase current [A] 800 1000 3L-NPC 3L-FLC 4L-FLC 5L-SC2LHB
100 3L-NPC 3L-FLC 4L-FLC 5L-SC2LHB
Efficiency [%]
99.5
99
98.5
200
400 600 Phase current [A]
800
1000
(a) Ull,rms,1 = 2.3kV

Converter semiconductor losses [kW] 60 50 40 30 20 10 0 200 400 600 Phase current [A] 800 1000 98.5 200 400 600 Phase current [A] 800 1000 3L-NPC 3L-FLC 4L-FLC 7L-SC2LHB 100 3L-NPC 3L-FLC 4L-FLC 7L-SC2LHB
Efficiency [%]
99.5
99
(b) Ull,rms,1 = 3.3kV

Converter semiconductor losses [kW] 80 70 60 50 40 30 20 10 0 200 400 600 Phase current [A] 800 1000 98.5 200 400 600 Phase current [A] 800 1000 3L-NPC 3L-FLC 4L-FLC 9L-SC2LHB 100 3L-NPC 3L-FLC 4L-FLC 9L-SC2LHB
Efficiency [%]
99.5
99
(c) Ull,rms,1 = 4.16kV

Figure 6-1 Converter semiconductor losses and efficiencies as functions of the phase current for the investigated output voltage classes (fC = 450Hz, ma = 1.15, cos = 0.9): (a) Ull,rms,1 = 2.3kV, (b) Ull,rms,1 = 3.3kV, and (c) Ull,rms,1 = 4.16kV (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
The switching losses of the 3L-FLC VSC are higher than that of the 3L-NPC VSC in the three considered output voltage classes (by 121% for 2.3kV, 127% for 3.3kV, and 115% for 4.16kV). Furthermore, the switching losses of the 4L-FLC VSC are increased by 145.6% (for 2.3kV), 58.6% (for 3.3kV), and 65.7% (for 4.16kV), compared to the corresponding 3L-NPC VSCs. In
111
contrast, the switching losses of the 5L-, 7L-, and 9L-SC2LHB VSC topologies are significantly lower than that of the 3L-NPC VSCs in all considered output voltage classes (by 10% for 2.3kV, 38% for 3.3kV, and 56% for 4.16kV), since the 1.7kV IGBTs generate distinctly less switching losses than the 3.3kV, 4.5kV, and 6.5kV IGBTs at their corresponding commutation voltage. The conduction losses of the 4L-FLC VSC occurring at line-to-line output voltages of 2.3kV and
Semiconductor loss distributions [kW] 45 40 35 30 25 P conT P conD P onT P offD
SCR [%] 120 100
=98.84% =99.11% =99.19%
115.6% 100% 93.5%
112.3%
P offT
80 60 40 20
20 =99.21% 15 10 5 0 3L-NPC
3L-FLC
4L-FLC
5L-SC2LHB
3L-NPC
3L-FLC
4L-FLC 5L-SC2LHB

Semiconductor loss distributions [kW] 50 P conT 40 30 P conD P onT P offT P offD =99.25% 20 =99.47% 10 0
=99.06% =99.14%
120 100 80 SCR [%] 60 40 20 3L-NPC 3L-FLC 4L-FLC 7L-SC2LHB 0 3L-NPC 100%
108.4%
110.8%
108.5%
3L-FLC
4L-FLC 7L-SC2LHB

Semiconductor loss distributions [kW] 70 60 50 40 P conT P conD P onT P offD
=99.17% =99.18%
150 136.0% 115.1% 100 SCR [%]

=99.02%
122.2%
100%
P offT
30 =99.31% 20 10 0 3L-NPC 3L-FLC
50
4L-FLC
9L-SC2LHB
3L-NPC
3L-FLC
4L-FLC 9L-SC2LHB

Figure 6-2 Converter semiconductor loss distribution at constant carrier frequency (fC = 450Hz, ma = 1.15, cos = 0.9, Iph,rms,1 = 600A): (a) Ull,rms,1 = 2.3kV, (b) Ull,rms,1 = 3.3kV, (c) Ull,rms,1 = 4.16kV (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
112
3.3kV are increased by 27% and 88% while decreased by 11.7% for 4.16kV, compared to the corresponding 3L-NPC VSCs. The right part of Figure 6-2 shows that the SC2LHB VSCs and the FLC VSCs feature higher converter switch utilization than the 3L-NPC VSC, as a reference in the three investigated output voltage classes, while the converter switch utilization of the 4L-FLC VSC is decreased by 6.5% if a line-to-line output voltage of 2.3kV is applied. Figure 6-3 illustrates that the first carrier band of the line-to-line output voltage of the 3L-NPC VSC occurs around the carrier frequency of fC = 450Hz. In contrast, the first carrier band of the line-to-line output voltage of the 3L-FLC VSC, 4L-FLC VSC, 5L-, 7L-, and 9L-SC2LHB VSC is centred around two, three, four, six, and eight times the carrier frequency. Hence, an output filter of the SC2LHB VSCs could be smaller than the corresponding filters of other topologies. The THD decreases when the number of levels increases. The WTHD of the 9L-SC2LHB VSC is clearly lower than that of other topologies due to the nine-level characteristic of the output voltage. Assuming a constant carrier frequency (fC = 450Hz), the WTHD of the 3L-NPC VSC (1.49%) is almost three, three, five, and fifteen times larger than that of the 4L-FLC VSC, 5LSC2LHB VSC, 7L-SC2LHB VSC, and 9L-SC2LHB VSC respectively (Table 6-2). It is important to note that the above-mentioned differences of the output voltage THD and WTHD are primarily caused by the circuit configurations.
10 10 Normalized line-to-line voltage 10 10 10 10 10 10 10
0
10
3L-NPC
5L-SC2LHB
-1
10 Normalized line-to-line voltage 10 10 10 10 10 10 10
-1
-2 0
-2 0
3
3L-FLC
3
7L-SC2LHB
-1
-1
-2 0
-2 0
3
4L-FLC
3
9L-SC2LHB
-1
-1
-2
-2
2 3 Frequency [kHz]
2 3 Frequency [kHz]
Figure 6-3 Harmonic spectrum of line-to-line output voltage at constant carrier frequency (fC = 450Hz, fo = 50Hz, ma = 1.15, f1Cb,3L-NPC = 450Hz, f1Cb,3L-FLC = 900Hz, f1Cb,4L-FLC = 1350Hz, f1Cb,5L-SC2LHB = 1800Hz, f1Cb,7L-SC2LHB = 2700Hz, f1Cb,9L-SC2LHB = 3600Hz) (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
6.1.2. Comparison of Maximum Carrier Frequency at Constant Installed Switch Power and Constant Apparent Converter Output Power In the second step, a constant installed switch power SS (which is a measure for the expense of semiconductors) as well as an equal output current (Iph,rms,1 = 600A) and constant converter output power SC are assumed (Table 6-3) to calculate the maximum carrier frequency of the considered converter topologies.
113
Table 6-3
Maximum carrier frequency for constant apparent converter output power and constant installed switch power (Iph,rms,1 = 600A, ma = 1.15, cos = 0.9)
5L-SC2LHB
FZ600R17KE3
Converter line-to-line voltage Ull,rms,1 = 2.3kV 3L-NPC 3L-FLC 4L-FLC Converter topology FZ1000R25KF1 FZ800R33KF2 FZ800R33KF2 Device part number 450 1000 450 1000 450 1000 Carrier frequency fC [Hz] 41.91 50.06 41.91 50.06 41.91 50.06 Installed switch power SS [MVA] 604.8 722.4 705.5 842.8 620.8 845.8 Rated IGBT current IC,n (IF,n) [A] 600 600 600 600 600 600 Phase current Iph,rms,1 [A] Maximum apparent converter 2.39 2.39 2.39 2.39 2.39 2.39 output power SC,max [MVA] Maximum carrier frequency fC,max 1000 880 1410 250 1240 [Hz], @ Tj,max = 125C, Iph,rms,1 = 450 600A Frequency of the first harmonics 450 1000 1760 2820 750 3720 carrier band f1Cb [Hz] 26.86 29.5 29.6 20 20.2 Total harmonic distortion THD [%] 22.5 Weighted total harmonic 1.49 1.02 0.53 0.32 0.84 0.27 distortion WTHD [%] Converter line-to-line voltage Ull,rms,1 = 3.3kV 3L-NPC 3L-FLC 4L-FLC Converter topology CM600HB-90H CM600HB-90H FZ800R33KF2 Device part number 450 1000 450 1000 450 1000 Carrier frequency fC [Hz] 60.67 95.88 60.67 95.88 60.67 95.88 Installed switch power SS [MVA] 642 1014.6 749 1183.7 681 1076 Rated IGBT current IC,n (IF,n) [A] 600 600 600 600 600 600 Phase current Iph,rms,1 [A] Maximum apparent converter 3.43 3.43 3.43 3.43 3.43 3.43 output power SC,max [MVA] Maximum carrier frequency fC,max 1000 635 1160 790 2210 [Hz], @ Tj,max = 125C, Iph,rms,1 = 450 600A Frequency of the first harmonics 450 1000 1270 2320 2370 6630 carrier band f1Cb [Hz] 26.86 29.5 29.6 20 20.2 Total harmonic distortion THD [%] 22.5 Weighted total harmonic 1.49 1.02 0.76 0.39 0.46 0.27 distortion WTHD [%] Converter line-to-line voltage Ull,rms,1 = 4.16kV 3L-NPC 3L-FLC 4L-FLC Converter topology CM600HB-90H FZ600R65KF1 FZ600R65KF1 Device part number 450 1000 450 1000 450 1000 Carrier frequency fC [Hz] 101.1 157.2 101.1 157.2 101.1 157.2 Installed switch power SS [MVA] 740.4 1152 863.7 1344 832 1294 Rated IGBT current IC,n (IF,n) [A] 600 600 600 600 600 600 Phase current Iph,rms,1 [A] Maximum apparent converter 4.32 4.32 4.32 4.32 4.32 4.32 output power SC,max [MVA] Maximum carrier frequency fC,max 1000 595 1180 850 1490 [Hz], @ Tj,max = 125C, Iph,rms,1 = 450 600A Frequency of the first harmonics 450 1000 1190 2360 2550 4470 carrier band f1Cb [Hz] 22.5 26.86 29.5 29.6 20 20.2 THD [%] 1.49 1.02 0.8 0.38 0.22 0.22 WTHD [%]
450 41.91 684.8 600 2.39 1585 6340 20.6 0.12
1000 50.06 818 600 2.39 3050 12200 20.8 0.07
7L-SC2LHB
FZ600R17KE3
450 60.67 660.8 600 3.43 1300 7800 15.3 0.078
1000 95.88 1044 600 3.43 5250 31500 15.5 0.024
9L-SC2LHB
FZ600R17KE3
450 101.1 825.8 600 4.32 3450 27600 9.5 0.02
1000 157.2 1285 600 4.32 7700 61600 9.5 0.05
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The installed switch powers of all topologies are equal to those of the 3L-NPC VSC (Table 6-2) including NPC diodes. According to section 6.1.1, the maximum switching frequency results from the losses and junction temperatures of the mostly stressed devices (Tj,max = 125C) at critical operating points. Table 6-3 shows that the SC2LHB VSCs enables a higher maximum carrier frequency than the other investigated topologies. Figure 6-4 depicts the total converter losses (on the left) and efficiencies (on the right) as a function of the carrier frequency in the three investigated output voltage classes. These figures demonstrate that the 5L-, 7L-, and 9L-SC2LHB VSC feature less losses and therefore high efficiencies, compared to the 3L-NPC VSCs, for a carrier frequency beyond 1000Hz, 2290Hz, and 790Hz respectively. Figure 6-5 depicts the power loss distribution and the maximum possible carrier frequencies for a constant apparent converter output power in the three investigated output voltage classes. Assuming a nominal phase current of Iph,rms,1 = 600A, the converter losses of the 5L-, 7L-, and 9L-SC2LHB VSC are increased by 42%, 105%, and 126% at the maximum carrier frequency in comparison to that of the 3L-NPC VSC. It is obvious that the 9L-SC2LHB VSC has the maximum converter losses at the maximum possible carrier frequencies and a line-to-line output voltage 4.16kV, compared to the other topologies. The switching and conduction losses of the 5L-, 7L-, and 9L-SC2LHB VSC are higher than that of the corresponding 3L-NPC VSCs (by 227% and 5% for 2.3kV, 83% and 117% for 3.3kV, and 207% and 70% for 4.16kV). It is interesting to note that the 5L-, 7L-, and 9L-SC2LHB VSC clearly realize the maximum carrier frequencies in the three investigated output voltage classes. The harmonic spectra of the line-to-line output voltage of the considered converters are shown in Figure 6-6 to Figure 6-8. The maximum carrier frequencies of the 3L-FLC VSCs are increased by factors of 1.95 (880Hz for 2.3kV), 1.4 (635Hz for 3.3kV), and 1.32 (595Hz for 4.16kV), compared to those of the 3L-NPC VSCs (fC,max = 450Hz). On the other hand, the maximum carrier frequency of the 4L-FLC VSC are increased by factors of 1.75 (790Hz for 3.3kV) and 1.88 (850Hz for 4.16kV), compared to those of the 3L-NPC VSCs (fC,max = 450Hz), whereas it is decreased by factors of 0.45 (250Hz for 2.3kV) (Table 6-3). Furthermore, the maximum carrier frequencies of the 5L-SC2LHB VSC (fC,max = 1585Hz), 7L-SC2LHB VSC (fC,max = 1300Hz), and 9L-SC2LHB VSC (fC,max = 3450Hz) are increased by factors of 3.5, 2.88, and 7.8, compared to those of the 3L-NPC VSCs (Table 6-3). The first carrier band of the line-to-line voltage of the 4L-FLC VSC occurs around three times (f1Cb = 3fC) the carrier frequencies (750Hz for 2.3kV, 2370Hz for 3.3kV, and 2550Hz for 4.16kV). The first carrier band of the line-to-line voltage of the 5L-, 7L-, and 9L-SC2LHB VSCs occur around 6.34kHz, 7.8kHz, and 27.6kHz respectively, whereas the first carrier band generated by the 3L-NPC VSC occurs around the carrier frequency fC = 450Hz (Figure 6-8). Thus, for the three considered output voltage classes, the SC2LHB VSCs enable substantially reduced sine output filters, compared to those of the 3L-NPC VSCs and both flying capacitor topologies. Comparing the WTHD at the maximum possible carrier frequency, the 9L-SC2LHB VSC features the minimum value of 0.02% since the harmonics of the first carrier band (f1Cb = 27.8kHz) are strongly damped. The WTHD of the 5L-SC2LHB VSC (0.12%) and the 7LSC2LHB VSC (0.078%) are about 95% and 92% smaller than that of the 3L-NPC VSC (1.49%) since the first harmonics of the 5L-SC2LHB VSC and the 7L-SC2LHB VSC occur at four (f1Cb = 4fC) and six (f1Cb = 6fC) times the carrier frequency, compared to those of the 3L-NPC VSC (f1Cb = fC).
115
60 50 40 30 20 10 0 500 1000 1500 Frequency [Hz] 2000 2500 3L-NPC 3L-FLC 4L-FLC 5L-SC2LHB
100 99 Efficiency [%] 98 97 96 95
3L-NPC 3L-FLC 4L-FLC 5L-SC2LHB 500 1000 1500 Frequency [Hz] 2000 2500

Converter semiconductor losses [kW] 100 80 60 40 20 0 3L-NPC 3L-FLC 4L-FLC 7L-SC2LHB 100 99 Efficiency [%] 98 97 96 95
500
1000 1500 Frequency [Hz]
2000
2500

Converter semiconductor losses [kW] 150 3L-NPC 3L-FLC 4L-FLC 9L-SC2LHB 100 99 Efficiency [%] 98 97 96 0 95
100
50
500
2000
2500

Figure 6-4 Converter semiconductor losses and efficiencies as functions of the carrier frequency for the investigated output voltage classes: (a) Ull,rms,1 = 2.3kV, (b) Ull,rms,1 = 3.3kV, and (c) Ull,rms,1 = 4.16kV (fC = 450Hz, Iph,rms,1 = 600A, ma = 1.15, cos = 0.9) (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
116
Semiconductor losses distributions [kW]
45 40 35 30 25 P conT P conD P offT =98.82% =98.88% =98.98% P offD fC,max / fC [%] P onT
400 352.2% 300
200
195.6%
20 =99.21% 15 10 5 0 3L-NPC 3L-FLC 4L-FLC 5L-SC2LHB
100
100% 55.6%
3L-NPC
3L-FLC
4L-FLC 5L-SC2LHB

50 Power loss distributions [kW] PconT 40 30 PconD PonT PoffT PoffD 20 =99.47% 10 0 0
=99.04% =98.82% =98.91%
350 300 fC,max / fC [%] 288.9%
200 141.1% 100 100%
175.6%
3L-NPC
3L-FLC
4L-FLC 7L-SC2LHB
3L-NPC
3L-FLC
4L-FLC 7L-SC2LHB

Semiconductor losses distributions [kW] 70 60 50 40 P conT P conD P onT P offT P offD
=98.81% =98.78% =98.45%
800
766.7%
fC,max / fC [%]
600
30 =99.31% 20 10 0 3L-NPC 3L-FLC 4L-FLC 9L-SC2LHB
400
200 100% 0 3L-NPC
188.9% 132.2%
3L-FLC
4L-FLC 9L-SC2LHB

Figure 6-5 Converter semiconductor loss distribution at maximum carrier frequency (fo = 50Hz, ma = 1.15, cos = 0.9, Iph,rms,1 = 600A, fC = 450Hz), (fC,3L-NPC = 450Hz, fC,3LFLC,2.3kV = 880Hz, fC,3L-FLC,3.3kV = 635Hz, fC,3L-FLC,4.16kV = 595Hz, fC,4L-FLC,2.3kV = 250Hz, fC,4L-FLC,3.3kV = 790Hz, fC,4L-FLC,4.16kV = 850Hz, fC,5L-SC2LHB = 1585Hz, fC,7L-SC2LHB = 1300Hz, fC,9L-SC2LHB =3450Hz) (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
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10 10 Normalized line-to-line voltage 10 10 10 10 10 10 10 10 10 10
0 -1 -2 0 -1 -2 0 -1 -2 0 -1 -2
3L-NPC
6 3L-FLC
6 4L-FLC
6 5L-SC2LHB
2 4 Frequency [kHz]
Figure 6-6 Harmonic spectrum of line-to-line voltage at maximum carrier frequency (f1Cb,3L-NPC = 450Hz, f1Cb,3L-FLC,2.3kV = 1760Hz, f1Cb,4L-FLC,2.3kV = 750Hz, f1Cb,5L-SC2LHB = 6340Hz, fo = 50Hz, fC = 450Hz, ma = 1.15, cos = 0.9, Iph,rms,1 = 600A) (3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
0 -1 -2 0 -1 -2 0 -1 -2 0 -1 -2
3L-NPC
3L-FLC
4L-FLC
7L-SC2LHB
3 4 5 6 Frequency [kHz]
Figure 6-7 Harmonic spectrum of line-to-line voltage at maximum carrier frequency (f1Cb,3L-NPC = 450Hz, f1Cb,3L-FLC,3.3kV = 1270Hz, f1Cb,4L-FLC,3.3kV = 2370Hz, f1Cb,7L-SC2LHB = 7800Hz, fo = 50Hz, fC = 450Hz, ma = 1.15, cos = 0.9, Iph,rms,1 = 600A) (4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 1.7kV/600A: FZ600R17KE3)
118
0 -1 -2 0 -1 -2 0 -1 -2 0 -1 -2
3L-NPC
10
20 3L-FLC
30
10
20 4L-FLC
30
10
20
30
9L-SC2LHB
10 20 Frequency [kHz]
30
Figure 6-8 Harmonic spectrum of line-to-line voltage at maximum carrier frequency (f1Cb,3L-NPC = 450Hz, f1Cb,3L-FLC,4.16kV = 1190Hz, f1Cb,4L-FLC,4.16kV = 2550Hz, f1Cb,9L-SC2LHB = 27600Hz, fo = 50Hz, fC = 450Hz, ma = 1.15, cos = 0.9, Iph,rms,1 = 600A) (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 1.7kV/600A: FZ600R17KE3)
6.1.3. Comparison of Converter Power and Loss Distribution at Constant Installed Switch Power and Constant Frequency of the First Carrier Band The conditions for the third comparison are constant installed switch power SS and constant frequency of the first harmonic carrier band f1Cb. To place the first harmonic carrier band at the frequency occurring in the 3L-NPC VSC (f1Cb = fC = 450Hz), the carrier frequencies of the different topologies have to be reduced (Table 6-4). This approach allows a comparison of the converter output power and the losses of the considered converter topologies. If the first harmonic carrier band occurs around the same frequency, the design of an output filter of about the same size and cost range is enabled. The maximum apparent converter output powers SC,max of the 5L-, 7L-, and 9L-SC2LHB VSCs are increased by 15%, 10.5%, and 37%, in comparison to the 3L-NPC VSC (Table 6-4). Figure 6-9 shows the total converter losses and efficiencies as a function of the phase current and Figure 6-10 illustrates the power loss distribution and the converter switch utilization of the investigated topologies whereas the installed switch power and the frequency of the first harmonics carrier band are constant (f1Cb = fC = 450Hz). The losses of the 5L SC2LHB VSC are smaller in the entire current range (left part of Figure 6-9) and therefore its efficiency is higher (right part of Figure 6-9), compared to that of the corresponding 3L-NPC VSC, assuming a lineto-line output voltage of 2.3kV. In contrast, the 7L- and 9L SC2LHB VSCs feature fewer losses at a phase current of up to 213A and 518A than the corresponding 3L-NPC VSC. The semiconductor losses of the 4L-FLC VSC are larger in the entire current range for a line-to-line output voltage of 2.3kV, compared to those of the corresponding 3L-NPC VSC. Assuming a nominal phase current of Iph,rms,1 = 600A, the 5L-, 7L-, and 9L-SC2LHB VSCs feature 8.4% lower, 44.2%, and 3.3% higher losses, compared to the corresponding 3L-NPC VSCs (Figure 6-10).
119
Table 6-4
Maximum phase current and apparent converter output power for the constant carrier frequency of the first carrier band and installed switch power (Iph,rms,1 = 600A, f1Cb = 450Hz / 1000Hz, ma = 1.15, cos = 0.9) Converter line-to-line voltage Ull,rms,1 = 2.3kV
5L-SC2LHB
FZ600R17KE3
3L-NPC 3L-FLC 4L-FLC Converter topology FZ1000R25KF1 FZ800R33KF2 FZ800R33KF2 Device part number Frequency of the first harmonics 450 1000 450 1000 450 1000 carrier band f1Cb [Hz] 41.91 50.06 41.91 50.06 41.91 50.06 Installed switch power SS [MVA] 604.8 722.4 705.5 842.8 620.8 845.8 Rated IGBT current IC,n (IF,n) [A] 450 1000 225 500 150 333.3 Carrier frequency fC [Hz] Maximum phase current Iph,max [A] 600 600 750 816 621 804 @ Tj,max = 125C Maximum apparent converter 2.39 2.39 2.98 3.25 2.47 3.2 output power SC,max [MVA] Relative apparent converter output 100 100 124.7 136 103.3 133.9 power SCR [%] 26.86 29.5 29.5 20 20.1 Total harmonic distortion THD [%] 22.5 Weighted total harmonic 1.49 1.02 1.6 1.06 1.45 0.82 distortion WTHD [%] Converter line-to-line voltage Ull,rms,1 = 3.3kV 3L-NPC 3L-FLC 4L-FLC Converter topology CM600HB-90H CM600HB-90H FZ800R33KF2 Device part number Frequency of the first harmonics 450 1000 450 1000 450 1000 carrier band f1Cb [Hz] 60.67 95.88 60.67 95.88 60.67 95.88 Installed switch power SS [MVA] 642 1014.6 749 1183.7 681 1076 Rated IGBT current IC,n (IF,n) [A] 450 1000 225 500 150 333.3 Carrier frequency fC [Hz] Maximum phase current Iph,max [A] 600 600 717 1005 715 1086 @ Tj,max = 125C Maximum apparent converter 3.43 3.43 4.09 5.74 4.08 6.2 output power SC,max [MVA] Relative apparent converter output 100 100 119.2 167.3 118.9 180.7 power SCR [%] 22.5 26.86 29.5 29.5 20 20.1 THD [%] 1.49 1.02 1.6 1.06 1.45 0.82 WTHD [%] Converter line-to-line voltage Ull,rms,1 = 4.16kV 3L-NPC 3L-FLC 4L-FLC Converter topology CM600HB-90H FZ600R65KF1 FZ600R65KF1 Device part number Frequency of the first harmonics 450 1000 450 1000 450 1000 carrier band f1Cb [Hz] 101.1 157.2 101.1 157.2 101.1 157.2 Installed switch power SS [MVA] 740.4 1152 863.7 1344 832 1294 Rated IGBT current IC,n (IF,n) [A] 450 1000 225 500 150 333.3 Carrier frequency fC [Hz] Maximum phase current Iph,max [A] 600 600 885 1020 801 1188 @ Tj,max = 125C Maximum apparent converter 4.32 4.32 6.37 7.35 5.77 8.56 output power SC,max [MVA] Relative apparent converter output 100 100 147.4 170 133.6 198 power SCR [%] 22.5 26.86 29.5 29.5 20 20.1 THD [%] 1.49 1.02 1.6 1.06 1.45 0.82 WTHD [%]
450 41.91 684.8 112.5 689 2.75 115 21.6 1.2
1000 50.06 818 250 806 3.21 134.3 20.8 0.92
7L-SC2LHB
FZ600R17KE3
450 60.67 660.8 75 664 3.79 110.5 15.3 1.1
1000 95.88 1044 166.7 1046 5.98 174.3 15.9 1.02
9L-SC2LHB
FZ600R17KE3
450 101.1 825.8 56.25 821 5.92 137 9.5 0.98
1000 157.2 1285 125 1316 9.48 219.4 10.5 0.79
120
50 40 30 20 10 0 3L-NPC 3L-FLC 4L-FLC 5L-SC2LHB
100 3L-NPC 3L-FLC 4L-FLC 5L-SC2LHB
Efficiency [%] 800 1000
99.5
99
200
98.5
200
800
1000

Converter semiconductor losses [kW] 60 50 40 30 20 10 0 200 400 600 Phase current [A] 800 1000 98.5 200 400 600 Phase current [A] 800 1000 3L-NPC 3L-FLC 4L-FLC 7L-SC2LHB 100 3L-NPC 3L-FLC 4L-FLC 7L-SC2LHB
Efficiency [%]
99.5
99

Converter semiconductor losses [kW] 70 60 50 40 30 20 10 0 200 400 600 Phase current [A] 800 1000 98.5 200 400 600 Phase current [A] 800 1000 3L-NPC 3L-FLC 4L-FLC 9L-SC2LHB 100 3L-NPC 3L-FLC 4L-FLC 9L-SC2LHB
Efficiency [%]
99.5
99
Figure 6-9 Converter semiconductor losses as functions of the phase current for the investigated output voltage classes: (a) Ull,rms,1 = 2.3kV, (b) Ull,rms,1 = 3.3kV, and (c) Ull,rms,1 = 4.16kV (fC,3L-NPC = 450Hz, fC,3L-FLC = 225Hz, fC,4L-FLC = 150Hz, fC,5L-SC2LHB = 112.5Hz, fC,7L-SC2LHB = 75Hz, fC,9L-SC2LHB = 56.25Hz, fo = 50Hz, f1Cb = 450Hz, ma = 1.15, cos = 0.9, Iph,rms,1 = 600A), (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
121
Semiconductor loss distributions [kW]
45 40 35 30 25 P conT P conD P onT SCR [%] P offT P offD

=99.04% =99.27%
140 125% 120 100 80 60 40 20 3L-NPC 3L-FLC 4L-FLC 5L-SC2LHB 0 3L-NPC 3L-FLC 4L-FLC 5L-SC2LHB 100% 103.5% 114.8%
20 =99.21% =99.25% 15 10 5 0

Semiconductor loss distributions [kW] 45 40 35 30 25 20 15 10 5 0 3L-NPC 3L-FLC 4L-FLC 7L-SC2LHB 20 0 3L-NPC 3L-FLC 4L-FLC 7L-SC2LHB P conT P conD P onT P offD
=99.47% =99.46%
120 100 SCR [%]

=99.24% =99.23%
119.5% 100%
119.2% 110.7%
P offT
80 60 40

Semiconductor loss distributions [kW] 60 P conT 50 40 30 =99.31% =99.31% 20 10 0 3L-NPC 3L-FLC 4L-FLC 9L-SC2LHB P conD P onT P offD
=99.46% =99.29%
160 140 120 SCR [%] 100 80 60 40 20 0 3L-NPC 100%
147.5% 133.5% 136.8%
P offT
3L-FLC
4L-FLC 9L-SC2LHB

Figure 6-10 Converter semiconductor loss distribution at constant frequency of the first carrier band (fC = f1Cb = 450Hz, ma = 1.15, cos = 0.9, Iph,rms,1 = 600A): (a) Ull,rms,1 = 2.3kV, (b) Ull,rms,1 = 3.3kV, (c) Ull,rms,1 = 4.16kV (fC,3L-NPC = 450Hz, fC,3L-FLC = 225Hz, fC,4L-FLC = 150Hz, fC,5L-SC2LHB = 112.5Hz, fC,7L-SC2LHB = 75Hz, fC,9L-SC2LHB = 56.25Hz, fo = 50Hz, f1Cb = 450Hz, ma = 1.15, cos = 0.9, Iph,rms,1 = 600A), (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
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The switching losses of the 5L-, 7L-, and 9L-SC2LHB VSCs are significantly lower than those of the 3L-NPC VSC (76% for 2.3kV, 88% for 3.3kV, and 94% for 4.16kV), since the 1.7kV IGBTs generate distinctly less switching losses than the 2.5kV, 3.3kV, 4.5kV, and 6.5kV IGBTs at their corresponding commutation voltage. On the other hand, the conduction losses of the 5L-, 7L-, and 9L-SC2LHB VSCs are increased by 5% for 2.3kV, 118% for 3.3kV, and 70% for 4.16kV, compared to the corresponding 3L-NPC VSC topologies. For a line-to-line output voltage of 2.3kV, the 4L-FLC VSC features the highest losses and the lowest converter output power, whereas the 7L- and 9L-SC2LHB VSCs have the maximum value for line-to-line output voltages of 3.3kV and 4.16kV respectively. The 3L-FLC VSC enables the maximum converter switch utilization, compared to that of the corresponding 3L-NPC VSCs in the three investigated output voltage classes, as shown in the right part of Figure 6-10. Furthermore, both three-level topologies provide the poorest THD and WTHD (Table 6-4). Both the THD and the WTHD of the 9L-SC2LHB VSC are clearly the smallest, since the distortion of the output voltage is at a minimum due to the applied nine levels. The harmonic spectra of the converters are shown in Figure 6-11. The first carrier band of all investigated topologies occurs at about the first harmonic carrier band f1Cb.
0
0
10
3L-NPC
-1
5L-SC2LHB 10 Normalized line-to-line voltage 10 10 10 10 10 10 10

-1
-2 0 0
-2 0
500
1000
1500 3L-FLC
2000
500
1000
1500 7L-SC2LHB
2000
-1
-1
-2 0 0
-2 0
500
1000
1500 4L-FLC
2000
500
1000
1500 9L-SC2LHB
2000
-1
-1
-2
-2
500
2000
500
2000
Figure 6-11 Harmonic spectrum of line-to-line voltage at constant frequency of the first carrier band (fC,3L-NPC = 450Hz, fC,3L-FLC = 225Hz, fC,4L-FLC = 150Hz, fC,5L-SC2LHB = 112.5Hz, fC,7LSC2LHB = 75Hz, fC,9L-SC2LHB = 56.25Hz, fo = 50Hz, f1Cb = 450Hz, ma = 1.15, cos = 0.9, Iph,rms,1 = 600A), (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
Figure 6-12 shows the junction temperatures of IGBTs and diodes of one phase leg of the investigated topologies. It is apparent that all IGBTs and diodes reach their maximum junction temperature at the critical operating point 2, see Table 5-1. Figure 6-12a demonstrates that the junction temperatures of a 3L-NPC VSC are not equally distributed, unlike in the other topologies (Figure 6-12b through Figure 6-12d). This non-
123
equality leads to the maximum junction temperature to the outer IGBTs (T2 and 1 ). Obviously both switches are subject to switching losses as well as substantial conduction losses at a large modulation index and unity power factor. In contrast, the inner switches (T1 and 2 ) cause only conduction losses at this operating point. Since there are no conduction and switching losses in the inverse diodes, the sum of conduction and switching losses and thus the junction temperatures of the NPC diodes (D2, D1) are larger than those of the inner inverse diodes ( DT1 ,DT2 ).
Junction Temperature [C]
120 100 80 60 40 20 0
3 L-N P C
120 100 80 60 40 20
3 L-F LC
T2
T1
T2
T1 DT 2 DT 1 DT 2 DT 1 D2 D1
4 L-F LC
T2
T1
T1
T2
DT 2
DT 1 DT 1
DT 2
Junction Temperature [C]
120 100 80 60 40 20 0
120 100 80 60 40 20
9 L-SC 2 LH B
T3 T2 T1
T1 T2 T3 DT 3 DT 2 DT 1 DT 1 DT 2 DT 3
TL
TL
TR
TR
DL
DL
DR
DR
Figure 6-12 Average junction temperature of IGBTs and diodes (Udc,n = 6118V, ma = 1.15, cos = 1, Th = 80C): (a) 3L-NPC VSC (Eupec 6.5kV/740.4A IGBT, Iph,max = 600A, SC = 4.32MVA, fC = 450Hz), (b) 3L-FLC VSC (Eupec 6.5kV/863.4A IGBT, Iph,max = 919A, SC = 6.62MVA, fC = 225Hz), (c) 4L-FLC VSC (Mitsubishi 4.5kV/832A IGBT, Iph,max = 1061A, SC = 7.64MVA, fC = 150Hz), (d) 9L-SCHB VSC (Eupec 1.7kV/825.8A IGBT, Iph,max = 891A, SC = 6.42MVA, fC = 56.25Hz)
6.1.4. Comparison of 4.16kV, 4.32MVA Multi-Level Converters at Constant Efficiency The conditions for the fourth aspect of comparison are a constant converter efficiency of about 99% at a constant converter power of SC = 4.32MVA, assuming a line-to-line voltage of 4.16kV. To compare the converter switch utilization of the three-level topologies (i.e. the 3L-NPC VSC and 3L-FLC VSC), 6.5kV IGBTs/diodes and a series connection of two 3.3kV IGBTs/diodes are considered. Table 6-5 summarizes the design of the power semiconductors while assuming a carrier frequency of fC = 450Hz in all topologies. In a second step, the carrier frequencies, the ideal rated IGBT/diode currents, and thus the installed switch powers were determined in an iterative simulation procedure to achieve both the efficiency requirement ( 99%) at the specified converter power and a junction temperature of
124
Tj,max = 125C at one worst case operating point [25], [29]. Table 6-6 depicts the resulting ideal rated currents, installed switch powers, and carrier frequencies.
The 3L-NPC VSC is used as a reference. Figure 6-13b shows the efficiencies as a function of the phase current. It is remarkable that the efficiency of the 3L-NPC VSC (fC = 450Hz) is higher and that there are thus smaller losses than in the other topologies in the entire current range.
Table 6-5 Converter voltage and semiconductor specifications for a constant converter power and carrier frequency (Ull,rms,1 = 4.16kV, Iph,rms,1 = 600A, SC = 4.32MVA, fC = 450Hz, Tj,max = 125C), (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3) 4.16kV 6118.5V
3L-NPC 6.5kV 2x3.3kV IGBT IGBT 3L-FLC 6.5kV 2x3.3kV IGBT IGBT 4L-FLC 4.5kV IGBT 9L-SC2LHB 1.7kV IGBT
Converter line-to-line voltage Ull,rms,1 Dc link voltage Udc,n Converter topology Rated device voltage UCE,n Commutation voltage Ucom
Udc,n / 2
3059.2V 3600V 0.85
Udc,n / 4
1529.6V 2x1800V 0.85 594.4A 82.38 MVA 100%
Udc,n / 2
3059.2V 3600V 0.85 768A 89.85 MVA 106.6%
Udc,n / 4
1529.6V 2x1800V 0.85 601.6A 71.47 MVA 86.7%
Udc,n / 3
2039.5V 2250V 0.91 681A 82.74 MVA 100.4%
Udc,n / 8
765V 900V 0.85 607.2A 74.32 MVA 90.2%
Ucom@100FIT Ucom/Ucom@100FIT Rated IGBT current IC,n (IF,n) @ Tj,max = 125C, fC =450Hz, 704.4A Iph,rms,1 = 600A Installed switch power SS Relative installed power SSR switch
101.06 MVA
122.6%
Table 6-6
Carrier and harmonic carrier band frequencies, capacity of flying capacitors, and installed switch power for a converter efficiency of about 99% (Ull,rms,1 = 4.16kV, Iph,rms,1 = 600A, SC = 4.32MVA), (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3) 3L-NPC
6.5kV IGBT 704.4A 99.3% 450Hz 2x3.3kV IGBT 748A 98.95% 1250Hz 1250Hz 103.67 MVA 100%
Converter topology Nominal devices voltage
3L-FLC
6.5kV IGBT 768A 98.96% 475Hz 950Hz 1946F 27314J 60.83 MVA 58.7% 2x3.3kV IGBT 638.4A 98.88% 650Hz 1300Hz 1422F 19960J 75.84 MVA 73.2%
4L-FLC
4.5kV IGBT 734.1A 98.99% 610Hz 1830Hz 1316F 41078J 87.41 MVA 84.3%
9L-SC2LHB
1.7kV IGBT 655.7A 98.92% 1155Hz 9240Hz 79.32 MVA 76.5%
Nominal devices current Converter efficiency Carrier frequency fC Frequency of the first 450Hz harmonics carrier band f1Cb Capacity of the flying capacitors C1,2 Stored energy of the flying capacitors EC Installed switch power SS Relative installed switch 97.5% power SSR
101.06 MVA
125
It is furthermore interesting to note that the application of two series connected 3.3kV IGBTs/diodes increases the installed switch power by 2.6% at a 277.8% higher switching frequency, compared to the use of 6.5kV IGBTs/diodes. The distribution of conduction and switching losses (Figure 6-13a) demonstrates that the series connection of 3.3kV IGBTs enables an almost equal share of switching and on state losses for fC = 1250Hz. In contrast, the switching losses of 6.5kV IGBTs cause about two-thirds of the total losses at fC = 450Hz, because these devices are optimized for distinctly lower switching frequencies. Both on state and switching losses of the 3L-FLC VSC are slightly higher, compared to the 3LNPC VSC, at an identical frequency of the first carrier band since the ideal current ratings of the switches in the 3L-FLC VSC are distinctly lower due to the better loss distribution [20], [24], [25]. The installed switch powers of the 3L-, 4L-FLC VSCs, and the 9L-SC2LHB VSC are reduced by 41.3%, 15.7%, and 23.5% respectively, in comparison to the 3L-NPC VSC (fC = 1250Hz), applying two series connection of a 3.3kV IGBT/diode (Figure 6-13c). Therefore, unlike the other topologies, the 3L-FLC VSC enables maximum switch utilization (Figure 6-13d). The loss distribution shows an extremely low share of switching losses in the 9L-SC2LHB VSC (Figure 6-13a).
Semiconductor losses distributions [kW] 50 40
PconT PconD PonT PoffT PoffD
2(3.3kV) 2(3.3kV) 6.5kV 4.5kV
1.7kV
Efficiency [%]
99.8 99.6 99.4 99.2 99
30 6.5kV 20 10 0
3L-NPC(6.5kV IGBT) 3L-NPC(2*3.3kV IGBT) 3L-FLC(6.5kV IGBT) 3L-FLC(2*3.3kV IGBT) 4L-FLC(4.5kV IGBT) 9L-SC2LHB(1.7kV IGBT)
98.8
3L-NPC
3L-FLC
4L-FLC 9L-SC2LHB
98.6
200
800
1000
(a)
100% 100 97.5% 84.3% 80 SSR [%] 60 2*(3.3kV IGBT) 6.5kV IGBT 40 20 0 73.2% 58.7% 2*(3.3kV IGBT) 76.5%
(b)
6.5kV IGBT
4.5kV IGBT
3L-NPC
3L-FLC
4L-FLC 9L-SC2LHB
(c)
Figure 6-13 Loss distribution (a), efficiency (b), and relative installed switch power (c) (Sc = 4.32MVA, Iph,rms,1 = 600A, fo = 50Hz, ma = 1.15, cos = 0.9, Tjmax = 125C, fC,3LNPC-6.5kV = 450Hz, fC,3L-NPC-3.3kV = 1250Hz, fC,3L-FLC-6.5kV = 475Hz, fC,3L-FLC-3.3kV = 650Hz, fC,4L-FLC-4.5kV = 610Hz, fC,9LSC2LHB-1.7kV = 1125Hz), (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
1.7kV IGBT
126
The values of the flying capacitors are depicted in Table 6-6, according to equation (5-5). The stored energy in the flying capacitors of the 4L-FLC VSC is more than the factors of 1.5 (fC = 475Hz) and 2 (fC = 650Hz) and higher than that of the 3L-FLC VSC, which results in substantially higher expenses of capacitors in the 4L-FLC VSC. The simulated voltage ripple UC and current iC,rms of the flying capacitors are depicted in Figure 6-14 and Figure 6-15 as functions of the modulation index ma and the phase shift between the converter output voltage and current for the carrier frequency of fC = 1200Hz [24], [29]. The maximum voltage ripple and current stress of the 3L-FLC VSC occur at a modulation index of ma = 0 (UC,max = 460V, iC,max = 600A (see Figure 6-14)), while the maximum voltage ripple of the 4L-FLC VSC occurs at ma = 0.808 and = 90 (UC,max = 589V (see Figure 6-15)). The capacitor current of the 4L-FLC VSC reaches a maximum in the modulation range of 0 < ma < 0.33 independent of (iC,max = 489A (see Figure 6-15)). The voltage and current ripple of the 4L-FLC VSC are about 29% higher and 18% lower respectively than that of the 3L-FLC VSC [29].
600 iC,rms [A] 400 200 0 180 1.2 90 Phase shift [deg] 0 0 0.8 0.4 Modulation index ma
480 320 160 0 180 1.2 90 Phase shift [deg] 0 0 0.8 0.4 Modulation index ma
(a) iC,max = 600A @ ma = 0, = 0180
Figure 6-14 Flying capacitor current (a) and voltage ripple (b) of a 3L-FLC VSC as functions of the modulation index and phase shift (Iph,rms,1 = 600A, fC,3L-FLC = 1200Hz, C = 770F)
500 iC2,rms [A] UC2 [V] 330 165 0 180 1.2 90 Phase shift [deg] 0 0 0.8 0.4 Modulation index ma
UC [V]
(b) UC,max = 460V @ ma = 0, = 0180
600 400 200 0 180 1.2 90 Phase shift [deg] 0 0 0.8 0.4 Modulation index ma
(a) iC,max = 489A @ 0 < ma < 0.33, = 0180
(b) UC,max = 589V@ ma = 0.808, = 90
Figure 6-15 Flying capacitor current (a) and voltage ripple (b) of a 4L-FLC VSC as functions of the modulation index and phase shift (Iph,rms,1 = 600A, fC,4L-FLC = 1200Hz, C1,2 = 518F)
127
The harmonic spectra of the line-to-line output voltage of the considered converters are shown in Figure 6-16. The first carrier band of the line-to-line voltage of the 3L-NPC VSC occurs at the carrier frequency of fC = 450Hz using 6.5kV IGBTs. On the other hand, the first carrier band of the line-to-line voltage of the 3L- and 4L-FLC VSCs are increased by a factor of 2 (f1Cb = 950Hz) and 4 (f1Cb = 1830Hz) respectively, compared to the 3L-NPC VSC (Table 6-6). In contrast, the first carrier band of the line-to-line output voltage of the 9L-SC2LHB VSC (f1Cb = 9240Hz) is centred around twenty times the carrier frequency (f1Cb = 20fC) (Figure 6-16). Hence, an output filter of the 9L-SC2LHB VSC could be smaller than the corresponding filters of the other topologies.
0
fC,3L-NPC-6.5kV = 450Hz
-1
fC,3L-FLC-6.5kV = 475Hz
-1
-2 0 0
-2 0
10
10
fC,3L-NPC-3.3kV = 1250Hz
-1
-1
-2 0
-2 0
10
10
-1
fC,9L-SCHB-1.7kV = 1125Hz
-1
-2
-2
4 6 Frequency [kHz]
10
4 6 Frequency [kHz]
10
Figure 6-16 Harmonic spectrum of line-to-line voltage at constant efficiency (Iph,rms,1 = 600A, fo = 50Hz, ma = 1.15, cos = 0.9, Tjmax = 125C, fC,3L-NPC-6.5kV = 450Hz, fC,3L-NPC-3.3kV = 1250Hz, fC,3L-FLC-6.5kV = 475Hz, fC,3L-FLC-3.3kV = 650Hz, fC,4L-FLC-4.5kV = 610Hz, fC,9LSC2LHB1.7kV = 1125Hz)
6.2. Comparison of Power Semiconductor Utilization and Loss Distribution for 2.3kV-6kV Multi-Level Converters (3L-NPC VSC and SC2LHB VSCs) Among the aforementioned medium voltage converters, this section takes only the 3L-NPC VSC and the SC2LHB VSCs into account. The converter output power and the semiconductor utilization are examined at the three different carrier frequencies of 450Hz, 750Hz, and 1050Hz for line-to-line output voltages of 2.3kV, 3.3kV, 4.16kV, and 6kV. Table 6-7 depicts the technical data and conditions of the considered converter topologies. The loss distribution and the relative installed switch power of the investigated converter topologies are shown in Figure 6-17, assuming the constant carrier frequency (450Hz, 750Hz, and 1050Hz) and a constant phase current (Iph,rms,1 = 600A). It is interesting to note that the 5L-, 7L-, and 9L-SC2LHB VSCs generate higher converter losses than the corresponding 3L-NPC VSCs in the output voltage classes of 2.3kV, 3.3kV, and 4.16kV. In contrast, for a line-to-line output voltage of 6kV, the converter losses of the 11L-SC2LHB VSC are reduced by 8% at fC = 450Hz, 13.2% at fC = 750Hz, and 18.9% at fC = 1050Hz, compared to the 3L-NPC VSCs. The switching losses of the SC2LHB VSCs (5L-, 7L-, 9L-, and 11L) topologies are significantly lower than that of the 3L-NPC VSCs in all considered output voltage classes and carrier
128
frequencies (for example, 11% for 2.3kV, 39% for 3.3kV, and 59% for 4.16kV, and 6kV at fC = 450Hz), since the 1.7kV IGBTs generate distinctly less switching losses than the 3.3kV, 4.5kV, and 6.5kV IGBTs at their corresponding commutation voltage. On the other hand, the conduction losses of the SC2LHB VSCs occurring at line-to-line output voltages of 2.3kV, 3.3kV, 4.16kV, and 6kV are increased in all considered carrier frequencies, compared to the 3LNPC VSC topology (16%, 145%, 121%, and 27% at fC = 750Hz). It is remarkable that the relative installed switch power SSR of the SC2LHB VSCs decreases when increasing the line-to-line output voltage and the carrier frequency (Figure 6-17).
Table 6-7 Topology IGBT/Diode Device number Ucom [V] fC [Hz] f1Cb [Hz] IC,n (IF,n) [A] SS [MVA] SSR [%] Topology IGBT/Diode Device number Ucom [V] fC [Hz] f1Cb [Hz] IC,n (IF,n) [A] SS [MVA] SSR [%] Topology IGBT/Diode Device number Ucom [V] fC [Hz] f1Cb [Hz] IC,n (IF,n) [A] SS [MVA] SSR [%] Topology IGBT/Diode Device number Ucom [V] fC [Hz] f1Cb [Hz] IC,n (IF,n) [A] SS [MVA] SSR [%] Power semiconductor design (Iph,rms,1 = 600A, ma = 1.15, cos = 0.9) Converter line-to-line voltage Ull,rms,1 = 2.3kV 3L-NPC VSC 5L-SCH2LB VSC
3.3kV/800A IGBT FZ800R33KF2 1691.4 450 750 1050 450 750 1050 604.8 660 697.6 41.91 45.74 48.34 100% 100% 100% 1.7kV/600A IGBT FZ600R17KE3 845.7 450 750 1050 1800 3000 4200 609.6 630 648 37.31 38.56 39.66 89% 84% 82%
7L-SCH2LB VSC
1.7kV/600A IGBT FZ600R17KE3 563.8 450 750 1050 2700 4500 6300 602.4 613.2 626.4 55.3 56.29 57.5 132% 123% 119%
Converter line-to-line voltage Ull,rms,1 = 3.3kV 3L-NPC VSC

4.5kV/600A IGBT CM600HB-90H
2426.7
7L-SCH2LB VSC
1.7kV/600A IGBT FZ600R17KE3
808.9
450 450 642 60.67 100%
750 750 783 74 100%
1050 1050 1015.2 95.94 100%
2 (3.3kV/800A IGBT) 2 (FZ800R33KF2) 2 (1213.35) 450 750 1050 450 750 1050 1054.4 1124.4 1216 73.1 77.95 84.27 120% 105% 88%
450 2700 609.6 55.96 92%
750 4500 627 57.56 78%
1050 6300 645 59.21 62%
Converter line-to-line voltage Ull,rms,1 = 4.16kV 3L-NPC VSC

6.5kV/600A IGBT FZ600R65KF1
3059.2
9L-SCH2LB VSC
764.8
450 450 740.4 101.1 100%
750 750 936 127.8 100%
1050 1050 1158 158.1 100%
2 (3.3kV/800A IGBT) 2 (FZ800R33KF2) 2 (1529.6) 450 750 1050 450 750 1050 1084.8 1180.8 1312 75.18 81.83 90.92 74.4% 64% 58%
450 3600 607.2 74.32 73.5%
750 6000 623.4 76.3 60%
1050 8400 640.8 78.43 50%
Converter line-to-line voltage Ull,rms,1 = 6kV 3L-NPC VSC

2 (6.5kV/600A IGBT) 2 (FZ600R65KF1) 2 (2206.2) 450 750 1050 450 750 1050 1224 1572 1932 167.1 214.6 263.7 100% 100% 100% 3 (3.3kV/800A IGBT) 3 (FZ800R33KF2) 3 (1470.7) 450 750 1050 450 750 1050 1620 1752 1941.6 112.3 121.4 134.6 67% 57% 51%
11L-SCH2LB VSC
882.5
450 4500 610.8 93.5 56%
750 7500 630 96.4 45%
1050 10500 651 99.6 38%
129
Relative installed switch power [%]
70 Power loss distribution [kW] 60 50 40 30 20 10 0

1.7kV 1.7kV 3.3kV 5L-SC2LHB 7L-SC2LHB 3L-NPC 4.5kV 7L-SC2LHB 9L-SC2LHB 3L-NPC 3L-NPC 3L-NPC 3L-NPC 3L-NPC 3L-NPC 2*3.3kV 3*3.3kV 2*6.5kV 1.7kV 1.7kV 2*3.3kV
140 120 100 80

%100
%132 %120 %100 %92 %74 %74 3L-NPC (3.3kV IGBT) 3L-NPC (4.5kV IGBT) 3L-NPC (6.5kV IGBT) %56 11L-SC2LHB(1.7kV IGBT)
11L-SC2LHB 11L-SC2LHB %38
%100
%100
%89
5L-SC2LHB (1.7kV IGBT)
%67 3L-NPC (2*6.5kV IGBT)

%100 3L-NPC (2*6.5kV IGBT) 3L-NPC (2*6.5kV IGBT) %100
3L-NPC (2*3.3kV IGBT)
1.7kV 6.5kV
60 40 20 0
2.3kV
3.3kV
4.16kV
6kV
2.3kV
3.3kV
4.16kV
6kV
(a) fC = 450Hz
1.7kV 1.7kV 3.3kV 5L-SCHB 7L-SCHB 4.5kV 11L-SCHB 7L-SCHB 9L-SCHB 2*3.3kV 1.7kV 1.7kV 2*3.3kV 6.5kV
Relative installed switch power [%]
70 Power loss distribution [kW] 60 50 40 30 20 10 0

2*6.5kV 3*3.3kV 1.7kV
%123
120 100 80
5L-SC2LHB (1.7kV IGBT) 7L-SC2LHB (1.7kV IGBT) 3L-NPC (2*3.3kV IGBT) %100 %84 %78 7L-SC2LHB (1.7kV IGBT) %64 3L-NPC (2*3.3kV IGBT) 3L-NPC (6.5kV IGBT) %60 9L-SC2LHB(1.7kVIGBT) %105 %100 %100
3L-NPC(3*3.3kVIGBT) 3L-NPC(3*3.3kV)
60
3L-NPC (3.3kV IGBT)
%57 %45
40 20 0
2.3kV
3.3kV
4.16kV
6kV
2.3kV
3L-NPC (4.5kV IGBT)
3L-NPC
3L-NPC
3L-NPC
3L-NPC
3L-NPC
3L-NPC
3L-NPC
3.3kV
4.16kV
6kV
(b) fC = 750Hz
Relative installed switch power [%] 70 Power loss distribution [kW] 60 50 40 30 20 10 0
1.7kV 3.3kV 5L-SCHB 7L-SCHB

1.7kV 4.5kV
2*6.5kV 3*3.3kV 1.7kV
120 100 80 60
3L-NPC (3.3kV IGBT) %100
%119 %100 %88 %82 %100
2*3.3kV 1.7kV 2*3.3kV 6.5kV 1.7kV
%62 7L-SC2LHB(1.7kVIGBT) 3L-NPC (2*3.3kV IGBT) 3L-NPC (4.5kV IGBT) 3L-NPC (6.5kV IGBT)
%58 3L-NPC(2*3.3kVIGBT) %50 9L-SC2LHB(1.7kV)
%51
40 20 0
2.3kV
3.3kV
4.16kV
6kV
11L-SCHB
7L-SCHB
9L-SCHB
3L-NPC
3L-NPC
3L-NPC
3L-NPC
3L-NPC
3L-NPC
3L-NPC
2.3kV
3.3kV
4.16kV
6kV
(c) fC = 1050Hz
Figure 6-17 Semiconductor loss distribution and relative installed switch power occurring at line-to-line output voltages of 2.3kV, 3.3kV, 4.16kV, and 6kV at the different switching frequencies of 450Hz, 750Hz, and 1050Hz (Iph,rms,1 = 600A, fo = 50Hz, ma = 1.15, cos = 0.9, Tjmax = 125C), (6.5kV/600A: FZ600R65KF1, 4.5kV/600A: CM600HB-90H, 3.3kV/800A: FZ800R33KF2, 2.5kV/1000A: FZ1000R25KF1, 1.7kV/600A: FZ600R17KE3)
For all examined output voltage classes and carrier frequencies, the SC2LHB VSCs enable a minimum installed switch power which is decreased, for example, by 18% for 2.3kV, 38% for
11L-SC2LHB
130
3.3kV, 50% for 4.16kV, and 62% for 6kV at the carrier frequency of fC = 1050Hz, in comparison to the corresponding 3L-NPC VSCs (Table 6-7). Furthermore, the first carrier band of the line-to-line output voltage of the 3L-NPC VSC occurs around the carrier frequency (f1Cb = fC), whereas the first carrier band of the line-to-line output voltage of the 5L-, 7L-, 9L-, and 11L-SC2LHB VSCs are centred around four, six, eight, and ten times the carrier frequency respectively. Hence, an output filter of the SC2LHB VSCs could be smaller than the corresponding filters of the 3L-NPC VSC topology. 6.3. Comparison of the DC Link Capacitor for a 24-pulse, 4.16kV, 4.32MVA, 3L-NPC VSC and 9L-SC2LHB VSC Comparison of the dc link capacitor for a 24-pulse, 4.16kV, 4.32MVA, 3L-NPC VSC and 9LSC2LHB VSC is the purpose of this section (refer to Figure 4-1). Design criteria like the dc link voltage ripples and the dc link capacitor storage energy are considered to determine the suitable size of the dc link capacitor. In a first step, the maximum value of the ripple in the dc link capacitor current is computed, considering the influence of the operating parameters at the inverter mode, e.g. load angle ( = 180180) and the modulation index (ma = 01.15). Due to capacitor voltage balancing in the 3L-NPC VSC, the dc link capacitors are replaced by constant ideal voltage sources, of which each is one-half of the dc link voltage. A three-phase sinusoidal current source with a constant amplitude of 850A is assumed as a load. Figure 6-18 illustrates the root mean square (rms), average and ripple current at the dc rail of the capacitor bank (according to Figure 3-6 and Figure 3-39) as a function of the modulation index ma and load angle . They show that the result is symmetrical concerning the axle of the load angle, and the maximum value of the ripple current occurs at ma = 0.6 and = 0, 180 in the 3L-NPC VSC (Figure 6-18c) and ma = 1.15 and = 0, 180 in the 9L-SC2LHB VSC (Figure 6-18f). In a second step, to investigate the dc link voltage ripple, the grid, and load currents (according to Figure 4-1) the modulation index of ma = 0.6 (for the 3L-NPC VSC) and ma = 1.15 (for the 9L-SC2LHB VSC) are accepted. The minimum size of the dc link capacitor is determined by using equation (5-3) for the 3L-NPC VSC and equation (5-4) for the 9L-SCHB VSC, applying a voltage ripple of 5%, and equation (5-5), assuming a stored energy of 6J/kVA and 12J/kVA. A standard three-phase symmetric load model was realized by applying a load power factor cos = 0.9 and a machine leakage inductance of LL = 20% (1.37mH). The machine resistance is assumed insignificant. The system is simulated by a MATLAB program. Figure 6-18Figure 6-19 through Figure 6-28 present the simulation results in the steady state at 100% load for carrier frequency fC = 750Hz. Figure 6-19 and Figure 6-20 show the grid currents, the transformer primary and secondary winding currents in each 12-pulse transformer, and their harmonic spectrum at a stored energy of 6J/kVA and 12J/kVA for the 3L-NPC VSC respectively. Because of the first dominant utility grid, the phase current harmonics are 23rd and 25th; then the low-frequency harmonic waves are eliminated. The first dominant transformer primary current harmonics are 11th and 13th. The transformer secondary winding currents have harmonic components with low ordinal numbers (h=6k 1, where k=1, 2 ...). It is evident that the amplitude of all harmonics are reduced applying a stored energy of 12J/kVA instead of 6J/kVA. The rectifier output voltage, the rectifier output current, the capacitor voltage ripples, and their harmonic spectrum are depicted in Figure 6-23 and Figure 6-24 at a stored energy of 6J/kVA and 12J/kVA for the 3L-NPC VSC respectively. The results show that the dc link voltage ripple and the dc link current are about 1.3% and 4.96% for the stored energy of 6J/kVA, while they
131
enable a reduction by 55% and by 47.6% at twice the stored energy. It is to remark that the dc link voltage ripple of each H-bridge cell of the 9L-SC2LHB VSC is larger than the acceptable value of 5%, assuming a stored energy of 12J/kVA (Figure 6-21, Figure 6-25). Therefore, in order to place the dc link voltage ripple at a permissible limit, an increase in the dc link capacitor by the factor of 2.83 and a recalculation of the stored energy of 34J/kVA are necessary, compared to the stored energy of 12J/kVA (Figure 6-22, Figure 6-26). Figure 6-27 and Figure 6-28 illustrate the capacitor currents, the output phase-midpoint voltage, the load phase currents, and their harmonic spectrum at a stored energy of 6J/kVA and 12J/kVA respectively. It can be seen that the odd harmonics in the phase-midpoint voltage UaM1 centred around the switching frequency and its multiples.
132
(a)
(d)
(b)
(e)
(c)
(f)
Figure 6-18 The effective, average, and ripple capacitor current as a function of the modulation index and load angle in the 3L-NPC VSC according to Figure 3-6: (a-c) (idc2,eff,max/iph,peak = 85.6% at = 180, 0 and ma = 1.15), (idc2,avg,max/iph,peak = 80.3% at = 0 and ma = 1.15), (idc2,rip,max/iph,peak = 45.8% at = 180, 0 and ma = 0.6), and in the 9L-SC2LHB VSC according to Figure 3-39 (d-f).(idc21,eff,max/iph,peak = 68.7% at = 180, 0 and ma = 1.15), (idc21,avg,max/iph,peak = 57.5% at = 0 and ma = 1.15), (idc21,rip,max/iph,peak = 54.3% at = 90, and ma = 1.15), (iph,rms,1 = 600A, fC = 750Hz, fo = 50Hz)
133
200
10
100 is,x [A] isA 0 isB isC -100
Amplitude i s,x
10
-200 4.88
4.89
4.9 Time [sec.]
4.91
4.92
10
-2
10
40
50
(a)
100
10
2
(b)
50 Ip1,x [A] Ip1U 0 Ip1V Ip1W -50

Amplitude I p1x
10
-100 4.88
4.89
4.9 Time [sec.]
4.91
4.92
10
-2
10
40
50
(c)
400 Is1,u 200 Is,x [A] Is2,u Is4,u 0 Amplitude I s,x Is3,u 10
2
(d)
10
-200
-400 4.88
4.89
4.9 Time [sec.]
4.91
4.92
10
-2
10
40
50
(e)
(f)
Figure 6-19 (a, b): Utility grid phase current and its harmonic spectra in the 3L-NPC VSC, (c, d): transformer primary phase currents of the 12-pulse transformer and their harmonic spectra in the 3L-NPC VSC, (e, f): transformer secondary phase currents of the 12-pulse transformer and their harmonic spectra in the 3L-NPC VSC (E = 6J/kVA, C1 = C2 = 2.77mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9)
134
200 10 100 is,x [A] isA 0 isB isC -100 Amplitude i s,x
2
10
-200 5.66
5.67
5.68 Time [sec.]
5.69
5.7
10
-2
10
40
50
(a)
100 10
2
(b)
50 Ip1,x [A] Ip1U 0 Ip1V Ip1W -50 Amplitude I p1,x
10
-100 5.66
5.67
5.68 Time [sec.]
5.69
5.7
10
-2
10
40
50
(c)
400 Is1,u 200 Is,x [A] Is2,u Is4,u 0 Amplitude I s,x Is3,u 10
2
(d)
10
-200
-400 5.66
5.67
5.68 Time [sec.]
5.69
5.7
10
-2
10
40
50
(e)
(f)
Figure 6-20 (a, b): Utility grid phase current and its harmonic spectra in the 3L-NPC VSC, (c, d): transformer primary phase currents of the 12-pulse transformer and their harmonic spectra in the 3L-NPC VSC, (e, f): transformer secondary phase currents of the 12-pulse transformer and their harmonic spectra in the 3L-NPC VSC (E = 12J/kVA, C1 = C2 = 5.54mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9)
135
200 10 100 isx [A] isA 0 isB isC -100 Amplitude isx
2
10
-200 0.18
0.19
0.2 Time [sec.]
0.21
0.22
10
-2
10
40
50
(a)
100 10 50 Ip1x [A] Ip1U 0 Ip1V Ip1W -50 Amplitude Ip1x
2
(b)
10
-100 0.18
0.19
0.2 Time [sec.]
0.21
0.22
10
-2
10
40
50
(c)
10 Is1 500 Is2 Is4 0 Amplitude Isx Is3 Isx [A] 10
2 4
(d)
10
-500 10
-2
0.26
0.27
0.28 Time [sec.]
0.29
0.3
10
40
50
(e)
(f)
Figure 6-21 (a, b): Utility grid phase current and its harmonic spectra in the 9L-SC2LHB VSC, (c, d): transformer primary phase currents of the 12-pulse transformer and their harmonic spectra in the 9L-SC2LHB VSC, (e, f): transformer secondary phase currents of the 12-pulse transformer and their harmonic spectra in the 9L-SC2LHB VSC (E = 12J/kVA, C1 = C2 = 14.8mF, fC = 750Hz, fo = 50Hz, ma = 1.15, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9)
136
200 10 100 isx [A] isA 0 isB isC -100 Amplitude isx
2
10
-200 0.12
0.13
0.14 Time [sec.]
0.15
0.16
10
-2
10
40
50
(a)
100 10 Ip1 0 Ip2 Ip3 -50 Amplitude Ipx
2
(b)
50 Ipx [A]
10
-100 0
0.01
0.02 Time [sec.]
0.03
0.04
10
-2
10
40
50
(c)
(d)
500 Amplitude Isx 0.19 0.2 Time [sec.] 0.21 0.22
10
Isx [A]
10
-500 10
-2
0.18
10
40
50
(e)
(f)
Figure 6-22 (a, b): Utility grid phase current and its harmonic spectra in the 9L-SC2LHB VSC, (c, d): transformer primary phase currents of the 12-pulse transformer and their harmonic spectra in the 9L-SC2LHB VSC, (e, f): transformer secondary phase currents of the 12-pulse transformer and their harmonic spectra in the 9L-SC2LHB VSC (E = 34J/kVA, C1 = C2 = 44mF, fC = 750Hz, fo = 50Hz, ma = 1.15, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9)
137
6246
10
Amplitude Udc 2.98 2.99 Time [sec.] 3
10
Udc [V]
10
6168 10
-2
10
40
50
(a)
330 320 310 300 290 280 4.88
(b)
10 Amplitude i dc
idc [A]
10
4.89
4.9 Time [sec.]
4.91
4.92
10
-2
10
40
50
(c)
3184 UC1 UC2
Amplitude UCx 10
2
(d)
UCx [V]
3107
10
3030 4.88 4.89 4.9 Time [sec.] 4.91 4.92
10
-2
10
40
50
(e)
(f)
Figure 6-23 (a, b): DC link voltage ripple and its harmonic spectra in the 3L-NPC VSC, (c, d): dc link current and its harmonic spectra, (e, f): capacitor voltage ripples and their harmonic spectra in the 3L-NPC VSC (E = 6J/kVA, C1 = C2 = 2.77mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9)
138
10 6225 Amplitude Udc 5.685 5.69 Time [sec.] 5.695 5.7
Udc [V]
10
10
6197 5.68 10
-2
10
40
50
(a)
330 320 310 300 290 280 5.66 10
-2
(b)
10 Amplitude i dc 5.67 5.68 Time [sec.] 5.69 5.7
idc [A]
10
10
40
50
(c)
3148 10 UC1 UC2 Amplitude UCx 10
2 4
(d)
UCx [V]
3110
10
3066 5.66 5.67 5.68 Time [sec.] 5.69 5.7 10
-2
10
40
50
(e)
(f)
Figure 6-24 (a, b): DC link voltage ripple and its harmonic spectra in the 3L-NPC VSC, (c, d): dc link current and its harmonic spectra in the 3L-NPC VSC, (e, f): capacitor voltage ripples and their harmonic spectra in the 3L-NPC VSC (E = 12J/kVA, C1 = C2 = 5.54mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9)
139
1000 800 600 UdcHB,1 400 200 0 0.26 UdcHB,2 UdcHB,3 UdcHB,4 0.27 0.28 Time [sec.] 0.29 0.3 Amplitude Udc,HB UdcHB [V] 10
2
10
10
-2
10
40
50
(a)
1000 idc1 800 idcx [A] 600 400 200 0 0.26 idc2 idc4 Amplitude Udc,HB idc3 10
2
(b)
10
10 0.27 0.28 Time [sec.] 0.29 0.3
-2
10
40
50
(c)
3000 2000 Uan [V] 1000 0 -1000 -2000 10 -3000 0.26 0.27 0.28 Time [sec.] 0.29 0.3 0 10 Amplitude Uan 10
2
(d)
10
-2
40
50
(e)
(f)
Figure 6-25 (a, b): DC link voltage ripple and its harmonic spectra in the 9L-SC2LHB VSC, (c, d): dc link current and its harmonic spectra in the 9L-SC2LHB VSC, (e, f): phase output voltage and its harmonic spectra in the 9L-SC2LHB VSC (E = 12J/kVA, C1 = C2 = 14.8mF, fC = 750Hz, fo = 50Hz, ma = 1.15, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9)
140
1000 800 600 400 200 0 0.26 Amplitude idc,x UdcHB [V] 10
2
UdcHB,1 UdcHB,2 UdcHB,3 UdcHB,4
10
10
-2
0.27
0.28 Time [sec.]
0.29
0.3
10
40
50
(a)
1000 idc1 800 idcx [A] 600 400 200 0 0.26 idc2 idc4 Amplitude idc,x idc3 10
2
(b)
10
10 0.27 0.28 Time [sec.] 0.29 0.3
-2
10
40
50
(c)
(d)
3000 2000 Uan [V] 1000 0 -1000 -2000 10 -3000 0.26 0.27 0.28 Time [sec.] 0.29 0.3 0 10 20 30 Harmonics order 40 50 Amplitude Uan 10
2
10
-2
(e)
(f)
Figure 6-26 (a, b): DC link voltage ripple and its harmonic spectra in the 9L-SC2LHB VSC, (c, d): dc link current and its harmonic spectra in the 9L-SC2LHB VSC, (e, f): phase output voltage and its harmonic spectra in the 9L-SC2LHB VSC (E = 34J/kVA, C1 = C2 = 44mF, fC = 750Hz, fo = 50Hz, ma = 1.15, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9)
141
500 iC2 [A] 0 -500 5.66 500 iC1 [A] 0 -500 5.66 5.67 5.68 Time [sec.] 5.69 5.7 10
-2
10 Amplitude i C2
5.67
5.68
5.69
5.7
10
10
40
50
(a)
10
3000 2000
4
(b)
Amplitude UaM1
UaM1 [V]
1000 0 -1000 -2000 -3000 4.88 4.89 4.9 Time [sec.] 4.91 4.92
10
10
10
-2
10
40
50
(c)
1000
(d)
500 iL,x [A] iLa 0 iLb iLc -500
10 Amplitude i L,x
10
-1000 4.88
4.89
4.9 Time [sec.]
4.91
4.92
10
-2
10
40
50
(e)
(f)
Figure 6-27 (a, b): Capacitor current ripples and their harmonic spectra in the 3L-NPC VSC, (c, d): phase-midpoint output voltage and its harmonic spectra in the 3L-NPC VSC, (e, f): phase output load currents and their harmonic spectra in the 3L-NPC VSC (E = 6J/kVA, C1 = C2 = 2.77mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9)
142
500 iC2 [A] 0 -500 5.66 500 iC1 [A] 0 -500 5.66 5.67 5.68 Time [sec.] 5.69 5.7 10
-2
10 Amplitude i C2
5.67
5.68
5.69
5.7
10
10
40
50
(a)
3000 2000 Amplitude UaM1 UaM1 [V] 1000 0 -1000 -2000 -3000 5.66 5.67 5.68 Time [sec.] 5.69 5.7 10
-2
(b)
10
4
10
10
10
40
50
(c)
1000
(d)
500 iL,x [A] iLa 0 iLb iLc -500
10 Amplitude i L,x
10
-1000 5.66
5.67
5.68 Time [sec.]
5.69
5.7
10
-2
10
40
50
(e)
(f)
Figure 6-28 (a, b): Capacitor current ripples and their harmonic spectra in the 3L-NPC VSC, (c, d): phase-midpoint output voltage and its harmonic spectra in the 3L-NPC VSC, (e, f): phase output load currents and their harmonic spectra in the 3L-NPC VSC (E = 12J/kVA, C1 = C2 = 5.54mF, fC = 750Hz, fo = 50Hz, ma = 0.6, Vll,rms,1 = 4.16kV, Iph,rms,1 = 600A, cos = 0.9)
7. CONCLUSION AND DISCUSSION

In this thesis, different multi-level converters (the 2L-VSC, 3L-NPC VSC, 3L-, 4L-FLC VSCs, SC2LHB VSCs, and SC3LHB VSCs) have been investigated in terms of the feasibility of their utilization in medium voltage applications. The medium voltage drives in the 2.4MVA to 6.2MVA range with voltage ratings from 2.3kV to 6kV have been studied, applying 1.7kV, 2.5kV, 3.3kV, 4.5kV, and 6.5kV IGBT modules. The modelling of the converter has been derived and the principles of operation that include the structure, the design of the power semiconductor devices and passive components, the design of the dc link capacitor, and the function of the multi-pulse isolation transformer have been discussed. To evaluate the converter topologies for a variety of applications, three commercially available MV topologies (i.e. the 3L-NPC VSC, FLC VSCs, and SC2LHB VSCs) have been compared in detail and the simulation results (regarding the converter losses, the semiconductor loss distribution, the efficiency, the installed switch power, and the harmonic spectrum) have been investigated, assuming a maximum junction temperature of Tj,max = 125C at a phase current of Iph,rms,1 = 600A and a carrier frequency of fC = 450Hz...1050Hz. In the first comparison, a constant carrier frequency fC and a constant installed switch power SS (which is a measure for the expense of semiconductors) have been examined to compare the maximum converter output power SC,max and the semiconductor utilization of the considered converter topologies. The simulation results show that the SC2LHB VSCs provided the maximum converter output power SC,max in all investigated line-to-line output voltage classes. The switching losses of the SC2LHB VSC topologies were significantly lower than those of the other topologies in all considered output voltage classes, since the 1.7kV IGBTs generate distinctly less switching losses than other IGBTs at their corresponding commutation voltage. An output filter of the SC2LHB VSCs could be smaller than the corresponding filters of other topologies due to the first carrier band of the line-to-line output voltage of the 5L-, 7L-, 9L-, and 11L-SC2LHB VSCs being centred around four, six, eight, and ten times the carrier frequency. The weighted total harmonic distortion WTHD of the 11L-SC2LHB VSC was significantly lower than that of other topologies due to the eleven-level characteristic of its output voltage. In the second comparison, a constant installed switch power SS as well as an equal output current (Iph,rms,1 = 600A) and a constant converter output power SC with line-to-line output voltages of 2.3kV, 3.3kV, and 4.16kV have been assumed to calculate the maximum carrier frequency fC,max of the considered converter topologies. The simulation results illustrate that the SC2LHB VSCs realized a higher maximum carrier frequency than that of all investigated topologies for all the considered line-to-line output voltages. Moreover, the first carrier band f1Cb of the line-to-line output voltage of the 5L-, 7L-, and 9L-SC2LHB VSC occurred around 6.34kHz, 7.8kHz, and 27.6kHz at fC = 450Hz, and 12.2kHz, 31.5kHz, and 61.6kHz at fC = 1000Hz respectively. Thus, for all considered output voltage classes, the SC2LHB VSCs could enable the smallest sine output filters, compared to other topologies. When comparing the WTHD at the maximum possible carrier frequency, the 9L-SC2LHB VSC featured the minimum value, since the harmonics of the first carrier band (f1Cb = 27.6kHz at fC = 450Hz, and f1Cb = 61.6kHz at fC = 1000Hz) are strongly damped. The conditions for the third comparison were the constant installed switch power SS as well as the constant frequency of the first harmonic carrier band f1Cb, which enables the design of an
144
CONCLUSION AND DISCUSSION
output filter of about the same size and cost. To place the first harmonic carrier band at the frequency occurring in the 3L-NPC VSC (f1Cb = fC = 450Hz / 1000Hz), the carrier frequencies of the different topologies have been reduced. The maximum apparent converter output power SC,max of the 5L-, 7L-, and 9L-SC2LHB VSCs have been increased by 15%, 10.5%, and 37% at fC = 450Hz and by 34.3%, 74.3%, and 119.4% at fC = 1000Hz, in comparison to the 3L-NPC VSC in the corresponding output voltage classes of 2.3kV, 3.3kV, and 4.16kV. In comparison to the corresponding 3L-NPC VSC topologies, the switching losses of the 5L-, 7L-, and 9LSC2LHB VSCs were significantly lower due to using the 1.7kV-IGBTs (for example, by 76% for 2.3kV, by 88% for 3.3kV, and by 94% for 4.16kV at fC = 450Hz), while their conduction losses were increased (for example, by 5% for 2.3kV, by 118% for 3.3kV, and by 70% for 4.16kV at fC = 450Hz). Both the THD and the WTHD of the 9L-SC2LHB VSC were still the smallest, since the distortion of the output voltage was at a minimum due to the applied ninelevels (fC = 450Hz). The conditions for the fourth comparison were a constant converter efficiency of about 99% at a constant converter power of SC = 4.32MVA, assuming a line-to-line voltage of 4.16kV for a medium switching frequency of fC = 450Hz in all considered topologies.The efficiency of the 3L-NPC VSC at fC = 450Hz was higher and there were thus smaller losses than in the other topologies. The comparison of 6.5kV IGBTs/diodes and a series connection of two 3.3kV IGBTs/diodes per switch position in a (4.16kV, 4.32MVA) 3L-NPC VSC and a 3L-FLC VSC shows that 3.3kV IGBT modules enable a substantially higher converter switch utilization and efficiency in the examined switching frequency range of fC 1kHz [29]. The application of a series connection of two 3.3kV IGBT/diode increased the installed switch power by 2.6% at a 277.8% higher switching frequency, compared to the use of 6.5kV IGBTs/diodes. The distribution of conduction and switching losses demonstrates that the series connection of 3.3kV IGBTs enable an almost equal share of switching and on state losses for fC = 1250Hz. In contrast, the high share of switching losses of 6.5kV IGBTs cause about two-thirds of the total losses at fC = 450Hz and a reduction of the installed switch power, because these devices are optimized for distinctly lower switching frequencies. A maximum first carrier band frequency of f1Cb = 900Hz can be achieved by supposing an installed switch power of SS = 101.06MVA. The unsymmetrical loss distribution within the 3L-NPC VSC [19], [28], [29], [119] and the additional neutral point clamp diodes are the reason for the 3L-NPC VSC requiring the highest installed switch power among the different ML topologies. In comparison to the 3L-NPC VSC, the installed switch powers of the FLC VSCs are reduced and the maximum first carrier band frequencies of the 3L-FLC VSC as well as 4L-FLC VSC are increased. However, both of the FLC VSCs required a substantial expense of flying capacitors at low and medium switching frequencies. Therefore, the flying capacitor topology is not competitive in applications that require only low and medium switching frequencies (f1Cb 1500-1800Hz) [29]. Still, the symmetrical semiconductor loss distribution and the resulting high first carrier band frequency of the converter voltage make this topology attractive for high speed drives or applications with very low current ripple requirements (e.g. test benches) [29]. The 9L-SC2LHB VSC requires a lower installed switch power than the 3L-NPC VSC (by 23.5% at fC = 1250Hz, applying two series connection of a 3.3kV IGBT/diode). Furthermore, an extremely low share of switching losses and an extraordinary high maximum first carrier band of the line-to-line output voltage of the 9L-SC2LHB VSC (f1Cb = 9240Hz) can be achieved at a given installed switch power. Hence, an output filter of the 9L-SC2LHB VSC could be smaller than the corresponding filters of other topologies. When taking only the 3L-NPC VSC and the SC2LHB VSCs into account, the 5L-, 7L-, and 9LSC2LHB VSCs generate higher converter losses than the corresponding 3L-NPC VSCs in the output voltage classes of 2.3kV, 3.3kV, and 4.16kV, assuming a constant carrier frequency
CONCLUSION AND DISCUSSION
145
(450Hz, 750Hz, and 1050Hz) and a constant phase current (Iph,rms,1 = 600A), while the converter losses of the 11L-SC2LHB VSC are reduced by 8% at fC = 450Hz, 13.2% at fC = 750Hz, and 18.9% at fC = 1050Hz, compared to the 3L-NPC VSCs for a line-to-line output voltage of 6kV. Furthermore, the switching losses of the SC2LHB topologies are significantly lower (11%, 39%, 59%, and 59% at fC = 450Hz) than those of the 3L-NPC VSCs in all considered output voltage classes (2.3kV, 3.3kV, 4.16kV, and 6kV) and carrier frequencies (450Hz, 750Hz, and 1050Hz), whereas the conduction losses of the SC2LHB VSCs are increased in all considered carrier frequencies and output voltage classes (16%, 145%, 121%, and 27% at fC = 750Hz). Thus, for all examined output voltage classes and carrier frequencies, the SC2LHB VSCs enable a minimum installed switch power, which is decreased, for example, by 18% for 2.3kV, 38% for 3.3kV, 50% for 4.16kV, and 62% for 6kV at the carrier frequency of fC = 1050Hz. In the last section, the dimensioning of the dc link capacitor has been investigated for a 24pulse, 4,16kV, 4.32MVA, 3L-NPC VSC and the 9L-SC2LHB VSC, assuming the dc link voltage ripples of 5% and the dc link capacitor storage energy of 6J/kVA and 12J/kVA at fC = 750Hz. The simulation results show that the maximum value of the ripple current occurred at modulation index ma = 0.6 and load angle = 0, 180 for the 3L-NPC VSC, and ma = 1.15 and = 90 for the 9L-SC2LHB VSC. It is to remark that the dc link voltage ripple and the dc link current are about 1.3% and 4.96% for the stored energy of 6J/kVA, while they enable a reduction by 55% and by 47.6% at twice the stored energy for the 3L-NPC VSC. Furthermore, the dc link voltage ripple of each H-bridge cell of the 9L-SC2LHB VSC is larger than the acceptable value of 5%, assuming a stored energy of 6-12J/kVA. Therefore, in order to place the dc link voltage ripple at a permissible limit, an increase in the dc link capacitor by the factor of 2.8 and a recalculation of the stored energy of 34J/kVA are necessary, compared to the stored energy of 12J/kVA. In conclusion, the 3L-NPC VSC is a competitive and widely used topology for a large variety of low and medium switching frequency applications (e.g. fC 1500Hz) in a voltage range of 2.3kV Vll 4kV [29]. A simple grid transformer, a small dc link capacitor, and the possible modular realization of common dc bus configurations are attractive additional features of this topology [119]. However, for the more than three-level configuration, the NPC voltage imbalance problem cannot be overcome by utilizing control techniques. Therefore, an increase of the output voltage of the 3L-NPC-VSC requires the use of the series connection of commercially available 3.3kV-6.5kV IGBTs or IGCTs or development of new devices with increased blocking voltages (e.g. 10kV IGCTs) [28]. is makes the NPC unsuccessful in high voltage applications. To synthesize the same number of voltage levels, the SC2LHB requires the least number of total main components. Another dominant advantage of the SC2LHB is its circuit layout flexibility. Each level has the same structure and there are no extra clamping diodes or voltage balancing capacitors, which are required in the NPC and the FLC topologies. The number of output voltage levels can then be easily adjusted by changing the number of H-bridge cells. Moreover, redundancy can be easily applied to enhance the reliability of the entire system. The high converter switch utilization, the high maximum carrier frequencies, and the low total harmonic distortions of the converter voltage and current are attractive features of the SC2LHB VSC topology, compared to the 3LNPC VSC which is widely used in MV applications today. The modular topology structure of the SC2LHB enables a simple extension of the converter voltage range to Ull,rms,1 > 4kV [29]. However, the high number of semiconductors, a complex and expensive multi-pulse isolation transformer, increased dc link capacitance values and the absence of a common dc voltage bus are disadvantages of this topology [29], [119]. Overall, the SC2LHB VSC is an attractive topology for manifold MVDs, including high speed drives [29].
APPENDIX A
A.1. MODULATION METHOD There are different PWM methods which have been extended for the use in H-bridge converters by using multiple carriers. These methods are described in many publications in the technical literature [26-32]. They can be categorized into three groups: Phase Shifted (PS), which is linked to FLC VSC and SCHB VSCs, Carrier Disposition (CD), which is used for NPC VSC, and Hybrid (H) methods. The following subsections describe these methods. I. Phase Shifted (PS) Method
This PWM method uses four carrier signals of the same amplitude and frequency, which are phase shifted by TC/4, where TC is the period of the carrier signal. The modulation method for a 5-level H-Bridge is shown in Figure A-2a. II. Carrier Disposition (CD) Methods
This carrier disposition can be classified into the following three methods, which are usually applied to the neutral point clamped topology [33], [34]. These methods may not be used naturally for the H-Bridge converter applications. However, an implementation strategy has been suggested to apply PD method to the H-Bridge converter [31], which uses discontinuous PWM reference signals with phase-shifted carriers. 1. Phase Disposition (PD) Method: This PD method has all carrier waveforms in phase, as shown in Figure A-2b. The zero reference is placed in the middle of the carrier sets. 2. Phase Opposition Disposition (POD) Method: With the POD method the carrier waveforms above or below the zero reference value are in phase. However, they are phase shifted by 180 between the carrier waveforms above and below zero, as shown in Figure A-2c. 3. Alternative Phase Opposition Disposition (APOD) Method: All carrier waveforms in this APOD method are phase-displaced by 180 alternatively, as shown in Figure A-1d. III. Hybrid (H) method This method is the combination of the PS and CD methods [30], [35]. Figure A-2e shows a triangular carrier, which is divided into a set of carrier signals. The gate signal of one switch is determined by the comparison of this set of carrier signals and the reference signal. The gate signals for the remaining switches are generated by phase shifting the set of carriers by TC/4 of the carrier set frequency. IV. Space vector method
The space vector modulation (SVM) is based on the description of symmetrical three-phase systems in the - reference frame. The three-phase reference voltages are represented as a single reference phasor with constant length and angular speed. It substitutes the demanded voltage space vectors by the nearest real voltage space vectors in an appropriate combination in each sampling interval. The basic principles of the SVM are shown in Figure A-1 for threelevel converters, which involves 27 different converter switch states (= number of level)3.
148
APPENDIX A
A.2. Output Waveforms and Spectrum The line-to-line output voltage waveform of the 5L-H-Bridge VSC is depicted in Figure A-2 (ei) for different PWM methods. The spectra of the line-to-line output voltage waveforms are depicted in Figure A-3 at ma = 1.15 and m f = 15 for different PWM methods.
Compared to the PWM modulation method for an 5L-H-Bridge converter, the CD methods have unbalanced switch utilization, dependent on ma , and the first carrier band of the line-toline voltage centred around in the carrier frequency. In contrast, the PS method offers a balanced switch utilization and simple implementation. The first carrier band of the line-to-line voltage for the PS and H methods is centred around four times the carrier frequency. Although, the H method has the same switch utilization as the PS method, it is the most complex to implement.
- +0+++ -
-+ 0
0 +0 -0-
++ 0 00 -
+0-
- ++
0 ++ - 00
--000 +++
Vref + 00 0 --
+ --
-0+
00 + --0
+0 + 0-0
+-0
-- +
0-+
+-+
Figure A-1 Space vector modulation of three-level converters
APPENDIX A
149
(a) Udc Udc / 2 0 -Udc / 2 -Udc (b) Udc Udc / 2 0 -Udc / 2 -Udc (c) Udc Udc / 2 0 -Udc / 2 -Udc (d) Udc Udc / 2 0 -Udc / 2 -Udc (e) Udc Udc / 2 0 -Udc / 2 -Udc 0 90 H 180 APOD POD PD PS
2Udc Udc 0 -Udc -2Udc 2Udc Udc 0 -Udc -2Udc 2Udc Udc 0 -Udc -2Udc 2Udc Udc 0 -Udc -2Udc 2Udc Udc 0 -Udc -2Udc 0 H APOD POD PD PS
(e)
(f)
(g)
(h)
(i)
180
360
Figure A-2 Different PWM methods and their line-to-line output voltage waveforms of the 5L-HBridge VSC
150
APPENDIX A
100 10-1 10-2 10-3 100
(a)
(U ab )h
U dc
PS
mf = 15, ma = 1.15
(b)
(U ab )h
10-1
PD
mf = 15, ma = 1.15
U dc
10-2
100
(c)
(U ab )h
10-1
POD
mf = 15, ma = 1.15
U dc
10-2 100
(d)
(U ab )h
10-1
APOD
mf = 15, ma = 1.15
U dc
10-2 100
(e)
(U ab )h
10-1 10-2 0.005 1 mf
mf = 15, ma = 1.15
U dc
Harmonic Order
2mf
3mf
4mf
Figure A-3 Harmonic spectra of the line-to-line output voltage for the 5L-H-Bridge VSC
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Technische Universitt Berlin

Investigation and Comparison of Multi-Level Converters for Medium Voltage Applications

Seyed Saeed Fazel

Zur Erlangung des akademischen Grades eines

Tag der Einreichung: 11.07.2007

Seyed Saeed Fazel

Investigation and Comparison of Multi-Level Converters for Medium Voltage Applications

Seyed Saeed Fazel Berlin, July 2007

112 118 123

127 130 143 147 151

GLOSSARY OF SYMBOLS AND ACRONYMS

D jxi ,D jxi DTjkxi ,DTjkxi

VgTk,x ,VgTk,x ,VgT1j,xi ,VgT1j,xi

Acronyms and Abbreviations

2. OVERVIEW OF MEDIUM VOLTAGE CONVERTER TOPOLOGIES

OVERVIEW OF MEDIUM VOLTAGE CONVERTER TOPOLOGIES

OVERVIEW OF MEDIUM VOLTAGE CONVERTER TOPOLOGIES

(a) Cabinet of Siemens (SIMOVERT MV)

(b) Cabinet of ASI Robicon (Perfect Harmony)

OVERVIEW OF MEDIUM VOLTAGE CONVERTER TOPOLOGIES

OVERVIEW OF MEDIUM VOLTAGE CONVERTER TOPOLOGIES

Power Semiconductors GTO

*: Asymetric blocking device

**: Reverse conducting device ***: Symetric blocking device

Schottky PIN Double (PIN)

BJT MOSFET IGBT

GTO IGCT GCT MCT MTO

Schottky JBS PIN

Low importance on the market today

Figure 2-3 Classification of state-of-the-art power semiconductors [21]

OVERVIEW OF MEDIUM VOLTAGE CONVERTER TOPOLOGIES

3. BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES

BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES

BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES

Switch positions for each phase of the two-level VSC

State Positive + (UxM = +Udc/2) Negative - (UxM = -Udc/2)

3.1.3. Sine-Triangle Modulation

BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES

BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES

-Udc 1 Vg1, a 0 1 Vg2, a 0 Udc / 2 UaM 0 (b)

-Udc / 2 Udc Uab (d)

-Udc Udc / 2 Udc / 6 0 -Udc / 6 -Udc / 2 0 90 180 270 360 (e)

BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES

0 1 Harmonic Magnitude (p.u.) 0.8 0.6 0.4 0.2 0

BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES

D(N-2)a S(N-2)a D(N-3)a S(N-3)a D2a S2a S1a iph,a a

BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES

D2a C2 Udc M1 C1 Uc2 idc1

Figure 3-6 Three-phase Three-Level Neutral Point Clamped Converter

3.2.1.1.1. Switch States and Commutations

BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES

Positive phase current

Negative phase current

BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES

S 2x U dc 2 D2 x E rec D1 x S2x S1 x S1x

BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES

Positive phase current

Negative phase current

3.2.1.1.2. Sine-Triangle Modulation

BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES

-Udc 1 Vg2, a 0 1 Vg1, a 0 Udc / 2 UaM1 0 (c) (b)

BASIC STRUCTURE AND FUNCTION OF VOLTAGE SOURCE CONVERTER TOPOLOGIES

1 U aM1 + U bM1 + U cM1 3

: Reverse conducting device *: Symetric blocking device