EXPT NO:1(a)

DESIGN OF HALF ADDER AND FULL ADDER USING VHDL

DATE:30.07.2011

AIM:
To design the program for half adder and full adder using VHDL

PROGRAM FOR HALF ADDER USING VHDL:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity halfadd is
port(a,b:in std_logic;
s,cout:out std_logic);
end halfadd;
architecture behavioral of halfadd is
begin
s <= a xor b;
cout <= a and b;
end behavioral;

HALF ADDER:

TRUTH TABLE:

OUTPUT:

SUM

CARRY

PROGRAM FOR FULL ADDER USING VHDL:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fulladd is
port(a,b,c:in std_logic;
s,cout:out std_logic);
end fulladd;
architecture behavioral of fulladd is
begin
s <= a xor b xor c;
cout <= (a and b) or ((a xor b) and c);
end behavioral;

FULL ADDER:

TRUTH TABLE:
A

SUM

CARRY

OUTPUT:

RESULT:
Thus the program for halfadder & Full adder was simulated by
using VHDL and verified successfully.

EXPT NO:1(b) DESIGN OF HALF ADDER AND FULL ADDER USING VERILOG

DATE:30.07.2011

AIM:

To design the program for half adder and full adder using verilog

PROGRAM FOR HALF ADDER USING VERILOG:

module half_adder(a, b, sum, carry);

input a;
input b;
output sum;
output carry;
xor g1(sum,a,b);
and g2(carry,a,b);
endmodule

HALF ADDER:

TRUTH TABLE:

SUM

CARRY

OUTPUT:

PROGRAM FOR FULL ADDER USING VERILOG:

module full_adder(a, b,cin, sum, carry);

input a;
input b;
input cin;
output sum;
output carry;
wire e,f,g;
xor g1(e,a,b);
xor g2(sum,e,cin);
and g3(f,a,b);
and g4(g,e,cin);
or g5(carry,f,g);
endmodule
FULL ADDER :

TRUTH TABLE:

SUM

CARRY

OUTPUT:

RESULT:
Thus the program for halfadder & Full adder was simulated by
using VERILOG and verified successfully.

EXPT NO:2(a) DESIGN OF HALF SUBTRACTOR AND FULL SUBTRACTOR USING

DATE:13.08.2011

VHDL

AIM:

To design the program for half subtractor and full subtractor using VHDL

PROGRAM FOR HALF SUBTRACTOR USING VHDL:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity hasub is
port(a,b:in std_logic;
d, bout:out std_logic);
end hasub;
architecture behavioral of hasub is
begin
d <= a xor b;
bout <= (not a) and b;
end behavioral;
HALF SUBTRACTOR:

TRUTH TABLE:

DIFFERENCE

BORROW

OUTPUT:

PROGRAM FOR FULL SUBTRACTOR USING VHDL:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fulsub1 is
port(a,b,c:in std_logic;
d, bout:out std_logic);
end fulsub1;
architecture behavioral of fulsub1 is
begin
d <= a xor b xor c;
bout <= ((not a) and b) or ((not (a xor b)) and c) ;
end behavioral;
FULL SUBTRACTOR:

TRUTH TABLE:

DIFFERENCE

BORROW

OUTPUT:

RESULT:
Thus the program for halfsubtractor& Fullsubtractorwas simulated
by using VHDL and verified successfully.

EXPT NO:2(b)DESIGN OF HALF SUBTRACTOR AND FULL SUBTRACTOR USING

DATE:13.08.2011

VERILOG

AIM:
To design the program for half subtractor and full subtractor using verilog

PROGRAM FOR HALF SUBTRACTOR USING VERILOG:

module half_sub(a,b,diff,bout);
input a,b;
output diff,bout;
wire c;
xor g1(diff,a,b);
not g2(c,a);
and g3(bout c,b);
endmodule
HALF SUBTRACTOR

TRUTH TABLE:

OUTPUT:

DIFFERENCE

BORROW

PROGRAM FOR FULL SUBTRACTOR USING VERILOG:

module ful_sub(a,b,cin,diff,bout);
input a,b,cin;
output diff,bout;
wire e,f,g,h,i;
xor g1(e,a,b);
xor g2(diff,e,cin);
not g3(f,a);
not g4(g,e);
and g5(h,f,b);
and g6(i,g,cin);
or g7(bout,i,h);
endmodule
FULL SUBTRACTOR:

TRUTH TABLE:

DIFFERENCE

BORROW

OUTPUT:

RESULT:
Thus the program for halfsubtractor& Fullsubtractorwas simulated
by using VERILOG and verified successfully.

EXPT NO:3(a)DESIGN OF MULTIPLEXER AND DEMULTIPLEXER USING VHDL

DATE:20.08.2011

AIM:

To design the program for multiplexer and demultiplexer using VHDL

PROGRAM FOR MULTIPLEXER USING VHDL:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity multip is
port (a,b,c,d,s1,s0:in std_logic;
y :out std_logic);
end multip;
architecture behavioral of multip is
signal e,f,g,h,i,j : std_logic;
begin
y <= g or h or i or j;
e <= not s1;
f <= not s0;
g <= a and e and f;
h <= b and e and s0;
i <= c and s1 and f;
j <= d and s1 and s0;
end behavioral;

MULTIPLEXER

TRUTH TABLE:

S1

S0

OUTPUT

D0

D1

D2

D3

OUTPUT:

PROGRAM FOR DEMULTIPLEXER USING VHDL:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity demulti is
port (x,s1,s0:in std_logic;
a,b,c,d :out std_logic);
end demulti;
architecture behavioral of demulti is
signal e,f : std_logic;
begin
e <= not s1;
f <= not s0;
a <= x and e and f;
b <= x and e and s0;
c <= x and s1 and f;
d <= x and s1 and s0;
end behavioral;
DEMULTIPLEXER

TRUTH TABLE:

S1
0
0
0
0
1
1
1
1

S0
0
0
1
1
0
0
1
1

I/P
0
1
0
1
0
1
0
1

D0
0
1
0
0
0
0
0
0

D1
0
0
0
1
0
0
0
0

D2
0
0
0
0
0
1
0
0

D3
0
0
0
0
0
0
0
1

OUTPUT:

RESULT:
Thus the program for Multiplexer& Demultiplexerwas simulated
by using VHDL and verified successfully.

EXPT NO:3(b) DESIGN OF MULTIPLEXER AND DEMULTIPLEXER USING VERILOG

DATE:20.08.11

AIM:
To design the program for multiplexer and demultiplexer using verilog

PROGRAM FOR MULTIPLEXER USING VERILOG:

module mux_4(s,d,y);
input [1:0]s;
input [3:0]d;
output y;
wire a,b,c,e,f,g;
not g1(a,s[1]);
not g2(b,s[0]);
and g3(c,a,b,d[0]);
and g4(e,a,s[0],d[1]);
and g5(f,s[1],b,d[2]);
and g6(g,s[1],s[0],d[3]);
or g7(y,c,e,f,g);
endmodule

MULTIPLEXER

TRUTH TABLE:

OUTPUT:

S1

S0

OUTPUT

D0

D1

D2

D3

PROGRAM FOR DEMULTIPLEXER USING VERILOG:

module dmux_4(s,d,y);
input [1:0]s;
input d;
output [3:0]y;
wire a,b;
not g1(a,s[1]);
not g2(b,s[0]);
and g3(y[0],a,b,d);
and g4(y[1],a,s[0],d);
and g5(y[2],s[1],b,d);
and g6(y[3],s[1],s[0],d);
endmodule

DEMULTIPLEXER:

TRUTH TABLE:

S1
0
0
0
0
1
1
1
1

S0
0
0
1
1
0
0
1
1

I/P
0
1
0
1
0
1
0
1

D0
0
1
0
0
0
0
0
0

D1
0
0
0
1
0
0
0
0

D2
0
0
0
0
0
1
0
0

D3
0
0
0
0
0
0
0
1

OUTPUT:

RESULT:
Thus the program for Multiplexer& Demultiplexerwas simulated
by using Verilog and verified successfully.

EXPT NO:4(a)DESIGN OF ENCODER AND DECODER USING VHDL

DATE:27.08.2011

AIM:
To design the program for encoder and decoder using VHDL

PROGRAM FOR ENCODER USING VHDL:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity encoder is
port (x0,x1,x2,x3,x4,x5,x6,x7:in std_logic;
a,b,c :out std_logic);
end encoder;
architecture behavioral of encoder is
begin
a <= x4 or x5 or x6 or x7;
b <= x2 or x3 or x6 or x7;
c <= x1 or x3 or x5 or x7;
end behavioral;

ENCODER :

TRUTH TABLE:
INPUTS

OUTPUTS

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

OUTPUT:

PROGRAM FOR DECODER USING VHDL:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port (a,b,c:in std_logic;
x0,x1,x2,x3,x4,x5,x6,x7 :out std_logic);
end decoder;
architecture behavioral of decoder is
signal e,f,g: std_logic;
begin
e <= not a;
f <= not b;
g <= not c;
x0 <= e and f and g;
x1 <= e and f and c;
x2 <= e and b and g;
x3 <= e and b and c;
x4 <= a and f and g;
x5 <= a and f and c;
x6 <= a and b and g;
x7 <= a and b and c;
end behavioral;

DECODER:

TRUTH TABLE:

OUTPUT:

D0

D1

D2

D3

RESULT:
Thus the program for encoder& decoderwas simulated by using
VHDL and verified successfully.

EXPT NO:4(b)DESIGN OF ENCODER AND DECODER USING VERILOG

DATE:27.08.2011
AIM:
To design the program for encoder and decoder using verilog
PROGRAM FOR ENCODER USING VERILOG:
module encoder8(x,y);
input [7:0]x;
output [2:0]y;
or g1(y[0],x[1],x[3],x[5],x[7]);
or g2(y[1],x[2],x[3],x[6],x[7]);
or g3(y[2],x[4],x[5],x[6],x[7]);
endmodule
ENCODER:

TRUTH TABLE:
INPUTS

OUTPUTS

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

OUTPUT:

PROGRAM FOR DECODER USING VERILOG:

module decoder4(a,b,en,y);
input a,b;

input en;
output [3:0]y;
wire c,d;
not g1(c,a);
not g2(d,b);
and g3(y[0],c,d,en);
and g4(y[1],c,b,en);
and g5(y[2],a,d,en);
and g6(y[3],a,b,en);
endmodule
DECODER:

TRUTH TABLE:

D0

D1

D2

D3

OUTPUT:

RESULT:
Thus the program for encoder& decoderwas simulated by using
verilog and verified successfully.
EXPT NO:5(a)DESIGN OF D - FLIP FLOP, T- FLIP FLOP, JK- FLIP FLOP AND SR-

DATE:10.09.2011

FLIPFLOP USING VHDL

AIM:
To design the program for D - Flip Flop, T- Flip Flop, JK- Flip Flop and SRFlip Flop using VHDL

PROGRAM FOR D FLIP FLOP USING VHDL:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dff is
port( d, clk,rst:in std_logic;
q,qbar: inout std_logic);
end dff;
architecture behavioral of dff is
begin
process(clk)
begin
if rst ='1' then
q <= '0';
qbar <= '1';
else if clk'event and clk = '1' then
q <= d;
qbar <= not(d);
end if;
end if;
end process;
end behavioral;

D-FLIPFLOP:

TRUTH TABLE:
D
0
1

Q
X
X

Qn
0
1

OUTPUT:

PROGRAM FOR T FLIP FLOP USING VHDL:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tff is
port( t:in std_logic;
clk,rst:in std_logic;
q,qbar: inout std_logic);
end tff;
architecture behavioral of tff is
begin
process(clk)
begin
if rst ='1' then
q <= '0';
qbar <= '1';
else if clk'event and clk = '1' then
if t ='0' then
q <=q;
qbar <= qbar;
else
q <= qbar;
qbar <= q;
end if;
end if
end if;
end process;
end behavioral;
T-FLIP FLOP:

TRUTH TABLE:

OUTPUT:

Commen
t
Hold
state
Hold
state

Qnext

Toggle

Toggle

PROGRAM FOR JK FLIP FLOP USING VHDL:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jk_ff is
port ( clk : in std_logic;
jk : in std_logic_vector(1 downto 0);
q, qb : out std_logic);
end jk_ff;
architecture Behavioral of jk_ff is
begin
process(clk)
variable temp1, temp2 : std_logic;
begin
if rising_edge(clk) then
case jk is
when "01"=> temp1 :='0';
when "10"=> temp1 :='1';
when "00"=> temp1 := temp1;
when "11"=>temp1 := not temp1;
when others => null;
end case;
q<= temp1;
temp2 := not temp1;
qb <= temp2;
end if;
end process ;
end Behavioral

JK- FLIPFLOP:

TRUTH TABLE:
J
0
0
0
0
1
1
1
1

K
0
0
1
1
0
0
1
1

Q
0
1
0
1
0
1
0
1

Qn
0
1
0
0
1
1
1
0

OUTPUT:

PROGRAM FOR SR FLIP FLOP USING VHDL:

Comment
No Change
No Change
Reset
Reset
Set
Set
Toggle
Toggle

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity SR_ff is
port ( clk, s, r : in std_logic;
q : buffer std_logic);
end SR_ff;
architecture Behavioral of SR_ff is
begin
process( clk)
begin
if (clk'event and clk = '1') then
if (s='0' and r='0')then q<= q;
elsif (s='0' and r='1')then q<= '0';
elsif (s='1' and r='0')then q<= '1';
elsif (s='1' and r='1')then q<= 'Z';
end if ;
end if;
end process ;
end Behavioral;

SR- FLIPFLOP:

TRUTH TABLE:
S
0
0
0
0
1
1

R
0
0
1
1
0
0

Q
0
1
0
1
0
1

Qn
0
1
0
0
1
1

Comment
No Change
No Change
Reset
Reset
Set
Set
Indetermin
e
Indetermiin
e

OUTPUT:

RESULT:
Thus the program for D-flipflop,T-flipflop,JK-flipflop,SR-flipflop
was simulated by using VHDL and verified successfully.

EXPT NO:5(b)DESIGN OF D - FLIP FLOP,T- FLIP FLOP,JK- FLIP FLOPAND

DATE:10.09.2011

SR-FLIPFLOP USING VERILOG

AIM:
To design the program for D - Flip Flop, T- Flip Flop, JK- Flip Flop and SRFlip Flop using verilog

PROGRAM FOR D FLIP FLOP USING VERILOG:

module d_ff (q,d,clk,clr) ;
output q ;
input d,clk,clr ;
reg q ;
always @ (posedge clk)
if (~clr) q = 0 ;
else q = d ;
endmodule
D-FLIPFLOP:

TRUTH TABLE:

D
0
1

OUTPUT:

Q
X
X

Qn
0
1

PROGRAM FOR T FLIP FLOP USING VERILOG:

module t_ff (q,t,clk,clr,rst) ;
output q ;
input t,clk,clr,rst ;
reg q ;
always @ (posedge clk or negedge rst)
if (~clr) q = 0 ;
else
assign q = t^q ;
endmodule.
T- FLIPFLOP:

TRUTH TABLE:

OUTPUT:

Commen
t
Hold
state
Hold
state

Qnext

Toggle

Toggle

PROGRAM FOR JK FLIP FLOP USING VERILOG:

module jkff(jk, clk, q, qb);
input [1:0]jk;
input clk;
output q, qb;
reg q, qb;
always@(posedge clk)
begin
case (jk)
2'd1:q=q;
2'd1:q=0;
2'd2:q=1;
2'd3:q=~q;
endcase
qb=~q;
end
endmodule

JK- FLIPFLOP:

TRUTH TABLE:
J
0
0
0
0
1
1
1
1

OUTPUT:

K
0
0
1
1
0
0
1
1

Q
0
1
0
1
0
1
0
1

Qn
0
1
0
0
1
1
1
0

Comment
No Change
No Change
Reset
Reset
Set
Set
Toggle
Toggle

PROGRAM FOR SR FLIP FLOP USING VERILOG:

module srff(sr, clk, q, qb);
input [1:0] sr;
input clk;
output q, qb;
reg q,qb;
always@(posedge clk)
begin
case (s,r)
2'd0 : q= q;
2'd1 : q=0;
2'd2 : q=1;
2'd3 : q=q;
endcase
qb=~q;
end
endmodule.
SR FLIPFLOP:

TRUTH TABLE:
S
0
0
0
0
1
1

R
0
0
1
1
0
0

Q
0
1
0
1
0
1

Qn
0
1
0
0
1
1

Comment
No Change
No Change
Reset
Reset
Set
Set
Indetermin
e
Indetermiin
e

OUTPUT:

RESULT:
Thus the program for D-flipflop,T-flipflop,JK-flipflop,SR-flipflop
was simulated by using VHDL and verified successfully.
EXPT NO:6(a)DESIGN OF UP/DOWN SYNCHRONOUS COUNTERUSING VHDL
DATE:24.09.2011

AIM:
To design the program for UP/DOWN synchronous counter using VHDL
PROGRAM FOR SYNCHRONOUS UP COUNTER USING VHDL:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(clk, clr: in std_logic;
q: out std_logic_vector(3 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process(clk,clr)
begin
if(clr ='1') then
tmp <= "0000";
else if clk'event and clk='1' then
tmp <= tmp+1;
end if;
end if;
end process;
q <= tmp;
end archi;

SYNCHRONOUS UP COUNTER:

TRUTH TABLE:
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

QD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

QC
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

QB
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

QA
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

OUTPUT:

PROGRAM FOR SYNCHRONOUS DOWN COUNTER USING VHDL:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(clk, clr: in std_logic;
q: out std_logic_vector(3 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process(clk,clr)
begin
if(clr ='1') then
tmp <= "1111";
else if clk'event and clk='1' then
tmp <= tmp-1;
end if;
end if;
end process;
q <= tmp;
end archi;

SYNCHRONOUS DOWN COUNTER:

TRUTH TABLE:

CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

QD
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

QC
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

QB
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

QA
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

OUTPUT:

RESULT:
Thus the program for synchronous UP/DOWN counter simulated
by using VHDL module and verified successfully.
EXPT NO: 6(b)DESIGN OF UP/DOWN SYNCHRONOUS COUNTERUSING VERILOG

DATE:24.09.2011

AIM:
To design the program for UP/DOWN synchronous counter using VHDL
PROGRAM FOR SYNCHRONOUS UP COUNTER USING VERILOG:
module up_counter(q,clk,clr);
output [3:0] q;
input clk, clr;
reg [3:0] q;
always @(posedge clk)
if (clr) begin
q <= 4'b0 ;
end
else
begin
q <= q + 1;
end
endmodule.
SYNCHRONOUS UP COUNTER:

TRUTH TABLE:

CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

QD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

QC
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

QB
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

QA
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

OUTPUT:

PROGRAM FOR SYNCHRONOUS DOWN COUNTER USING VERILOG:

module down_counter(q,clk,clr);
output [3:0] q;
input clk, clr;
reg [3:0] q;
always @(posedge clk)
if (clr)
begin
q <= 4'b1111 ;
end
else
begin
q <= q - 1;
end
endmodule

SYNCHRONOUS DOWN COUNTER:

TRUTH TABLE:

CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

QD
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

QC
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

QB
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

QA
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

OUTPUT:

RESULT:
Thus the program for synchronous UP/DOWN counter simulated
by using verilog module and verified successfully.
EXPT NO:7(a)DESIGN OF 4 BIT RIPPLE COUNTERUSING VHDL

DATE:08.10.2011

AIM:
To design the program for 4 bit Ripple counter using VHDL

PROGRAM FOR 4 BIT RIPPLE COUNTER USING VHDL:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port(clk, clr : in std_logic;
q : out std_logic_vector(3 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (clk, clr)
begin
if (clr='1') then
tmp <= "0000";
elsif (clk'event and clk='1') then
tmp <= tmp + 1;
end if;
end process;
q <= tmp;
end archi;

4 BIT RIPPLE COUNTER:

TRUTH TABLE:
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

QD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

QC
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

QB
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

QA
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

OUTPUT:

RESULT:
Thus the program for 4-bit ripple counter was simulated by using
VHDL module and verified successfully.
EXPT NO:7(b)

DESIGN OF 4 BIT RIPPLE COUNTER USING VERILOG

DATE:08.10.2011

AIM:
To design the program for 4 bit ripple counter using verilog
PROGRAM FOR 4 BIT RIPPLE COUNTER USING VERILOG:
module co(q,clk,clr);
input clk,clr;
output[3:0]q;
reg[3:0]q;
always@(posedge clr or negedge clk)
begin
if(clr)
q<=4'b0000;
else
q<=q+1;
end
endmodule.
4 BIT RIPPLE COUNTER:

TRUTH TABLE:

CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

QD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

QC
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

QB
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

QA
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

OUTPUT:

RESULT:
Thus the program for 4-bit ripple counter was simulated by using
Verilog module and verified successfully.
EXPT NO:8(a)

DESIGN OF RING COUNTER AND BCD COUNTER USING VHDL

DATE:15.10.2011

AIM:
To design the program for ring counter and BCD counter using VHDL
PROGRAM FOR RING COUNTER USING VHDL:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ringc is
Port ( clk,rst : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end ringc;
architecture Behavioral of ringc is
signal r_reg: std_logic_vector(3 downto 0);
signal r_next: std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if(rst='1') then
r_reg<= (0=> '1', others =>'0');
elsif(clk'event and clk='1') then
r_reg<= r_next;
end if;
end process;
r_next<= r_reg(0) & r_reg(3 downto 1);
q<= r_reg;
end Behavioral;

RING COUNTER :

TRUTH TABLE:

CLK
0
1
2
3
4
5
6
7

QD
0
1
0
0
0
0
0
1

QC
0
0
1
0
0
0
1
0

OUTPUT:

PROGRAM FOR BCD COUNTER USING VHDL:

QB
0
0
0
1
0
1
0
0

QA
0
0
0
0
1
0
0
0

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter2_VHDL is
port( Clock_enable: in std_logic;
Clock: in std_logic;
Reset: in std_logic;
Output: out std_logic_vector(0 to 3));
end Counter2_VHDL;
architecture Behavioral of Counter2_VHDL is
signal temp: std_logic_vector(0 to 3);
begin process(Clock,Reset)
begin
if Reset='1' then
temp <= "0000";
elsif(Clock'event and Clock='1') then
if Clock_enable='0' then
if temp="1001" then
temp<="0000";
else
temp <= temp + 1;
end if;
else
temp <= temp;
end if;
end if;
end process;
Output <= temp;
end Behavioral;

BCD COUNTER:

TRUTH TABLE:
CLK
0
1
2
3
4
5
6
7
8
9
10

QD
0
0
0
0
0
0
0
0
1
1
0

QC
0
0
0
0
1
1
1
1
0
0
0

QB
0
0
1
1
0
0
1
1
0
0
0

QA
0
1
0
1
0
1
0
1
0
1
0

OUTPUT:

RESULT:
Thus the program for ring counter and BCD counter was simulated
by using VHDL and verified successfully.
EXPT NO:8(b)DESIGN OF RING COUNTER AND BCD COUNTER USING VERILOG

DATE:15.10.2011

AIM:
To design the program for ring counter and BCD counter using VHDL
PROGRAM FOR RING COUNTER USING VERILOG:
module ringc(count,load,i,clk,clr,a,c0);
input count,load;
input clk,clr;
input [3:0]i;
output[3:0]a;
output c0;
reg[3:0]a;
assign c0=count&~load&(a==4'b1111);
always@(posedge clk or negedge clr)
if(~clr)
a=4'b0000;
else if(load)
a=i;
else if(count)
a=a+1'b1;
else
a=a;
endmodule

RING COUNTER:

TRUTH TABLE:

CLK
0
1
2
3
4
5
6
7

QD
0
1
0
0
0
0
0
1

QC
0
0
1
0
0
0
1
0

QB
0
0
0
1
0
1
0
0

OUTPUT:

PROGRAM FOR BCD COUNTER USING VERILOG:

QA
0
0
0
0
1
0
0
0

module bcdcount(clk,clr,e,bcd1,bcd0);
input clk,clr,e;
output[3:0]bcd1,bcd0;
reg[3:0]bcd1,bcd0;
always@(posedge clk)
begin
if(clr)
begin
bcd1<=0;
bcd0<=0;
end
else if(e)
if(bcd0==4'b1001)
begin
bcd0<=0;
if(bcd1==4'b1001)
bcd1<=0;
else
bcd1<=bcd1+1;
end
else
bcd0<=bcd0+1;
end
endmodule

BCD COUNTER:

TRUTH TABLE:
CLK
0
1
2
3
4
5
6
7
8
9
10

QD
0
0
0
0
0
0
0
0
1
1
0

QC
0
0
0
0
1
1
1
1
0
0
0

QB
0
0
1
1
0
0
1
1
0
0
0

QA
0
1
0
1
0
1
0
1
0
1
0

OUTPUT:

RESULT:
Thus the program for ring counter and BCD counter was simulated
by using verilog and verified successfully.
EXPT NO:9(a)DESIGN OF JOHNSON COUNTER USING VHDL

DATE:22.10.2011

AIM:
To design the program for johnson counter using VHDL
PROGRAM FOR JOHNSON COUNTER USING VHDL:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity johnson_counter is
port (q : out unsigned(3 downto 0);
clr,clk : in std_logic; );
end johnson_counter;
architecture Behavioral of johnson_counter is
signal temp : unsigned(3 downto 0):=(others => '0');
begin
q <= temp;
process(clk)
begin
if( rising_edge(clk) ) then
if (clr = '1') then
temp <= (others => '0');
else
temp(1) <= temp(0);
temp(2) <= temp(1);
temp(3) <= temp(2);
temp(0) <= not temp(3);
end if;
end if;
end process;
end Behavioral;

JOHNSON COUNTER:

TRUTH TABLE:

CLK
0
1
2
3
4
5
6
7
8

QD
0
1
1
1
1
0
0
0
0

QC
0
0
1
1
1
1
0
0
0

QB
0
0
0
1
1
1
1
0
0

QA
0
0
0
0
1
1
1
1
0

OUTPUT:

RESULT:
Thus the program for Johnson counter was simulated by using
VHDL module and verified successfully.
EXPT NO:9(b)DESIGN OF JOHNSON COUNTER USING VERILOG

DATE:22.10.2011

AIM:
To design the program for johnson counter using verilog
PROGRAM FOR JOHNSON COUNTER USING VERILOG:
module johnson(count,termcount,clk,resetn);
parameter width=0;
output[width+3:0]count;
output termcount;
input clk, resetn;
reg[width+3:0]count;
reg termcount;
always@(posedge clk or negedge resetn)
begin
if(!resetn)
begin
count<=0;
termcount<=0;
end else
begin
count<={count[width+4:0],~count[width+3]};
termcount<=(count[width+3]==1&count[width+4]==0);
end
end
endmodule

JOHNSON COUNTER:

TRUTH TABLE:

CLK
0
1
2
3
4
5
6
7
8

QD
0
1
1
1
1
0
0
0
0

QC
0
0
1
1
1
1
0
0
0

QB
0
0
0
1
1
1
1
0
0

QA
0
0
0
0
1
1
1
1
0

OUTPUT:

RESULT:
Thus the program for Johnson counter was simulated by using
Verilog module and verified successfully.
EXPT NO:10(a)DESIGN OF 4 BIT SHIFT REGISTERUSING VHDL
DATE:05.11.2011

AIM:
To design the program for 4 bit shift register using VHDL
PROGRAM FOR 4 BIT SHIFT REGISTER USING VHDL:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Shift_register_VHDL is
port( Clock, L,w: in std_logic;
Output: out std_logic_vector(3 downto 0);
Input: in std_logic_vector( 3 downto 0));
end Shift_register_VHDL;
architecture Behavioral of Shift_register_VHDL is
signal temp: std_logic_vector(3 downto 0);
begin
process
begin
wait until Clock'event and Clock='1';
if L='1' then
temp <= Input;
else
for i in 0 to 2 loop
temp(i) <= temp(i+1);
end loop;
temp(3) <= w;
end if; end process;
Output <= temp;
end Behavioral;

4 BIT SHIFT REGISTER:

TRUTH TABLE:

CLK

DA
1
0
1

1
2
3

INPUTS
DB
DC
0
0
1
1
0
1

DD
1
1
0

QA
1
0
1

OUTPUTS
QB
QC
0
0
1
1
0
1

QD
1
1
0

OUTPUT:

RESULT:
Thus the program for 4 bit shift register was simulated by using VHDL
module and verified successfully.
EXPT NO: 10(b)DESIGN OF 4 BIT SHIFT REGISTER USING VERILOG
DATE:05.11.2011

AIM:
To design the program for 4 bit shift register using verilog
PROGRAM FOR 4 BIT SHIFT REGISTER USING VERILOG:
module shift4(r,l,w,clk,q);
input[3:0]r;
input l,w,clk;
output [3:0]q;
reg [3:0]q;
always@(posedge clk)
if(l)
q<=r;
else
begin
q[0]<=q[1];
q[1]<=q[2];
q[2]<=q[3];
q[3]<=w;
end
endmodule
4 BIT SHIFT REGISTER:

TRUTH TABLE:

CLK

DA
1
0
1

1
2
3

INPUTS
DB
DC
0
0
1
1
0
1

DD
1
1
0

QA
1
0
1

OUTPUTS
QB
QC
0
0
1
1
0
1

QD
1
1
0

OUTPUT:

RESULT:
Thus the program for 4 bit shift register was simulated by using Verilog
module and verified successfully.

EXPT NO: 11DESIGN OF MULTIPLEXER USING TEST BENCH USING VHDL

DATE:12.11.2011

AIM:
To design the program for multiplexer using test bench using VHDL
PROGRAM FOR MULTIPLEXER USING TEST BENCH USING VHDL:
module mux1(out,i0,i1,i2,i3,s1,s0);
output out;
input i0,i1,i2,i3;
input s1,s0;
wire s1n,s0n;
wire y0,y1,y2,y3;
not (s1n,s1); not (s0n,s0);
and (y0,i0,s1n,s0n); and (y1,i1,s1n,s0);
and (y2,i2,s1,s0n);
and (y3,i3,s1,s0);
or (out,y0,y1,y2,y3);
endmodule
module stimulus;
reg in0,in1,in2,in3; reg s1,s0;
wire output1; mux1(output1,in0,in1,in2,in3,s1,s0);
initial
begin
in0=1;in1=0;in2=1;in3=0;
#100$display
("in0=%b,in1=%b,in2=%b,in3=%b/n",in0,in1,in2,in3);
s1=0;s0=0;
#100$display
("s1=%b,s0=%b,output1=%b/n", s1,s0,output1);
s1=0;s0=1;
#100$display
("s1=%b,s0=%b,output1=%b/n", s1,s0,output1);
s1=1;s0=0;
#100$display
("s1=%b,s0=%b,output1=%b/n", s1,s0,output1);
s1=1;s0=1;
#100$display
("s1=%b,s0=%b,output1=%b/n", s1,s0,output1);
end

endmodule
OUTPUT:

RESULT:
Thus the program for multiplexer using testbench was simulated by
using VHDL and verified successfully.
EXPT NO:12(a)DESIGN OF ALU USING VHDL

DATE:19.11.2011

AIM:
To design the program for ALU using VHDL
PROGRAM FOR ALU USING VHDL:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity alu1 is
port(code:in std_logic_vector(2 downto 0);
a:in std_logic_vector(3 downto 0);
b:in std_logic_vector(3 downto 0);
c:out std_logic_vector(3 downto 0));
end alu1;
architecture behavioral of alu1 is
begin
process(code,a,b)
begin
case code is
when "000"=>
c <= "0000";
when "001"=>
c <= a+b;
when "010"=>
c <= a-b;
when "011"=>
c <= a and b;
when "101"=>
c <= not a;
when "110"=>
c <= a nand b;
when "111"=>
c <= a or b;
when others=>
c <= "1111";
end case;
end process;

end behavioral;
OUTPUT:

RESULT:
Thus the program for ALU was simulated by using VHDL and verified
successfully.
EXPT NO:11(b)
DATE:19.11.2011

DESIGN OF ALU USING VERILOG

AIM:
To design the program for ALU using verilog
PROGRAM FOR ALU USING VERILOG:
module alu(code,a,b,c);
input[2:0]code;
input[3:0]a,b;
output[3:0]c;
reg[3:0]c;
always@(code,a,b)
case(code)
3'b000: c="0000";
3'b001: c=a+b;
3'b010: c=a-b;
3'b011: c=a/b;
3'b100: c=~(a&b);
3'b101: c=~(a/b);
3'b110: c=a^b;
3'b111: c=~a;
endcase
endmodule
OUTPUT:

RESULT:
Thus the program for ALU was simulated by using Verilog and verified
successfully.