You are on page 1of 19

INDEX

S.No. DATE TITLE SIGN REMARK

EXPERIMENT: 1
OBJECTIVE: Plot DC Response, Transient Analysis for a pulse input and sinusoidal input of RTL
Inverter circuit using H SPICE Simulation tool. The design parameter are given below: (Vdd=5V; Vin= 1V; L=1um; W=90.9um; Vtn=1V; kn=22um gamma=0.2)

TOOL: H SPICE A-2008.0 3(32 BIT) THEORY:


RTL inverter implemented is using resistor-transistor logic, the earliest form of logic

implemented with transistors. When the input is high, the output is low, and vice versa. When the input is high a current flows from the drain to source of the NMOS transistor. So, the transistor is in saturation mode; it gets the collector voltage down to the saturation voltage which is almost equal to zero. When the input voltage the transistor is off, and the drain terminal stays at Vdd.

DIAGRAM:

NETLIST:
(1) HSPICE CODE FOR RTL INVERTER FOR DC INPUT ***RTL INVERTER*** VDD 3 0 DC 5 VIN 1 0 DC 0.1 R1 3 2 1K M1 2 1 0 0 NMOD ( W=90.9U L=1U) .MODEL NMOD NMOS (VT0=1 KP=22U GAMMA=0.2) .DC VIN 0 5 0.1 .PROBE .OPTION POST .END
2

SIMULATION RESULTS:

CONCLUSION: As the input voltage is varying for 0 to 5 volts the inverted output has been plotted in the above graph. The output stays at Vdd=5 till Vin is smaller than Vth ie 1V. After which the NMOS enters saturation region and output begins to drop. Eventually the NMOS enters triode region and output voltage continues to decrease.

(2) HSPICE CODE FOR RTL INVERTER WITH AC INPUT FOR PULSE INPUT ***RTL INVERTER*** VDD 3 0 DC 5 VIN 1 0 PULSE (0 5 0 0 0 10U 20U) R1 3 2 1K M1 2 1 0 0 NMOD ( W=90.9U L=1U) .MODEL NMOD NMOS (VT0=1 KP=22U GAMMA=0.2) .TRAN 0.1U 100U .PROBE .OPTION POST .END
3

SIMULATION RESULTS:

CONCLUSION: The transient analysis of the RTL inverter is obtained by applying a pulse input voltage of frequency 50kHz. The output is in accordance with the dynamic inverter characteristics.

(3) HSPICE CODE FOR RTL INVERTER WITH AC INPUT FOR SINOSOIDAL INPUT ***NMOS SIN*** VDD 3 0 DC 5 VIN 1 0 SIN ( 2V 0.3V 100KHZ ) R1 3 2 1K M1 2 1 0 0 NMOD W=90.9U L=1U .MODEL NMOD NMOS (VTO=1 KN=22U GAMMA=0.2) .TRAN 0.001U 100U .PLOT DC V(2) .PROBE .OPTION POST .END SIMULATION RESULTS:

CONCLUSION: The transient analysis of the RTL inverter is obtained using a sinusoidal input voltage of frequency 100kHz.The output is in accordance with the inverter characteristics. For negative cycle we have positive half cycle in output and vice versa.

RESULT:
The DC response and Transient response of an NMOS RTL Inverter for pulse and sinusoidal input was obtained using HSPICE.

EXPERIMENT: 2
OBJECTIVE: Plot the I-V characteristics for sinusoidal input and drain current of NMOS and PMOS
circuit by sweeping Gate voltage using HSPICE Simulation tool. The design parameter are given below ( Vdd=5V; Vin= 1V; L=1um; W=90.9um; Vtn=1V; kn=22um; gamma=0.2)

TOOL: H SPICE A-2008.0 3(32 BIT) (1) NMOS TRANSISTOR:


THEORY:

DIAGRAM:

(i) NETLIST:

I-V CHARACTERISTICS-

*** TRANSFER CHARACTERISTICS OF NMOS (ID VS VDS)*** VDS 2 0 DC 5 VGS 1 0 DC 3 M1 2 1 0 0 NMOD W=90U L=1U .MODEL NMOD NMOS (KN=20U VTO=0.7 LAMBDA=0.05) .DC VGS 0 5 100M .PLOT DC I(M1) V(2) .PROBE .OPTION POST .END

SIMULATION RESULTS:

CONCLUSION:

The I-V characteristics of NMOS transistor is obtained by varying input voltage VGS from 0 to 5V in steps of 0.1V. The drain current remains zero till the input voltage is less then threshold voltage that is 1 volt and after that the NMOS starts conducting and value of current increases.
(ii) DRAIN CURRENT BY SWEEPING GATE VOLTAGE

NETLIST: *** TRANSFER CHARACTERISTICS OF NMOS (ID VS VDS)*** VDS 2 0 DC 5 VGS 1 0 DC 3 M1 2 1 0 0 NMOD W=90U L=1U .MODEL NMOD NMOS (KN=20U VTO=0.7 LAMBDA=0.05) .DC VDS 0 5 100M SWEEP VGS 0 3 0.5 .PLOT DC I(M1) V(2) .PROBE
7

.OPTION POST .END

SIMULATION RESULTS:

CONCLUSION:

The variation in drain current on sweeping gate voltage is obtained by varying the gate voltage from 0 to 3 in steps of 1V. For each value of Vgs, Vds is varied from 0 to 5V.

(2) PMOS TRANSISTOR:THEORY:

DIAGRAM:

(i) I-V CHARACTERISTICS: NETLIST: *** TRANSFER CHARACTERISTICS OF PMOS (ID VS VDS)*** VDS 2 0 DC -5 VGS 1 0 DC -3 M1 0 1 2 0 PMOD W=90U L=1U
8

.MODEL PMOD PMOS (KP=22U VTO=-0.8 LAMBDA=0.2) .DC VGS 0 -5 100M .PLOT DC I(M1) V(2) .PROBE .OPTION POST .END SIMULATION RESULT:

CONCLUSION:

(ii) NETLIST:

DRAIN CURRENT BY SWEEPING GATE VOLTAGE-

*** TRANSFER CHARACTERISTICS OF PMOS (ID VS VDS)*** VDS 2 0 DC -5 VGS 1 0 DC -3 M1 0 1 2 0 PMOD W=90U L=1U .MODEL PMOD PMOS (KP=22U VTO=-0.8 LAMBDA=0.2) .DC VDS 0 -5 100M SWEEP VGS 0 -3 0.5 .PLOT DC I(M1) V(2)
9

.PROBE .OPTION POST .END SIMULATION RESULT:

CONCLUSION:

RESULT:
The I-V characteristics of an NMOS and PMOS was obtained and the variation of drain current of a simple NMOS PMOS circuit was observed and plotted using HSPICE.

10

EXPERIMENT -4
OBJECTIVE: Plot DC Response, Transient Analysis for a pulse input and sinusoidal input of CMOS
Inverter circuit using HSPICE Simulation tool. The design parameter are given below (Vdd=5V; Vin= 1V ; L=1um; W=90.9um; Vtn=1V; Vtp=-1V; kn=22um; kp=22um; gamma=0.2)

TOOL: H SPICE A-2008.0 3(32 BIT) THEORY: A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate
terminals, a supply voltage VDD at the PMOS source terminal, and a ground connected at the NMOS source terminal, were VIN is connected to the gate terminals and VOUT is connected to the drain terminals.(See diagram). It is important to notice that the CMOS does not contain any resistors, which makes it more power efficient that a regular resistor-MOSFET inverter. When the input is high the PMOS is off and the NMOS is on which results in a direct path between output and Gnd causing the output to go low. When the input is low the NMOS is off and the PMOS is on which results in a direct path between output and Vdd causing the output to go high.

DIAGRAM:

CMOS Inverter Circuit

NETLIST:

(1) HSPICE CODE FOR CMOS


*** CMOS INVERTOR *** VDD 3 0 DC 5 VIN 1 0 DC 0.1 M1 2 1 0 0 NMOD (W=90.9U L=1U) M2 2 1 3 3 PMOD(W=90.9U L=1U)

INVERTER FOR DC INPUT

11

.MODEL NMOD NMOS (VTO=1 KP=22U GAMMA=0.2) .MODEL PMOD PMOS (VTO= -1 KP=22U GAMMA=0.2) .DC VIN 0 5 0.1 .PLOT DC V(2) .PROBE .OPTION POST .END SIMULATION RESULTS:

CONCLUSION: As the input voltage is varying for 0 to 5 volts the inverted output has been plotted in the above graph. For low input the PMOS transistor is in ON state and output directly connects to Vdd and for high input PMOS is off and NMOS starts conducting so the output is directly connects to ground and shows inverted output.

(2) HSPICE CODE FOR CMOS INVERTER WITH AC INPUT *** CMOS INVERTOR *** VDD 3 0 DC 5

12

VIN 1 0 PULSE (0 5 0 0 0 10U 20U) M1 2 1 0 0 NMOD (W=90.9U L=1U) M2 2 1 3 3 PMOD(W=90.9U L=1U) .MODEL NMOD NMOS (VTO=1 KP=22U GAMMA=0.2) .MODEL PMOD PMOS (VTO= -1 KP=22U GAMMA=0.2) .TRAN 0.1U 100U .PLOT DC V(2) .PROBE .OPTION POST .END SIMULATION RESULT

CONCLUSION The transient analysis of the RTL inverter is obtained by applying a pulse input voltage of frequency 50kHz. The output is in accordance with the dynamic inverter characteristics. For high output PMOS is ON and for low output NMOS is in ON stage.

(3) HSPICE CODE FOR CMOS INVERTER WITH AC INPUT FOR SINOSOIDAL INPUT

NETLIST:
13

*** CMOS INVERTOR FOR SIN WAVE*** VDD 3 0 DC 5 VIN 1 0 SIN (2V 0.3V 100KHZ) M1 2 1 0 0 NMOD (W=90.9U L=1U) M2 2 1 3 3 PMOD(W=90.9U L=1U) .MODEL NMOD NMOS (VTO=1 KP=22U GAMMA=0.2) .MODEL PMOD PMOS (VTO= -1 KP=22U GAMMA=0.2) .TRAN 0.001U 100U .PLOT DC V(2) .PROBE .OPTION POST .END

CONCLUSION: The transient analysis of the RTL inverter is obtained by applying a pulse input voltage of frequency 50kHz. The output is in accordance with the dynamic inverter characteristics.

RESULT:
The dc response of an CMOS Inverter was obtained using HSPICE.

14

EXPERIMENT-5
OBJECTIVE: (a) Perform Differential mode and common mode analysis of Differential Amplifier
using HSPICE Simulation The design parameter are given below (Vdd=5V; Vin= 1V; L=1um; W=90.9um; Vtn=1V; kn=22um gamma=0.2)

TOOL: H SPICE A-2008.0 3(32 BIT) (1) DIFFERENTIAL MODE ANALYSIS


THEORY: The differential amplifier, or differential pair, is an essential building block in all integrated amplifiers. In general, the input stage of any analog integrated circuit with more than one input consists of a differential pair or differential amplifier. The basic differential pair circuit consists of two-matched NMOS transistors M1 and M2 , whose source are joined together and biased a constant current source. The current source can be achieved using an active current mirror cicuit which mirrors a reference current. DIAGRAM:

15

Differential Amplifier in Differential mode NETLIST: ***DIFFERENTIAL AMPLIFIER WITH DIFF INPUT*** VDD 3 0 DC 5 V1 1 0 DC 1.65 AC 1 V2 7 0 DC 2.5 AC 0 IREF 6 0 DC -1M R1 3 2 2.2K R2 3 4 2.2K M1 2 1 5 0 NMOD W= 90.9U L= 1U M2 4 7 5 0 NMOD W= 90.9U L= 1U M3 5 6 0 0 NMOD W= 90.9U L= 1U M4 6 6 0 0 NMOD W= 90.9U L= 1U .MODEL NMOD NMOS (VTO= 1 KN= 22U GAMMA=0.1) .DC V1 0 5 0.1 .PLOT DC V(2) .PLOT DC V(4) .PLOT DC V(5) .PLOT DC I(M1) .PLOT DC I(M2) .PROBE .OPTION POST
16

.END

SIMULATION RESULTS:

CONCLUSION:

(2) COMMON MODE ANALYSIS THEORY: A common mode signal is one that drives both inputs of a differential amplifier equally. The common mode signal is interference, static and other kinds of undesirable pickup etc. The connecting wires on the input gate act like small antennas. If a differential amplifier is operating in an environment with lot of electromagnetic interference, each base picks up an unwanted interference voltage. If both the transistors were matched in all respects then the balanced output would be theoretically zero. This is the important characteristic of a differential amplifier. It discriminates against common mode input signals. In other words, it refuses to amplify the common mode signals. DIAGRAM:

17

Differential Amplifier in Common mode NETLIST: ***DIFFERENTIAL AMPLIFIER WITH COMMON MODE INPUT*** VDD 3 0 DC 5 VIN 1 0 DC 0.1 IREF 6 0 DC -1M R1 3 2 2.2K R2 3 4 2.2K M1 2 1 5 0 NMOD W= 90.9U L= 1U M2 4 1 5 0 NMOD W= 90.9U L= 1U M3 5 6 0 0 NMOD W= 90.9U L= 1U M4 6 6 0 0 NMOD W= 90.9U L= 1U .MODEL NMOD NMOS (VTO= 1 KN= 22U GAMMA=0.1) .DC VIN 0 5 0.1 .PLOT DC V(2) .PLOT DC V(4) .PLOT DC V(5) .PLOT DC I(M1) .PLOT DC I(M2) .PROBE .OPTION POST .END
18

SIMULATION RESULTS:

CONCLUSION

RESULT:
The Common mode response of a Differential Amplifier was obtained using HSPICE.

19