Introduction

SPICE compatibility

Annex E SPICE compatibility
E.1 Introduction
Analog simulation has long been performed with SPICE and SPICE-like simulators. As such, there is a huge legacy of SPICE netlists. In addition, SPICE provides a rich set of predefined models and it is considered neither practical nor desirable to convert these models into a Verilog-AMS HDL behavioral description. In order for Verilog-AMS HDL to be embraced by the analog design community, it is important Verilog-AMS HDL provide an appropriate degree of SPICE compatibility. This annex describes the degree of compatibility which Verilog-AMS HDL provides and the approach taken to provide that compatibility. E.1.1 Scope of compatibility SPICE is not a single language, but rather is a family of related languages. The first widely used version of SPICE was SPICE2g6 from the University of California at Berkeley. However, SPICE has been enhanced and distributed by many different companies, each of which has added their own extensions to the language and models. As a result, there is a great deal of incompatibility even among the SPICE languages themselves. Verilog-AMS HDL makes no judgement as to which of the various SPICE languages should be supported. Instead, it states if a simulator which supports Verilog-AMS HDL is also able to read SPICE netlists of a particular flavor, then certain objects defined in that flavor of SPICE netlist can be referenced from within a Verilog-AMS HDL structural description. In particular, SPICE models and subcircuits can be instantiated within a Verilog-AMS HDL module. This is also true for any SPICE primitives which are built into the simulator. In general, anything that can be instantiated in the particular flavor of SPICE can also be instantiated within a Verilog-AMS HDL module. E.1.2 Degree of incompatibility There are four primary areas of incompatibility between versions of SPICE simulators. 1. The version of the SPICE language accepted by various simulators is different and to some degree proprietary. This issue is not addressed by Verilog-AMS HDL. So whether a particular Verilog-AMS simulator is SPICE compatible, and with which particular variant of SPICE it is compatible, is solely determined by the authors of the simulator.

LRM 2.3 draft 14/8/07

Verilog-AMS Language Reference Manual Copyright (c) 2007 Accellera International, Inc

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it is not possible to anticipate all SPICE primitives and parameters which could be supported. This level of incompatibility can be overcome by using wrapper modules to map names. However. it is expected to provide the basic set of SPICE primitives (see Annex E. a list of what names shall be used for the more common components is shown in Table E. while the Verilog-AMS HDL built-in primitives are standardized.2.1 Case sensitivity Some SPICE netlists are case insensitive. To reduce this.SPICE compatibility Accessing Spice objects from Verilog-AMS HDL 2. Again. SPICE primitives built into the simulator shall be treated in the same manner in VerilogAMS HDL as built-in primitives of gate. a particular SPICE netlist can reference a primitive which is unsupported. 390 Verilog-AMS Language Reference Manual Copyright (c) 2007 Accellera International. In addition to SPICE primitives. From within Verilog-AMS HDL. However. the primitive can be rewritten as a module. 4. and parameters and ports can. When instantiating SPICE primitives in Verilog-AMS HDL. their parameters. incompatible enhancements of the models have crept in through the years. Verilog-AMS HDL offers no solution in this case other than the possibility that if the model equations are known.and switch-level modeling. As with the netlist syntax. parameters. The mathematical description of the built-in primitives can differ.3 draft 14/8/07 . the SPICE primitives are not. Not all SPICE simulators support the same set of component primitives.1. the primitive can be rewritten as a module. The names of the built-in SPICE primitives. be named. 3. Thus. there is a high likelihood of incompatibility cropping up in these names. The subcircuits and models contained within the SPICE netlist are treated as module definitions.2 Accessing SPICE objects from Verilog-AMS HDL If an implementation of a Verilog-AMS tool supports SPICE compatibility. so different implementations can end up using different names. All aspects of SPICE primitives are implementation dependent. VerilogAMS HDL offers no alternative in this case other than the possibility that if the model equations are known. a mixed-case name matches the same name with an identical case (if one is defined in a Verilog-AMS HDL description). E. E. Inc LRM 2. This is particularly true because many primitives. it shall also be possible to access subcircuits and models defined within SPICE netlists.3) and be able to read SPICE netlists which contain models and subcircuit statements. whereas Verilog-AMS HDL descriptions are case-sensitive. the primitives shall. or their ports can differ from simulator to simulator. and ports are unnamed in SPICE. Since there are no established standard names.

E. the optional substrate port s is defaulted by simply not giving it. b. e.3NS TR=6NS This model can be instantiated in a Verilog-AMS HDL module as shown in Figure E. c1 b1 e c2 b2 Figure E.1 Accessing SPICE models Consider the following SPICE model file being read by a Verilog-AMS HDL simulator. In the instantiation of Q1. they can just as easily be T1 and T2. Inc 391 . E. ). b2. the ports are passed by order. vertNPN Q1 (c1. . and e) and one optional port (s). endmodule Unlike with SPICE. the ports are passed by name.2 Accessing SPICE subcircuits As an example of how a SPICE subcircuit is referenced from Verilog-AMS HDL.2 Examples This subsection shows some examples.1.e(e)). e.2.2. In both cases. b1. is not constrained by the primitive type.c(c2). With Q2.1—Instantiated module module diffPair (c1.2.MODEL VERTNPN NPN BF=80 IS=1E-18 RB=100 VAF=50 + CJE=3PF CJC=2PF CJS=2PF TF=0. E. This BJT primitive has 3 mandatory ports (c. the first letter of the instance name.3 for more details. electrical c1. b2. c2. .2. e. c2). LRM 2. For example.3 draft 14/8/07 Verilog-AMS Language Reference Manual Copyright (c) 2007 Accellera International. b1.b(b2). in this case Q1 and Q2. the mixed-case name shall match the same name defined within SPICE regardless of the case.2. b1. vertNPN Q2 (. See Annex E.Accessing Spice objects from Verilog-AMS HDL SPICE compatibility However. The ports and parameters of the BJT are determined by the BJT primitive itself and not by the model statement for the BJT. if no exact match is found. . consider the following SPICE subcircuit definition of an oscillator.

2. inductor #(. capacitor #(. resistor #(. out). capacitor #(. electrical out.2. idc #(. out).SPICE compatibility Preferred primitive.7PF C3 B1 GND 3NF R1 B1 GND 10K C4 B2 GND 3NF R2 B2 GND 10K . e.r(10k)) R2 (b2. parameters. gnd).ic(1)) C1 (vcc. E. gnd. For connection by order instead of by name. vdc #(. gnd). endmodule Note: In Verilog-AMS HDL the name of the subcircuit instance is not constrained to start with X as it is in SPICE.c(3n)) C4 (b2.1 shows the required names for primitives. capacitor #(.ENDS ECPOSC This oscillator can be referenced from Verilog-AMS HDL as: module osc (out.c(1p). and ports which are otherwise unnamed in SPICE. . Inc LRM 2. gnd). electrical out. vertNPN Q2 (out. gnd).SUBCKT ECPOSC (OUT GND) VA VCC GND 5 IEE E GND 1MA Q1 VCC B1 E VCC VERTNPN Q2 OUT B2 E OUT VERTNPN L1 VCC OUT 1UH C1 VCC OUT 1P IC=1 C2 OUT B1 272. vertNPN Q1 (vcc.dc(1m)) Iee (e. endmodule E. e.3 Preferred primitive.3 draft 14/8/07 .2 is translated to native Verilog-AMS HDL. capacitor #(. b2. parameter. the subcircuit in Section E. gnd).dc(5)) Vcc (vcc. gnd.3 Accessing SPICE primitives To show how various SPICE primitives can be accessed from Verilog-AMS HDL.l(1u)) L1 (vcc. and port names .c(3n)) C3 (b1. module ecpOsc (out. gnd). gnd). and port names Table E. gnd). out).7p)) C2 (out. b1). parameter.r(10k)) R1 (b1.c(272. gnd). the ports and 392 Verilog-AMS Language Reference Manual Copyright (c) 2007 Accellera International. resistor #(.2. ecpOsc Osc1 (out. vcc).2. b1.

and port names SPICE compatibility parameters shall be given in the order listed. fall. tau0. damp. fmmodfreq I = offset + ampl ⋅ ( 1 – F AM ⋅ cos ( 2 π ⋅ f AM ⋅ ( t – td ) – ϕ AM ) ) ⋅ ( 1 – damp ⋅ ( t – td ) ) ⋅ cos ( 2 π ⋅ freq ⋅ ( 1 – F FM ⋅ cos ( 2 π ⋅ f FM ⋅ ( t – td ) ) ) ⋅ ( t – td ) – ϕ SIN ) with F AM = ammodindex. f AM = ammodfreq. period      I=       val0 t – t0 val0 + ( val1 – val0 ) ⋅ -----------rise val1 t – t2 val1 + ( val0 – val1 ) ⋅ -----------fall val0 t ≤ t0 t0 < t ≤ t1 t1 < t ≤ t2 t2 < t ≤ t3 t3 < t ≤ t4 with the following definitions ( n is a non-negative integer): t0 t1 t2 t3 t4 ipwl p. ammodindex. tc2 c.Preferred primitive. td1.3 draft 14/8/07 Verilog-AMS Language Reference Manual Copyright (c) 2007 Accellera International. amp1. ipulse p.1—Required names Primitive resistor capacitor inductor iexp Port name p. val1. parameter. ammodphase. freq. F FM = fmmodindex. n Parameter name r. The default discipline of the ports for these primitives shall be electrical and their descriptions shall be inout. sinephase. ic l. n p. n p. Inc 393 . width. n offset. td0. n p. f AM = fmmodfreq. ic val0.⋅ ∫0 I dτ + ic c I = l ⋅ ∫0 V dτ + ic t 2   val0  td0 – t -------------- I =  val1 – ( val1 – dc ) ⋅ e tau0  td1 – t --------------  val0 – ( val0 – I td1 ) ⋅ e tau1  t ≤ td0 td0 < t ≤ td1 td1 < t with I td1 the value of I at time t = td1 . rise. n val0. tau1 Behavior V = I ⋅ r ⋅ ( 1 + tc1 ⋅ T + tc2 ⋅ T ) 1 t V = -. LRM 2. val1. and ϕ SIN =sinephase. n wave = = = = = td + n ⋅ period rise + td + n ⋅ period width + rise + td + n ⋅ period fall + width + rise + td + n ⋅ period td + ( n + 1 ) ⋅ period I = wave [ i + 1 ] + t – wave [ i ] ( wave [ i + 3 ] – wave [ i + 1 ] ) ⋅ -----------------------------------------------------wave [ i + 3 ] – wave [ i ] for wave [ i ] ≤ t < wave [ i + 2 ] and 0 ≤ i < len ( wave ) . td. Table E. fmmodindex. ϕ AM = ammodphase. isine p. tc1. td. ammodfreq.

freq. src. ammodindex. b1. n wave = = = = = td + n ⋅ period rise + td + n ⋅ period width + rise + td + n ⋅ period fall + width + rise + td + n ⋅ period td + ( n + 1 ) ⋅ period V = wave [ i + 1 ] + t – wave [ i ] ( wave [ i + 3 ] – wave [ i + 1 ] ) ⋅ -----------------------------------------------------wave [ i + 3 ] – wave [ i ] for wave [ i ] ≤ t < wave [ i + 2 ] and 0 ≤ i < len ( wave ) . n. damp. val1. F FM = fmmodindex. val1. f AM = ammodfreq. sinephase.3. td1. ϕ AM = ammodphase. vsine p. n val0. tau1 Behavior   dc  td0 – t -------------- V =  val1 – ( val1 – dc ) ⋅ e tau0  td1 – t --------------  val0 – ( val0 – V td1 ) ⋅ e tau1  t ≤ td0 td0 < t ≤ td1 td1 < t with V td1 the value of V at time t = td1 . t2. ammodphase. ns) V(p.3 draft 14/8/07 . Inc LRM 2. ns) E. period      V=       val0 t – t0 val0 + ( val1 – val0 ) ⋅ -----------rise val1 t – t2 val1 + ( val0 – val1 ) ⋅ -----------fall val0 t ≤ t0 t0 < t ≤ t1 t1 < t ≤ t2 t2 < t ≤ t3 t3 < t ≤ t4 with the following definitions ( n is a non-negative integer): t0 t1 t2 t3 t4 vpwl p. ps. and mutual 394 Verilog-AMS Language Reference Manual Copyright (c) 2007 Accellera International. amp1. tau0. fall. cccs. td. nl gm gain I(src. td.1 Unsupported primitives Verilog-AMS HDL does not support the concept of passing an instance name as a parameter. width. As such.SPICE compatibility Preferred primitive. f AM = fmmodfreq. vpulse p. ns z0. fmmodfreq V = offset + ampl ⋅ ( 1 – F AM ⋅ cos ( 2 π ⋅ f AM ⋅ ( t – td ) – ϕ AM ) ) ⋅ ( 1 – damp ⋅ ( t – td ) ) ⋅ cos ( 2 π ⋅ freq ⋅ ( 1 – F FM ⋅ cos ( 2 π ⋅ f FM ⋅ ( t – td ) ) ) ⋅ ( t – td ) – ϕ SIN ) with F AM = ammodindex. ps. td. sink) = gm ⋅ V(ps. fmmodindex. ns p. parameter. b2 sink. ammodfreq. rise. td0. and port names Table E. n) = gain ⋅ V(ps.1—Required names Primitive vexp Port name p. and ϕ SIN =sinephase. f. tline vccs vcvs t1. the following primitives are not supported: ccvs. n offset. n Parameter name val0.

then the discipline of the analog primitive shall be set to the same discipline.3. A port_discipline attribute on the analog primitive 2. Attributes are defined in the IEEE 1364-2001 LRM and will not be described in this document.Preferred primitive.2 Discipline of primitives To afford the ability to use analog primitive in any design. // not needed as default resistor #(.2. The following provides an example of this attribute. the disciplines of other instances on the same net. If they are. If they are not compatible. then the discipline shall default to electrical. It shall only apply to the instance to which it is attached. then an error will occur as defined in Section 3. these primitives can be instantiated inside a SPICE subcircuit that itself is instantiated in Verilog-AMS. parameter. The resolution of the discipline 3.8 of this LRM.2 Resolving the disciplines of analog primitives If no attribute exists on the instance of an analog primitive. then the discipline may be determined by the disciplines of other instances connected to the same net segment.2.1 Setting the discipline of analog primitives A new optional attribute shall be provided called "port_discipline".r(1k)) (* port_discipline="electrical" . *) r2 (node1. The precedence for the discipline of analog primitives is as follows: 1.r(1k)) (* port_discipline="rotational" . The disciplines of the vpiLoConn of all other instances on the net segment shall be evaluated to determine if they are of domain continuous and compatible with each other. The default analog primitive of electrical E. or default to electrical if it cannot be determined. E.3 draft 14/8/07 Verilog-AMS Language Reference Manual Copyright (c) 2007 Accellera International. and port names SPICE compatibility inductors. Inc 395 .3. node2).3. If there are no continuous disciplines defined on the net segment. however. E. which shall have as a value the desired discipline for the analog primitive. node2). the default discipline override is provided. This attribute shall only apply to analog primitives and for all other modules shall be ignored. LRM 2. resistor #(. including mixed disciplines. *) r1 (node1. The discipline of analog primitives will be resolved based on instance specific attributes. The value shall be of type string and the value must be a valid discipline of domain continuous.

In the case a module is defined whose name matches that of a SPICE primitive. subcircuits defined as modules could not support automatic M factors. This allows a Verilog-AMS module to use the same limiting algorithms available to built-in SPICE primitives. In case of a name match with differences in case.3. Table E. Table E.5. or subcircuit. Inc LRM 2. and their intended uses. can be used in the $limit() function of Section 10. the module does not shadow the SPICE primitive. the multiplicity factor is supported for subcircuits defined as modules in Verilog-AMS using the hierarchical system parameter $mfactor.1 Multiplicity factor on subcircuits Some SPICE simulators support a multiplicity factor (M) parameter on subcircuits without the parameter being explicitly being declared.1 shall apply. The arguments are described in Section 10. This factor is typically used to indicate the subcircuit should be modeled as if there are a specified number of copies in parallel.2—SPICE limiting functions Function name fetlim pnjlim vdslim Arguments vth vte.2.3 Name scoping of SPICE primitives A module defined in the Verilog-AMS always wins over a SPICE primitive. Starting with LRM Version 2.5 Other issues This section highlights some other issues E. model.SPICE compatibility Limiting algorithms E. In previous versions of Verilog-AMS HDL.2. 396 Verilog-AMS Language Reference Manual Copyright (c) 2007 Accellera International.2. The function name. enclosed in quotation marks. vcrit (none) Meant for limiting: gate-to-source voltage of field-effect transistors voltage across diodes and pn junctions in other devices drain-to-source voltage of field-effect transistors E.4 Limiting algorithms Many SPICE simulators use limiting algorithms to improve convergence in NewtonRaphson iterations.2 lists the preferred names for three functions that may be available in a simulator.6.3 draft 14/8/07 .9.9. E. their arguments. model or subcircuit exactly the Verilog-AMS simulator shall issue a warning stating that the Verilog-AMS module is used instead of the SPICE primitive. but the resolution method described in Section E. as described in Section 7.

Examples include model binning or corners support.2. and instance may refer to a paramset identifier.3 draft 14/8/07 Verilog-AMS Language Reference Manual Copyright (c) 2007 Accellera International. Inc 397 .Other issues SPICE compatibility E. Support of SPICE model cards is implementation specific (including those using these mechanisms). LRM 2. it appears as if the instance is referencing a simple SPICE model.3.5.2 Binning and libraries Some SPICE netlists provide mechanisms for mapping an instance to a group of models. as described in Section 7. supporting these additional capabilities in Verilog-AMS HDL is supported via the instance line by default. Instead of referencing a specific module. The final determination of which paramset to use is made according to rules specified in Section 7.3. From within an instance statement. and there may be several paramsets with the same identifier (name). Similar functionality for Verilog-AMS is supported through use of the paramset. with the final determination of which model to use being based on rules encapsulated in the SPICE netlist.

3 draft 14/8/07 .SPICE compatibility Other issues 398 Verilog-AMS Language Reference Manual Copyright (c) 2007 Accellera International. Inc LRM 2.

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