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04 Logic Gates

04 Logic Gates

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Logic gates

Last lecture

Boolean algebra

Axioms

Useful laws and theorems

Simplifying Boolean expressions

Today's lecture

Logic gates and truth tables

!mplementing logic functions

CNOS switches

2 CSE370, Lecture +

X Y Z

0 0 0

0 1 0

1 0 0

1 1 1

X

Y

Z

X Y Z

0 0 0

0 1 1

1 0 1

1 1 1

X

Y

Z

Logic gates and truth tables

AND X-Y XY

OR X+Y

NOT X X'

Buffer X

X Y

0 1

1 0

X Y

X Y

0 0

1 1

X Y

3 CSE370, Lecture +

X Y Z

0 0 1

0 1 1

1 0 1

1 1 0

X

Y

Z

Logic gates and truth tables (con't)

NAND

NOR

XOR

XNOR

X Y XY

X Y +

X Y

X Y

X Y Z

0 0 1

0 1 0

1 0 0

1 1 0

Z

X

Y

X Y Z

0 0 0

0 1 1

1 0 1

1 1 0

X

Y

Z

X Y Z

0 0 1

0 1 0

1 0 0

1 1 1

Z

X

Y

+ CSE370, Lecture +

Definitions

Schematic: A drawing of interconnected gates

Net: Wires at the same voltage (electrically connected)

Netlist: A list of all the devices and connections in a

schematic

Fan-in: The # of inputs to a gate

Fan-out: The # of loads the gate drives

5 CSE370, Lecture +

Example: F = (A-B)' + C-D

Example: F = C-(A+B)'

Napping Boolean expressions to logic gates

D

C

A

B

F

16

AND2

19

NAND2

17

OR2

C

F

A

B

22

AND2

21

NOR2

6 CSE370, Lecture +

1-bit binary adder

!nputs: A, B, Carry-in

Outputs: Sum, Carry-out

A B Cin S Cout

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0

1

1

0

1

0

0

1

0

0

0

1

0

1

1

1

Cout = A'BCin + AB'Cin + ABCin' + ABCin

Sum = A'B'Cin + A'BCin' + AB'Cin' + ABCin

Example: A binary full adder

A

B

Cin

Cout

Sum

Adder

7 CSE370, Lecture +

Full adder: Sum

Before Boolean minimization

Sum = A'B'Cin + A'BCin'

+ AB'Cin' + ABCin

After Boolean minimization

Sum = (AB) Cin

Cin

Sum

B

A

33

XOR

32

XOR

Cin

A

B

Cin'

Cin'

A

B'

Sum

Cin

A'

B

B'

A'

31

AND3

30

AND3

29

AND3

27

OR4

28

AND3

8 CSE370, Lecture +

Before Boolean minimization

Cout = A'BCin + AB'Cin

+ ABCin' + ABCin

After Boolean minimization

Cout = BCin + ACin + AB

Cin

A

B

Cin

Cin'

B'

A

B

Cout

Cin

B

A'

A

4

AND3

2

AND3

3

AND3

5

OR4

1

AND3

A

B

Cin

A

Cout

Cin

B

13

AND2

12

AND2

14

OR3

11

AND2

Full adder: Carry-out

9 CSE370, Lecture +

Preview: A 2-bit ripple-carry adder

A

1

B

1

C

out

C

in

Sum

1

A

B

Cin

A

Cout

Cin

B

13

AND2

12

AND2

14

OR3

11

AND2

Cin

Sum

B

A

33

XOR

32

XOR

A

Sum

C

out

C

in

B

1-Bit Adder

A

2

B

2

Sum

2

C

out

C

in

0

Overflow

10 CSE370, Lecture +

Napping truth tables to logic gates

Given a truth table

Write the Boolean expression

Ninimize the Boolean expression

Draw as gates

A B C F

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

F = A'BC'+A'BC+AB'C+ABC

= A'B(C'+C)+AC(B'+B)

= A'B+AC

C

A

A'

B

F

25

AND2

26

AND2

24

OR2

11 CSE370, Lecture +

Nany possible mappings

Nany ways to map expressions to gates

Example:

Z A B C D A B C D

= +

( )

= +

( )

A

B

C

D

Z

A

B

C

D

Z

Z

12 CSE370, Lecture +

What is the optimal gate realization?

We use the axioms and theorems of Boolean algebra

to optimize" our designs

Design goals vary

Reduce the number of inputs?

Reduce the number of gates?

Reduce number of gate levels?

How do we explore the tradeoffs?

CAD tools

Logic minimization: Reduce number of gates and complexity

Logic optimization: Naximize speed andfor minimize power

13 CSE370, Lecture +

X Y X nand Y

0 0 1

1 1 0

X Y X nor Y

0 0 1

1 1 0

We can implement any logic function from NOT, NOR,

and NAND

Example: (X and Y) = not (X nand Y)

!n fact, we can do it with only NOR or only NAND

NOT is just NAND or NOR with two identical inputs

NAND and NOR are duals: Can implement one from the other

X nand Y = not ((not X) nor (not Y))

X nor Y = not ((not X) nand (not Y))

Ninimal set

1+ CSE370, Lecture +

Nark Bohr

!ntel

0.13m

X Y

0V 1.8V

1.8V 0V

X Y

X Y

1.8v

0v

Y X

1.8v

0v

Nost digital logic is CNOS

CNOS technology

Complementary Netal-

Oxide Semiconductor

Transistors act as voltage-

controlled switches

0V Logic 0

1.8V Logic 1

15 CSE370, Lecture +

Nulti-input logic gates

CNOS logic gates are inverting

Get NAND, NOR, NOT

Don't get AND, OR, Buffer

X Y Z

0 0 1

0 1 1

1 0 1

1 1 0

Z

X

1.8v

0v

Y

1.8v

X Y

X

Z

1.8v

0v

Y

1.8v

X Y

X

Y

Z

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