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ąą

TLC7226C, TLC7226I, TLC7226M QUADRUPLE 8ĆBIT DIGITALĆTOĆANALOG CONVERTERS ą
SLAS060E – JANUARY 1995 – REVISED JANUARY 2003

features

D D D D D

DW OR N PACKAGE (TOP VIEW)

Four 8-Bit D/A Converters Microprocessor Compatible TTL/CMOS Compatible Single Supply Operation Possible CMOS Technology

applications

D Process Control D Automatic Test Equipment D Automatic Calibration of Large System
Parameters, e.g. Gain/Offset

OUTB OUTA VSS REF AGND DGND DB7 DB6 DB5 DB4

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

OUTC OUTD VDD A0 A1 WR DB0 DB1 DB2 DB3

description
The TLC7226C, TLC7226I, and TLC7226M consist of four 8-bit voltage-output digital-toanalog converters (DACs) with output buffer amplifiers and interface logic on a single monolithic chip. Separate on-chip latches are provided for each of the four DACs. Data is transferred into one of these data latches through a common 8-bit TTL/CMOS-compatible 5-V input port. Control inputs A0 and A1 determine which DAC is loaded when WR goes low. The control logic is speed compatible with most 8-bit microprocessors. Each DAC includes an output buffer amplifier capable of sourcing up to 5 mA of output current.

FK PACKAGE (TOP VIEW)

OUTC DB2

3

2

1

20 19 18 VDD 17 A0 16 A1 15 WR 14 DB0

REF AGND DGND DB7 DB6

4 5 6 7 8 9 10 11 12 13

DB5

DB4

DB3

The TLC7226 performance is specified for input reference voltages from 2 V to VDD – 4 V with dual supplies. The voltage mode configuration of the DACs allows the TLC7226 to be operated from a single power supply rail at a reference of 10 V. The TLC7226 is fabricated in a LinBiCMOS™ process that has been specifically developed to allow high-speed digital logic circuits and precision analog circuits to be integrated on the same chip. The TLC7226 has a common 8-bit data bus with individual DAC latches. This provides a versatile control architecture for simple interface to microprocessors. All latch-enable signals are level triggered. Combining four DACs, four operational amplifiers, and interface logic into either a 0.3-inch wide, 20-terminal dual-in-line IC (DIP) or a small 20-terminal small-outline IC (SOIC) allows a dramatic reduction in board space requirements and offers increased reliability in systems using multiple converters. The Leadless Ceramic Chip Carrier (LCCC) package provides for operation at military temperature range. The pinout is aimed at optimizing board layout with all of the analog inputs and outputs at one end of the package and all of the digital inputs at the other.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinBiCMOS is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 2003, Texas Instruments Incorporated

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

DB1

OUTD

OUTB

OUTA

V SS

1

TLC7226I. The TLC7226I is characterized for operation from –25°C to 85°C. The TLC7226M is characterized for operation from –55°C to 125°C. TLC7226M QUADRUPLE 8ĆBIT DIGITALĆTOĆANALOG CONVERTERS ą description (continued) ą The TLC7226C is characterized for operation from 0°C to 70°C. TEXAS 75265 .SLAS060E – JANUARY 1995 – REVISED JANUARY 2003 TLC7226C. AVAILABLE OPTIONS PACKAGE TA 0°C to 70°C –25°C to 85°C –55°C to 125°C SMALL OUTLINE (DW) TLC7226CDW TLC7226IDW — PLASTIC DIP (N) TLC7226CN TLC7226IN — LCCC (FK) — — TLC7226MFKB functional block diagram REF 4 _ 8 Latch A 8 DAC A + 2 OUTA _ 8 DB0–DB7 7–14 8 Latch B 8 DAC B + 1 OUTB _ 8 Latch C 8 DAC C + 20 OUTC _ 8 Latch D 8 DAC D + 19 OUTD 15 WR 17 A0 16 A1 Control Logic schematic of outputs EQUIVALENT ANALOG OUTPUT VDD Output 450 µA VSS 2 POST OFFICE BOX 655303 • DALLAS.

. . . . . TA: C suffix . VSS: AGND or DGND . . . . . . . . . . . . . . . . . . . . . DACC. . . . .3 V Voltage range between AGND and DGND . . TLC7226I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 V to 17 V VSS‡ . Digital DAC data inputs. . . . . . . . 2. . . . . . . . N. . DB0–DB7 are the input digital data used for conversion. . . . . . . . . . . . . . . . . . . . . . . –0. . . . DACA output. Positive supply voltage input terminal Negative supply voltage input terminal Write input. . . . . . OUTB is the analog output of DACB. . . WR selects DAC transparency or latch mode. . . . .3 V to 24 V Supply voltage range. . . . . . and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. VSS to VDD Continuous total power dissipation at (or below) TA = 25°C (see Note 2) . . . . . . . . . . . . . Typically short circuit current to AGND is 60 mA. . . . . . DACD output. . . DACC output. . . . . . . . . . . . . . . . . . . . . . DAC select inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OUTD is the analog output of DACD. . . . –0. . . . . . . . . . . derate linearly at the rate of 2 mW/°C. . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. –55°C to 125°C Storage temperature range. . . AGND is the reference and return terminal for the analog signals and supply.3 V to VDD + 0. . . . . † Terminal numbers shown are for the DW. . –17 V to 17 V Input voltage range. . . These are stress ratings only. . OUTA is the analog output of DACA. . . . . . . . The combination of high or low levels select either DACA. VDD: AGND or DGND . . . . . . . . . . .† 5 17. . . . . . . . . . . . . . . . . . . . . . . . DACB. . . . . . . . . . . . . . . . . . . . . . . . and FK packages. –25°C to 85°C M suffix . . . . . . . . . . DGND is the reference and return terminal for the digital signals and supply. . . . . . . . . . . . . . . . . . . .3 V to 20 V Output voltage range. . . Voltage reference input. . . . . . . absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range. . . . . . . . . . . . . . Output voltages may be shorted to AGND provided that the power dissipation of the package is not exceeded. . . . . . . . . –65°C to 150°C Lead temperature 1. . . . . . . . . . Tstg . . . . . . . . . . . . Digital ground. . . . . . . . . . . . . . . . . . . . .ą TLC7226C. . . . . –0. . . VI (to DGND) . . . . . . . . . . –0. . . . . . . . . . . . . . .3 V to VDD Vref (to VSS) . . TEXAS 75265 3 . OUTC is the analog output of DACC. . . . POST OFFICE BOX 655303 • DALLAS. . . . . . . . . . . . . . . . . . . . . . . . –7 V to 0. . .3 V Reference voltage range: Vref (to AGND) .6 mm (1/16 inch) from case for 10 seconds: DW or N packages . . . . . . . . . . . VO (to AGND) (see Note 1) . . . . . . . 0°C to 70°C E suffix . . . . . . . . . . . . . . . . . . . . . DACB output. . . . . . . . . . . . . . . . . . . . TLC7226M QUADRUPLE 8ĆBIT DIGITALĆTOĆANALOG CONVERTERS ą SLAS060E – JANUARY 1995 – REVISED JANUARY 2003 Terminal Functions TERMINAL NAME AGND A0. . . . . . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. . . . . . . . . . . . . The selected input latch is transparent when WR is low. 500 mW Operating free-air temperature range. . . 16 6 14–7 2 1 20 19 4 18 3 15 I I O O O O I I I/O DESCRIPTION Analog ground. . . . . . . . –0. . . . . . NOTES: 1. . ‡ The VSS terminal is connected to the substrate and must be tied to the most negative supply voltage applied to the device. . . . . . . . . . . . . . . . For operation above TA = 75°C. . . . A1 DGND DB0–DB7 OUTA OUTB OUTC OUTD REF VDD VSS WR NO. 260°C Case temperature for 10 seconds: FK package . The voltage level on REF determines the full scale analog output. . . or DACD. . . . . . . . . . . . . . . . .

5 0 ą UNIT V V V V V kΩ ns ns ns ns ns electrical characteristics over recommended operating free-air temperature range dual power supply over recommended power supply and reference voltage ranges. All 0s loaded All 1s loaded C and I suffix M suffix M suffix 65 *30 *300 8 *12 pF F TEST CONDITIONS VI = 0 V or VDD VI = 0. TLC7226I. TA * This parameter is not tested for M suffix devices.4 V to 16. No load No load 2 MIN TYP MAX ±1 6 4 4 0.SLAS060E – JANUARY 1995 – REVISED JANUARY 2003 TLC7226C. VIL Reference voltage. erature. RL Setup time.4 V to 16.4 V to 16. VDD Supply voltage. address valid before WR↑. AGND = DGND = 0 V (unless otherwise noted) PARAMETER II I(DD) I(SS) ri(ref) Input current. tsu(AW) (see Figure 6) Setup time. VSS = – 5 V. TLC7226M QUADRUPLE 8ĆBIT DIGITALĆTOĆANALOG CONVERTERS ą recommended operating conditions MIN Supply voltage. VDD = 16.8 V or 2. Vref Load resistance.5 V C suffix I suffix M suffix 0 2 *0 *45 *0 *10 *50 0 –25 –55 70 85 125 °C 11.5 2 0. VSS High-level input voltage.4 V.5 V VDD = 11. TEXAS 75265 . VI = 0. digital Supply current Supply current Reference input resistance Power supply sensitivity ∆VDD = ±5% C and I suffix REF input in ut Ci Input In ut capacitance ca acitance Digital inputs * This parameter is not tested for M suffix devices. WR low.8 VDD–4 MAX 16.5 V VDD = 11.5 V VDD = 11.4 V to 16. VDD = 11. address valid before WR↓. tw (see Figure 6) Operating O erating free free-air air tem temperature.01 16 10 UNIT µA mA mA kΩ %/% 4 POST OFFICE BOX 655303 • DALLAS. data valid before WR↑. tsu(DW) (see Figure 6) Hold time. th(AW) (see Figure 6) Hold time.4 V.5 V VDD = 11. th(DW) (see Figure 6) Pulse duration.8 V or 2. data valid before WR↑. VIH Low-level input voltage.4 V to 16.4 –5.5 V.

75 V. IDD Slew rate Positive full scale Settling time to 1/2 LSB Resolution Total unadjusted error Full-scale error Full scale Temperature coefficient of gain Linearity error Digital crosstalk-glitch impulse area * This parameter is not tested for M suffix devices. TLC7226M QUADRUPLE 8ĆBIT DIGITALĆTOĆANALOG CONVERTERS ą SLAS060E – JANUARY 1995 – REVISED JANUARY 2003 operating characteristics over recommended operating free-air temperature range dual power supply over recommended power supply and reference voltage ranges.25 ±20 ±50 ±20 50 ±80 Negative full scale Vref = 10 V 8 ±2 ±1 ±2 TEST CONDITIONS MIN *2. Zero-code error Differential 50 VDD = 14 V to 16.5 V. Vref = 10 V ±20 ±50 ±1 Negative full scale 8 ±2 ±2 TEST CONDITIONS VI = 0.4 V. AGND = DGND = 0 V (unless otherwise noted) PARAMETER Slew rate Positive full scale Settling time to 1/2 LSB Resolution Total unadjusted error Linearity error Full-scale error Gain error Full scale Temperat re coefficient of gain Temperature Zero-code error Digital crosstalk glitch impulse area * This parameter is not tested for M suffix devices. VDD = 14. 5% Vref = 10 V ±0. No load *2 *5 *20 MIN TYP 5 MAX 13 UNIT mA V•µs µs bits LSB LSB ppm/°C µV/°C LSB nV•s POST OFFICE BOX 655303 • DALLAS. Vref = 10 V Differential/integral VDD = 15 V ±5%.8 V or 2. Vref = 10 V (unless otherwise noted) PARAMETER Supply current.5 *5 *7 TYP MAX UNIT V•µs µs bits LSB LSB LSB LSB ppm/°C µV/°C mV nV•s single power supply.25 V to 15. VSS = AGND = DGND = 0 V.5 V. Vref = 0 Zero-code error VDD = 14 V to 16. TEXAS 75265 5 .ą TLC7226C. TLC7226I.

TEXAS 75265 . Invalid data during this time can cause erroneous outputs. TLC7226M QUADRUPLE 8ĆBIT DIGITALĆTOĆANALOG CONVERTERS ą PARAMETER MEASUREMENT INFORMATION tsu(DW) VDD Data 0V th(DW) VDD Address 0V tsu(AW) th(AW) tw VDD 0V ą WR NOTES: A.2 –0. Figure 1. The timing measurement reference level is equal to VIH + VIL divided by 2.SLAS060E – JANUARY 1995 – REVISED JANUARY 2003 TLC7226C. tr = tf = 20 ns over VDD range. C. TLC7226I. B.4 –2 –1 0 TA = 25°C VSS = –5 V Digital In = 0 V Sinking Current Source 1 2 VO – Output Voltage – V Source Current Short-Circuit Limiting VDD = 15 V I O – Output Current (Sink) – µ A 700 600 500 400 300 200 OUTPUT CURRENT (SINK) vs OUTPUT VOLTAGE TA = 25°C VDD = 15 V VSS = –5 V VSS = 0 100 0 0 1 2 3 4 5 6 7 8 9 10 VO – Output Voltage – V Figure 2 Figure 3 6 POST OFFICE BOX 655303 • DALLAS.1 –0.3 –0. The selected input latch is transparent while WR is low. Write-Cycle Voltage Waveforms TYPICAL CHARACTERISTICS OUTPUT CURRENT vs OUTPUT VOLTAGE 200 150 I O – Output Current – mA 100 50 0 –0.

TLC7226I. This configuration provides an excellent method for providing a direct bipolar output with no additional components. Supply voltages VDD and VSS for the TLC7226 should be referenced to DGND. The output voltage. Since the AGND terminal is common to all four DACs. VO. Increasing AGND above system GND reduces the output range. REF (Vref = 5 V) 4 TLC7226‡ _ 2 AGND 5 3 VSS –5 V ‡ Digital inputs omitted for clarity. DGND. at OUTA can be expressed as: V O +V BIAS )D A ǒVIǓ (1) where DA is a fractional representation of the digital input word (0 ≤ D ≤ 255/256). Bipolar (Offset Binary) Code DAC LATCH CONTENTS MSB LSB 1111 1000 1000 0111 0000 0000 1111 0001 0000 1111 0001 0000 *V ANALOG OUTPUT )V )V 127 ref 128 1 ref 128 0V ǒ Ǔ ǒ Ǔ ǒ Ǔ * V ǒ127Ǔ ref 128 –V ǒ128Ǔ + * V ref ref 128 1 ref 128 AGND bias for positive output offset The TLC7226 AGND terminal can be biased above or below the system ground terminal. this method biases up the output voltages of all the DACs in the TLC7226. TEXAS 75265 7 . 6 DGND DAC A + OUT Output range (5 V to –5 V) 18 VDD Figure 4. VDD – Vref must be at least 4 V to ensure specified operation. TLC7226M QUADRUPLE 8ĆBIT DIGITALĆTOĆANALOG CONVERTERS ą SLAS060E – JANUARY 1995 – REVISED JANUARY 2003 PRINCIPLES OF OPERATION AGND bias for direct bipolar output operation The TLC7226 can be used in bipolar operation without adding more external operational amplifiers as shown in Figure 4 by biasing AGND to VSS.ą TLC7226C. to provide an offset analog output voltage level. POST OFFICE BOX 655303 • DALLAS. The transfer values are shown in Table 1. AGND Bias for Direct Bipolar Operation Table 1. Figure 5 shows a circuit configuration to achieve this for channel A of the TLC7226.

Function Table CONTROL INPUTS WR H L ↑ L ↑ L ↑ L ↑ L = low. TEXAS 75265 .SLAS060E – JANUARY 1995 – REVISED JANUARY 2003 TLC7226C. A1 X L L L L H H H H H = high. A2 X L L H H L L H H OPERATION No operation Device not selected DAC A transparent DAC A latched DAC B transparent DAC B latched DAC C transparent DAC C latched DAC D transparent DAC D latched X = irrelevant 8 POST OFFICE BOX 655303 • DALLAS. AGND Bias Circuit interface logic information Address lines A0 and A1 select which DAC accepts data from the input port. When the WR signal is low. the analog outputs remain at the value corresponding to the data held in their respective latches. TLC7226M QUADRUPLE 8ĆBIT DIGITALĆTOĆANALOG CONVERTERS ą PRINCIPLES OF OPERATION AGND bias for positive output offset (continued) Vref TLC7226† VI _ 2 AGND 5 Vbias 3 VSS 6 DGND DAC A + OUTA VDD ą 4 18 † Digital inputs omitted for clarity. Figure 5. Table 2. While WR is high. The data is latched into the addressed DAC latch on the rising edge of WR. the input latches of the selected DAC are transparent and the output responds to activity on the data bus. Figure 6 shows the input control logic. Table 2 shows the operations of the four DACs. TLC7226I.

Connections for the unipolar output operation are shown in Figure 7. TEXAS 75265 9 . _ REF 4 DAC A + _ 1 DAC B + _ DAC C + _ 19 DAC D + OUTD OUTB Table 3. Transfer values are shown in Table 3. TLC7226I. Input Control Logic unipolar output operation The unipolar output operation is the basic mode of operation for each channel of the TLC7226. The TLC7226 can be operated with a single power supply (VSS = AGND) or with positive/negative power supplies. 1 LSB + V ǒ ref 2 –8 + V Ǔ 1 ref 256 ǒ Ǔ 0V Figure 7. TLC7226M QUADRUPLE 8ĆBIT DIGITALĆTOĆANALOG CONVERTERS ą SLAS060E – JANUARY 1995 – REVISED JANUARY 2003 PRINCIPLES OF OPERATION interface logic information (continued) 17 To Latch A A0 A1 16 To Latch B To Latch C WR 15 To Latch D Figure 6. with the output voltages having the same positive polarity as Vref. Unipolar Output Circuit POST OFFICE BOX 655303 • DALLAS. Unipolar Code 2 OUTA DAC LATCH CONTENTS MSB LSB 1111 1000 1000 20 OUTC 0111 0000 0000 1111 0001 0000 1111 0001 0000 ANALOG OUTPUT )V )V 255 ref 256 129 ref 256 ǒ Ǔ ǒ Ǔ V ) V ǒ128Ǔ + ) ref ref 256 2 ǒ Ǔ )V ǒ 1 Ǔ ref 256 )V 127 ref 256 NOTE A.ą TLC7226C. The voltage at Vref must never be negative with respect to AGND to prevent parasitic transistor turnon.

the output voltage remains at zero volts until the input code value produces a sufficient output voltage to overcome the inherent negative offset voltage. the output cannot be driven to a negative voltage. However. So when the output offset voltage is negative. with a negative voltage offset. because the most negative supply rail is ground. So the linearity in the unipolar mode is measured between full scale code and the lowest code which produces a positive output voltage. Effect of Negative Offset (Single Power Supply) This negative offset error. The output amplifier. The code is calculated from the maximum specification for the negative offset. TLC7226I. However.SLAS060E – JANUARY 1995 – REVISED JANUARY 2003 TLC7226C. linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. The transfer function would have followed the dotted line if the output buffer could be driven to a negative voltage. With a positive offset. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. TLC7226M QUADRUPLE 8ĆBIT DIGITALĆTOĆANALOG CONVERTERS ą PRINCIPLES OF OPERATION ą linearity. TEXAS 75265 . attempts to drive the output to a negative voltage. produces the breakpoint. 10 POST OFFICE BOX 655303 • DALLAS. the output voltage changes on the first code change. the voltage offset can still be either positive or negative. and gain error using single-ended power supplies When an amplifier is operated from a single power supply. For a DAC. not the linearity error. single power supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. Output Voltage 0V Negative Offset DAC Code Figure 8. resulting in a transfer function shown in Figure 8. offset.

TLC7226M QUADRUPLE 8ĆBIT DIGITALĆTOĆANALOG CONVERTERS ą SLAS060E – JANUARY 1995 – REVISED JANUARY 2003 APPLICATION INFORMATION bipolar output operation using external amplifier Each of the DACs of the TLC7226 can also be individually configured to provide bipolar output operation. Therefore.ą TLC7226C. TEXAS 75265 11 . Bipolar Output Circuit staircase window comparator In many test systems. Figure 9 shows a circuit used to implement offset binary coding (bipolar operation) with DAC A of the TLC7226. these resistors must match and track over temperature. then the output for that window is higher. it is important to be able to determine whether some parameter lies within defined limits. using an external amplifier and two resistors per channel. POST OFFICE BOX 655303 • DALLAS. REF R1† 4 TLC7226 _ _ DAC A † R1 = R2 = 10 kΩ ±0. With a reference of 2. The TLC7226 can be operated with a single power supply or from positive and negative power supplies. the minimum window size is 10 mV. A Mismatch between R1 and R2 causes gain and offset errors. Upper and lower limits on both VOH and VOL can be programmed using the TLC7226. In this case: V O + 1 ) R2 R1 ǒDA Ǔ V ref V ref Ǔ * R2 ǒVrefǓ R1 (2) with R1 + R2 V O + 2D * 1 A ǒ where D is a fractional representation of the digital word in latch A. TLC7226I.56 V applied to the REF input. When the test voltage (Vtest) is within a window.1% + –15 V 2 + VO 15 V R2† Figure 9. Each adjacent pair of comparators forms a window of programmable size (see Figure 11). The staircase window comparator shown in Figure 10 is a circuit that can be used to measure the VOH and VOL thresholds of a TTL device under test.

TLC7226M QUADRUPLE 8ĆBIT DIGITALĆTOĆANALOG CONVERTERS ą APPLICATION INFORMATION staircase window comparator (continued) Reference Voltage Vtest From DUT 4 REF + _ 5V 2 VOH 10 kΩ + _ Window 2 + _ + _ Window 1 5V 10 kΩ ą OUTA TLC7226 1 VOH 5V 10 kΩ OUTB + _ Window 3 + _ 5V 10 kΩ + _ Window 4 + _ 5V 10 kΩ + _ Window 5 + _ OUTC 20 VOL OUTD AGND 5 19 VOL Figure 10. Logic Level Measurement 12 POST OFFICE BOX 655303 • DALLAS.SLAS060E – JANUARY 1995 – REVISED JANUARY 2003 TLC7226C. TLC7226I. TEXAS 75265 .

TEXAS 75265 13 .ą TLC7226C. Reference Voltage Vtest From DUT 4 REF OUTA 2 + _ 5V 1 10 kΩ + _ Window 2 20 + _ + _ Window 1 5V 10 kΩ OUTB TLC7226 OUTC 5V 10 kΩ OUTD 19 + _ Window 3 + _ AGND 5 Figure 12. TLC7226M QUADRUPLE 8ĆBIT DIGITALĆTOĆANALOG CONVERTERS ą SLAS060E – JANUARY 1995 – REVISED JANUARY 2003 APPLICATION INFORMATION staircase window comparator (continued) REF Window 1 OUTA Window 2 OUTB Window 3 OUTC Window 4 OUTD Window 5 AGND Figure 11. five different nonoverlapping programmable window possibilities can again be defined (see Figure 13). When the three outputs from this circuit are decoded. TLC7226I. Adjacent Window Structure The circuit can easily be adapted as shown in Figure 12 to allow for overlapping of windows. Overlapping Window Circuit POST OFFICE BOX 655303 • DALLAS.

TLC7226I. TLC7226M QUADRUPLE 8ĆBIT DIGITALĆTOĆANALOG CONVERTERS ą APPLICATION INFORMATION staircase window comparator (continued) REF OUTB Windows 1 and 2 OUTA Window 2 OUTD Windows 2 and 3 OUTC Window 3 Window 1 ą AGND Figure 13. AC Signal Input Scheme 14 POST OFFICE BOX 655303 • DALLAS. The output can be shorted to AGND indefinitely or it can be shorted to any voltage between VSS and VDD consistent with the maximum device power dissipation. Figure 14 shows the general schematic.75 V.SLAS060E – JANUARY 1995 – REVISED JANUARY 2003 TLC7226C. 15 V R1 15 V _ AC Reference Input Signal R2 + OP07 Vref 4 DAC AGND 5 1/4 TLC7226 _ + DGND 6 VO Figure 14. When this configuration is used. A low output-impedance buffer should be used so that the input signal is not loaded by the resistor ladder.25 V to 15. TEXAS 75265 . VDD should be 14. Overlapping Window Structure output buffer amplifier The unity-gain output amplifier is capable of sourcing 5 mA into a 2-kΩ load and can drive a 3300-pF capacitor. multiplying DAC The TLC7226 can be used as a multiplying DAC when the reference signal is maintained between 2 V and VDD – 4 V.

012 (0.49) 0. Falls within JEDEC MS-013 POST OFFICE BOX 655303 • DALLAS.016 (0.03) 0.78) A MAX A MIN 0.050 (1.ą TLC7226C.006 (0.610 (15.510 (12. B.014 (0.050 (1.95) 0.10) 0. TEXAS 75265 15 .15).010 (0.104 (2.51) 0.35) 16 9 0. D.15) 0.25) NOM Gage Plane 0. TLC7226I.45) 0.710 (18.299 (7. TLC7226M QUADRUPLE 8ĆBIT DIGITALĆTOĆANALOG CONVERTERS ą SLAS060E – JANUARY 1995 – REVISED JANUARY 2003 MECHANICAL DATA DW (R-PDSO-G**) 16 PIN SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0.010 (0.41) 0. All linear dimensions are in inches (millimeters).293 (7.25) 1 A 8 0°–ā8° 0.70) 24 0.004 (0.10) 4040000/B 03/95 NOTES: A.400 (10.020 (0.700 (17.010 (0.30) 0.400 (10.25) M PINS ** 16 0.24) 28 0.600 (15.500 (12.65) MAX 0.410 (10.59) 0.004 (0.65) 0. C.40) Seating Plane 0. Body dimensions do not include mold flash or protrusion not to exceed 0.27) 0. This drawing is subject to change without notice.16) 20 0.419 (10.27) DIM 0.

40) 0. C.020 (0.064 (1.78) 0.080 (2.76) 0.22) 0.09) 0.020 (0.010 (0.028 (0. TLC7226M QUADRUPLE 8ĆBIT DIGITALĆTOĆANALOG CONVERTERS ą MECHANICAL INFORMATION FK (S-CQCC-N**) 28 TERMINAL SHOWN ą LEADLESS CERAMIC CHIP CARRIER 18 17 16 15 14 13 12 NO.23) 0.99) MAX 0. TLC7226I.458 (11.63) 0. OF TERMINALS ** 11 10 28 9 8 7 6 68 5 84 44 52 20 A MIN 0.51) 0.858 (21.358 (9.035 (0.14) 0.022 (0.047 (26.342 (8.165 (29.358 (9.6) 1.938 (23.09) 0.43) 1. D.26) 0.63) 0.89) 4040140/D 10/96 NOTES: A.54) 0.31) 0.89) 0.8) 1.6) B MAX 0.739 (18.660 (16.442 (11.850 (21.14) 0.307 (7.58) 0.59) MIN 0.63) 0.51) 0. This package can be hermetically sealed with a metal lid.141 (28.560 (14. The terminals are gold plated.25) 0.495 (12.962 (24. TEXAS 75265 .14) 0. B.045 (1.761 (19.495 (12.03) 0.035 (0. Falls within JEDEC MS-004 16 POST OFFICE BOX 655303 • DALLAS.055 (1.22) 0.045 (1.045 (1.32) 0.010 (0.458 (11. E.640 (16.406 (10.560 (14. All linear dimensions are in inches (millimeters).69) 0.25) 0.SLAS060E – JANUARY 1995 – REVISED JANUARY 2003 TLC7226C.0) 19 20 21 B SQ 22 A SQ 23 24 25 26 27 28 1 2 3 4 0.80) 0.71) 0.063 (27. This drawing is subject to change without notice.58) 0.83) 1.050 (1.27) 0.

38) 0°–ā15° 0.10) 1 8 0.69) 0.25) NOM 0.310 (7.290 (7. C.010 (0.37) 0. B.78) MAX 0.37) 0.ą TLC7226C.60) 0.010 (0.940 (23.745 (18.975 (24.240 (6. All linear dimensions are in inches (millimeters).070 (1.775 (19.035 (0.260 (6.775 (19.59) 20 0.020 (0.53) 0.850 (21. TLC7226I.54) 0.89) MAX 0.25) M 14/18 PIN ONLY 4040049/C 08/95 NOTES: A.92) 18 0. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001) POST OFFICE BOX 655303 • DALLAS.920 (23.021 (0. This drawing is subject to change without notice.92) 16 0.200 (5. TLC7226M QUADRUPLE 8ĆBIT DIGITALĆTOĆANALOG CONVERTERS ą SLAS060E – JANUARY 1995 – REVISED JANUARY 2003 MECHANICAL DATA N (R-PDIP-T**) 16 PIN SHOWN PINS ** DIM A 16 9 A MAX PLASTIC DUAL-IN-LINE PACKAGE 14 0. TEXAS 75265 17 .015 (0.125 (3.18) MIN 0.88) A MIN 0.87) 0.08) MAX Seating Plane 0.69) 0.77) 0.100 (2.745 (18.51) MIN 0.

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