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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 7, JULY 2007

**Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester
**

Yoshiyuki Nakamura, Member, IEEE, Thomas Clouqueur, Member, IEEE, Kewal K. Saluja, Fellow, IEEE, and Hideo Fujiwara, Fellow, IEEE

Abstract—Numerous solutions have been proposed to reduce test data volume and test application time during manufacturing testing of digital devices. However, time to market challenge also requires a very efﬁcient debug phase. Error identiﬁcation in the test responses can become impractically slow in the debug phase due to large debug data, slow tester speed, and limited memory of the tester. In this paper, we investigate the problems and solutions related to using a relatively slow and limited memory tester to observe the at-speed behavior of fast circuits. Our method can identify all errors in at-speed scan BIST environment without any aliasing and using only little extra overhead by way of a multiplexer and masking circuit for diagnosis. Our solution takes into account the relatively slower speed of the tester and the reload time of the expected data to the tester memory due to limited tester memory while reducing the test/debug cost. Experimental results show that the test application time by our method can be reduced by a factor of 10 with very little hardware overhead to achieve such advantage. Index Terms—Error analysis, fault diagnosis, self-testing.

I. INTRODUCTION UILT-IN self-test (BIST) has become one of the major test techniques for today’s large scale and high speed designs. Pseudo-random BIST designs are the most widely used due to their relative simplicity and low cost [1]. Since BIST compacts test responses, BIST requires only small tester memory and it can perform at-speed test even if the tester frequency is substantially lower than the frequency of the circuit during test. On the other hand, BIST causes problems in diagnosis due to its compacted responses. Indeed, pass/fail information obtained from a BIST response analyzer is insufﬁcient for diagnosis. Two kinds of information are required to identify a fault in a circuit under test (CUT), namely the time information, and the space information. Using time information, fault diagnosis can be performed for a given fault model by methods using dictionary or fault simulation [2]. Using space information, diagnosis

Manuscript received October 21, 2006; revised January 30, 2007. This work was supported in part by the Japan Society for the Promotion of Science (JSPS) under Grants-in-Aid for Scientiﬁc Research B 15300018, JSPS Invitation Fellowship for Research L04509, and by the 21st Century Center of Excellence (COE) Program (Ubiquitous Networked Media Computing). Y. Nakamura is with Design Systems Division, NEC Electronics Corporation, Nakahara, Kawasaki 211-8668, Japan (e-mail: y.nak@necel.com). T. Clouqueur was with Nara Institute of Science and Technology, Nara 6300192, Japan. He is now with Advanced Micro Devices Inc., Boxborough, MA 01719 USA (e-mail: thomas.cloucueur@amd.com). K. K. Saluja is with Department of Electrical Engineering, University of Wisconsin-Madison, WI 53706-1691 USA (e-mail: saluja@ece.wisc.edu). H. Fujiwara is with the Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science City, Nara 630-0192, Japan (e-mail: fujiwara@is.naist.jp). Digital Object Identiﬁer 10.1109/TVLSI.2007.899235

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can be performed by cone of logic methods [3]. High resolution diagnostic for a given fault model can be achieved by diagnosis techniques combining space information with time information [4], [5]. A number of methods to identify space information have been proposed, especially for scan-based BIST architecture [6]–[11], however, only a few practical techniques have been developed to identify time information. Some of the existing techniques are based on signature analysis using cycling register [11], [12] and error correcting codes [13]. These methods compact the complete test response into one signature and attempt to identify errors from the signature. Since they observe signature only once, they require only small tester memory and they are also usable even if the circuit frequency is much higher than the tester frequency. However, for large number of error bits, say errors, they need as many as -LFSRs or signature registers and may have over 40% diagnostic aliasing if the actual number of errors is higher than [13]. Thus, they either have poor diagnostic resolution or require impractically high hardware overhead to achieve maximum diagnostic resolution. An alternative approach trades off overhead for time by repeating the test sequence and compacting it at each iteration into a different signature [14]. Thus, instead of using -LFSRs, the test sequence is repeated times using programmable LFSR to identify errors. Since it is mathematically equivalent to [13], diagnostic aliasing is the same as using -LFSRs. Thus, identifying all the errors requires repeating the test sequence an impractically large number of times. Techniques that use two phases for diagnosis have also been proposed [15]–[17]. During the ﬁrst phase, intermediate signature is checked a few times during test in order to narrow down the failing candidates within some windows of ﬁxed or variable size. The failing patterns are then identiﬁed inside the windows by applying the corresponding patterns one at a time [15], [16]. These methods use small hardware overhead and/or reduce test application time but they assume the existence of a mechanism to observe the at-speed behavior inside of failing windows. Enhancement of these methods has also been studied using multiple signature analyzers [17], but they do not achieve maximum diagnostic resolution. A commonly used diagnosis technique that requires and collects the failing space and time information, without compacting responses, during the diagnosis phase [18] suffers from the following two problems. 1) it requires the circuit to operate at the tester frequency during test; therefore, the faults that affect only at-speed operation may not be diagnosable. Note that in at-speed scan based BIST environment, the circuit needs to be operated in at-speed conditions only for the capture cycles, and it needs not operate in at-speed conditions in the shift cycles. However,

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Fig. 1–3 demonstrate this through an example. Therefore. 1. achieves minimum test application time in general. Therefore. However. Section VI summarizes the conclusions of our analysis. slow down of frequency of shift cycles to meet the tester limit frequency. A preliminary version of this paper was presented at the 19th Asian Test Symposium [21]. the tester cannot observe every response by simply repeating are observed repeatthe sequence since only bits edly. it is important that we operate shift cycles as fast as possible unless such operation can cause critical damage for layout or power reasons. 2) this method requires all expected responses of scan cells to be loaded into the tester. while observing its reand are not co-prime sponse at every time period . but the second problem remains. In Section IV. Problem Formulation In this section. we also consider tester loading time in optimizing the overall diagnosis effort. II. often testers do not have enough memory to store all expected scan cell data of all BIST sequences. frequency of shift operation tends to exceed the tester frequency. and this can be very time consuming. we formulate the problem of identifying every error occurrence in minimum test time. and propose a method to reduce test application time by pattern grouping and using signature analyzers. Scan out and observed results (error unobservable). Every error can be identiﬁed even if the circuit test frequency is higher than the tester frequency. The tester can observe all responses by apwhere plying the BIST test sequence times. applying 51 clocks).. we describe the method given in [19] that can identify all failing responses by observing scan outputs even if the CUT test frequency is faster than the maximum tester frequency (in sequel. every cycle can be observed by repeating the BIST sequence three times (i. if the length of the BIST sequence is 18. We assume that the pattern generator (PG) is reset to the initial state after generating the last pattern. expected data in such a scheme must be reloaded many times to the tester memory. If or or both can be adjusted to make them co-prime. In Section III. Therefore. this can be very time consuming. In Section V. Then bits quence. We ﬁrst identify some . In addition. thus making at-speed diagnosis impossible. be the clock frequency of the CUT. Fig. For example. Figs. During the ﬁrst se. a tester can observe only 1/3 of the responses. Therefore. by inserting no more than clock cycles. the tester observes response bits are observed during the second sequence and bits during the third sequence. Multiple iteration observation (successful). III. OBSERVING RESPONSES BY A SLOW SPEED TESTER Before providing a formulation of the problem. . In this paper. and it cannot be changed during testing. including tester loading time. it will not be able to identify all possible failing responses in one BIST sequence. Clearly one of the reasons to move to BIST environments is to contain the cost of testing by employing low cost testers. we will call the maximum test frequency tester frequency limitation). Let be the length of the BIST sequence. 3. the low cost testers are unlikely to have sufﬁcient memory to store all expected scan cell data of all BIST sequences [20].e.NAKAMURA et al. we formulate the problem of identifying failing responses in minimum test time. If the BIST sequence is 17 cycles long. Fig. we brieﬂy introduce a procedure to identify every error without any aliasing in at-speed scan BIST environment proposed in [19]. In addition. the ratio of a frequency of capture clock cycle and frequency of shift cycle is usually ﬁxed at BIST design phase. We can identify all erroneous responses with a slow speed tester using this method. CUT and observe intervals. we show the effectiveness of our method through experimental results and discuss the relationship between the error probability and optimal group size. there is a way to observe all responses without adding any extra hardware. unlike the conventional approaches. USING SIGNATURE ANALYZERS A. we must reload the expected data many times to the tester. albeit requiring all expected responses of scan cells to be loaded into the tester. 2. will also slow down the capture cycle frequency. for the sake of completeness of this paper. The method proposed in [19] addresses the ﬁrst problem. Nevertheless.: DIAGNOSING AT-SPEED SCAN BIST CIRCUITS 791 to contain the testing time. This paper is organized as follows. and be the tester frequency limitation. Note that such a method may not always allow observing all bits by simple repetition of the sequence. However. then It is shown in [19] that increasing only the length of the BIST additional dummy sequence . then the conditions to observe all responses is . as shown in Fig. We must also point out that in a BIST environment the frequency of shift cycles is not limited by the tester frequency because scan outs are not observed directly by the tester in product testing phase. When the CUT clock period is 2 ns and the tester observing period is 6 ns. In Section II. we analyze the test time of the method proposed in Section III to ﬁnd the optimal group size. we investigate methods to identify every error occurrence in at-speed scan-based BIST environment. A formal description of this problem and its proof are given in Appendix II. 3. Clearly. Thus.

thus satisfying the constraints speciﬁed in the problem formulation. This study aims at minimizing the test time. 4. we assume that the CUT scan out operates at frequency . however.792 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. it will be acceptable to base a diagnostic decision when sufﬁciently many erroneous responses for diagnosis are identiﬁed. 4. Thus.. Test data of ﬁrst phase. the error bits would need to be identiﬁed only in these two groups during the second phase. error detection methods using signature analyzer(s) require less tester memory. B. the test time. Our formulation concerns the error identiﬁcation of a scan-based BIST circuit. however. which are identiﬁed in the ﬁrst phase. Test data of second phase. In this example. test time will be much shorter than the method introduced in Section II. Some erroneous responses may be dropped due to aliasing of signature analyzers in the ﬁrst phase. test data of the second group and the group are loaded onto the tester as shown in Fig. it is important that the fault diagnosis algorithm is not overwhelmed by excessive error information. Another characteristic of the diagnosis process is that the quality of diagnosis is far more important than any other factor. We also constrain the number of errors to be identiﬁed to . such that can be slower than scan capture clock frequency which should be operated at-speed frequency. Therefore. which reduces test time including tester loading time. the fault diagnosis must not be overloaded by the error information to achieve the required diagnostic resolution. During the ﬁrst phase. including the test application time. The second phase identiﬁes erroneous bits in the erroneous pattern groups identiﬁed in the ﬁrst phase. Diagnosis can be performed for devices that did not pass the production test or devices that passed the production test and were found to be faulty in the ﬁeld. Signature Analyzers for Error Identiﬁcation The method introduced in Section II does not use signature analyzers. i. Note that the test data size for error identiﬁcation is much smaller than the prior approach explained in Section II since only the test data of erroneous groups are loaded onto the tester. Note that at a frequency higher than . Notice that the seed of PG is needed only for the ﬁrst group since all groups are tested consecutively. It is imperative that the reported (required) number of errors be limited to achieve the targeted diagnostic resolution. fewer reloadings. The objective of the problem is to minimize the test time while meeting the error identiﬁcation requirement. In the at-speed BIST environment. any error-free response will not be identiﬁed as erroneous. testing during diagnosis should be performed at the speed that resulted in the failure of the device. Each pattern group includes the seed for the pattern generator that consists of the state of the pattern generator at the end of the previous group. as argued in the previous subsection. it can achieve maximum diagnostic resolution without aliasing. Note that the tester loading time should be included in the test time as mentioned in Section II. The failing responses are then identiﬁed inside the windows during the second phase using the method introduced in Section II for at-speed BIST environment. In each case. all the BIST sequences are divided into Fig. are loaded onto the tester and by using error identiﬁcation procedure proposed in Section II all errors. 5. we propose an error identiﬁcation procedure that uses signature analyzers in two phases. But. The test data is divided into groups. The erroneous pattern groups are identiﬁed by observing the results of the signature analyzers. can be identiﬁed. larger groups in the ﬁrst phase imply increased error . including tester loading time signiﬁcantly increases when the test sequence becomes very long. In the ﬁrst phase. Also. Fig. NO. larger groups result into a larger reduction in the test data. However. VOL. in particular by determining the optimal window size for use in phase one. We constrain BIST to operate at-speed during diagnosis. the formulation we are interested in this paper is to optimize the test application time subject to meeting the given quality of diagnosis. 7. Thus. the test results of the second and th groups are found to be erroneous. In this paper. On the other hand. Therefore. the intermediate signature is checked in order to narrow down the error candidates within some windows [15]–[17]. The ﬁrst phase identiﬁes erroneous groups. The seeds of the ﬁrst group and all expected signatures are loaded onto the tester. The test pattern is then generated by the pattern generator and the scan out responses are compacted into signature analyzers. 5 and all responses are observed to identify the errors. For the example th shown in Fig.e. Let us explain this through an example as shown in Fig. 1) Two-Phase Error Identiﬁcation: To enable two-phase error identiﬁcation. The group size should be large enough to reduce the test data in this ﬁrst phase. The seeds and the expected responses of the erroneous pattern groups. Each pattern group also includes the expected signature for the group. in each error group. Note that the methods using signature analyzers cause diagnostic aliasing and it is undesirable when an erroneous response is miss-identiﬁed as error-free since it can lead to misdiagnosis. and an error-free response must not be identiﬁed as erroneous. therefore. groups. whereas the tester has a frequency limitation and cannot operate . JULY 2007 characteristics of the diagnosis and production testing processes. 4. 15.

we could achieve this by repeating the BIST sequence times. detects no error and the signature analyzer SA2. Later in this paper. there is an optimal group size for minimum test time. using signature analyzers can be estimated as follows. 7. the clocks are usually generated by a PLL circuit. lected by masking circuit. the probability of skipping one BIST iteration is . selected by the multiplexers. (2) where is the probability that iterations are is skipped. each signature analyzer compacts responses of one scan chain which is sesignature analyzers. A Register FF is inserted at the multiplexer output to synchronize the scan chain with the tester since the CUT test frequency may be higher than the tester frequency. 7 is based on the scan-based BIST which is one of the most commonly used architectures. only one group in one scan chain. provided more than three signature analyzers are used. The number of BIST iterations. in turn. In the ﬁrst phase of the identiﬁcation procedure. where is the size of a pattern group. 7. can be tested since we use noncompaction-based approach in the second phase. . Therefore. scanouts are connected to an output port via a multiplexer during diagnosis as in the noncompactionbased approach [19]. A counter is associated with each SA to select the responses to be observed by the signature analyzer. If a signature is not erroneous. using signature analyzer(s) (3) where is the size of each signature analyzer. Further. and so on. Diagnosis with error detector signature analyzers. Multiple input signature registers can be used as signature analyzers during testing. a masking circuit allows only one scan chain to feed a signature analyzer which is selected by input “mask select. signature analyzers compact the responses which are to be observed by the tester in the second and the third BIST iterations.” As shown in Fig. BIST Architecture Fig. 7 shows a BIST architecture with a single output and the logic required for diagnosis. The hardware overhead of the scheme consists of these signature analyzers and counters. 2) Reducing BIST Iterations: Fig. Assuming that we can skip iterations using signature analyzers. If there are pattern groups in different scan chains can be simultaneously tested. If no signature analyzers were used and we wish to observe all responses with a slow tester. The number of BIST iterations is . If then the previous expression can be approximated as is large (4) This equation will be used later for optimizing the group size. during the third iteration the signature analyzers compact the responses which are to be observed by the tester in the fourth and ﬁfth iterations.NAKAMURA et al. On the other hand. it is shown that the expected value of computed as follows: can be Fig. The BIST pattern generator (PG) provides scan inputs and the signature analyzers (SAs) compact the responses. While the tester observes the response of the ﬁrst iteration of the BIST sequence. it is also shown in [19] that nearly equal to the probability of no errors ( ).: DIAGNOSING AT-SPEED SCAN BIST CIRCUITS 793 Fig. The CUT and the BIST circuits operate at-speed. The FF samples the signal produced by the scan chain and holds the value during one tester period. will cause larger test data in the second phase Therefore. During diagnosis. probability for each pattern group. if the signature analyzer SA1. BIST architecture for two-phase error identiﬁcation. in the second phase. Also. 6. C. the tester skips the second iteration and observes the third iteration. 6 shows a BIST structure with the error detectors proposed in [19]. detects an error. we can skip the corresponding iteration. For example. The BIST architecture of Fig. A responses in one BIST signature analyzer compacts iteration. we deduce the optimal group size for the previous two phase error identiﬁcation method. This. then (1) In [19].

e. Clearly the group size should be chosen to minimize test time. ﬁed in Step 1. Step 1. Apply scan output every test cycles by the tester. 7.1. set iteration number which corresponds to the signature analyzer with erroneous result. However. The size of pattern group is . Select an erroneous group which is identi. as follows: Set the next BIST iteration counter if no signature analyzer detects errors then. Repeat Step 2-wsa. identify erroneous pattern groups.2. set . the number of groups . Tester Loading Rate Test data is prepared for each faulty chip in the fault diagnosis phase. erroneous pattern groups. Test frequency of CUT: . NO. Step 2-sa. If an error is detected at the vation.. Step 2-sa. To satisfy the condition it is sufﬁcient to adjust only by inserting dummy clocks for the minimum test application time. Target number of errors identiﬁed: .7 until at most errors are identiﬁed. Observe each signature analyzer by the tester. while observing one scan output every test cycles. Failing scan pattern . Total number of BIST iterations is: Step 2-wsa. Step 2-sa. Erroneous scan cell Step 2-wsa. The counter is incremented by each tester observation. the problem formulation and solution related to this aspect is given in Section IV. Number of signature analyzers: BIST test length: . . VOL. Set observation time period . Apply clocks to BIST pattern generator. Step 2-sa.4.2.3. where is the minimum BIST else. This step is followed if signature analyzers are not used during the error identiﬁcation phase. th obserStep 2-wsa. such that Adjust the BIST test length to and are co-prime. Adjust the BIST test length to where is the number of iterations to be skipped Set and tester observation counter to Step 2-sa. Thus the tester loading time and : follows using two constants #of tester loads (5) where is the test volume. 15. Let be the tester memory size. .1–1. . the tester should load the test data several times. Select an erroneous group which is identiﬁed .4..1 to Step 2-wsa.e. Identify erroneous scan cell and pattern (without using signature analyzer). Repeat Step2-sa.8.5. The maximum resolution is and the number of BIST achieved if and only if . OPTIMIZING GROUP SIZE A. Note that each of the signature analyzers compacts the scan output which will be observed by the tester in BIST iteration.3 to Step2-sa. Note that is small and can be found easily as shown in Appendix II. Repeat Step2-sa. The size of pattern group is Step 2-wsa. clocks to CUT. Number of pattern groups: . Therefore. Step 1. Step 2-sa. iterations is at least .2. If an error is detected at the th observation.3. Step 2-wsa. the tester loading (7) . it has not been shown yet how to decide the size of group . Set observation time period such that and Adjust the BIST test length to are co-prime. tester loading time cannot be ignored especially in view of the fact that the tester may not have sufﬁcient memory for all test data. In this case. Number of scan out clock cycles including capture operation: . IV.4 until at most errors are identiﬁed.1. i. Given condition.5 while . Step 1. respectively. Reset the BIST iteration and tester observation counter .7. Reset the BIST iteration counter and tester observation counter . Erroneous scan cell Step 2-sa. .3. Step 2-sa.1.794 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. Apply BIST sequence and identify signature analyzers containing erroneous signatures. JULY 2007 D. As shown in Appendix I. Identify erroneous scan cell and pattern (with signature analyzer). Procedure of Error Identiﬁcation Based on Sections III-A–III-C.6. Select untested pattern groups for each signature analyzer. while observing a Step 2-sa. Therefore (6) Note that and the tester. then: . The tester loading time will normally be proportional to the test data volume and the overhead associated with each tester can be expressed as loading. Denote time is are parameters associated only with . i. then: Failing scan pattern = .1 to Step2-sa. Repeat step 1. then the number of tester loading is . Step 1. in Step 1. Note that is small and can be obtained as shown in Appendix II. This step is followed if signature analyzers are used during the error identiﬁcation phase.5.2 until all pattern groups are tested. Tester frequency limitation: . counter Step 2-wsa. the procedure for identifying error occurrences is as follows.

we estimate the test time for the error identiﬁcation procedure which is proposed in Section III-D. We use (13) and (15) to obtain Total test time including loading time is 2) Analysis of Step 2-wsa (Without Signature Analyzer): We identify erroneous responses in the error identiﬁcation procedure Step 2. The total test time including tester loading time is Total test time test application time tester loading time. number of signature analyzers. the expected number of erroneous bits in one group is (11) Therefore. the test application time of Step 2 without signature analyzer is (13) The test volume is (14) 3) Analysis of Step 2-sa (With Signature Analyzer): When we use signature analyzers in Step 2 as introduced in Section III-B. size of the expected response of one group. CUT test frequency. At the end of the BIST session. tester frequency.1% and we need to identify 1000 errors. Let the size of signature analyzer and pattern generator be 64 bits. total test time including loading time is (10) Example 1: Let the total length of a BIST sequence be 500-M clocks which is divided into 5-M groups. And since only erroneous groups are tested in Step 2. 1) Analysis of Step 1: The error identiﬁcation procedure Step 1 identiﬁes erroneous pattern groups. In Step 1 we groups simultaneously using signature analyzers. we have to read out signature at the end of each BIST session. the test application time of Step 1 is B. the test application time of Step 1 is (8) The total test volume for Step 1 is Total test time including loading time is (9) Therefore. We use following notation in the analysis that follows: total length of the BIST sequence. the expected number of groups contains errors is (12) If we do not use signature analyzers in Step 2. we use that the parameter as the bit rate of tester loading. number of groups of all scan chains . Note reﬂects tester memory limitation also. target number of errors to be identiﬁed. the tester frequency be 40 MHz. Analysis of Test Time In this subsection. Therefore.NAKAMURA et al. The test application time of Step 1 can be estimated as follows. Let the CUT test frequency be 800 MHz. number of groups identiﬁed erroneous in Step 1. the test application time without reading signature analyzer and setting pattern generator is (16) . The test time for Step 1 is computed as follows: We have the following parameters: (15) Example 2: Let all the parameters be the same as in Example 1. bit size of signature. In this case the test time for Step 2 is computed as follows. the BIST pattern should be applied in / times. Let the probability of 1 bit error occurrence be 0. the average number of BIST iterations using signature analyzer in Step 2. 7. and tester loading rate be 150 Mbit/s. we read out the signature. we must apply BIST sequence times for erroneous groups. Therefore.: DIAGNOSING AT-SPEED SCAN BIST CIRCUITS 795 In this paper. be the average number of BIST iterations using signaLet ture analyzer which is deduced in Section III-D. The error identiﬁcation procedure will be ﬁnished when we identify predetermined errors. We assume that we read out signatures on one output port as shown in Fig. bit rate for loading to the tester. bit size of pattern generator. test Therefore.

796 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. . 9. resulting in more time being spent in observing signatures. We can ﬁnd the optimal . EXPERIMENTAL RESULTS A. Therefore. The PG and SA are general LFSR and MISR. we analyze the total test time including tester loading time for Step 1 and Step 2 with and without signature analyzers. In Section V. respectively. and propose a practical group size . tester can observe scan out at 40 MHz by a tester synchronization circuit as described in Section III-C. since the BIST operation is adjusted and repeated several times as described in Section III-D. we have to load all BIST sequences to the tester memory. It is because very small groups need too much expected signature data to be loaded onto the tester which causes many tester reloadings. 8. we show the distribution of the error probability for a large industrial circuit which is obtained by simulating randomly selected 100 single stuck-at faults. Test time as a function of group size (at typical error probability). there is an optimal point of group size to minimize total test time. However. 7. 9 shows that the test time of Step 1 is signiﬁcantly increased when group size becomes very small. 4) Optimizing the Group Size: In this section. Fig. . there is an unknown parameter in (19) which depends on the existence of fault(s) in the chip and its manifestation as an error. In this experimental case. It is because we perform Step 2 only for groups identiﬁed as erroneous in Step 1. JULY 2007 TABLE I EXPERIMENTAL CIRCUIT Fig. the error probability is almost in the . The test time of Step 1 becomes constant when we use sufﬁciently 5000 bits). we will show the effect of using signature analyzers in Step 2. We ﬁrst conduct an experiment without signature analyzers in Step 2 to ﬁgure out the relationship between group size and the error probability. 2) Typical Error Probability Case: We plot the total test time including tester loading time using equations deduced in Section IV. 9 also shows that smaller group size is efﬁcient to minimize the test time of Step 2. The experimental circuit is a part of an SoC developed at NEC Electronics Co. Distribution of error probability. each scan operation needs a capture cycle. 15. we will do some experiments to show the relationship between error probability and optimal group size . and typically near range of . 5860 bits is the optimal group size. which minimizes grouping size (19) by using common solver tools. in this section. Optimal Group Size 1) Distribution of Error Probability: We have shown that the test time of error identiﬁcation depends on the error probability. Since we do not know which BIST iteration can be skipped beforehand. In Fig. the test volume is (17) Again. VOL. Later. and then we investigate both lower and higher error probability cases. we ﬁrst investigate the typical case. By using (16) and (18). Fig. In this section. to identify 200 errors which we believe is sufﬁcient error information for diagnosing scan based design [3]–[5]. we get Fig. 9 shows the Step 1. 8. the total BIST test length will be much longer than the testing phase. An 800-MHz scan clock generated by PLL and provided to each scan FF is used. The total test time including loading time is (18) Example 3: Consider again the case described in Example 2 with using ﬁve signature analyzers. This total test time will be analyzed by experiments in this section. The BIST architecture shown in Fig. V. In the chip testing phase. Step 2 (without signature analyzer) and total test time as a function of group size . . and details of the circuit are provided in Table I. However. large group size ( Fig. 7 is used in this experimental circuit. the BIST test length is in the diagnosis phase. The parameters reﬂect the experimental circuit shown in Table I and we assume error probability is typical . and more error-free responses can be pruned when the size of group is smaller. 8. Therefore. Note that therefore. As shown in Fig. NO.

e. Fig. 14.: DIAGNOSING AT-SPEED SCAN BIST CIRCUITS 797 Fig. Optimized group size as a function of the error probability (using signature analyzer in Step 2). Fig. Step 2 (without signature analyzer) and total test time as a function of group size . Fig. Fig. which is around optimal solution for typical case. 13. 14 compares the test time with and without signature analyzers. By using smaller size of signature. procedure is terminated by ﬁnding Therefore. The optimal when the error probability is lower than group size much larger for higher error probability case. aliasing . to identify 200 errors. however. 3) High Error Probability Case: In the next experiment. we plot the test time for the case when the error probability is very low . 11 shows the Step 1. 12 shows the optimal group size as a function of the error probability. we have already shown in Section V-A3 that test time is not so inﬂuenced. sumption of B. Test time as a function of group size (at high error probability). to identify 200 errors. 10. we assume the error probability is very high .NAKAMURA et al. 11. no-grouping is needed. As shown in Figs. optimizing group size is much more important for low error probability case. Effect of Using Signature Analyzers in Step 2-sa In Section V-A. test time can be reduced. the solution for the optimal group size under typical error probability is also practically suitable for higher error probability case. Test time as a function of group size (at low error probability). Fig. range of error probability When we use signature analyzers for error identiﬁcation. Fig. 10 shows that the total test time is almost dominated by Step 1 when the error probability is very high. 13 shows the optimal group size as a function of . test time will reduce . However. Fig. 10 also shows that when the group size is larger than 5000. Fig. 4) Low Error Probability Case: Next. Figs. Fig. i. 12 shows that the optimal group size is almost constant . the test time grows signiﬁcantly longer in lower error probability case when we use larger group size. 14. 12 and 13. Test time with and without signature analyzers. Fig. the optimal group size of the case using signature analyzers in Step 2 also is can be obtained by solving (19) assuming sufﬁciently low. Fig. 9 and 11 show that the test time with optimal size group is almost identical for both typical and low error probability cases. the optimal grouping strategy for high error probability case may be as large as possible. Therefore. test time is almost constant. However. we discussed the optimal group size for the case that we do not use signature analyzers in Step 2 identiﬁcation procedure. As shown in Fig. by using signature for practical analyzers in Step 2. the optimal group size is larger than the case signature analyzers are not used. 5) Optimized Group Size: The next question is the relationship between the optimized group size and the error probability. Optimized group size as a function of the error probability. Step 2 (without signature analyzer) and total test time as a function of group size . As shown in Section III-B we can use signature analyzers in Step 2 to reduce the BIST iterations. Fig. Therefore. 10 shows the Step 1. however. Therefore. we conclude that the optimal size which minimizes test time can be obtained by solving (19) under the asto be fairly low. however. the relation between the error probability and the optimal size group is quite similar. Therefore. 12. it is also important to determine the proper signature size to minimize test time as argued in the following.. The test time of Step 2 is much shorter than the typical case since the Step 2 errors.

However. As shown in Fig. . The solution that miniTheorem 2: If and co-prime is such that . aliasing does not impact the test time even if the signature size is very small. Our method takes into consideration the tester loading time. VOL. there exists a co-prime of in any consecutive integers. the aliasing of signature analyzers is also taken into account by using (4). relative time at Fig. then the equation cannot have more can be expressed in two ways than one solution. Therefore. and . JULY 2007 We use the following notation: length of the BIST test sequence. However. . period of the tester relative to the CUT test clock period. 15 shows the test time for large signature and small signature is actually not so much different. Theorem 1: The maximum resolution is achieved if and only and the number of BIST iterations is at least if . we have to try other groups to identify more errors and it may increase test time. 15 shows that test time as a function of size of signature analyzers with optimized sized groups and typical error probability . Relative Time: The number of a scan clock cycle starting from the beginning of the current BIST iteration.e. which shows that . We also proposed how to decide the size of pattern group to minimize test time. imum resolution implies Let us assume that the number of BIST iterations is and . We assume that P is an integer and that . When a signature indicates no errors for erroneous responses. we conclude that our method can identify sufﬁciently many errors for diagnosis with minimum test application time with very little hardware overhead. 7. i. Let BIST sequence and be the adjusted tester observing period. ADJUSTING APPENDIX II ACHIEVE MAXIMUM RESOLUTION OF OBSERVATION AND MINIMUM TAT OR TO The adjustment of and/or is chosen to minimize the test be the adjusted length of the application time. In this experiment. The test application time is (20) APPENDIX I CONDITIONS TO ACHIEVE MAXIMUM RESOLUTION We use the following terms. it implies The number of observations in BIST iterations is . Test time as a function of size of signature analyzers. VI. Our approach requires only multiplexer and masking circuit for diagnosis which is quite negligible hardware overhead. otherwise using two solutions This shows that divides and since .. the maxor . The signature size when used in production testing is also suitable for diagnosis.. is and The range of assuming the response at is observed during the th BIST iteration. Then the response at the relative time 1 is observable has a solution . we conclude that the size of signature is not important for error identiﬁcation procedure. and. Therefore. Proof: Let us assume that the maximum resolution is achieved. 15. The proposed equations that are used to decide the optimal group size include the error probability. i. 15. probability will be increased. bits are observed in BIST sequences. The problem is to ﬁnd a pair that minimizes . Fig.e. with and co-prime. to achieve the We derive the relationship between and maximum resolution of observation. the set has to be . th observation. the experimental results show that the group size which is obtained under assumption of low error probability is also optimal for higher error probability cases. CONCLUSION In this paper. mizes (20) with for any integer Proof: Since . the observing resolution is maximum. 15.798 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. Our approach is efﬁcient even if the CUT test clock frequency is much higher than the tester frequency. we proposed a method for identifying erroneous responses for the BIST architecture in minimum test time. Absolute Time: The number of a scan clock cycle starting from the beginning of the ﬁrst BIST iteration. . Since for every are different. Therefore. Furthermore. Experimental results also show that our method reduces the test time by a factor of 10 compared to the methods that do not employ the signatures analyzers during diagnosis. therefore. minimum number of BIST iterations to observe every response. using different signature size will cost more hardware overhead and Fig. NO.

Kawasaki. [17] C. and a fellow of the JSPS. K.” in Proc. pp.. Kewal K. 2006. Int. we consider the case when . 230–235. no. Newcastle. “Improved fault diagnosis in scanbased BIST via superposition. Saluja served as an Editor of the IEEE TRANSACTIONS ON COMPUTERS (1997–2001). 451–460.. VLSI design and testing. First. Test Conf. and Ph. Kawasaki. Savir and W. therefore Next. Thomas Clouqueur (S’01–M’04) received the Engineering degree in electrical engineering from the Ecole Superieure d’Electricite. 2003. Liu and K. G. Bayraktaroglu and A. T. Comput. E-89-D. where he teaches courses in logic design. Prior to this. degrees in electrical and computer engineering from the University of Wisconsin. “Diagnosing at-speed scan BIST circuits using a low speed and low memory tester. A. W. pp. Maston.. 322–328. and has been engaged in the development of electronic design automation (EDA) for testing. New York: Wiley Interscience. Chakrabarty. Des. [14] Y. “Effective diagnostics through interval unloads in a BIST environment. he was at the University of Newcastle. France. 894–902. Chakrabarty. The worst case of minimum is the case where . C. Syst. Fujiwara. A.D.” in Proc.. His research interests include VLSI design and testing and fault-tolerant computing. Shigeta and T.” in Proc. in 2004–2005. Damarla.. 2000. Saluja. “Failure diagnosis of structured VLSI. “An improved fault diagnosis algorithm based on path tracing with dynamic circuit extraction. pp. “Salvaging test windows in BIST diagnostics. Tyszer. and G. Japan. “Fault diagnosis in scan-based BIST. [5] K. Patel. 2001.. The best case of minis the case where . University of Wisconsin-Madison. microprocessorbased systems.-Aided Des. CA. pp. McAnney. 1999. in 1999.” in Proc. Autom.” in Proc. 39th Des. degrees in electronics and communication engineering from Meiji University. “A rapid and scalable diagnosis scheme for BIST environments with a large number of scan chains. 1997. 49–60. pp.NAKAMURA et al. Inf. E. pp. pp. He is a member of Eta Kappa Nu. He is currently a Senior Engineer at NEC Electronics Corporation. if mizes test application time. [15] J. Nara. H. Bayraktaroglu and A. In 1990.” in Proc.” in Proc. vol.. Boxborough. 2000. 593–604. 7. Similarly. San Jose. “Error identiﬁcation in at-speed scan BIST environment in the presence of circuit and tester speed mismatch. pp. Adham.” in Proc. He has held visiting and consulting positions at various national and international institutions including University of Southern California.E. He is currently a Professor with the Department of Electrical and Computer Engineering. [10] C.. vol. and H. Test Conf. 95–102. 1988. pp.. pp. Japan. Stroud. Orailoglu. and A. India. Touba. Hiroshima University. 235–244. therefore imum [19] Y. Dastidar. Nakamura. “BIST fault diagnosis in scan-based VLSI environments. Integr. 6. and the M. pp. (ATS’06). Waicukauski and E. Int. pp. in 2006. Fault Diagnosis of Digital Systems. O. and the Ph. 409–414. 3. Int. Test Eur. K. A. 2003. 273–282. Nara. Clouqueur. in 1967. Rajski and J. 6. C-29.” 2005. R. “Multiple fault diagnosis in combinational circuits based on effect-cause analysis. vol. Touba. S. “Deterministic partitioning techniques for fault diagnosis in scan-based BIST. VLSI Test Symp. the range of in (20) is . Saluja. 2006.” in Proc. Exhibition. Des. H. Int. Saluja (S’70–M’73–SM’89–F’95) received the Bachelor of Engineering (BE) degree in electrical engineering from the University of Roorkee. Ishiyama. Gif-sur-Yvette. [9] J. Conf. . [18] P. Bardell. Yoshiyuki Nakamura (S’04–M’06) received the B. degree in information science from Nara Institute of Science and Technology. 2000. 1987. [4] M. Ercevik. Abramovici and M. New York: Wiley.D. degrees in electrical and computer engineering from the University of Iowa. vol. Aug.” IEEE Trans. Saluja.S. Manning. Therefore.E.. the . Mets. in 1999 and 2003.D. 391–396. he joined NEC Corporation. 73–78. 1165–1172.” in Proc.: DIAGNOSING AT-SPEED SCAN BIST CIRCUITS 799 Therefore. and H. Liu and K. [20] The Semiconductor Industry Association (SIA). Japan.. Wohl. Savir. Nakamura.” IEICE Trans. Madison. pp. Sathaye. Das. “Identiﬁcation of failing tests with cycling registers. Wu and S. [2] H. 1997. we consider the case where range of is . Lindbloom. and G. H. vol. [7] I. 48–57. He was a COE Postdoctoral Fellow at the Nara Institute of Science and Technology. Comput. Jun. Testing: Theory Appl. Prof. Conf. “International technology roadmap of semiconductors. Tau Beta Pi. K. 1995. respectively.S. computer architecture. Int.” in Proc. [3] J.. 1989. D. in 1972 and 1973. He was the general chair of the 29th FTCS. Electron. 15th IEEE Asian Test Symp. “Multiple error detection and identiﬁcation via signature analysis. Kawasaki. 10–14. and H. Autom. and the University of Roorkee. [21] Y. and A. He has also served as a consultant to the United Nations Development Program. “Efﬁcient signature-based fault diagnosis using variable size windows. 55–58.. K. MA. pp. in 1988 and 1990. Japan. Japan.” J. 22. Test Conf. Circuits Syst. Chen. Ghosh-Dastidar and N. 1996. He is currently with Advanced Micro Devices Inc. Test Conf. Nara Institute of Science and Technology. 1970. Clouqueur. Fujiwara. He is currently the Associate Editor for the letters section of the Journal of Electronic Testing: Theory and Applications (JETTA). pp. 2000.. [11] J. and Ph. and M.” IEEE Trans. K. [13] T. built-in self-test. Takahashi. Built-in Test for VLSI: Pseudorandom Techniques. He has authored or co-authored over 250 technical papers that have appeared in conference proceedings and journals. Autom. including SCAN.” in Proc.. A. Conf. pp. and J. “Failing vector identiﬁcation based on overlapping intervals of test vectors in a scan-BIST environment. Australia. K. 4. is the solution that mini- REFERENCES [1] P. pp. [8] I. and the M. Breuer. “Fault diagnosis in scan-based BIST using both time and space information.” IEEE Design Test. His research interests include design for test. [12] J. Dr. and fault-tolerant computing. Savir. no. VLSI Test Symp. Orailoglu. Test Conf. T. 416–425. 193–207. Waicukauski. J. E. Y. Roorkee. “A partition-based approach for identifying failing scan cells in scan-BIST with application to system-on-chip fault diagnosis. [16] T. Test Conf. respectively. Iowa City. [6] J. Int. no. and SOC testing. 1980.” in Proc.. 2002. VLSI Des. pp. Information and Communication Engineers of Japan (IEICE) and a member of the Information Processing Society of Japan (IPSJ). Clouqueur. McAnney. Nakamura is a member of the Institute of Electronics.

parallel processing. digital systems design and test.E. 1971. test pattern generation. and. VOL. a fellow of the Institute of Electronics.800 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. an Okawa Prize for Publication in 1994. JULY 2007 Hideo Fujiwara (M’74–SM’83–F’89) received the B.. NO. and Ph. QC.. He served as an Editor of the IEEE TRANSACTIONS ON COMPUTERS. built-in self-test. in 1969. Osaka. an Editor of VLSI Design: Application Journal of Custom-Chip Design. Simulation. and 2001. Presently. Systems and Computers. Fujiwara was a recipient of an IECE Young Engineer Award in 1977. and computational complexity. an Associate Editor of the Journal of Circuits. and fault tolerant computing. Nara. he is a Professor at the Graduate School of Information Science. design for testability. He also served as an Advisory Member of IEICE Editorial Board and is currently an Advisory Member of the IEICE Transactions on Information and Systems. . Waterloo. He is the author of Logic Testing and Design for Testability (MIT Press. in 1984. he was a Visiting Associate Professor at McGill University. Dr. He is a Golden Core member of the IEEE Computer Society. test synthesis. 1985). and 1974. Montreal. including high-level/logic synthesis for testability. VLSI CAD. he was a Visiting Research Assistant Professor at the University of Waterloo. Japan. an IEEE Computer Society Certiﬁcate of Appreciation Award in 1991.E. respectively. and Testing. His research interests include logic design. an IEEE Computer Society Meritorious Service Award in 1996. Nara Institute of Science and Technology. M. and an IEEE Computer Society Outstanding Contribution Award in 2001. and joined Nara Institute of Science and Technology in 1993. Canada. ON. and a fellow of the Information Processing Society of Japan (IPSJ). 2000.D. In 1981. He was with Osaka University from 1974 to 1985 and Meiji University from 1985 to 1993. Canada. 15. Japan. 7. and several guest editors of special issues of IEICE Transactions. Information and Communication Engineers of Japan (IEICE). He served as an Associate Editor of the Journal of Electronic Testing: Theory and Application. degrees in electronic engineering from Osaka University.

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