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Introduction to Digital VLSI Design ‫ספרתי‬VLSI ‫מבוא לתכנון‬

Clock

Lecturer: Gil Rahav Semester B’ , EE Dept. BGU. Freescale Semiconductors Israel

Clock
Reference Signal in Sequential Elements.

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Most critical signal in synchronous designs Reference for all the timing measurements Single clock signal serves multiple flops/latches

Tdly2 Clock Skew = Tdly2 – Tdly1 For a successful signal launch and capture :i) ii) Tck-qff1 + Tdly3 <= T + Skew – Tsetupff2 Tck-qff1 + Tdly3 >= Skew + Tholdff2 .Clock tree concepts Clock Insertion Delay = Tdly1.

Skew calculated based on Rise edge at Clock Root Fall Skew :. .Clock Tree Concepts Rise Skew :.The time taken by signal to make a transition from 20%-80% of the full value.Skew calculated based on arrival times of active signal on clock pins Transition time :.Skew calculated based on Fall edge at Clock Root Triggering edge Skew :.

Clock Tree Architecture .

H-Tree Mesh .

clock skew is zero Clock Can insert clock gating at multiple levels in clock tree Can shut off entire subtree if all gating conditions are satisfied Idle condition Clock Gated clock .H-Tree Clock Network If the paths are perfectly balanced.

? .Clock Tree Synthesis :i) Achieve Insertion Delay number ii) Achieve Skew Targets iii) Maintain Transition limits iv) Limit Power Numbers Compare the three Structures …….

SoC Clock Distribution Network IP Core or Module Global Clock Net Core Internal Clock Net Core Internal Clock Driver/PLL: • Buffer • Freq. Multiply • Align SoC External clock PLL .

. The clock distribution of the Power4 microprocessor. ISSCC2002 .Example: H-Tree Clock Distribution PLL Ref clk in Ref clk out Bypass 3 PLL out 2 1 Feedback Restle et al.

PLL Block Diagram Reference clock Up Phase detector Down Charge pump Loop filter vcont VCO Local clock Divide by N System Clock .

Power reduction in Clock trees – Clock Gating .

In-die process variation Dynamic reasons = drift and jitter: .Unequal buffer delay . coupling .Switching load supply voltage variation.Unequal load .Unequal wire length .What’s the Problem ? Clock variation Difference in arrival times to flops Static reasons = skew: .IR drop .Temperature . IR drop.

Two Methods of Clock Distribution Networks Zero skew at clock inputs to IP cores (a) IP 1 IP 2 IP 3 Zero skew at the flip-flops (b) IP 1 IP 2 IP 3 IP 4 clock clock distribution network IP 4 IP 5 IP 6 IP 7 IP 8 IP 9 clock clock distribution network IP 5 IP 6 IP 7 IP 8 IP 9 0 clock delay 0 clock delay Assume perfectly balanced clock tree ! .

Clock Tree Synthesis when? Clock Tree synthesis is needed for nets which have high fanout: ➢ Clocks ➢ Asynchronous resets ➢ Scan signals which feed all the Flip-flops in the design .

max capacitance . Minimal insertion delay .Clock Tree Synthesis Why? ➢ ➢ ➢ Minimal skew . DRC (Design Rule Constraints) – max transition.

Clock Tree Synthesis Why? Minimum Skew – Hold violation B ➢ A C Hold time violation when A + B < C .

Clock Tree Synthesis Why? Minimum Skew – Setup violation B ➢ A C Setup time violation when A + B > C + T .

Total skew Timing Violation Add Buffers On Logic Path Total Power & Area .Clock Tree Synthesis Why? Minimum Insertion Delay / Buffers Stages ➢ Large insertion delay increase power but also results with increased skew cause of On-Chip-Variation (OCV) .

Clock Tree Synthesis Symmetric Clock tree ➢ All flops of a symmetric clock tree . The clock tree is balanced at a specific corner which should fit all corners . traced back from the clock tree root are passing the same number of levels and the same cell references at each level. ➢ ➢ . Asymmetric tree results with increased skew variations at different corners .

Relaxed constraints for skew.Clock Tree Synthesis Asymmetric Clock Tree Asymmetric Clock Tree is used for non clock signals such as asynchronous resets & DFT signals. Asymmetric clock tree features: ➢ Requires max delay & max transition. ➢ .

Review: Synchronous Timing Basics R1 In D Q tclk1 tc-q. when tclk1 = tclk2) T ≥ tc-q + tplogic + tsu thold ≤ tcdlogic + tcdreg Under real conditions.e. tcdreg Combinational logic R2 D Q tclk2 tplogic. the clock signal can have both spatial (clock skew) and temporal (clock jitter) variations skew is constant from cycle to cycle (by definition).. thold. tcdlogic clk Under ideal conditions (i. tsu. skew can be positive (clock and data flowing in the same direction) or negative (clock and data flowing in opposite directions) jitter causes T to change on a cycle-by-cycle basis .

Sources of Clock Skew and Jitter in Clock Network 4 power supply 3 interconnect clock 1 generation 6 capacitive load 7 capacitive PLL 2 clock drivers coupling 5 temperature Skew manufacturing device variations in clock drivers interconnect variations environmental variations (power supply and temperature) Jitter clock generation capacitive loading and coupling environmental variations (power supply and temperature) .

but makes thold harder to . If thold is not met (race conditions).Positive Clock Skew Clock and data flow in the same direction R1 In clk D Q tclk1 T 1 R2 Combinational logic delay 3 D Q tclk2 T+δ δ>0 2 4 δ + thold T: thold : T + δ ≥ tc-q + tplogic + tsu so T ≥ tc-q + tplogic + tsu . the circuit malfunctions independent of the clock period! δ > 0: Improves performance.δ meet.δ thold + δ ≤ tcdlogic + tcdreg so thold ≤ tcdlogic + tcdreg .

but thold is easier to meet .Negative Clock Skew Clock and data flow in opposite directions R1 In D Q tclk1 delay T T+δ 1 2 4 3 R2 Combinational logic D Q tclk2 clk δ<0 T: thold : T + δ ≥ tc-q + tplogic + tsu so T ≥ tc-q + tplogic + tsu .δ (eliminating race conditions) δ < 0: Degrades performance.δ thold + δ ≤ tcdlogic + tcdreg so thold ≤ tcdlogic + tcdreg .

2tjitter ≥ tc-q + tplogic + tsu so T ≥ tc-q + tplogic + tsu + 2tjitter Jitter directly reduces the performance of a sequential circuit .Clock Jitter Jitter causes T to vary on a cycle-bycycle basis R1 In clk tclk T Combinational logic -tjitter +tjitter T : T .

δ + 2tjitter thold ≤ tcdlogic + tcdreg – δ – 2tjitter even harder to meet.Combined Impact of Skew and Jitter Constraints on the minimum clock period (δ > 0) R1 In D Q tclk1 T 1 R2 Combinational logic D Q tclk2 T+δ δ>0 6 12 -tjitter T ≥ tc-q + tplogic + tsu . (The acceptable skew is reduced by jitter.) δ > 0 with jitter: Degrades performance. and makes thold .

can eliminate skew .In the ideal case.Could take multiple cycles for the clock signal to propagate to the leaves of the tree Clock grids . the clock network must support clock gating (shutting down (disabling the clock) units) Clock distribution techniques Balanced paths (H-tree network. To reduce dynamic power. so designing a clock network that minimizes both is important In many high-speed processors.Clock Distribution Networks Clock skew and jitter can ultimately limit the performance of a digital system.Typically used in the final stage of the clock distribution network .Minimizes absolute delay (not relative delay) . matched RC trees) . a majority of the dynamic power is dissipated in the clock network.

If possible. route data and clock in opposite directions. The use of gated clocks to help with dynamic power consumption make jitter worse. . Beware of temperature and supply rail variations and their effects on skew and jitter. Shield clock wires (route power lines – VDD or GND – next to clock lines) to minimize/eliminate coupling with neighboring signal nets. Use dummy fills to reduce skew by reducing variations in interconnect capacitances due to interlayer dielectric thickness variations. eliminates races at the cost of performance.Dealing with Clock Skew and Jitter To minimize skew. Power supply noise fundamentally limits the performance of clock networks. balance clock paths using H-tree or other clock distribution structures.