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Design How-To

**Polyphase Video Scaling in FPGAs
**

Suhel Dhanani, Altera

9/6/2007 07:00 AM EDT Post a comment Tweet

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Video scaling is an increasingly common function used to convert images of one resolution and aspect ratio to another "target" resolution and/or aspect ratio. The most familiar example of video scaling is scaling a VGA signal (640 x 480) output from a standard laptop to an SXGA signal (1280 x 1024) for display on LCD monitors. For high-volume systems dealing with standardized image sizes (i.e. high definition (HD) television), video scaling is most efficiently done using application specific standard products (ASSPs). However, many video applications such as video surveillance, broadcast display and monitoring, video conferencing, and specialty displays, need solutions that can handle custom image sizes and differing levels of quality. This often requires custom multi-tap polyphase scaling algorithms. FPGAs with an array of high-performance DSP structures are ideally suited for such algorithms, and FPGA vendors are beginning to offer usercustomizable video scaling IP blocks that can be quickly configured for any application. This article gives a basic overview of polyphase video scaling followed by a detailed description of how to implement polyphase scaling in an FPGA. Understanding Video Scaling Video scaling, whether upscaling or downscaling, is the process of generating pixels that did not exist in the original image. To illustrate this, let's look at a simple example; scaling a 2 x 2 pixel image to a 4 x 4 pixel image, as shown in Figure 1. In the 'New Image', the white pixels are pixels from the 'Existing Image' and the black pixels are those that need to be generated from the existing pixels. There are many methods for generating new pixels; the simplest is called the nearest neighbor method, or 1x1 interpolation. In this method a new pixel value is simply equal to the value of the preceding pixel. In a slightly more sophisticated approach, called bilinear scaling, a new pixel is equal to the average of the two neighboring pixels in both the vertical and horizontal dimensions. Both of these techniques are illustrated in Figure 1.

http://www.eetimes.com/document.asp?doc_id=1275450&print=yes

2013-11-28

Bilinear scaling implicitly assumes equal weighting of the four neighboring pixels. A 2 x 2 pixel image is enlarged (upscale) to a 4 x 4 pixel image.e. Unlike the previous example. making this a four phase scaler.print=yes 2013-11-28 .Polyphase Video Scaling in FPGAs 페이지 2 / 6 (Click to enlarge) Figure 1. it has two taps in the horizontal dimension. consider the 4x scaler shown in Figure 2. i. and has one phase (i. each pixel is multiplied by 0. it has two taps in the horizontal dimension. two taps in the vertical dimension. To further illustrate this.eetimes. i. l l l l New pixel 1 will just be a copy of the original pixel 1 New pixel 2 will weigh 75% of original pixel 1 and 25% of original pixel 2 New pixel 3 will weigh 50% of original pixel 1 and 50% of original pixel 2 New pixel 4 will weigh 25% of original pixel 1 and 75% of original pixel 2 Figure 2.e. The term "taps" is in reference to filter taps. Figure 3 shows an example of what is known as bicubic scaling. http://www. Here four new (black) pixels are generated for every one existing (white) pixel. In video terminology this scaler function is scalar (all coefficients are equal). a 4 x 4 matrix of pixels is reduced to a single pixel). Like the previous example. as scaling is mathematically identical to generalized filtering.EE Times .e. a sample 4 x 4 matrix of image pixels is downscaled by a factor of 4 in both the horizontal and the vertical dimension (i. one set of coefficients).asp?doc_id=1275450&. each new pixel is generated using a different weighting of the two existing pixels. In this example.com/document. Two pixels are used to generate the value of the new pixels. Now let's consider some more complex.e. more commonly used algorithms. The weighting coefficients for each pixel are given below. or 4 x 4 scaling. More complex algorithms Bilinear and nearest neighbor are the easiest scaling algorithms.25. multiplying coefficients by inputs (taps) and summing.

This type of efficient implementation is feasible only in a programmable logic device such as an FPGA with abundant hardware resources. Figure 4 shows an efficient FPGA implementation of this algorithm. (Click to enlarge) Figure 3.e. As mentioned previously. FPGA architecture used to implement a 2-D scaling by cascading two 1-D scalers. each new pixel may use a different set of coefficients depending on its location. This structure can be extended to perform 5 x 5. four multipliers are needed for scaling in the vertical dimension (one for each column of the scaling kernel). larger kernels will require more FPGA resources.print=yes 2013-11-28 . However. and filters the 'horizontal pixels' output from the first stage to produce the final output pixel. The outputs of the multipliers are then summed and sent to a 'Bit Narrower' which adjusts the size of the output to fit into the number of bits allowed. Scaling first in the vertical dimension and then in the horizontal dimension.EE Times .com/document. 2-D filter) is by cascading two 1-D filters.eetimes. The principles remain the same.Polyphase Video Scaling in FPGAs 페이지 3 / 6 A resource-efficient way to implement this 2-D scaler (i. the horizontal pixels are filtered in the horizontal dimension to create a single output pixel. the vertical lines of pixels are fed into line delay buffers and then fed to an array of parallel multipliers. or 9 x 9 multi-tap scaling. each vertical line is filtered to create four pixels. as shown in Figure 3. The second stage has the same basic structure as the first. one for each 1-D filter. 6 x 6.asp?doc_id=1275450&. In the first stage. Then. First. The implementation in Figure 4 consists of two stages. (Click to enlarge) Figure 4. four multipliers are need for scaling in the horizontal dimension (one for each http://www. In the implementation presented. thereby requiring different coefficient sets.

FPGA implementation Implementing Video Scaling in FPGAs To speed up FPGA implementations of video scalers. enabling designers to implement highly complex scaling algorithms in a matter of minutes. For polyphase scaling.EE Times . 16phase filter. Coefficients can be selected by the user or derived by choosing one of the built-in filtering http://www. (Click to enlarge) Figure 5.asp?doc_id=1275450&. The scaler allows implementation of both simple nearest neighbor/bilinear scaling as well as polyphase scaling. FPGA vendors provide IP megacores that abstract away all the mathematical details. The number of phases can also be set independently in each dimension. These megacores can generate a set of scaling coefficients using a standard polynomial interpolation algorithm or allow the customer to use their own custom coefficients. A scaling function allows easy implementation of multi-tap. which typically have 1-2 multiply-and-accumulate (MAC) units and significantly lower memory bandwidth. This makes FPGAs the only real choice for quickly implementing custom multi-tap scaling of HD quality images in real time. do not have the parallelism for such an implementation. A preview of the vertical coefficient set created by a 4-tap.print=yes 2013-11-28 . Figure 5 shows the GUI of an Altera-based polyphase scaler.Polyphase Video Scaling in FPGAs 페이지 4 / 6 row of the kernel). DSP architectures. and a significant amount of on-chip memory is needed for delay-line buffers. Figure 6 shows an example coefficient set generated by the IP function for a four tap. the number of vertical and horizontal taps can be selected independently. polyphase scaling algorithms.com/document.eetimes. Figure 6. sixteen phase filter.

e. The number of phases and number of bits of precision used are less important to the image quality. The parameters which have the largest effect on image quality are the number of taps and the filter function used to generate the coefficients. Scaling modes higher than bicubic (i. However. which uses a windowed product of sinc functions to calculate the coefficients. 5 x 5. The bicubic scaling mode uses cubic curve-fitting. This is necessitating an exponential increase in the amount of processing power required to encode. would be well advised to familiarize themselves with the ever expanding range video-oriented IP offered by FPGA vendors. decode. not only in television sets. Altera provides a set of guidelines on selecting scaling parameters in their Video Image Processing User Guide.) use polynomial fitting. and broadcasting systems. and power advantages of FPGAs. price. The Lanczos algorithm is a multivariate interpolation method.Polyphase Video Scaling in FPGAs 페이지 5 / 6 functions shown in Figure 7. A scaling megacore can implement custom OR built-in coefficients based on the Lanzcos interpolation technique. while shortening their design cycles. System designers wishing to realize the performance. medical. industrial. surveillance. or enhance HD quality video streams. the scaling parameters must be chosen carefully. FPGA vendors are beginning to provide a range of increasingly sophisticated IP cores that can dramatically simplify the mapping of complex algorithms onto an FPGA platform.asp?doc_id=1275450&.com/document. Figure 7. but in video conferencing. sharpen.EE Times . Mapping a video design onto an FPGA is no trivial design task. Scaling coefficients are generated based on the Lanczos function. 6 x 6. resize. Conclusion Video is rapidly going HD. etc. In polyphase mode.print=yes 2013-11-28 . About the author http://www. military. FPGAs are unique in providing the required digital signal processing power in a single device. A more exhaustive description of this function is beyond the scope of this article.eetimes.

com/document. and M. EMAIL THIS PRINT COMMENT Copyright © 2013 UBM Electronics. A UBM company.E.Polyphase Video Scaling in FPGAs 페이지 6 / 6 Suhel Dhanani is Senior Product Marketing Manager in the IP and Technology Marketing group. Suhel has completed a graduate certificate in Management Science from Stanford and also holds M.print=yes 2013-11-28 .eetimes. Privacy Policy | Terms of Service http://www.EE Times .B.S.A. degrees from Arizona State University. All rights reserved.E. He is responsible for all product marketing aspects of Altera's video and image processing solutions. Suhel has over 15 years of industry experience in semiconductors— with both large companies such as Xilinx and VLSI Technology as well as with Silicon Valley startups such as Anadigm and Tabula.asp?doc_id=1275450&.

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