MM74HC164 8-Bit Serial-in/Parallel-out Shift Register

September 1983 Revised February 1999

MM74HC164 8-Bit Serial-in/Parallel-out Shift Register
General Description
The MM74HC164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity and low consumption of standard CMOS integrated circuits. It also offers speeds comparable to low power Schottky devices. This 8-Bit shift register has gated serial inputs and CLEAR. Each register bit is a D-type master/slave flip-flop. Inputs A & B permit complete control over the incoming data. A LOW at either or both inputs inhibits entry of new data and resets the first flip-flop to the low level at the next clock pulse. A high level on one input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is HIGH or LOW, but only information meeting the setup and hold time requirements will be entered. Data is serially shifted in and out of the 8-Bit register during the positive going transition of the clock pulse. Clear is independent of the clock and accomplished by a low level at the CLEAR input. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.

I Typical operating frequency: 50 MHz I Typical propagation delay: 19 ns (clock to Q) I Wide operating supply voltage range: 2–6V I Low input current: 1 µA maximum I Low quiescent supply current: 80 µA maximum (74HC Series) I Fanout of 10 LS-TTL loads

Ordering Code:
Order Number MM74HC164M MM74HC164MTC MM74HC164N Package Number M14A MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram
Pin Assignments for DIP, SOIC and TSSOP

Truth Table
Inputs Clear Clock L H H H H X L ↑ ↑ ↑ A X X H L X B X X H X L QA L QAO H L L Outputs QB L QBO QAn QAn QAn ... QH L QHO QGn QGn QGn

H = HIGH Level (steady state), L = LOW Level (steady state) X = Irrelevant (any input, including transitions) ↑ = Transition from LOW-to-HIGH level. QAO, Q BO, QHO = the level of QA, Q B, or QH, respectively, before the indicated steady state input conditions were established. QAn, QGn = The level of QA or QG before the most recent ↑ transition of the clock; indicated a one-bit shift.

Top View

© 1999 Fairchild Semiconductor Corporation


MM74HC164 Logic Diagram 2 .

0V 4.5 3.0V −1.0V 6.9 3.0V Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH.2 mA VOL Maximum LOW Level Output Voltage VIN = VIH or VIL |IOUT| ≤ 20 µA 2. per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.1 0.35 1.1 0.2 TA = 25°C Typ 1.8 1.1 0.1 0. tf) VCC = 2.5 to VCC +0. per pin (IOUT) DC VCC or GND Current.33 ±1. 3 www.7 5.5V −0. DC Electrical Characteristics Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| ≤ 20 µA Conditions (Note 4) VCC 2.2 5.15 4.) The worst case leakage current (IIN.5 3.5V.2 0.4 5.5V 6.26 ±0.5 to +7.33 0.0 TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits 1.0V values should be used.98 5.0V 2.85V.0V 4.2 0.15 4.0V 2.9 3.9 4.1 0.1 0.0 mA |IOUT| ≤ 5.15 4. and VOL) occur for HC at 4.5V 6.0 80 1.5V 6. (The VIH value at 5.35 1.2 0.0 160 Units V V V V V V V V V V V V V V V V µA µA VIN = VIH or VIL |IOUT| ≤ 4.2 mA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN = VCC or GND IOUT = 0 µA 6.34 0.5V VCC = 6.4 5. VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr.8 1.5V is 3.5 1.1 0.2 0.48 0. Thus the 4.4 0. ICC.5V respectively.1 0.4 5. Package only Lead Temperature (TL) (Soldering 10 seconds) 260°C 600 mW 500 mW − .5V and 4.0V VCC = 4.5 6.9 4. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C.5 1.5V ±20 mA ±25 mA ±50 mA −65°C to +150°C Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN.5V values should be used when designing with this supply. IOK) DC Output Current.1 8.26 0. Note 2: Unless otherwise specified all voltages are referenced to ground.0V VIN = VCC or GND 4.5 to VCC +1.1 0.MM74HC164 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK.0V 4.0V 4. Worst case VIH and VIL occur at VCC = 5.9 4.0 mA |IOUT| ≤ 5.0V 4.0 4.fairchildsemi.0 4.O.0V 2.9 3.7 0 0 0 0.4 ±1. and IOZ) occur for CMOS at the higher voltage and so the 6.5V 6.2 0.5V 6.0V VIN = VIH or VIL |IOUT| ≤ 4.5 3.8 1.84 5.0V 1000 500 400 ns ns ns 0 −40 VCC +85 V °C 2 Max 6 Units V Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.5 1.35 1.5V 6.

0V 4. tr = tf = 6 ns Symbol fMAX tPHL. CL = 15 pF. TA = 25°C.5V 6.0V 4. tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Maximum Operating Frequency tPHL.0V CPD CIN Power Dissipation Capacitance (Note 5) Maximum Input Capacitance (per package) 5.0V 150 5 10 10 10 115 13 20 140 28 24 −7 −3 −2 25 14 12 −2 0 1 22 11 10 TA = 25°C Typ 5 27 31 175 35 30 205 41 35 0 0 0 100 20 17 5 5 5 80 16 14 75 15 13 1000 500 400 TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits 4 21 24 218 44 38 256 51 44 0 0 0 125 25 21 5 5 5 100 20 18 95 19 16 1000 500 400 3 18 20 254 51 44 297 59 51 0 0 0 150 30 25 5 5 5 120 24 20 110 22 19 1000 500 400 Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF Note 5: CPD determines the no load dynamic power consumption.5V 4 . tTLH Maximum Output Rise and Fall Time tr. Clear to Output tREM Minimum Removal Time Clear to Clock tS Minimum Setup Time Data to Clock tH Minimum Hold Time Clock to Data tW Minimum Pulse Width Clear or Clock tTHL.0V 2.5V 6.0V 2. www. Clock to Output Maximum Propagation Delay. tPLH Maximum Propagation Delay.0V 2. Clear to Clock Minimum Setup Time Data to Clock Minimum Hold Time Clock to Data Minimum Pulse Width Clear or Clock 10 16 ns 1 5 ns 12 20 ns −2 0 ns 23 35 ns 19 30 ns Conditions Typ Guaranteed Limit 30 Units MHz AC Electrical Characteristics CL = 50 pF.MM74HC164 AC Electrical Characteristics VCC = 5V.0V 4.0V 4.0V 4. IS = CPD VCC f + ICC.0V 4. Clock to Output tPHL.fairchildsemi. PD = CPD VCC2 f + ICC VCC.5V 6. tPLH Maximum Propagation Delay. Clear to Output Minimum Removal Time. tf Maximum Input Rise and Fall Time Conditions VCC 2.5V 6.5V 6.0V 4.0V 2. tPLH tREM tS tH tW Parameter Maximum Operating Frequency Maximum Propagation Delay.0V 2.5V 6. tPLH tPHL.5V 6.0V 4.0V 2.0V 2.5V 6. and the no load dynamic current consumption.0V 2.0V 4.

com .MM74HC164 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC). JEDEC MS-120. 0.fairchildsemi.150” Narrow Package Number M14A 5 www.

4mm Wide Package Number MTC14 www.MM74HC164 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP).fairchildsemi. 6 . JEDEC MO-153.

no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. or to affect its safety or effectiveness.fairchildsemi. . to perform when properly used in accordance with instructions for use provided in the labeling. Fairchild does not assume any responsibility for use of any circuitry described. As used herein: 2. and (c) whose failure device or system. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich.300” Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. A critical component in any component of a life support 1. can be reasonably expected to result in a significant injury to the www. (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body. or (b) support or sustain life. JEDEC MS-001. 0.MM74HC164 8-Bit Serial-in/Parallel-out Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP).com user.

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