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2102440 Introduction to Microprocessors Chapter 6 The 8086 Hardware Architecture

Suree Pumrin, Ph.D.

Minimum-mode and maximum-mode

systems DEMUX address/Data bus Bus cycle and time states

2102440 Introduction to Microprocessors



3-state Output. 3-state Output. • Many pins have multiple functions. The 8086 in Minimum Mode • 3 2102440 Introduction to Microprocessors Common Signals in both Minimum and Maximum Modes Name AD15-AD0 A19/S6-A16/S3 Function Address/data bus Address/status Bus High Enable/Status Type Bidirectional. • The minimum mode is selected by making the MN/MX equal to 1. • The maximum mode is selected by making the MN/MX equal to 0. 3-state Input Output.The 8086 Microprocessor • It is a 40-pin dual in-line package. • It can work in two modes: minimum mode and maximum mode. • Minimum mode 8086 system has one microprocessor. 3-state Input Input Input Input Input Input Input Input BHE / S 7 MN / MX Minimum/maximum Mode control Read control RD TEST READY RESET NMI INTR CLK VCC GND Wait on test control Wait state control System reset Nonmaskable Interrupt request Interrupt request System clock +5 V Ground 2102440 Introduction to Microprocessors 4 2 . • Maximum mode is used when it needs to connect to an 8087 math coprocessor.

0 LOCK Output. 3-state WR IO/ M DT / R DEN ALE Address latch enable Interrupt acknowledge Output Output INTA The 8086 in Minimum Mode 2102440 Introduction to Microprocessors 5 Unique Maximum Mode Signals Name Function Request/grant bus access control Bus priority lock control Bus cycle status Type Bidirectional RQ / GT 1. 3-state Output. 3-state S2− S0 QS1. QS0 Instruction queue status Output The 8086 in Maximum Mode 2102440 Introduction to Microprocessors 6 3 .Unique Minimum Mode Signals Name HOLD HLDA Function Hold request Hold acknowledge Write control IO/memory control Data transmit/receive Data enable Type Input Output Output. 3-state Output. 3-state Output. 3-state Output.

Minimum Mode Interface Power supply Vcc GND INTR Address/data bus AD0-AD15. A16/S3-A19/S6 DEN MN/MX LOCK BHE RD READY QS1. A16/S3-A19/S6 ALE Interrupt interface INTA TEST NMI RESET 8086 MPU BHE/S7 M/IO DT/R Memory/IO controls DMA interface Mode select HOLD HLDA Vcc RD WR DEN READY MN/MX CLK 2102440 Introduction to Microprocessors 7 Maximum Mode Interface CLK Vcc GND CLK S0 S1 S2 S0 AEN MRDC MWTC AMWC AEN Interrupt interface INTR TEST CLK S1 8288 Bus Controller IORC IOWC AIOWC INTA MCE/PDEN NMI S2 DEN DT/R ALE RESET ALE DT/R 8086 MPU AD0-AD15.QS0 RQ/GT1 RQ/GT0 Local Bus Control 2102440 Introduction to Microprocessors 8 4 .

The data bus – transfers data between CPU and the targeted device. There are many controls signals. however. The process of separating address and data from pins AD0AD0-AD15 is called demultiplexing. we emphasis on the read read and write operations: RD 0 1 0 1 0 WR 1 0 1 0 0 IO/M 0 0 1 1 x Signal IOR IOW MEMR MEMW Never happens 10 Control bus 2102440 Introduction to Microprocessors 5 . 2102440 Introduction to Microprocessors 9 Microprocessor Buses (II) Address/Data bus The address bus is 20 bits long (A0-A19).Microprocessor Buses (I) The 8086 has three sets of separate buses The address bus – provides the path for the address to locate the targeted device. The ALE ( Address Latch Enable) is set high to indicate the information on AD0AD0-AD15 is address. The data bus D0-D15 are multiplexed with address bus A0-A15 -> AD0 – AD15. The control bus – provides the signals to indicate the type of operation being executed. ALE is low when AD0AD0-AD15 carry data. demultiplexing.

Read timing: • The first clock cycle -. 2102440 Introduction to Microprocessors 12 6 .Address. • The end of fourth clock cycle – the data must be at the pins of the CPU to be fetched in. and Control Buses in 8086 Based System 2102440 Introduction to Microprocessors 11 Bus Timing of the 8086 The 8086 uses 4 clocks for memory and I/O bus activities. Data.ALE latches the address • The second and third clock cycles – the read signal is provided.