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CBUS device description

The CBUS device is a hardware device that carries the GCLK signal on the backplane. A specific CBUS is dedicated to a GCLK. The state of the CBUS does not follow the state of the GCLK as due to hardware redundanc a CBUS can still be used b the s ste! even though its GCLK is ""S. The user transitions are not supported for the CBUS. Control of the CBUS is b the GCLK transitions.

CBUS alarms and fault resolution procedures


Overview
CBUS alarms are generated when the system detects a problem with the clock signal on the CBUS. These alarms typically result from a primary failure elsewhere in the clock generation and distribution function. With the single exception shown below, on site troubleshooting is not normally re!uired.

PBUS alarms and fault resolution procedures


Overview
"BUS alarms are generated for faults associated with the "rocessor Bus #"BUS$. The "BUS is the software de%ice representing the &otorola Cellular 'd%anced "rocessor #&C'"$ bus. The &C'" transports data between the (")*Cs and the following full si+e digital boards, &S-.)/C0). (C12. (0". 2SW.TSW. 0)-.0)-&.

PBUS: Device Failure


Hardware
BSC and -nCell.

Description
This alarm is generated if the "BUS de%ice is placed **S due to a fault translation triggered by background system tests on the &C'" bus. Since the &C'" bus transports data from the (")*Cs to the full si+e boards listed in the preceding Overview, it is likely that the problem is in these participating modules, in the bus

terminator cards #BTCs$, or in the physical &C'" bus itself. This bus runs through the backplane. 0epending on the hardware configuration, this alarm can therefore be caused by, 3ailed &S-./C0). 3ailed (C12. 3ailed (0". 3ailed 2SW.TSW. 3ailed 0)-.0)-&. 3ailed BTC#s$. 3ailed backplane or backplane edge connectors.

PBUS alarms
This chapter describes the alarms and *&C ) troubleshooting procedures associated with the "rocessor Bus #"BUS$ de%ice. The "BUS is the software de%ice representing the &otorola Cellular 'd%anced "rocessor #&C'"$ bus. The &C'" transports data between the (")*Cs and the following full si+ed digital boards, &ultiple Serial -nterface #&S-$.Transcoder #/C0)$. (eneric Clock #(C12$. 2iloport Switch #2SW$. 0igital )adio -nterface #0)-$.0)- extended &emory #0)-&$. "BUS alarms apply only to BSC and -nCell e!uipment.

Serial Bus Connection Failure alarm


Hardware
This alarm applies to BSC, -nCell BTS, )/C0) only.

Description
The BCU" Serial Bus Connection 3ailure alarm is generated if a "ower Supply &odule #"S&$ fails to respond when it is polled from the (eneric "rocessor board #(")*C$, by the 3&S. This indicates that the 3&S on the (")*C is unable to communicate with the "S& board %ia the Serial Bus #SBUS$. The physical path for the SBUS is through the backplane. This alarm is therefore typically due to, 3aulty "S& board installation. 3aulty "S& board. 3aulty 3&S. 3aulty SBUS signal line through the backplane. 3aulty backplane edge connectors.

Before going to the site


The *&C ) must determine, The site number. Cage number. 0e%ice -0.

Procedure
Procedure !" Serial Bus Connection Failure alarm The two boards that ha%e failed to communicate %ia the SBUS are the (")*C and "S& boards. This procedure therefore checks that the rele%ant boards are properly seated. -f this fails to clear the alarm, the boards are checked in turn by substitution. -f the alarm persists, the backplane edge connectors are examined and, if necessary, the physical path through the backplane is tested for continuity.

SBUS alarm and fault resolution procedures


Overview
SBUS alarms are generated for fault conditions associated with the Serial Bus #SBUS$ de%ice. 'n SBUS is a logical de%ice that maps the communications path between the (")*Cs and 1'4/ cards. The communications path includes the half si+e cards installed in the cage. 5ach cage has two SBUSs, one acti%e and one standby. SBUS alarms apply to BSC and -nCell BSU based systems only, including 5xCell and TopCell. The single SBUS alarm does not normally re!uire on site troubleshooting

SBUS: Device Failure


Hardware
BSC, -nCell, including 5xCell and TopCell.

Description
This alarm is generated if the SBUS de%ice fails, causing the site to reset. The SBUS runs from the (")*C to the 1'4/ board, %ia the half si+e boards on the shelf. The SBUS is terminated on the backplane by a Bus Termination Card #BT$, which keeps signals on the bus at the correct TT1 le%el. This alarm can therefore be caused by, 1'4/ board not correctly inserted into the backplane. 1'4/ board failure. 3aulty (")*C board. &issing BTC causing signals to go out of range. ' half si+e board is not correctly seated in the backplane. 3aulty half si+e board. The SBUS edge connectors on the backplane are faulty. Two BTC modules must be fitted in each BSU or )/U shelf, in slot 16 and slot 178, at all times. Before a BTC is remo%ed, a BTC must therefore be inserted into a 2SW slot to maintain this re!uirement.

#ntroduction of SBUS alarms


SBUS alarms
This chapter describes the alarm and *&C ) troubleshooting procedures associated with the Serial Bus #SBUS$ de%ice. 'n SBUS is a logical de%ice made up of the communication path between the (")*Cs and 1'4/ cards in a cage. The communications path includes the half si+ed cards installed in the cage. 5ach cage has two SBUS de%ices #one acti%e and one redundant$.

SBUS: Device Failure


Clearing $%pe: 3&-C Severit% &evel: Critical Categor%: 5!uipment

Description
The SBUS de%ice failed causing the site to reset. This alarm is generated only for -nCell BSU based hardware #including 5xCell and TopCell$.

'dditional #nformation field


There is no additional information in the output for this alarm.

Possi(le cause)s*

The following are possible causes for this alarm, The 1'4/ card is not correctly inserted into the backplane. The 1'4/ card failed. The (")*C board is faulty causing it to be incapable of communication on the SBUS. ' Bus Terminator Card #BTC$ is not plugged into the backplane causing signals on the backplane to go out of the expected range. ' half si+e card is not correctly plugged into the backplane. The SBUS connections on the backplane are faulty.

TBUS
KSW device description
The KS# $Kiloport Switch% is a ti!e division digital switch that perfor!s ti!eslot interchange for the active T&' highwa . (t co!!unicates with the controlling G)*"C via the 'CA) bus and is connected to the T&' highwa . The &S# $&ouble Kiloport Switch% is an enhanced version of the KS# that supports double the nu!ber of ports and e+tended sub,rate switching down to - kbit.s. /or the double rate T&' bus the bandwidth is increased to 01- 'bit.s partitioned into 123- ti!eslots. All references to KS# appl e4uall to the &S#5 unless otherwise stated. The following section describes the states and transitions for the KS# device. (n the state transition diagra! /igure 1,665 and in the description5 (7S !eans the purpose of the transition is to bring the device into service. #hen the device is in an in service state5 it is currentl being used b the s ste! and is referred to as ACT(89. STA7&B: refers to the device that is read for use but is not bus . ""S refers to out of service. Thus5 if the device is in the ""S state5 it is not being used b the s ste!. Associated with each CAG9 device is a TBUS device. A TBUS is a logical device !ade up of a cageT&' backplane5 the KS# devices !anaging the CAG9.s T&' highwa 5 and local and re!ote KS#; devices and &S#; devices $if the e+ist%. Changes in a KS# state can affect the state of the TBUS devices controlled b that KS#. Associated with each S(T9 is a T&' device. The active T&' device chosen is based on the states of all the TBUS devices. Since changes in a KS# device state can affect the state of TBUS devices5 changes in a KS# device state can also affect the state of the T&' devices. (f T&' 2 is the active T&' device5 the A side KS# devices will be the active KS# devices $KS# devices in slot 1<%. (f T&' 0 is the active T&' device5 the B side KS# devices will be the active KS# devices $KS# devices in slot 0%. The active KS# follows the active T&' device.

BUS device
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TBUS device description


A TBUS is a logical device !ade up of a KS#5 the cage containing the TBUS5 local and re!ote KS#; devices $if the e+ist%5 and the fibre optic cable that interconnects the KS#; devices. 9ach cage has two $one active and one redundant% TBUS devices associated with it. The state of the TBUS depends upon the state of its parent KS#5 therefore a change in KS# state will also affect the corresponding TBUS. (n /igure 1,=0 and the state transition description5 (7S !eans the purpose of the transition is to bring the device into service. #hen the device is in an in,service state5 the device is currentl being used b the s ste!. STA7&B: refers to the device that is read for use but not bus . ""S refers to out,of,service. Thus5 if the device is in the ""S state5 it is not being used b the s ste!

TDM device
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TDM device description


The T&' $Ti!e &ivision 'ultiple+ing% bus can be viewed as an e+tension of the KS#. T&' is a logical device consisting of its associated TBUS devices. The T&' device is based e+clusivel on TBUS devices fro! one highwa $A or B% within a site. A co!bination of TBUS devices fro! both highwa s A and B is not allowed5 therefore T&' A consists of all TBUS A devices and T&' B consists of all TBUS B devices. "nl one T&' can be active at a given ti!e5 therefore onl TBUS A or TBUS B for a cage can be active at a given ti!e.

$BUS alarms and fault resolution procedures


Overview
TBUS alarms are generated for faults associated with the T0& Bus #TBUS$. ' TBUS is a logical de%ice consisting of a 2SW, the cage containing the TBUS, local and remote 2SW/.0SW/ cards #if used$, and the fibre optic cables interconnecting the 2SW/.0SW/ cards. 5ach cage has two TBUS de%ices, one acti%e and one redundant. ' TBUS may reside in the same cage as the controlling 2SW or it may reside in an extended cage. When the system detects a T0& :ighway fault condition related to a specific cage, a loopback test is initiated. This loopback test is performed between the (")*Cs in that cage and the acti%e 2SW. -f the loopback test fails, a specific TBUS loopback alarm is generated. TBUS alarms are also generated when a fault occurs within the TBUS fibre optic link between cages. The TBUS alarm is reported by a 2SW, a 2SW/, a (")*C, an &S-./C0), or a 0)-, to the designated (")*C software.

MCAP BUS
The GPROC2 module contains: A Motorola MC68C040 32- it !rocessor o!eratin" at 33 M#$% The &A' !rocessors( )hich are the inter*ace et)een the GPROC2 and the to+en rin" &A'% The COMM !rocessor )hich( in con,unction )ith the T-M inter*ace controller( is the inter*ace et)een the GPROC2 and the T-M hi"h)a.

Communication
The GPROC2 communicates )ith other *ull si$e modules /ia the MCAP us( and )ith hal* si$e modules 0and modules not on the module shel*1 /ia the 233 serial us% The &AP- !rocessor and the T-M inter*ace controller communicate /ia a hi"h s!eed !ri/ate us% The !ri/ate us ar iter is the inter*ace et)een the MC68&C040 address4data us and the hi"h s!eed !ri/ate us% The !arallel !ort controls out!ut si"nals to the *ront !anel &5-s( and recei/es in!ut si"nals 0/ia the re"ister !orts1 *rom the ac+!lane% These contain: S 3hel* 6-% S 3lot 6-% S 2ac+!lane t.!e% S 2ac+!lane re/ision le/el%