N2FC news compilation 19/12/2012

IEDM 2012 – Nanoelectronics provide a path beyond CMOS
Compiled from http://www.electroiq.com/index.html


N2FC news compilation CMOS is running out of steam.in 3 . “We can do better using better materials or device structures with better electrostatics (with existing CMOS technology). Charge-based emerging devices may enable low-power computation by making the FET transition steeper or introducing new switching concepts. That’s the real limit for the scaling. An Chen of GLOBALFOUNDRIES presented a survey of emerging nanoelectronic devices.” Chen said. facing fundamental limits. but what comes next? At the International Electron Devices Meeting (IEDM-2012) in San Francisco. Another class of devices based on spin are another option. That could limit how small we can shrink the device. “If we continue this trend. We have to look for devices that may consume less power during switching. low power beyond-CMOS devices have been developed based on novel state variables and/or computation mechanisms. we have to ask ourselves ‘What are the solutions that may be available beyond CMOS?’” One of the major challenges for scaling is escalating power density.”.iisc. “We cannot really eliminate power leakage and we cannot reduce the supply voltage in proportion to device dimensions. spintronics are one of the main types of noncharge emerging devices. we’re going to some ridiculous number (see chart below). “but. which he divided into two categories: Charge-based and non-charge based. To this end. N2 FC-CeNSE-IISc 2012 raghavan@ece.ernet.”.

4 .N2FC news compilation Leading nanoelectronic devices Tunneling FET (TFET) The tunneling FET employs quantum mechanical band-to-band tunneling mechanism. a lack of ability to extend low SS (subthreshold slope) over a wide current range. carrier effective mass. bandgap. and offers low Vdd. challenges with enhancing gate control on the internal E-field. etc. Challenges include: low saturation current. difficult engineering of the source tunneling region with regard to junction abruptness.. and problems with interface states. low power and an FET structure that is compatible with CMOS technology and infrastructure.

N2FC news compilation Impact Ionization MOS (IMOS) IMOS devices employ a gated p-i-n structure operated in the reverse bias regime. N2 FC-CeNSE-IISc 2012 raghavan@ece. and speed limitations due to carrier multiplication delay and statistical retardation delay.iisc. and susceptibility to hot carrier degradation. Key features include a steep sub-threshold slope and CMOS compatibility. There are also limitations in scaling the intrinsic supply voltage. Challenges: IMOS devices are intrinsically slow due to the statistical avalanche charge multiplication process.ernet.in 5 . where control of the gate impact ionization enables a steep increase of current via carrier multiplication.

and variability control. high pull-in voltage. scalability has yet to be proven. surface forces that cause sticking. Resonant Tunneling Diodes (RTD) Key features: Inherently high speed. and compatibility with CMOS. tunneling-limited scaling. 6 . immunity to electromagnetic shocks. speed is in question. integration of high quality single crystalline ferroelectric oxides on silicon.N2FC news compilation Nano-electro-mechanical Switch (NEMS) Advantages of NEMS. include zero leakage and zero sub-threshold swing (in principle). there have been demonstrations of negative capacitance in ferroelectric dielectrics and <60mV/dec SS in neg-Cg FET. it's compatible with CMOS. Negative-Cg FET Key features of the negative common gate FET: steep SS based on collective effects and internal feedback mechanisms. negative differential resistance (NDR). Challenges with NEMS include: Slow switching speed related to the beam movement and oscillatory pullout time. nanoscale contact reliability. high temperature tolerance. which operate as a mechnical switch with a cantilever beam as shown. integrating a pair of RTD with CMOS gate achieves bi-stable logic operation. low-power solutions are possible. precise control of layer thickness is important for fabrication. Challenges: the industry needs to identify appropriate materials (oxides and ferroelectrics) for the best swing with minimal hysteresis.

potentially high device density. There has been limited progress on FET recently. compatibility with CMOS Challenges include: size-temperature trade-off.in 7 . Mott FET Key features: FET-type structure with CMOS compatibility. novel functionalities and applications. potentially high power efficiency. although two-terminal Mott devices have been explored for memory applications. Other challenges include: transition temperature. large threshold voltage variation.iisc.N2FC news compilation Single Electron Transistor (SET) Key features: High speed.ernet. limited fan-out. low noise immunity. good scalability. modest to low gain. low output current and high output impedance. a lack of fundamental understanding of the gate oxide (functional channel N2 FC-CeNSE-IISc 2012 raghavan@ece. immature fabrication process. parasitic capacitance. fast phase transition speed.

N2FC news compilation interface and the local band structure changes under E-field is limited). and is 3D stackable. it’s a relatively simple process with potentially low cost. which can be gate-controlled. Challenges: Improve performance of 3-terminal devices (speed. and majority gate operation. novel information processing and transfer mechanisms. low operation voltage and power. Atomic Switch The atomic switch is based on the formation/annihilation of a metallic atomic bridge between two electrodes. molecular and magnetic dots could provide potentially low-power. Key features: Highly scalable. which has been experimentally demonstrated with semiconductor. endurance. 8 . two-terminal device for memory is the same as the conductive-bridge RAM (CBRAM). and a better understanding of the operation mechanisms is needed. uniformity). speed is determined by ionic transport and electrochemical reactions at the reactive electrode interface. Quantum Cellular Automata (QCA) QCA. Mott transition often coupled with thermal effects and structural changes. stability and variability may be concerns. Challenges include operating temperature and patterning at extreme scales.

. strength of gate modulation of spin-orbit interaction. scalability in question. FET-type structure and compatibility with CMOS. misalignment). layout efficiency. Room-temperature majority logic gate and cascaded logic operation based on NML have been demonstrated. room-temperature operation. and a transition from in-plane to perpendicular magnetization may further improve NML operations. Challenges: Magnetic materials and processing. N2 FC-CeNSE-IISc 2012 raghavan@ece. non-ballistic spinFETs. nonmagnetic spin transistors. requires high efficiency of spin injection and detection for sufficient on/off ratio.in 9 . wire crossing. and magnetic bipolar transistors. and nonvolatility and programmability.g. which makes novel architectures more feasible. Key features: Majority logic operation. Challenges: Clocking field design and optimization. dissipation-less transport in theory. Nanomagnet Logic (NML) With NML. potentially low switching energy.N2FC news compilation SpinFET Key features: Spin degree of freedom enables additional signal modulation and control. and regularity in layout and design. Other Spin Transistor concepts include spin-MOSFETs. defect tolerance (e. slow switching speed. potentially zero standby power. and spin relaxation and lifetime.iisc. logic bits are encoded in magnet polarization directions and computation is by magnetic coupling.ernet. nonvolatility.

can be a majority logic gate based on phase locking of STT oscillators. separate writing and sensing paths of MTJ and third-terminal controls). potentially low power. STT oscillator may provide clock functions. and impedance mismatch with CMOS.g. Spin Wave Logic With spin wave logic. reducing switching current and power. logic information is encoded in spin wave phase or amplitude and computation is by wave interference. or it can be based on STT switching in a multi-terminal magnetic tunnel junction (e. Many conceptual device proposals are supported by device and circuit models and there have been an increasing number of experimental demonstrations. Key features: Parallel data processing on multiple 10 . and it may enable novel architectures and designs based on combined logic and memory functions.. multiple logic states possible. plus significant effort on architectural design. non-volatility and programmability.N2FC news compilation Spin-Transfer-Torque (STT) for Logic STT for logic. Key features: Leverages technologies from STT-RAM. Challenges: Material and integration. which is enabled by a magnetic tunnel junction (MTJ).

majority logic gate operation. propagation. thickness control. Challenges: Room-temperature switching in a multimagnet networks interacting via spin currents. etc. Challenges include a high current to drive domain wall migration. and detection. Challenges: Efficiency and power consumption of spin wave generation. All Spin Logic Key features: Magnets inject spin + spins switch magnets. Introduction of high anisotropy magnetic materials into demonstration.ernet. proper choice of channel materials.N2FC news compilation frequencies on the same device. N2 FC-CeNSE-IISc 2012 raghavan@ece. alignment. potentially very low power. uses both analog (spin current) and digital (bistable magnet) properties. and current density. It’s an all metallic logic. low voltage clocking operation.g.. Domain Wall Logic Information is stored in a movable domain wall in ferromagnetic wires. and a low noise margin. but challenges exist in terms of operating temperature. including wave generation. and suitable for non-Von Neumann architectures. It potentially offers low power and fast speed. with potentially low power.in 11 . integration with magneto-electric cells enables nonvolatile information storage. So far it’s only theory without direct experimental demonstrations Bi-layer pseudo-Spin FET (BiSFET) BiSFETs are based on exciton condensation in bi-layer graphene. potentially low-power operation. low group velocity and speed of signal propagation (~ 107 cm/s). a relatively slow switching speed. and there’s the potential for inductive cross-talk. device fabrication (e. device scalability limited by spin wave length. Prototype spin wave logic devices have been demonstrated. spin wave signal degradation during propagation along spin waveguide. and information transmission without charge transfer and potential interconnect solution for spintronic devices. graphene and dielectric quality.).iisc. and the need for an external clock.

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