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UNIVERSITY OF NEBRASKA-LINCOLN

Stop Watch
ELEC 307 Project 2

Dongpu Jin, Sean Hicks
Instructor: Alvaro Pinto Demonstration: April/19/2011 Report: April/19/2011

................................................................................................. 12 Conclusion ..................................................................... 4 Mod 6 & Mod 10 Counter: ...................... 3 Background and Theory .................................................................................................................. 7 Procedure and Implementations....................................... 3 Introduction ...............................................................................................................................................................................................2 Contents Abstract ...................................................................................... 5 Seven-Segment Decoder: ............................................................................................................................................................................................ 9 Standards and Society Impact ......................... 6 Design .................................................................................................. 9 Results and Discussion .......... 3 Clock Converter:.................................................................................................................................................. 12 ............................................................................................................................................................................................................................................................................................................ 12 Reference ......................................................................

Pause and Reset. The board has internal clocks. User can press buttons to either start. This project is software and hardware co-design. We modeled the system in VHDL (Very-high-speed integrated circuit Hardware Description Language) and implemented the system using a FPGA board. We will use push buttons for the user interaction. . Therefore. we are going to make our design first in VHDL and program the FPGA. Introduction Stop watch is timepiece equipment which is designed to measure the amount of time elapsed from a particular time when activated to when it is deactivated. We will use the internal clock to drive the entire system. We used Cyclone II FPGA board to implement our stop watch. we will explain the operating principle of each component. Particularly. on board push buttons and on board LEDs. Our stop watch has the most commonly used functionalities—Start.3 Abstract This is the technical report for our ELEC 307 Project 2—Stop Watch. Those on board LEDs will be used to display each digit. The FPGA can be programmed by our VHDL design. we give a background on the knowledge and theory of our project. Background and Theory In this section. pause or reset the system.

will run at the speed of 10Hz. which is 5000000 times faster. the fasted digit—Tenth Second. Therefore. our internal clock is 50MHz. We used a clock converter (Figure 1) to accomplish this task: Figure 1 Clock Converter .1/6 = 1/60Hz (1/60)/10 = 1/600Hz As we can see.1Hz 0. the first thing we need to do is to slow down the clock.4 Clock Converter: The following is the table represents each digit and its corresponding running speed: Digit Tenth Second Second Ten Second Minute Ten Minute Speed 10Hz 1Hz 0. However.

there is a counter driven by the rising edge of the 50M clock. To be more specific. Figure 2 Slows down the clock Therefore. Because the clock is driving the entire system. And all the push buttons on the FPGA board are low active. Therefore. the values of Start. ten minute are mod 6 counters since their values can only go from 0 to 5. The same mechanism will be applies for each stage to get proper clock speed. Pause and Reset need to be inverted before connect to other components. each digit of our stop watch is implemented as a modulo counter (Figure 3). Inside the converter. second and minute are mod 10 counters because their values can only go from 0 to 9. it will invert the output clock and the counter will be reset to 0 (Figure 2). the output clock will be 10Hz. . Ten second.5 The 50MHz clock will be fed into the convert. Mod 6 & Mod 10 Counter: Essentially. so Start. Pause and Reset are also fed into the converter to control the clock. This also indicates that the maximum range of our stop watch is from 00:00:0 to 59:59:9. When it counts from 0 to 2500000. digits tenth second.

Seven-Segment Decoder: Each modulo counter will provide its corresponding digit in binary format. The following is the behavior of the decoder. We implemented the decoder in algorithmic level: Figure 4 Seven-Segment Decoder algorithmic behavior . which will decode each 4bit digit into 7-bit display format (Figure 4). we need a 4-to-7 decoder. In order to display them on the LEDs.6 Figure 3 Modulo Counter The modulo counter also contains the mechanism from previous section to provide proper clock speed to the next stage.

. our design will be implemented on the Altera DE II Board with Cyclone II FPGA. 50MHz internal clock is used to drive the entire system. Seven-Segment LEDs are used for display and push buttons will be used to interact with users. Design As we mentioned earlier. Thus. the segment will light only when its corresponding bit is 0. The following is the board we used for our development: Figure 5 Altera DE2 Board The Cyclone II FPGA will be used to implement our design. This is just the opposite of the regular decoder.7 One thing need to pay attention here is that each segment of the seven-segment LED on the board is also low active.

1Hz) to the next stage (second digit).8 The following is our design diagram (Figure 6): Figure 6 Stop Watch Design This is a structural model. Therefore. It has five stages and each stage corresponds to one digit. . second and ten minute will be ten times slower than their previous stages. it will go back to 0. The 50MHz internal clock will be slowed down to 10Hz. 50MHz is connected to the internal clock. so the tenth second digit will increment at every rising edge of this clock. We need a 4-to-7 sevensegment decoder to decode the value into display format. Each stage will provide one digit in 4-bit binary format. eventually. The outputs from the decoders will be mapped to their corresponding segments on the board. once it hits 9. Minute will be six times slower than its previous stage. In addition. the second digits will increment every second. Pause and Reset are mapped to the push buttons. this counter will provide a 10 times slower clock (0. There are four inputs to this system. Applying the same idea to connect the other three stages in cascade. Run. Since it’s a modulo 10 counter.

we put all the components together and did more testing to the system using waveforms. Then the count value will go through a formatter. It takes the 10Hz clock from the clock converter and straight counts up until the limit. After all the testing. We also did plenty of testing on each individual component to make sure they are correct both logically and functionally. The Start. After that. our design was in algorithmic level. we have to invert all the values coming from the push buttons and going into the LEDs. We were trying to implement an up counter. Then. we use seven-segment decoders to decode each digit for display. Therefore. This formatter will format the count value into time format. we first discussed how we should implement this stop watch. i. push buttons and LEDs. . such as the push buttons and LEDs. We also figured out the pin assignment of the clock. Then we started to test the hardware.e. we figured out that both of them are low active.9 Procedure and Implementations In order to accomplish this project. Results and Discussion Initially. we downloaded our design to the board and tested on the hardware. 00:00:0 formats. Pause and Reset functionality can be implemented and a finite state machine (Figure 7) since we want to change its state only when we press the buttons. We have two approaches: one is in algorithmic level and the other one is in structural level. We decided to use the structural level model. By doing this.

since the next state is determined by the current state as well as the input. The state transition will be triggered when button is pressed. it is a Mealy Machine implementation. run (S2) and pause (S3). This algorithmic model has been tested using waveform in ModelSim. The following is the simulation results: Figure 8 Algorithmic design simulation result .10 Figure 7 Stop Watch finite state machine implementation This finite state will have three states: idle (S1). Essentially.

so we have to start developing the structural model. For example. the counter resumes counting. So during the fifth pulse of the input clock. The solution is to initialize the clock at each . the counter will stall and keep its current value. the problem is caused by the initial value of the clock in each stage (Figure 9). When it followed by another run pulse. When there’s a pause pulse. this model doesn’t work with Altera Quartus.11 As we can see. However. when there’s a reset pulse. which will update next digit early. The state changes from run (S2) to pause (S3). the value becomes zeros and state changes back to idle (S1). which represented by the top case. ten second increments by one when second change from 4 to 5. when run has a pulse. ten second is supposed to increment when second change from 9 to 0. the output clock has a rising edge. The state changes back to run (S2). Another issue need to mention is that we ran into a problem that next digit update at the middle of its previous digit. the counter start to count and state change from idle (S1) to run (S2). we initialized clock in each stage to 0. Actually. However. Eventually. Figure 9 Clock Issue At the beginning.

In summary. we learn more fundamental principles of designing digital systems. Moreover.edu/people/starzykj/webcad/ee490/lab4_99/stopwatch. Standards and Society Impact Stop watch has plenty of applications. Measure the presentation time or even measure the time during an exam. Since our stop watch is implemented on FPGA. Then at the tenth pulse. We can set up a time and trigger some events when the stop watch reaches that time point. This will not update next digit. at the fifth pulse.12 stage to 1 (the bottom case). Conclusion In this project. Reference http://www.html http://www. we can add other extensions to it.edu/~zbaker/ece238/labs/lab5/sheet05.ohio. output clock changes from 0 to 1 and causes next digit to increment at the correct time. It can be used to measure the time in sports.pdf .edu/people/starzykj/webcad/ee490/final_design.html http://www.unm.ohio. this project is a good software hardware co-design practice. we obtained more experience with Altera DE II board and how to program a FPGA. Therefore. the output clock will change from 1 to 0.