L9362

QUAD LOW SIDE DRIVER

I

I I I

I I

I I

I I

QUAD LOW-SIDE DRIVER FOR AUTOMOTIVE APPLICATION CURRENT FEEDBACK OUTPUT FOR EACH POWER STAGE 5V SUPPLY VOLTAGE INTERNAL FAILURE DIAGNOSTIC OUTPUT VOLTAGE SLOPE CONTROL FOR LOW ELECTRO MAGNETIC EMISSIONS INTERNAL SHORT CIRCUIT PROTECTION OVERTEMPERATURE PROTECTION AND OVERCURRENT PROTECTION AND DISABLE SWITCHING FREQUENCY UP TO 2kHZ INTERNAL ZENER CLAMP OF THE OUTPUT VOLTAGE FOR INDUCTIVE LOADS PARALLEL INPUT SPI FOR DIAGNOSTIC INFORMATION EXCHANGE RESET INPUT

PowerSO36 ORDERING NUMBER: L9362

I

TYPICAL INTERNAL OSCILLATOR FREQUENCY 325kHZ

DESCRIPTION The Quad Driver is an integrated quad low-side power switch with power limitation, load interrupt and shorted load detection, thermal shutdown, error detection via SPI interface and integrated Z-diodes for output clamping, free running diodes.

BLOCK DIAGRAM
VCC VCC VCC = NON1 NON2 NON3 NON4 Reset VCC = SDI VCC = CLK VCC = NSC IRES SDO Under voltage RESET RESET = Oscillator Shift Register Reset 1 VCC OSC CFB1 CFB2 CFB3 CFB4 NRES Failure Register (FR) FR RESET IRES I_SCB Filter t_SCB NON1 = PGND1 I_OL Filter t_OL NON1 = PGND2 PGND3 PGND4 Reset Trigger S R Overtemp. NON1 OUT4 Driver =

ROL

= dV/dt Control

OUT1 OUT2 OUT3

SCG Filter t_SCG =

99AT0007

LGND

SGND

May 2002

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PIN CONNECTION

PGND1 N.C. CFB1 OUT1 OUT1 CLK NCS N.C. SGND LGND N.C. SDO SDI OUT4 OUT4 CFB4 N.C. PGND4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19

PGND2 N.C. CFB2 OUT2 OUT2 NON1 NON2 N.C. VCC N.C. NRES NON3 NON4 OUT3 OUT3 CFB3 N.C. PGND3

99AT0012

Frame connected to PGND

PIN FUNCTIONS
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name PGND1 N.C. CFB1 OUT1 OUT1 CLK NCS N.C. SGND LGND N.C. SDO SDI OUT4 OUT4 CFB4 N.C. PGND4 PGND3 N.C. CFB3 OUT3 OUT3 NON4 Output Current feedback Output Power Switch Output Power Switch Inverted Control Signal Input Digital input, Schmitt trigger, internal Pullup current Sinks current proportional to IOUT3 Power Ground Power Ground Serial Data Output Serial Data Input Output Power Switch Output Power Switch Output Current feedback Sinks current proportional to IOUT4 Digital tristate output Digital input, Schmitt trigger, internal Pullup current Signal Ground Ground of digital part Output Current feedback Output Power Switch Output Power Switch Input Clock inverted Chip Select Input Digital input, Schmitt trigger, internal Pullup current Digital input, Schmitt trigger, internal Pullup current Sinks current proportional to IOUT1 Pin Description Power Ground Notes

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PIN FUNCTIONS (continued)
Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name NON3 NRES N.C. VCC N.C. NON2 NON1 OUT2 OUT2 CFB2 N.C. PGND2 Power Ground Inverted Control Signal Input Inverted Control Signal Input Output Power Switch Output Power Switch Output Current feedback Sinks current proportional to IOUT2 Digital input, Schmitt trigger, internal Pullup current Digital input, Schmitt trigger, internal Pullup current 5V Supply Voltage Input Pin Description Inverted Control Signal Input Inverted Reset Input Notes Digital input, Schmitt trigger, internal Pullup current Digital input, Schmitt trigger, internal Pullup current

THERMAL DATA
Symbol Thermal resistance Rth j-case Thermal resistance junction to case (one powerstage in use) Thermal resistance junction-ambient Thermal resistance junction-ambient Die must be soldered on the frame. pad layout pad layout + 6 on board heat sink cm2 50 35 4.5 C/W Parameter Test Conditions Min. Typ. Max. Unit

Rthja Rthja ESD ESD

C/W C/W

MIL 883C

KV

ABSOLUTE MAXIMUM RATINGS For externally applied voltages or currents exceeding these limits damage of the circuit may occur
Symbol Supply Voltages VCC VOut Ioutc ISCBpeak WOFF VIN VOUT Supply voltage Continues output voltage Continues current Peak output current Clamped energy at the switching OFF Input voltage Output voltage For 2ms, see fig. 8 -0.3 -0.3 -10 With no reverse current. -0.3 -0.3 7 45 3.0 I_SCB 50 7 VCC +0.3 150 V V A A mJ V V Outputs (Out 1 ... 4) Parameter Test Conditions Min. Typ. Max. Unit

Inputs (NONx; NCS; CLK; NRES; SDI) Outputs (SDO; CFB)

Operating junction temperature Tj

Note:

Operating junction temperature

-40

The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result.

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ELECTRICAL CHARACTERISTICS 4.5V VCC 5.5V, -40C TJ 125C, unless otherwise specified.
Symbol Supply current ICCRES Standby current Without load. Tj 85C NRES = LOW IOUT 1 ... 4 = 2A VCC < 0,5V -0.3 0.7 VCC 0.85 VIN = VCC VIN 0.8VCC 20 3 (ISDO = -2mA) (ISDO = 3.2mA) (NCS = HIGH; VSDO = 0V ... VCC) (NON = HIGH; VOUT = 14V; VCC = 5V) Vclpa (IOUT = 0.5A) For 2ms, see fig. 8 IOUT = 2A; Tj = 150C; Tj = 25C 2) VOUT = 30% ... 80% of VBAT=16V 3) VOUT = VBAT ... 0.9 Vclp 3) 80% ... 30% of VBAT = 16V with inductive load 3) NON = 50%; VOUT = 0.8 VBAT NON = 50%; VOUT = 0.3 VBAT 0.3 0.75 0.3 0 0 0.9 4 4 45 50 -10 VCC - 0.4 0.4 10 10 100 20 11 1.3 mA Parameter Test Conditions Min. Typ. Max. Unit

ICCOPM ICCLV VINL VINH Vhyst IIN IIN IIN NRES VSDOH VSDOL ISDOL

Operating mode Low voltage supply current Low threshold High threshold Hysteresis Input leakage current Input current (NONx, NCS, CLK, SDI) Input current NRES High output level Low output level Tristate leakage current

17 80 0.2 VCC VCC +0.3

mA A V V V A A A V V A

Inputs (NONx; NCS; CLK; NRES; SDI)

Serial Data Output

Outputs (Out 1 ... 4) IOUTL1 Leakage current 1 10 A

Vclpa WOFF RDSON OVRp1 OVRp2 OVRn tdON tdOFF

Note 1:

Output clamp voltage Clamped energy at the switching OFF 1) ON resistance Positive output voltage ramp (with inductive load)

60 50 500 300 1.35 2.25 1.35 10 10

V mJ m m V/s V/s V/s s s

250 0.9

Negative output voltage ramp Turn ON delay Turn OFF delay

Note 2: Note 3:

Typical loads for the zener clamping and the output voltage ramps are: a) 10, 16mH at all outputs or b) 25, 160mH At 150C guaranteed by design and electrical characterisation Tested with resistive load of Rload = 50

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ELECTRICAL CHARACTERISTICS (continued) 4.5V VCC 5.5V, -40C TJ 125C, unless otherwise specified.
Symbol Powerstage protection ISCB t_SCB Vccmin TRatio 1 TMPS1 6) Short current detection and switch off threshold Short circuit switch off delay time VCC undervoltage ICFB / IOUT for IOUT=0.4...2A 4)
5)

Parameter

Test Conditions With filter-time t_SCB.

Min. 3.0

Typ.

Max. 5.0

Unit A s V mA/A %

3 3.0 VCFB 1.8V Temperature stability for 0.4A to < 2.0A, related to 25C Current stability gain/Gain at 2A TJ = -40C TJ = +25C TJ = +125C -12 -6 -5 0.2 1.45 1.65 3

30 4.0 2 6

Current feedback

CURS1

for IOUT = 0.4A to 2A 5)

17 10 5 1 0.7

% % % % %

CURlin1 6) CURlin2
Note 4: Note 5: Note 6:

for IOUT = 0.4A to 1.0A for IOUT = 1.0A to 2.0A

4) 4)

Linearity Error (within the calibration points at 0.5A, 1A, 2A)

At 150C guaranteed by design and electrical characterisation Guaranteed by design and electrical characterisation Values for TMPS1, CURlin1 and CURlin2 are typical values from testing results

Diagnostic VREF1 t_SCG IOL t_OL ROL TOFF

Note 7:

Short to GND threshold voltage Short to GND filter time Open load threshold current Open load filter time Pullup resistor at OUT1, OUT2, OUT3 and OUT4 for OL detection Temperature detection threshold 7)
Guaranteed by measurement and correlation

for IOUT 2A

0.390 VCC 140 10 140 2.0 155 170

0.435 VCC 250 55 265 8.0 190

V s mA s k C

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ELECTRICAL CHARACTERISTICS (continued) 4.5V VCC 5.5V, -40C TJ 125C, unless otherwise specified.
Symbol fclk tclh tcll tpcld tcsdv tsclch thclcl tscld thcld tsclcl thclch tpchdz tfNCS
Note: 8.

Parameter Clock frequency Minimum time CLK = HIGH Minimum time CLK = LOW Propagation delay NCS = LOW CLK low before NCS low CLK change L/H after NCS = LOW SDI input setup time SDI input hold time CLK low before NCS high CLK high after NCS high NCS L/H to output data float NCS filter-time

Test Conditions 50% duty cycle.

Min. 0 100 100

Typ.

Max. 3

Unit MHz ns ns

Serial diagnostic link (external Load capacitor at SDO = 100pF)

CLK to data at SDO valid. To data at SDO valid. Setup time CLK to NCS change H/L. 100 100 CLK change H/L after SDI data valid. SDI data hold after CLK change H/L. 20 20 150 150

100 100

ns ns ns ns ns ns ns ns

100 Pulses tfNCS will be ignored. 10 40

ns ns

Input Pin Capacitance of SDI, CLK, NCS, NON1, NON2, NON3, NON4 6pF typical; Output Pin Capacitance of SDO 12pF typica

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1.0 Diagnostic Register and SPI timing Figure 1. Impulse diagram to read the Diagnostic Register

NCS

CLK

SDO

FSL

LSB

D1

D2

D3

D4

D5

D6

MSB

SDI

LSB

D1

D2

D3

D4

D5

D6

MSB

FR_RESET
99AT0008
Note: FR_RESET means Reset failure storage (internal signal)

Figure 2. Diagnostic Failure Register Structure

MSB D7 D6 D5 D4 D3 D2 D1

LSB D0 FSL

Failure indicator bit (only valid during NCS = LOW to the first L to H CLK change 1: failure stored 0: no failures Status channel 4 D0 D1 Status 1 1 no failures 1 0 open circuit, channel on 0 1 short to battery or overtemperature 0 0 short to gnd, channel off Status channel 3 D2 D3 corresponding to D0 D1 Status channel 2 D4 D5 corresponding to D0 D1
99AT0009/A

Status channel 1 D6 D7 corresponding to D0 D1

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Figure 3. Timing of the Serial Interface
NCS tsclch thclcl CLK tpcld tclh thclch

tcll

tsclcl

tcsdv

tpchdz

SDO

FSL thcld

D0

D7

tscld

SDI
99AT0010

D0

D1

D7

Figure 4. Short-Circuit to GND Failure (SCG-Failure) Detection

Failure-detection time for a SCG-failure OFF NON ON

SCG-failure

Vdrain Vdrain < Vref at OFF-state

Vref

t_SCG (filter-time) Filter-time Failure-detection

Failure-store
00AT0002

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Figure 5. Open-Load Failure (OL-Failure) Detection
Sporadical failure-detection Failure detection active for a sporadical OL-failure NON Lload Lload > I_OL Lload > I_OL for t > t_OL Diagnostic active Retrigger t filter t_OL Failure-detection Failure-store
00AT0003

Statical failure-detection

OFF ON I_OL

t_OL (filter-time)

Retrigger filter Sporadical failure-detection

t < t_OL

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Figure 6. Different cases for an Open Load failure detection (case 1 to 10)
IOL = OL filter time t OL

CASE 1 Non Input

Failure Register Status CASE 2 Non Input Failure Register Reset Output Current IOL t OL

Failure Register Status CASE 3 Output Current t OL IOL

Failure Register Status CASE 4 Output Current t OL IOL t OL

Failure Register Status CASE 5 Output Current t OL IOL

Failure Register Status CASE 6 Output Current t OL

t OL

IOL

Failure Register Status CASE 7 Output Current t OL

t OL

t OL

IOL

Failure Register Status CASE 8 Output Current t OL IOL t OL t OL

Failure Register Status CASE 9 Output Current t OL

t OL

IOL

Failure Register Status CASE 10 Output Current t OL

t OL

t OL

IOL

Failure Register Status

00AT0004

t OL

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Figure 7. Different cases for an Open Load failure detection (case 11 to 20)

CASE 11 Output Current

IOL

t OL t OL t OL

Failure Register Status CASE 12 Output Current IOL t OL t OL IOL t OL

Failure Register Status CASE 13 Output Current

Failure Register Status CASE 14 Output Current t OL IOL t OL t OL IOL t OL t OL t OL t OL

Failure Register Status CASE 15 Output Current

Failure Register Status CASE 16 Output Current IOL t OL

Failure Register Status CASE 17 Output Current t OL IOL t OL

Failure Register Status CASE 18 Output Current t OL IOL t OL t OL

Failure Register Status CASE 19 Output Current t OL IOL t OL

Failure Register Status CASE 20 Non Input Failure Register Reset Output Current IOL t OL

t OL

t OL

t OL

t OL

Failure Register Status

00AT0005

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Figure 8. Max Clamp Energy Specification

1000 Temp=25C Temp=150C 800 Energy/[mJ]

600

400

200

0 0.0

2.0

4.0 6.0 Pulse width/[ms]

8.0

10.0

Figure 9. Tratio of Current Feedback output versus output current

1.80e-03 1.75e-03 1.70e-03 1.65e-03 1.60e-03 Tratio 1.55e-03 1.50e-03 1.45e-03 1.40e-03 1.35e-03 1.30e-03 0.0 0.2 0.4 0.6 0.8 1.0 1.2 IOUT/[A] 1.4 1.6 1.8 2.0 Temp=-40C Temp=-20C Temp=25C Temp=70C Temp=150C

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Figure 10. TMPS1 vs. Temperature (4.5V Vcc 5.5V; 0.5A Iout1...4 3A).

3 2 TMPS1/[%] 1 0 -1 -2 -3 -50

50 100 Temp./[C]

150

200

FUNCTIONAL DESCRIPTION Introduction The Quad Low Side Driver UF07 is built up of four identical channels (Low Side Drivers), controlled by four CMOS input stages. Each Channel is protected against short to VBat and by a zener clamp against overvoltage. A diagnostic logic recognizes four failure types at the output stage: overcurrent, short to GND, open-load and overtemperature. The failures are stored individually for each channel in one byte which can be read out via a serial interface (SPI). Each channel has a current feedback output which sinks a current proportional to the load current of the Low Side Switch. Output Stage Control Each of the four output stages is switched ON and OFF by an individual control line (NON-Input). The logic level of the control line is CMOS compatible. The output transistors are switched off when the inputs are not connected. Power Transistors Each of the four output stages has its own zener clamp. This causes a voltage limitation at the power transistors when inductive loads are switched off. Output voltage ramp occurring when the output is switched on or off, is within defined limits. Output transistors can be connected in parallel to increase the current capability. In this case, the associated inputs, outputs and current feedback outputs should be connected together. Diagnostics Following failures at the output stage are recognized: Short circuit to V Bat or overtemp................= SCB (Highest priority) Short circuit to GND...................................=SCG Open Load.................................................= OL (Lowest Priority)

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Short-Circuit and Overtemperature Protection (SCB) If the output current increases above the short current limit for a longer time than t_SCB or if the temperature increases above TOFF, then the power transistor is immediately switched off. It remains switched off until the control signal at the NON-Input is switched off and on again. This filter time has the purpose to suppress wrong detection on short spikes. All four outputs have an independent overtemperature detection and shutdown. This measurement is active while the powerstage is switched on. The Short circuit detection and the overtemperature detection are using the same bit in the Diagnostic (one for each channel). A SCG failure will be recognized, when the drain voltage of the output stage is lower as the Short Cut to Ground threshold voltage, while the output stage is switched off (see Fig. 4). The SCG failure is filtered with a digital filter (t_SCG) to suppress the storage of a failure at small SCG spikes, which are typical during the transition of the power output. This filter is triggered by the NON input and the (analog) SCG detection. If the current through the output stage is lower than the IOL-reference, then an OL failure will be recognized after a filter time. This measurement is active while the powerstage is switched on. The Open Load failure detection has 2 different modes, the statical failure detection and the sporadic failure detection. One main difference is, that a statical failure is transferred to the Failure register with the next rising edge of NON, whereas a sporadic failure is transferred immediately to the Failure register (see fig. 5, 6 and 7). In both failure modes the OL detection is filtered (t_OL=tOL) and is using together with the SCG detection the same digital filter for suppression of spikes. The failures are stored regarding to their priority (see above). A failure with a higher priority overwrites an eventually already detected failure with a lower priority. Diagnostic interface The communication between the microprocessor and the failure register runs via the SPI link. If there is a failure stored in the failure register, the first bit of the shift register is set to a high level. With the H/L change at the NCS pin the first bit of the diagnostic shift register will be transmitted to the SDO output. The SDO output is the serial output from the diagnostic shift register and it is tristate when the NCS pin is high. The CLK pin clocks the diagnostic shift register. New SDO data will appear on every rising edge of the CLK pin and new SDI data will be latched on every falling edge into the shift register. With the first positive pulse of the CLK the contents of the failure register is copied to the SPI shift register and a internal reset (FR_RESET) is generated. This internal reset clears the failure register and thus the failure register is capable of detecting failures also during the SPI read cycle. There is no bus collision at a small spike at the NCS. The CLK has to be LOW, while the NCS signal is changing. Current feedback Each channel has a current feedback output which sinks a current proportional to the load current of the Low Side Switch. Using this output servo loop applications can be realized by applying a PWM signal to the NON input. A typical diagram of the Current Feedback output at different temperatures is shown in figure 9.

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Reset There are two different reset functions realized: Undervoltage reset As long as the voltage of Vcc is lower than Vccmin, the powerstages are switched off, the failure register is reset and the SDO output remains tristate. External reset As long as the NRES pin is low following circuits are reset: Powerstages Failure register and the SDO output is tristate. Undervoltage protection At Vcc below Vccmin the device remains switched off even if there is a voltage ramp at the OUT pin. Figure 11. Application Circuit
VCC C1 C2 VCC VCC VCC = NON1 NON2 NON3 NON1 NON4 Reset C VCC = SDI VCC = CLK VCC = NSC IRES SDO LGND Under voltage RESET SGND Shift Register Reset 1 VCC OSC CFB2 CFB3 RESET NRES = Oscillator CFB4 ADC Failure Register (FR) IRES I_SCB Filter t_SCB NON1 = PGND1 PGND2 I_OL Filter t_OL NON1 = PGND3 PGND4 OUT4 C4 Trigger S R OUT3 Overtemp. C3 Driver = ROL VS

(optional for all channels) OUT1

= dV/dt Control

C1 OUT2 C2

Reset

FR RESET

SCG Filter t_SCG = CFB1

VCC

99AT0011

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mm TYP. inch TYP.

DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 E4 G H h L N S

MIN. 0.10 0 0.22 0.23 15.80 9.40 13.90

MAX. 3.60 0.30 3.30 0.10 0.38 0.32 16.00 9.80 14.50

MIN. 0.004 0 0.008 0.009 0.622 0.370 0.547

MAX. 0.141 0.012 0.130 0.004 0.015 0.012 0.630 0.385 0.570

OUTLINE AND MECHANICAL DATA

0.65 11.05 10.90 5.80 2.90 0 15.50 0.80 11.10 0.429 2.90 6.20 0.228 3.20 0.114 0.10 0 15.90 0.610 1.10 1.10 0.031 10(max.) 8 (max.)

0.0256 0.435 0.437 0.114 0.244 0.126 0.004 0.626 0.043 0.043

PowerSO36

(1): "D" and "E1" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (0.006 inch) - Critical dimensions are "a3", "E" and "G".

N a2 A DETAIL A e3 H lead e A a1 E DETAIL A

c DETAIL B

D a3
36 19

slug BOTTOM VIEW E3

B E2 E1 DETAIL B
0.35 Gage Plane

D1

-C-

S h x 45 b
0.12
M

SEATING PLANE G C

AB

PSO36MEC

(COPLANARITY)

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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com

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