Page I.01
I. INTRODUCTION
Contents
Introduction Analog Integrated Circuit Design Technology Overview Notation Analog Circuit Analysis Techniques
Page I.02
SYSTEMS
CIRCUITS
Chapter 5 CMOS Subcircuits SIMPLE Chapter 6 CMOS Amplifiers
DEVICES
Introduction
Page I.21
GLOBAL OBJECTIVES Teach the analysis, modeling, simulation, and design of analog circuits implemented in CMOS technology. Emphasis will be on the design methodology and a hierarchical approach to the subject.
SPECIFIC OBJECTIVES 1. Present an overall, uniform viewpoint of CMOS analog circuit design. 2. Achieve an understanding of analog circuit design. Hand calculations using simple models Emphasis on insight Simulation to provide secondorder design resolution 3. Present a hierarchical approach. Subblocks Blocks Circuits Systems 4. Examples to illustrate the concepts.
Allen and Holberg  CMOS Analog Circuit Design I.2 ANALOG INTEGRATED CIRCUIT DESIGN
Page I.21
FILTERS
AMPLIFICATION
Passive RLC circuits 19351950 ActiveRC Filters Requires precise definition of time constants (RC products) 1978 Switched Capacitor Filters Requires precise C ratios and clock 1983 Continuous Time Filters Time constants are adjustable 1992
Openloop amplifiers
Page I.22
Integrated Poor absolute accuracies No (kit parts) Very Dependent Layout, verification, and extraction
Not Important
Simulation
Model parameters vary widely Must be considered before the design Schematic capture, simulation, extraction, LVS, layout and routing Active devices, capacitors, and resistors
Testing
CAD
Components
All possible
Allen and Holberg  CMOS Analog Circuit Design THE ANALOG IC DESIGN PROCESS
Page I.23
Definition of the design Comparison with design specifications Comparison with design specifications
Implementation
Simulation
Physical Definition
Physical Verification
Parasitic Extraction
Fabrication
Product
Page I.24
Analog Circuits
Digital Circuits
are discontinuous in Signals are continuous in amplitude Signal and can be continuous or discrete in amplitude and time  binary signals have two amplitude states time Designed at the circuit level Designed at the systems level
Components must have a continuum Component have fixed values of values Customized CAD tools are difficult to apply Requires precision modeling Performance optimized Irregular block Difficult to route automatically Standard CAD tools have been extremely successful Timing models only Programmable by software Regular blocks Easy to route automatically
Dynamic range limited by power Dynamic range unlimited supplies and noise (and linearity)
Allen and Holberg  CMOS Analog Circuit Design I.3 TECHNOLOGY OVERVIEW
Page I.31
Seismic
Sonar
Radar
Audio
10
100
1k
10k
1G
10G
100G
Page I.32
BiCMOS Bipolar analog Bipolar digital logic MOS digital logic MOS analog Optical GaAs
10
100
1k
10k
1G
10G
100G
Allen and Holberg  CMOS Analog Circuit Design CLASSIFICATION OF SILICON TECHNOLOGY
Page I.33
Silicon IC Technologies
Bipolar
Bipolar/MOS
MOS
Junction Isolated
Dielectric Isolated
CMOS
NMOS
Aluminum gate
Silicon gate
Aluminum gate
Silicon gate
Allen and Holberg  CMOS Analog Circuit Design BIPOLAR VS. MOS TRANSISTORS
Page I.34
CATEGORY Turnon Voltage Saturation Voltage gm at 100 A Analog Switch Implementation Power Dissipation Speed Compatible Capacitors AC Performance Dependence Number of Terminals Noise (1/f) Noise Thermal Offset Voltage
BIPOLAR 0.50.6 V 0.20.3 V 4 mS Offsets, asymmetric Moderate to high Faster Voltage dependent DC variables only 3 Good OK < 1 mV 0.81 V
CMOS
0.20.8 V 0.4 mS (W=10L) Good Low but can be large Fast Good DC variables and geometry 4 Poor OK 510 mV
Page I.35
CMOS is nearly ideal for mixedsignal designs: Dense digital logic Highperformance analog
DIGITAL
ANALOG
MIXEDSIGNAL IC
Page I.41
I.4
NOTATION
Source Source/bulk nchannel, enhance nchannel, enhancement, bulk at most ment, VBS 0 negative supply
Drain
Source Source/bulk pchannel, enhance pchannel, enhancement, bulk at most ment, VBS 0 positive supply
Allen and Holberg  CMOS Analog Circuit Design SYMBOLS FOR CIRCUIT ELEMENTS
Page I.42
Operational Amplifier/Amplifier/OTA
+ AvV1 V1 
+ V1 
G mV1
VCVS
I1 Rm I 1 I1
VCCS
Ai I 1
CCVS
CCCS
Allen and Holberg  CMOS Analog Circuit Design Notation for signals
Page I.43
Id id
ID iD
time
Page II.01
Basic Fabrication Processes CMOS Technology PN Junction MOS Transistor Passive Components Latchup Protection ESD Protection Geometrical Considerations
Page II.02
SYSTEMS
CIRCUITS
Chapter 5 CMOS Subcircuits SIMPLE Chapter 6 CMOS Amplifiers
DEVICES
Page II.03
Provide an understanding of CMOS technology sufficient to enhance circuit design. Characterize passive components compatible with basic technologies. Provide a background for modeling at the circuit level. Understand the limits and constraints introduced by technology.
Allen and Holberg  CMOS Analog Circuit Design II.1  BASIC FABRICATION PROCESSES
Page II.11
Basic Steps Oxide growth Thermal diffusion Ion implantation Deposition Etching Photolithography Means by which the above steps are applied to selected areas of the silicon wafer. Silicon wafer
0.50.8 mm 125200 mm
Page II.12
The process of growing a layer of silicon dioxide (SiO2)on the surface of a silicon wafer.
Original Si surface tox
SiO 2
0.44 tox
Si substrate
Uses: Provide isolation between two layers Protect underlying material from contamination Very thin oxides (100 to 1000 ) are grown using dryoxidation techniques. Thicker oxides (>1000 ) are grown using wet oxidation techniques.
Page II.13
Movement of impurity atoms at the surface of the silicon into the bulk of the silicon  from higher concentration to lower concentration.
High Concentration
Low Concentration
ERFC
t1<t2<t3
N(x)
NB
t1
t2
t3
Depth (x)
Finitesource diffusion:
N0
Gaussian
t1<t2<t3
N(x)
NB
t1
t2
t3
Depth (x)
Page II.14
Ion implantation is the process by which impurity ions are accelerated to a high velocity and physically lodged into the target.
Path of impurity atom
Fixed atoms
Anneal required to activate the impurity atoms and repair physical damage to the crystal lattice. This step is done at 500 to 800 C. Lower temperature process compared to diffusion. Can implant through surface layers, thus it is useful for fieldthreshold adjustment. Unique doping provile available with buried concentration peak.
NB 0
Depth (x)
Page II.15
Deposition is the means by which various materials are deposited on the silicon wafer. Examples: Silicon nitride (Si3N4) Silicon dioxide (SiO2) Aluminum Polysilicon There are various ways to deposit a meterial on a substrate: Chemicalvapor deposition (CVD) Lowpressure chemicalvapor deposition (LPCVD) Plasmaassisted chemicalvapor deposition (PECVD) Sputter deposition Materials deposited using these techniques cover the entire wafer.
Page II.16
Etching is the process of selectively removing a layer of material. When etching is performed, the etchant may remove portions or all of: the desired material the underlying layer the masking layer Important considerations: Anisotropy of the etch lateral etch rate A = 1  vertical etch rate Selectivity of the etch (film toomask, and film to substrate) film etch rate Sfilmmask = mask etch rate Desire perfect anisotropy (A=1) and invinite selectivity. There are basically two types of etches: Wet etch, uses chemicals Dry etch, uses chemically active ionized gasses.
a Mask Film b Underlying layer c
Allen and Holberg  CMOS Analog Circuit Design Photolithography Components Photoresist material Photomask Material to be patterned (e.g., SiO2) Positive photoresistAreas exposed to UV light are soluble in the developer Negative photoresist
Page II.17
Areas not exposed to UV light are soluble in the developer Steps: 1. Apply photoresist 2. Soft bake 3. Expose the photoresist to UV light through photomask 4. Develop (remove unwanted photoresist) 5. Hard bake 6. Etch the exposed layer 7. Remove photoresist
Page II.18
Photomask
UV Light Photomask
Photoresist
Polysilicon
Page II.19
Polysilicon
Photoresist
Photoresist Polysilicon
Polysilicon
Positive Photoresist
Allen and Holberg  CMOS Analog Circuit Design II.2  CMOS TECHNOLOGY TWINWELL CMOS TECHNOLOGY Features
Page II.21
Two layers of metal connections, both of them of high quality due to a planarization step.
Optimal threshold voltages of both pchannel and nchannel transistors Lightly doped drain (LDD) transistors prevent hotelectron effects. Good latchup protection
Page II.22
Photoresist
SiO2
Photoresist
p substrate
(a)
Si3N4
SiO2
nwell p substrate
(b)
n field implant
Photoresist
Si3N4
Photoresist
nwell p substrate
(c)
p field implant
Si3N4
Photoresist
nwell p substrate
(d)
Page II.23
FOX
(e)
Polysilicon
FOX
(f)
Polysilicon FOX
p substrate
(h)
Page II.24
Polysilicon FOX
p substrate
(i)
(j)
n+ Diffusion
p+ Diffusion
Polysilicon
FOX
(k)
n+ Diffusion
p+ Diffusion
Polysilicon BPSG
FOX
(l)
Page II.25
(m)
Metal 2
Metal 1
(n)
Metal 1
(o)
Allen and Holberg  CMOS Analog Circuit Design Silicide/Salicide Purpose Reduce interconnect resistance,
Page II.26
Polysilicide
FOX
FOX
(a)
(b)
Allen and Holberg  CMOS Analog Circuit Design II.3  PN JUNCTION CONCEPT
Metallurgical Junction ptype semiconductor ntype semiconductor
Page II.31
iD
iD
vD + xd xp 0 xn x
1. Doped atoms near the metallurgical junction lose their free carriers by diffusion. 2. As these fixed atoms lose their free carriers, they build up an
electric field which opposes the diffusion mechanism. 3. Equilibrium conditions are reached when:
Page II.32
xn
ntype semiconductor
iD
+vD 
Impurity concentration ( cm3 ) ND 0 NA Depletion charge concentration ( cm3 ) qND xp 0 qNA Electric Field (V/cm) x Eo Potential (V) o v D x xn x x
xd
Allen and Holberg  CMOS Analog Circuit Design SUMMARY OF PN JUNCTION ANALYSIS Barrier potentialo = kT NAND NAND ln = V ln t 2 q ni ni2
Page II.33
1 =
1 N
Depletion capacitanceCj = A Breakdown voltagesi(NA+ND) 2 Emax BV = 2qN N A D siqNAND 2(NA+ND) Cj0 ovD
ovD
Page II.34
25 20
iD 15 Is 10
5 0 5
4
3
2
1
vD/Vt
10 x1016 8 x1016
16 iD 6 x10 Is 4 x1016
Allen and Holberg  CMOS Analog Circuit Design II.4  MOS TRANSISTOR ILLUSTRATION
Bulk Source Gate Drain
II.41
p+
Fig. 4.34 n+
psubstrate (bulk)
TYPES OF TRANSISTORS
iD
Depletion Mode
Enhancement Mode
Ch an n
Polysilicon
el W id th ,
VT (depletion)
VT (enhancement)
vGS
Allen and Holberg  CMOS Analog Circuit Design CMOS TRANSISTOR Nwell process
pchannel transistor Polysilicon L SiO2 nchannel transistor L
II.42
dra in ( p+)
n+
dra in ( n+) p+
Figure 2.31 Physical structure of an nchannel and pchannel transistor in an nwell technology.
Allen and Holberg  CMOS Analog Circuit Design TRANSISTOR OPERATING POLARTIES Polarity of vGS and V T + +
II.43
Type of Device nchannel, enhancement nchannel, depletion pchannel, enhancement pchannel, depletion
Polarity of vDS + + 
Polarity of vBULK Most negative Most negative Most positive Most positive
Source Source/bulk nchannel, enhance nchannel, enhancement, bulk at most ment, VBS 0 negative supply
Drain
Source Source/bulk pchannel, enhance pchannel, enhancement, bulk at most ment, VBS 0 positive supply
Allen and Holberg  CMOS Analog Circuit Design II.5  PASSIVE COMPONENTS CAPACITORS oxA C = tox
II.51
FOX
FOX
FOX
Interpoly SiO2 p substrate
Allen and Holberg  CMOS Analog Circuit Design MetalMetal and MetalMetalPoly Capacitors
II.52
M3 M2 B M1 Poly M3 T M2 M1 B T T
M2 B M1 Poly T
M2 M1 B
Figure 2.42 Various ways to implement capacitors using available interconnect layers. M1, M2, and M3 represent the first, second, and third metal layers respectively.
Cdesired
Figure 2.43 A model for the integrated capacitors showing top and bottom plate parasitics.
Allen and Holberg  CMOS Analog Circuit Design PROPER LAYOUT OF CAPACITORS Use unit capacitors Use common centroid Want A=2*B Case (a) fails Case (b) succeeds!
II.53
(a)
A1
A2
(b)
A1
A2
x1
x2
x3
Figure 2.62 Components placed in the presence of a gradient, (a) without commoncentroid layout and (b) with commoncentroid layout.
Allen and Holberg  CMOS Analog Circuit Design NONUNIFORM UNDERCUTTING EFFECTS
II.54
Largescale distortion
Cornerrounding distortion
II.55
C A B
C A B
Figure 2.61 (a)Illustration of how matching of A and B is disturbed by the presence of C. (b) Improved matching achieved by matching surroundings of A and B
Allen and Holberg  CMOS Analog Circuit Design IMPROVED LAYOUT METHODS FOR CAPACITORS
II.56
Corner clipping:
Clip corners
Streeteffect compensation:
Allen and Holberg  CMOS Analog Circuit Design ERRORS IN CAPACITOR RATIOS Let C1 be defined as
C1 = C1A + C1P and C2 be defined as C2 = C2A + C2P CXA is the bottomplate capacitance CXP is the fringe (peripheral) capacitance CXA >> CXP The ratio of C2 to C1 can be expressed as C2 C2A + C2P C1 = C1A + C1P =
2P 1 + C2A C2A C1A C1P 1 +
II.57
C1A
Thus best matching is achieved when the area to periphery ratio remains constant.
II.58
Top Plate
Desired Capacitor
Bottom Plate
Allen and Holberg  CMOS Analog Circuit Design RESISTORS IN CMOS TECHNOLOGY
Metal SiO2 p+
II.59
FOX
n well p substrate
FOX
(a)
FOX
p substrate
(b)
Metal n+
FOX
n well p substrate
FOX
FOX
(c)
Allen and Holberg  CMOS Analog Circuit Design PASSIVE COMPONENT SUMMARY (0.8 m Technology)
II.510
Component Range of Values Matching Type Accuracy Poly/poly 0.05% 0.81.0 fF/m2 capacitor MOS 0.05% 2.22.5 fF/m2 capacitor MOM 1.5% 0.020.03 fF/m2 capacitor Diffused 0.4% 20150 /sq. resistor Polysilicide R 215 /sq. Poly resistor 0.4% 2040 /sq. Nwell 0.4% 12k /sq. resistor
200ppm/V
Allen and Holberg  CMOS Analog Circuit Design BIPOLARS IN CMOS TECHNOLOGY
Metal Emitter (p+) Base (n+)
II.511
FOX
n well
FOX
WB
FOX
Depletion regions
p Emitter
n Base
p Collector
Carrier concentration
nn(x)
ppC
NA
npE
ppC x
II.61
S Substrate tie
D=B
VDD
p+
FOX
n+ Q1
n+
FOX
p+
Q2
p+ RN
FOX
n+ nwell
psubstrate
RP(a) VDD
RN
Q2 A
Q1 B RP
(b) Figure 2.53 (a) Parasitic lateral NPN and vertical PNP bipolar transistor in CMOS integrated circuits. (b) Equivalent circuit of the SCR formed from the parasitic bipolar transistors.
II.62
VDD
VSS
Allen and Holberg  CMOS Analog Circuit Design II.7  ESD PROTECTION
II.61
To internal gates
p+ resistor
Bonding Pad
Metal
n+
FOX
nwell
p+
FOX
psubstrate
(b)
Figure 2.55 Electrostatic discharge protection circuitry. (a) Electrical equivalent circuit (b) Implementation in CMOS technology
Allen and Holberg  CMOS Analog Circuit Design II.8  GEOMETRICAL CONSIDERATIONS
II.81
Minimum Dimension Resolution () 1. NWell 1A. width .........................................................................6 1B. spacing .................................................................... 12 2. Active Area (AA) 2A. width .........................................................................4 Spacing to Well 2B. AAn contained in nWell.............................................1 2C. AAn external to nWell............................................. 10 2D. AAp contained in nWell.............................................3 2E. AAp external to nWell...............................................4 Spacing to other AA (inside or outside well) 2F. AA to AA (p or n).......................................................3 3. Polysilicon Gate (Capacitor bottom plate) 3A. width..........................................................................2 3B. spacing .......................................................................3 3C. spacing of polysilicon to AA (over field)........................1 3D. extension of gate beyond AA (transistor width dir.) ........2 3E. spacing of gate to edge of AA (transistor length dir.) ......4 4. Polysilicon Capacitor top plate 4A. width..........................................................................2 4B. spacing .......................................................................2 4C. spacing to inside of polysilicon gate (bottom plate)..........2 5. Contacts
II.82
5A. size ....................................................................... 2x2 5B. spacing .......................................................................4 5C. spacing to polysilicon gate ............................................2 5D. spacing polysilicon contact to AA ..................................2 5E. metal overlap of contact ...............................................1 5F. AA overlap of contact ..................................................2 5G. polysilicon overlap of contact........................................2 5H. capacitor top plate overlap of contact.............................2 6. Metal1 6A. width..........................................................................3 6B. spacing .......................................................................3 7. Via 7A. size ....................................................................... 3x3 7B. spacing .......................................................................4 7C. enclosure by Metal1....................................................1 7D. enclosure by Metal2....................................................1 8. Metal2 8A. width..........................................................................4 8B. spacing .......................................................................3 Bonding Pad 8C. spacing to AA............................................................ 24 8D. spacing to metal circuitry ........................................... 24 8E. spacing to polysilicon gate .......................................... 24
Allen and Holberg  CMOS Analog Circuit Design 9. Passivation Opening (Pad)
II.83
9A. bondingpad opening ..............................100m x 100 m 9B. bondingpad opening enclosed by Metal2 ......................8 9C. bondingpad opening to pad opening space ................... 40 Note: For a PWell process, exchange p and n in all instances.
II.84
1B
1A
2E
2B
2A 2F
2C
2D
3C
3A
3E
3D
3B
II.85
4C
4B
4A
5C 5A 5B
5D
5E
5F
5G
5H
II.86
7A
7B 7C 6B
6A 7D
8A 8B
9B
9A
9C
PAA
METAL1
CONTACT
VIA
II.87
Polysilicon gate L
Contact
Cut W
Metal 1
Figure 2.63 Example layout of an MOS transistor showing top view and side view at the cut line indicated.
II.88
(a)
(b)
Figure 2.64 Example layout of MOS transistors using (a) mirror symmetry, and (b) photolithographic invariance.
PLI IS BETTER
II.89
Contact
Cut
Metal 1
Metal
FOX Substrate
FOX
FOX
Well diffusion
Cut
Metal 1
Figure 2.65 Example layout of (a) diffusion or polysilicon resistor and (b) Well resistor along with their respective side views at the cut line indicated.
II.810
Cut
Metal 1
(a)
Metal 3
Metal 2
Metal 1
FOX Substrate
Metal 3
Metal 2
Metal 1
Metal 3 Via 2
Via 1
Metal 1 (b) Figure 2.67 Example layout of (a) doublepolysilicon capacitor, and (b) triplelevel metal capacitor along with their respective side views at the cut line indicated.
Page III.01
SYSTEMS
CIRCUITS
Chapter 5 CMOS Subcircuits SIMPLE Chapter 6 CMOS Amplifiers
DEVICES
Page III.11
III.1  MODELING OF CMOS ANALOG CIRCUITS Objective 1. Hand calculations and design of analog CMOS circuits. 2. Efficiently and accurately simulate analog CMOS circuits. Large Signal Model The large signal model is nonlinear and is used to solve for the dc values of the device currents given the device voltages. The large signal models for SPICE: Basic drain current models 1. Level 1  ShichmanHodges (VT, K', , , , and NSUB) 2. Level 2  Geometrybased analytical model. Takes into account secondorder effects (varying channel charge, shortchannel, weak inversion, varying surface mobility, etc.) 3. Level 3  Semiempirical shortchannel model 4. Level 4  BSIM model. Based on automatically generated parameters from a process characterization. Good weakstrong inversion transition. Basic model auxilliary parameters include capacitance [Meyer and WardDutton (chargeconservative)], bulk resistances, depletion regions, etc.. Small Signal Model Based on the linearization of any of the above large signal models. Simulator Software SPICE2  Generic SPICE available from UC Berkeley (FORTRAN) SPICE3  Generic SPICE available from UC Berkeley (C) *SPICE* Every other SPICE simulator!
Page III.12
0
p substrate (bulk)
VT
2VT 3VT v GS
vGS = 2VT:
+ v GS = 2VT iD Gate Drain + VDS =0.1V iD
0
p substrate (bulk)
VT
2VT
3VT v GS
vGS = 3VT:
+ v GS = 3VTiD Gate Drain + iD VDS  =0.1V
0
p substrate (bulk)
VT
2VT
3VT v GS
Page III.13
p substrate (bulk)
0 0 0.5VT VT v DS
vDS = 0.5VT:
VGS + = 2VT iD Gate Drain + v DS = i D 0.5VT
0
p substrate (bulk)
0.5VT
VT
v DS
vDS = VT:
VGS + = 2VT iD Gate Drain + v DS =VT iD
p substrate (bulk)
0.5V T
VT
vDS
Page III.14
vDS(sat) 0
p substrate (bulk)
vGS = 2VT:
+ v GS = 2VT iD Gate Drain + v = iD DS  4VT
vDS(sat) 0
p substrate (bulk)
vGS = 3VT:
v GS = 3VT + Gate iD Drain + v = iD DS 4V T 
vDS(sat) 0
p substrate (bulk)
Page III.15
VGS=4V
0.5
VGS=3V
0 0 2 4 vDS (V) 6
VGS=2V VGS=1V 8 10
VDS=2V
0.5
0 0 1
2 vGS(V)
Page III.16
v(y)
p
dy y y+dy
Derivation Let the charge per unit area in the channel inversion layer be QI(y) = C ox[vGS v(y) VT] (coulombs/cm2) Define sheet conductivity of the inversion layer per square as 1 cm2 coulombs amps S = oQI(y) vs cm2 = volt = /sq. Ohm's Law for current in a sheet is iD dv JS = = E = S S y W dy . Rewriting Ohm's Law gives, iD iDdy dv = W dy = Q (y)W o I S where dv is the voltage drop along the channel in the direction of y. Rewriting as iD dy = WoQI(y)dv and integrating along the channel for 0 to L gives
vDS L vDS WoQI(y)dv = iDdy = WoCox[vGSv(y)VT] dv 0 0 0
Page III.17
ILLUSTRATION OF THE SAH EQUATION Plotting the Sah equation as iD vs. vDS results in iD vDS = vGS  VT
NonSat Region
Saturation Region
Define vDS(sat) = vGS VT Regions of Operation of the MOS Transistor 1.) Cutoff Region: iD = 0, vGS VT < 0 (Ignores subthreshold currents) 2.) Nonsaturation Region iD = CoxW 2L 2(vGS VT) v DS vDS , 0 < vDS < vGS VT
3.) Saturation Region iD = CoxW 2 2L (vGS VT) , 0 < vGS VT < vDS
Page III.18
SAH MODEL ADJUSTMENT TO INCLUDE EFFECTS OF VDS ON VT From the previous derivation:
vDS vDS L iD dy = WoQI(y)dy = WoCox[vGS v(y) V T]dv 0 0 0
Assume that the threshld voltage varies across the channel in the following way: VT(y) = VT + v(y) where V T is the value of the threshold voltage at the source end of the channel. Integrating the above gives,
v WoCox v2(y) DS (vGSVT)v(y) (1+ ) iD = L 2 0
To find vDS(sat), set the derivative of iD with respect to vDS equal to zero and solve for vDS = vDS(sat) to get, vGS VT 1+
vDS(sat) =
iD =
Page III.19
EFFECTS OF BACK GATE (BULKSOURCE) BulkSource (vBS) influence on the transconductance characteristicsiD Decreasing values of bulksource voltage VBS = 0 vDS vGS  VT
In general, the simple model incorporates the bulk effect into V T by the following empirically developed equationVT(V =V T0 + 2f + vBS 2f
BS)
Page III.110
Drain VDS>0
n+
VSB1>0V:
VSB1 + Bulk p+ pSubstrate/Bulk Source n+ Gate VGS>VT
Poly
Drain VDS>0
n+
Drain VDS>0
Source n+
n+
Page III.111
vBS  S
NonsaturationiD = SaturationWoCox vDS(sat)2 (1 + vDS) iD = (v VT)vDS(sat) L GS 2 = where: o = zero field mobility (cm2/voltsec) Cox = gate oxide capacitance per unit area (F/cm2) = channellength modulation parameter (volts1) VT = VT0 + 2f + vBS 2f VT0 = zero bias threshold voltage = bulk threshold parameter (volts1/2) 2f = strong inversion surface potential (volts) When solving for pchannel devices, negate all voltages and use the nchannel model with pchannel parameters and negate the current. Also negate VT0 of the p device. WoCox 2 2L (vGS VT) (1 + vDS) WoCox vDS2 (vGS V T)vDS L 2
Page III.112
Page III.113
GRAPHICAL INTERPRETATION OF Assume the MOS is transistor is saturatedCoxW iD = 2L (vGS VT) 2(1 + vDS) Define iD(0) = iD when vDS = 0V. iD(0) = Now, iD = iD(0) [1+vDS] = iD(0) + iD(0) vDS or 1 1 i vDS = D iD (0) Matching with y = mx + b gives
vDS 1 1 iD(0) iD iD(0)
1
or
iD iD3(0) iD2(0) iD1(0) VGS3 VGS2 VGS1 vDS
1
Page III.114
SPICE LEVEL 1 MODEL PARAMETERS FOR A TYPICAL BULK CMOS PROCESS (0.8m)
Typical Parameter Value NMOS PMOS 0.750.15 11010% 0.850.15 5010%
Units
Volts A/V2
Bulk Threshold Parameter Channel Length Modulation Parameter Surface potential at strong inversion
V V1
= 2F
0.7
0.8
Volts
These values are based on a 0.8 m silicongate bulk CMOS nwell process.
Page III.115
iD (nA) 1000.0 100.0 10.0 1.0 0 VT VON vGS 0 VT VON vGS Weak inversion region
iD
This model is appropriate for hand calculations but it does not accommodate a smooth transition into the stronginversion region.
qvGS W iD L IDO exp nkT
The transition point where this relationship is valid occurs at approximately kT vgs < V T + n q WeakModerateStrong Inversion Approximation
Moderate inversion region
Page III.21
INTRINSIC CAPACITORS OF THE MOSFET Types of MOS Capacitors 1. Depletion capacitance (CBD and CBS) 2. Gate capacitances (CGS, CGD, and CGB)
SiO2
C3
Page III.22
Depletion Capacitors Bulkdrain pn junction CBD Capacitance approximation for strong forward bias
CBD =
Page III.23
G C
CBX =
and CBX = vBX (CJ )(AX) 1 (1 + MJ ) FC + MJ PB (1 FC)1+MJ + v (CJSW)(PX) 1 (1 + MJSW )FC + BX (MJSW) , PB (1 FC)1+MJSW
vBX (FC)(PB) where AX = area of the source (X = S) or drain (X = D) PX = perimeter of the source (X = S) or drain (X = D) CJSW = zerobias, bulksource/drain sidewall capacitance MJSW = bulksource/drain sidewall grading coefficient
Page III.24
Overlap Capacitance
Mask L
Oxide encroachment
Actual L (Leff) LD
Mask W
Actual W (Weff)
Gate
Drain
Figure 3.25 Overlap capacitances of an MOS transistor. (a) Top view showing the overlap between the source or drain and the gate. (b) Side view.
Page III.25
Overlap
Overlap
FOX
C5
Gate Source/Drain
C5
FOX
Bulk
On a pertransistor basis, this is generally quite small Channel Capacitance C2 = Weff (L 2 LD)Cox = Weff (Leff )Cox Drain and source portions depend upon operating condition of transistor.
Page III.26
Capacitance C2 + 2C5
2 C1 + _ C 3 2 1 C1 + _ C 2 2
C1, C3 2C5 0
CGS, CGD
CGD CGB
Off VT
NonSaturation
vGS
Figure 3.27 Voltage dependence of CGS, CGD, and CGB as a function of VGS with VDS constang and VBS = 0.
iD
v DS = v GS  VT
NonSat Region
vDS = constant
Allen and Holberg  CMOS Analog Circuit Design CGS, CGD, and CGB
Page III.27
Off CGB = C2 + 2 C5 = Cox(Weff )(Leff ) + CGBO(Leff ) CGS = C1 Cox(LD)(Weff ) = CGSO(Weff ) CGD = C3 Cox(LD)(Weff ) = CGD O(Weff ) Saturation CGB = 2 C5 = CGBO (Leff ) CGS = C1 + (2/3)C2 = Cox(LD + 0.67Leff )(Weff ) = CGSO(Weff ) + 0.67Cox(Weff )(Leff ) CGD = C3 Cox(LD)(Weff ) = CGD O(Weff ) Nonsaturated CGB = 2 C5 = CGBO (Leff ) CGS = C1 + 0.5C2 = Cox(LD + 0.5Leff )(Weff ) = (CGSO + 0.5CoxLeff )Weff CGD = C3 + 0.5C2 = Cox(LD + 0.5Leff )(Weff ) = (CGDO + 0.5CoxLeff )Weff
Page III.31
gmvgs
gds
inrS
Cbs
Cgb
rS
The channel conductances, gm, gmbs, and gds are defined as gm = (at the quiescent point)
ID VBS ID
VDS
Allen and Holberg  CMOS Analog Circuit Design Saturation Region gm = (2K'W/L) ID(1 + VDS) (2K'W/L)ID
Page III.32
gmbs =
I D VT = VSB VT VSB
ID
Noting that
ID ID = , we get VT VGS
gmbs = gm
= gm 2(2F + VSB)1/2
gds = go =
ID 1 + VDS
ID
Relationships of the Small Signal Model Parameters upon the DC Values of Voltage and Current in the Saturation Region. Small Signal DC Current DC Current and DC Voltage Model Parameters Voltage 2K' W gm (2K' IDW/L)1/2 _ (V V ) gmbs gds
ID
GS
Allen and Holberg  CMOS Analog Circuit Design Nonsaturation region gm = Id = VDS VGS ID VDS = VBS 2(2F  + VSB)1/2
Page III.33
gmbs = and
Relationships of the SmallSignal Model Parameters upon the DC Values of Voltage and Current in the Nonsaturation Region. Small Signal DC Voltage and/or Current Model Parameters Dependence = VDS gm VDS gmbs
2(2F  + VSB)1/2
gds
= (VGS VT
VDS)
Noise
2 4kT i nrD = f rD 2 4kT i nrS = f rS
(A2)
(A2)
Page III.41
(6)
Note that PHI is the SPICE model term for the quantity 2f . Also be aware that PHI is always positive in SPICE regardless of the transistor type (p or nchannel). fn = DELTA si Weff 2 COX (7)
1/2 xj LD + wc wp 2 LD 1 fs = 1 x x Leff xj + wp j j
(8)
(9)
(10)
Allen and Holberg  CMOS Analog Circuit Design wp wp2 wc = xj k1 + k2 k3 xj xj k1 = 0.0631353 , k2 = 0.08013292 , k3 = 0.01110777 Threshold Voltage ETA8.1522 v + GAMMA f ( PHI + v )1/2 + f ( PHI + v ) VT = Vbi s SB n SB C L 3 DS ox eff vbi = vfb + PHI or vbi = VTO GAMMA PHI Saturation Voltage vsat = vgs VT 1 + fb
1/2
Page III.42
(11)
(12)
(13)
(14)
(15)
(16)
vC
VMAX Leff
(17)
s =
(18)
eff =
(19)
Allen and Holberg  CMOS Analog Circuit Design L = xd KAPPA (vDS vDS(sat)) when VMAX > 0 L = where ep = vC (vC + vDS(sat)) Leff vDS (sat) iDS 1 L ep xd 2
2 1/2
Page III.43
(20)
ep xd 2 2 2 (v + + KAPPA xd v (sat)) DS DS 2
1/2
(21)
(22)
iDS =
(21)
N F S is a parameter used in the evaluation of v on and can be extracted from measurements. The drain current in the weak inversion region, vGS less than von , is given as vGS  von iDS = iDS (von , vDE , vSB) e fast where iDS is given as (from Eq. (1), Sec. 3.4 with vGS replaced with von) 1 + fb v v iDS = BETAvon VT 2 DE DE (4)
(3)
Page III.44
Typical Model Parameters Suitable for SPICE Simulations Using Level3 Model (Extended Model). These Values Are Based upon a 0.8m SiGate Bulk CMOS nWell Process Parameter Parameter Typical Parameter Value Symbol Description NChannel PChannel Units VTO Threshold V 0.7 0.15 0.7 0.15 UO mobility 660 210 cm2/Vs DELTA Narrowwidth threshold 2.4 1.25 adjust factor ETA Staticfeedback threshold 0.1 0.1 adjust factor KAPPA Saturation field factor in 0.15 2.5 1/V channellength modulation THETA Mobility degradation factor 0.1 0.1 1/V NSUB Substrate doping cm3 3 1016 6 1016 TOX Oxide thickness 140 140 XJ Mettallurgical junction 0.2 0.2 m depth WD Delta width m LD Lateral diffusion 0.016 0.015 m NFS Parameter for weak 11 11 cm2 7 10 6 10 inversion modeling CGSO F/m 220 10 12 220 10 12 CGDO F/m 220 10 12 220 10 12 CGBO F/m 700 10 12 700 10 12 CJ F/m2 770 10 6 560 10 6 CJSW F/m 380 10 12 350 10 12 MJ 0.5 0.5 MJSW 0.38 0.35 NFS Parameter for weak cm2 7 1011 6 1011 inversion modeling
Page III.45
Temperature Dependence
The temperaturedependent variables in the models developed so far include the: Fermi potential, PHI, EG, bulk junction potential of the sourcebulk and drainbulk junctions, PB, the reverse currents of the pn junctions, IS, and the dependence of mobility upon temperature. The temperature dependence of most of these variables is found in the equations given previously or from wellknown expressions. The dependence of mobility upon temperature is given as T BEX UO(T) = UO(T0) T0 where BEX is the temperature exponent for mobility and is typically 1.5. vtherm(T) = KT q
T2 EG(T) = 1.16 7.02 104 T + 1108.0 EG(T0) T T EG(T) PHI(T) = PHI(T0) vtherm(T) 3 ln + T0 T0 vtherm(T0) vtherm(T) vbi (T) = vbi (T0) + PHI(T) PHI(T0) EG(T0) EG(T) + 2 2
VT0(T) = vbi (T) + GAMMA PHI(T) NSUB PHI(T)= 2 vtherm ln ni ( T ) ni(T) = 1.45 1016 T T0
3/2
1 T exp EG T0 1 2 v therm(T0)
For drain and source junction diodes, the following relationships apply. EG(T0) T T EG(T) PB(T) = PB vtherm(T) 3 ln + T0 T v ( T v 0 therm 0) therm(T) IS(T) = IS(T0) EG(T0) EG(T) T exp + 3 ln v ( T v ( T ) T N therm 0 therm 0)
Page III.31
Page III.32
Geometric Multiplier: M
To apply the unitmatching principle, use the geometric multiplier feature rather than scale W/L. This: M1 3 2 1 0 NCH W=20U L=1U is not the same as this: M1 3 2 1 0 NCH W=10U L=1U M=2 The following dual instantiation is equivalent to using a multiplier M1A 3 2 1 0 NCH W=10U L=1U M1B 3 2 1 0 NCH W=10U L=1U
(a)
(b)
Page III.33
MODEL Description
A SPICE simulation file for an MOS circuit is incomplete without a description of the model to be used to characterize the MOS transistors used in the circuit. A model is described by placing a line in the simulation file using the following format. .MODEL <MODEL NAME> <MODEL TYPE> <MODEL PARAMETERS> MODEL NAME e.g., NCH MODEL TYPE either PMOS or NMOS. MODEL PARAMETERS : LEVEL=1 VTO=1 KP=50U GAMMA=0.5 LAMBDA=0.01 SPICE can calculate what you do not specify You must specify the following surface state density, NSS, in cm2 oxide thickness, TOX, in meters surface mobility, UO, in cm2/Vs, substrate doping, NSUB, in cm3 The equations used to calculate the electrical parameters are
VTO = MS (2q si NSUB PHI)1/2 q(NSS) + + PHI (ox/TOX) (ox/TOX)
KP = UO
ox TOX
(2q si NSUB)1/2 (ox/TOX)
GAMMA = and
2kT NSUB PHI = 2F = q ln n i LAMBDA is not calculated from the process parameters for the LEVEL 1 model.
Page III.34
Other parameters:
IS: Reverse current of the drainbulk or sourcebulk junctions in Amps JS: Reversecurrent density in A/m2 JS requires the specification of AS and AD on the model line. If IS is specified, it overrides JS. The default value of IS is usually 1014 A. RD: Drain ohmic resistance in ohms RS: Source ohmic resistance in ohms RSH: Sheet resistance in ohms/square. RSH is overridden if RD or RS are entered. To use RSH, the values of NRD and NRS must be entered on the model line.
The drainbulk and sourcebulk depletion capacitors CJ: Bulk bottom plate junction capacitance MJ: Bottom plate junction grading coefficient CJSW: Bulk sidewall junction capacitance MJSW: Sidewall junction grading coefficient If CJ is entered as a model parameter it overrides the calculation of CJ using NSUB, otherwise, CJ is calculated using NSUB. If CBD and CBS are entered, these values override CJ and NSUB calculations. In order for CJ to result in an actual circuit capacitance, the transistor instance must include AD and AS. In order for CJSW to result in an actual circuit capacitance, the transistor instance must include PD and PS. CGSO: CGDO: AF: KF: GateSource overlap capacitance (at zero bias) GateDrain overlap capacitance (at zero bias) Flicker noise exponent Flicker noise coefficient
TPG: Indicates type of gate material relative to the substrate TPG=1 > gate material is opposite of the substrate TPG=1 > gate material is the same as the substrate TPG=0 > gate material is aluminum XQC: Channel charge flag and fraction of channel charge attributed to the drain
Page IV.01
Organization
Chapter 10 D/A and A/D Converters Chapter 11 Analog Systems
SYSTEMS
CIRCUITS
Chapter 5 CMOS Subcircuits SIMPLE Chapter 6 CMOS Amplifiers
DEVICES
Allen and Holberg  CMOS Analog Circuit Design I. Characterization of the Simple Transistor Model
Page IV.11
Determine V T0(V SB = 0), K', , and . Terminology: K'S for the saturation region K'L for the nonsaturation region
W eff (v GS  V T ) 2 (1 + v DS ) iD = K' S 2 L eff
(1)
(2) (3)
2 F  + v S B 
2 F 
Assume that vDS is chosen such that the vDS << 1 v SB =0 > V T = V T 0 . Therefore, Eq. (1) simplifies to
W eff (v GS  V T 0 ) 2 iD = K S 2 L eff 1/2 K' S W eff 1/2 1/2 K' S W eff iD = 2 L vGS  2L VT0 eff eff
(4)
x = v GS
Page IV.12
(9)
and
K' S W eff 1/2 b = VT0 2 L eff
(10)
Plot i D
1/2 1/2
Page IV.13
v DS > VDSAT ( iD )
1/2
KS Weff m= 2 L eff
1/2
b = VT 0
v GS (a)
vGS (b) Figure B.11 (a) iD1/2 versus vGS plot used to determine VT0 and K'S. (b) iD versus vGS plot to determine K'L.
Extract the parameter K'L for the nonsaturation region: v D S W eff W eff v DS v GS  K' L v DS V T + iD = K' L 2 L eff L eff Plot iD versus vGS as shown in Fig. B.11(b), the slope is seen to be 3
(11)
Allen and Holberg  CMOS Analog Circuit Design iD W eff vDS m = v = K' L L eff GS Knowing the slope, the term K'L is easily determined to be K' L = m
L eff W eff 1 vDS
Page IV.14
(12)
(13)
W eff, Leff, and vDS must be known. The approximate value o can be extracted from the value of K'L At this point, is unknown. Write Eq. (3) in the linear form where y = VT x= m= b = VT0 2F normally in the range of 0.6 to 0.7 volts. Determine VT at various values of vSB Plot VT versus x and measure the slope to extract Slope m, measured from the best fit line, is the parameter . 2 F  + v SB 2 F 
Page IV.15
(i D )
1/2
VT 0
VT 1 v GS
VT 2
VT 3
Figure B.12 iD1/2 versus vGS plot at different vSB values to determine .
VSB = 0 V
( vSB + 2 F )
0.5
( 2 F )
0.5
We still need to find , L, and W . should be determined for all device lengths that might be used. Rewrite Eq. (1) is as iD = i' D vDS + i' D
(18)
Allen and Holberg  CMOS Analog Circuit Design which is in the familiar linear form where y = iD (Eq. (1)) x = v DS m = i'D b = i'D (Eq. (4) with = 0)
Page IV.16
Plot iD versus v DS , and measure the slope of the data in the saturation region, and divide that value by the yintercept to get.
Calculating L and W. Consider two transistors, with the same widths but different lengths, operating in the nonsaturation region with the same vDS. The widths of the transistors are assumed to be very large so that W Weff. The largesignal model is given as
v K' L W eff DS iD = L ( v V ) v T 0 D S 2 eff G S 2
(23)
Page IV.17
(24)
The aspect ratios (W /L) for the two transistors are W1 L1 + L and W2 L2 + L
(25)
(26)
Implicit in Eqs. (25) and (26) is that L is assumed to be the same for both transistors. Combining Eq. (24) with Eqs. (25) and (26) gives K' L W (27) gm 1 = L + L v DS 1 and K' L W gm 2 = L + L v DS 2 (28)
where W 1 = W 2 = W (and are assumed to equal the effective width). With further algebraic manipulation of Eqs. (27) and (28), one can show that, L2 + L gm 1 = (29) gm1  gm2 L2  L1 which further yields (L 2  L 1) gm 1 L 2 + L = L eff = g m1  gm2 L2 and L1 known gm1 and gm2 can be measured Similarly for W eff : (W 1  W 2)g m 2 W 2 + W = W eff = g m1  gm2 (31) (30)
Equation (31) is valid when two transistors have the same length but different widths.
Page IV.18
One must be careful in determining L (or W ) to make the lengths (or widths) sufficiently different in order to avoid the numerical error due to subtracting large numbers, and small enough that the transistor model chosen is still valid for both transistors.
Page IV.31
II. Transistor Characterization for the Extended Model Equations (1) and (2) represent a simplified version of the extended model for a relatively wide MOS transistor operating in the nonsaturation, stronginversion region with VSB = 0.
sCoxW iD = L
v2 (v DS + v V ) v T DS 2 DS GS
2 F  (1)
where W and L are effective electrical equivalents (dropping the subscript, eff, for convenience).
s = o
(2)
Eq. (2) holds when the denominator term in the brackets is less than unity. Otherwise, o = s. To develop a procedure for extracting o, consider the case where mobility degradation effects are not being experienced, i.e., s = o, Eq. (1) can be rewritten in general as (3) iD = o f(C ox , W , L , v GS , V T , v DS , , 2 F ) This equation is a linear function of vGS and is in the familiar form of y = mx + b (4) where b = 0. Plot iD versus the function, f(Cox, W , L , v GS , V T , v DS , , 2  F ) and measure the slope = o. The data are limited to the nonsaturation region (small vDS ). The transistor must be in the stronginversion region (vGS > VT). The transistor must operate below the criticalmobility point.
Keep vGS as low as possible without encroaching on the weakinversion region of operation.
Page IV.32
Weakinversion region
Once o is determined, there is ample information to determine UCRIT and UEXP. Consider Eqs. (1) and (2) rewritten and combined as follows. iD = o[(UCRIT)f2]UEXPf1 where
v C ox W DS + v f1 = L ( v G S  V T ) v D S  DS 2 F  2 2 3 [( v DS + 2 F ) 1.5  (2 F )] 1.5 2
(5)
(1)
and
Page IV.33
si [ v GS  V T  (UTRA) v DS ] C o x
(7)
The units of f 1 and f 2 are FV2/cm2 and cm/V respectively. Notice that f 2 includes the parameter UTRA, which is an unknown. UTRA is disabled in most SPICE models. Equation (5) can be manipulated algebraically to yield log
iD = log( o) + UEXP[log(UCRIT)] + UEXP[log(f2)] (8) f1
By plotting Eq. (8) and measuring the slope, UEXP can be determined. The yintercept can be extracted from the plot and UCRIT can be determined by back calculation given UEXP, o, and the intercept, b.
Allen and Holberg  CMOS Analog Circuit Design III. Characterization of Substrate Bipolar Parameters of interest are: dc , and JS. For v BE >> kT/q, kT iC v BE = q ln JSA E and
Page IV.41
(1)
iE dc = i 1 (2) B AE is the crosssectional area of the emitterbase junction of the BJT. iE = iB ( dc + 1) Plot iB as a function of iE and measure the slope to determine dc. Once dc is known, then Eq. (1) can be rearranged and modified as follows. k T iE d c kT kT kT v BE = q ln i ) ln( J A ) = ln( dc E S E q q q 1 + d c ln( JSAE) Plotting ln[iE dc/(1 + dc)] versus vBE results in a graph where kT m = slope = q and b = yintercept =
k T ln(JSA E ) q
(3)
(5)
(6)
Allen and Holberg  CMOS Analog Circuit Design IV. Characterization of Resistive Components
Page IV.51
Resistors Contact resistance Characterize the resistor geometry exactly as it will be implemented in a design. Because sheet resistance is not constant across the width of a resistor the effects of bends result in inaccuracies termination effects are not accurately predictable Figure B.51 illustrates a structure that can be used to determine sheet resistance, and geometry width variation (bias). Force a current into node A with node F grounded while measuring the voltage drops across BC (Vn) and DE (Vw), the resistors Rn and Rw can be determined as follows Vn Rn = (1) I Rw = Vw I (2)
(3)
RS = Rw where
(3)
Rn = resistance of narrow resistor ( ) Rw = resistance of wide resistor () R S = sheet resistance of material (polysilicon, diffusion etc. /square) Ln = drawn length of narrow resistor 1
Allen and Holberg  CMOS Analog Circuit Design Lw = drawn length of wide resistor W n = drawn width of narrow resistor W w = drawn width of wide resistor
Page IV.52
Ln B C D
Lw E
Solving equations (3) and (4) yields W n  k Ww Bias = 1  k where RwLn k=R L n w and RS = Rn
W n  Bias W w  Bias = Rw Ln Lw
(5)
(6)
(7)
Allen and Holberg  CMOS Analog Circuit Design Determining sheet resistance and contact resistance
Page IV.53
10 squares
RA=220
20 squares
RB=420
R A = R 1 + 2R c ; and
R1 = N 1RS
(8) (9)
R B = R 2 + 2R c ; R2 = N 2RS N1 is the number of squares for R1 RS is the sheet resistivity in /square Rc is the contact resistance. RB  RA RS = N  N 2 1 and 2Rc = RA N 1RS = RB N 2RS
(10)
(11)
Allen and Holberg  CMOS Analog Circuit Design Voltage coefficient of lightlydoped resistors
V1 V2 IR IR V1 V2 V1 + V2 2
Page IV.54
R=
VBIAS =
27.0 26.5
Resistance (k)
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Back bias (volts) Figure B.54 Nwell resistance as a function of backbias voltage
Page IV.55
Metal pads
Diffusion or polysilicon
Pad 3
Pad 4
Metal pads
Pad 2
Pad 1
RC
R RC Pad 4 R RC Pad 3 RM RM
Pad 2
Allen and Holberg  CMOS Analog Circuit Design V. Characterization of Capacitance MOS capacitors CGS, CGD, and CGB Depletion capacitors CDB and CSB
Page IV.51
Interconnect capacitances Cpolyfield, Cmetalfield, and Cmetalpoly (and perhaps multimetal capacitors SPICE capacitor models C GS0, C GD 0, and C GB0 (at V GS = V GB = 0). Normally SPICE calculates CDB and CSB using the areas of the drain and source and the junction (depletion) capacitance, CJ (zerobias value), that it calculates internally from other model parameters. Two of these model parameters, MJ and MJSW , are used to calculate the depletion capacitance as a function of voltage across the capacitor.
Page IV.52
CGS0 and CGD0, are modeled in SPICE as a function of the device width, while the capacitor CGB0 is per length of the device Measure the CGS of a very wide transistor and divide the result by the width in order to get CGS0 (per unit width).
Source
Drain Gate
Source
Cmeas = W(n)(CGS0 + CGD 0) where Cmeas = total measured capacitance W = total width of one of the transistors n = total number of transistors
(1)
Page IV.53
For very narrow transistors, the capacitance determined using the previous technique will not be very accurate because of fringe field and other edge effects at the edge of the transistor. In order to characterize CGS 0 and CGD0 for these narrow devices, a structure similar to that given in Fig. B.61 can be used, substituting different device sizes. Such a structure is given in Fig. B.63. The equations used to calculate the parasitic capacitances are the same as those given in Eq. (1).
Polysilicon gate
Drain
Source
Drain
Source
Figure B.63 Structure for measuring CGS and CGD, including fringing effects, for transistors having small L.
Page IV.54
Drain
Diffusion source
CGB
Cpolyfield
This capacitance is approximated from the interconnect capacitance Cpolyfield (overhang capacitor is not a true parallelplate capacitor) Cmeas (F/m2 ) (2) Cpolyfield = L W R R where Cmeas = Cmeas = measured value of the polysilicon strip LR = length of the centerline of the polysilicon strip WR = width of the polysilicon strip (usually chosen as device length) Having determined Cpolyfield, CGB0 can be approximated as CGB 0 2 ( Cpolyfield)(doverhang) = 2C 5 (F/m) where doverhang = overhang dimension (see Rule 3D, Table 2.61) (3)
Allen and Holberg  CMOS Analog Circuit Design C BD and C BS VJ CJ(VJ) = ACJ(0) 1 + PB where VJ = the reverse bias voltage across the junction CJ(VJ) = bottom junction capacitance at VJ CJSW(VJ) = junction capacitance of sidewall at VJ A = area of the (bottom) of the capacitor P = perimeter of the capacitor MJ VJ + PCJSW(0)1 + PB
Page IV.55
MJSW (4)
PB = bulk junction potential The constants CJ and MJ can be determined by measuring a large rectangular capacitor structure where the contribution from the sidewall capacitance is minimal. For such a structure, CJ(VJ) can be approximated as VJ MJ 1 + PB (5) CJ(VJ) = ACJ(0) This equation can be rewritten in a way that is convenient for linear regression. VJ log[CJ(VJ)] = (MJ)log 1 + PB + log[ACJ(0)] (6)
Plotting log[CJ(VJ)] versus log[1 + VJ/PB] and determine the slope, MJ, and the Y intercept (where Y is the term on the left), Log[ACJ(0)]. Knowing the area of the capacitor, the calculation of the bottom junction capacitance is straightforward.
Page V.01
V. CMOS SUBCIRCUITS
Contents V.1 V.2 V.3 V.4 V.5 MOS Switch MOS Diode MOS Current Source/Sinks Current Mirrors/Amplifiers Reference Circuits V.51 Power Supply Dependence V.52 Temperature Dependence Summary
V.6
Organization
Chapter 10 D/A and A/D Converters Chapter 11 Analog Systems
SYSTEMS
CIRCUITS
Chapter 5 CMOS Subcircuits SIMPLE Chapter 6 CMOS Amplifiers
DEVICES
Page V.02
WHAT IS A SUBCIRCUIT? A subcircuit is a circuit which consists of one or more transistors and generally perfoms only one function. A subcircuit is generally not used by itself but in conjunction with other subcircuits. Example Design hierarchy of analog circuits illustrated by an op amp.
Operational Amplifier Complex Circuits Simple Circuits Biasing Circuits Input Differential Amplifier Second Gain Stage Output Stage
Current Source
Current Mirror
Current Sink
Diff. Amp.
Mirror Load
Inverter
Page V.11
Nonideal Switch
CAB
IOFF
+ C +
B
CBC RB
A
CAC RA VControl
Page V.12
C (G)
On Characteristics of A MOS Switch Assume operation in nonsaturation region (vDS < vGS  V T). v D S KW iD = L (v G S  V T )  2 vDS iD KW v G S V T v D S vDS = L Thus,
vDS 1 RON = i = KW D (v G S V T v D S ) L
OFF Characteristics of A MOS Switch If vGS < VT, then iD = I OFF = 0 when vDS 0V. If vDS > 0, then 1 1 ROFF i = I DS OFF
Page V.13
MOS SWITCH VOLTAGE RANGES Assume the MOS switch connects to circuits and the analog signal can vary from 0 to 5V. What are the voltages required at the terminals of the MOS switch to make it work properly?
The bulk voltage must be less than or equal to zero to insure that the bulksource and bulkdrain are reverse biased. The gate voltage must be greater than 5 + VT in order to turn the switch on. Therefore, VBulk 0V V G 5 + VT (Remember that the larger the value of VSB , the larger VT)
Page V.14
IV CHARACTERISTICS OF THE MOS SWITCH SPICE ON Characteristics of the MOS Switch
100A V1 =10V
V1 Id
60A
V2
20A Id 20A V1=2V V1=3V V1=4V 60A V1 =5V 100A 1V V1 =6V
5
0.6V
0.2V V2
0.2V
0.6V
1V
Page V.15
MOS SWITCH ON RESISTANCE AS A FUNCTION OF VGS SPICE ON Resistance of the MOS Switch
100k
W/L = 3m/3m MOS Switch On Resistance 10k W/L = 15m/3m W/L = 30m/3m 1k W/L = 150m/3m
100 1.0V
1.5V
2.0V
4.0V
4.5V
5.0V
Page V.16
INFLUENCE OF SWITCH IMPERFECTIONS ON PERFORMANCE Finite ON Resistance Nonzero charging and discharging rate.
1
VSS
CHold
Page V.17
EXAMPLES 1. What is the on resistance of an enhancement MOS switch if VS = 0V, VG = 10V, W/L = 1, VTO = 1V, and K' = 25A/V2? Assume that vDS 0V. Therefore, vDS L/W RON = iD K'(VGV S V T) RON = 106 25(101) = 4444 VG 2. If V G=10V at t=0, what is the W/L value necessary to discharge C1 to with 5% of its intial charge at t=0.1S? Assume K'=25A/V2 and V TO = 1V. v(t) = 5exp(t/RC) 107 107 = 20 RC = exp RC ln(20) 10 Therefore, R = 6 x 103 Thus, 10x103 L/W L/W = = 6 K'(VGV SV T) (2.5x105)(9) 5V +  C1=20pF C2=10pF + 
W Gives L = 2.67
Page V.18
INFLUENCE OF PARASITIC CAPACITANCES MOSFET Model for Charge Feedthrough Analysis Distributed Model
G CGDO D RCH CGSO S CGC=Cox
Cox 2
Cox 2
CGSO = Voltage independent (1storder), gatesource, overlap cap. CGDO = Voltage independent (1st order), drainsource overlap cap. CGC = Gatetochannel capacitance (C ox) RCH = Distributed draintosource channel resistance
Page V.19
vIN

CHold
Case 1  Slow Fall Time: Gate is inverted as vG goes negative . Channel time constant small enough so that the charge on CHold is absorbed by vIN. When gate voltage reaches vIN+VT, the device turns off and feedthru occurs via the overlap capacitance. Case 2  Fast Fall Time: Gate is inverted as vG goes negative. Fall rate is faster than the channel time constant so that feedthru occurs via the channel capacitance onto CHold which is not absorbed by v IN. Feedthru continues when vG reaches vIN+VT. Total feedthru consists of that due to both the channel capacitance and the overlap capacitances. Other Considerations: Source resistance effects the amount of charge shared between the drain and the source. The maximum gate voltage before negative transition effects the amount of charge injected.
Page V.110
Intuition about Fast and Slow Regimes To develop some intuition about the fast and slow cases, it is useful to model the gave voltage as a piecewise constant waveform (a quantized waveform) and consider the charge flow at each transition as illustrated below. In this figure, the range of voltage at CL illustrated represent the period while the transistor is on. In both cases, the quantized voltage step is the same, but the time between steps is different. The voltage accross CL is observed to be an exponential whose time constant is due to the channel resistance and channel capacitance and does not change from fast case to slow case.
vCL
V vGATE
Voltage
Time (d)
Voltage
Time (e) Figure 4.110 (a) Illustration of slow ramp and (b) fast ramp using a quantized voltage ramp to illustrate the effects due to the time constant of the channel resistance and capacitance.
Page V.111
CGD + 
C1
vC1
CGS and CGD result in clock feedthrough CBS and CBD cause loading on the desired capacitances Clock Feedthrough Assume slow fall and rise times
1 1 Switch ON Switch OFF 1
Clock signal couples through CGD on the rising part of signal when switch is off, but V IN charges C1 to the right value regardless.
CGD + 
Clock signal couples through CGD on the falling part of the signal when the switch is off.
C1
vC1
Page V.112
EXAMPLE regime)
Switched
Capacitor
Integrator
(slow
clock
edge
1
M1
2
M2
C2 +
vOUT 
assuming:
CGS1=CGS2=CGD1=CGD2 = CG
At t3, additional charge has been added due to CGS overlap of M2 as 2 goes positive. Note that M2 has not turned on yet.
CG V C1 (t2t3) = C +C VT G 1
Page V.113
+ Once M2 turns on (at t3 ), all of the charge on C1 is transferred to C2. CG C1 C1 VO = VC1 = V IN 1 C1+CG C2 C2 + Between times at t3 and t4 additional charge is transferred to C1 from the channel capacitance of M2. VO (t3t4)=
Cch (Vclk V T) C2
The final change in Vout is: CG C1 Cch V O = V IN 1 (Vclk V T) C2 C1+CG C2 Ideally the output voltage change is VIN feedthrough is:
C1 CG Cch V O (error) = VIN (Vclk V T) C2 C1+CG C2 C1 so the error due to charge C2
Page V.114
Consider the gate voltage traversing from VH to VL (e.g., 5.0 volts to 0.0 volts, respectively) described in the time domain as v G = V H Ut When operating in the slow regime defined by the relationship (3)
V HT 2CL >> U
where VHT is defined as V HT = V H V S V T
(4)
(5)
the error (the difference between the desired voltage V S and the actual voltage, VCL) due to charge injection can be described as
Page V.115
W C G D 0 V error = CL
2
C c h 2
U CL W C G D 0 + (V S + V T V L ) 2 CL
(6)
V HT 2CL << U
the error voltage is given in Eq. (8) below as C ch W CGD0 + 2 V error = V CL H T
(7)
V HT WCGD0 6 U C + C (V S + V T V L ) L L
3
(8)
The following example illustrates the application of the chargefeedthrough model given by Eqs. (3) through (8). Example 4.11 Calculation of charge feedthrough error
Calculate the effect of charge feedthrough on the circuit shown in Fig. 4.19 where Vs = 1.0 volts, CL = 200 fF, W/L = 0.8m/0.8m, and VG is given for two cases illustrated below. Use model parameters from Tables 3.12 and 3.21. Neglect L and W effects.
vG
Case 2
Case 1 0
0.2 ns 10 ns Time
Case 1: The first step is to determine the value of U in the expression vG = VH  Ut For a transition from 5 volts to 0 volts in 0.2 ns, U = 25 109 In order to determine operating regime, the following relationship must be tested.
Page V.116
2 2 VHT VHT 2CL >> U for slow or 2CL << U for fast Observin g that there is a backbias on the transistor switch effecting VT, VHT is VHT = VH  VS  VT = 5  1  0.887 = 3.113 giving 2 VHT 110106 3.1132 = 2.66 109 << 25 109 thus fast regime. 2C L = 2 200f Applying Eq. (8) for the fast regime yields 1.581015 1761018 + 3.32103 1761018 2 Verror = (5 + 0.887  0) 3.113 + 2001015 30103 2001015 Verror = 19.7 mV Case 2: The first step is to determine the value of U in the expression v G = VH  Ut For a transition from 5 volts to 0 volts in 10 ns, U = 5 108 thus indicating the slow regime according to the following test 2.66 109 >> 5 108 1.581015 1761018 + 2 Verror = 2001015 Verror = 10.95 mV 314106 1761018 + (5 + 0.887  0 ) 220106 2001015
Page V.117
POSSIBLE SOLUTIONS TO CLOCK FEEDTHROUGH 1.) Dummy transistor (MD) W1 L1 M1 VSS MD VSS WD = W1 LD 2L1
Complete cancellation is difficult. Requires a complementary clock. 2.) Limit the clock swing when one terminal of the switch is at a defined potential. vG 0V C + vin > 0 vG 3VT 2VT VT t ON OFF ON
VSS
+ vout 
Page V.118
VSS VDD
Advantages 1.) Larger dynamic range. 2.) Lower ON resistance. Disadvantages 1.) Requires complementary clock. 2.) Requires more area.
Page V.119
DYNAMIC RANGE LIMITATIONS OF SWITCHES Must have sufficient vGS to give a sufficiently low on resistance Example: VDD
50 2
A + VAB 3k Switch On Resistance 2.5k 2k 1.5k 1k 0.5k 0k 0V 1V 2V VDD = 4V VDD = 4.5V VDD = 5V
B VDD
50 2
1 A
VAB
3V
4V
5V
SPICE File:
Simulation of the resistance of a CMOS transmission switch M1 1 3 2 0 MNMOS L=2U W=50U M2 1 0 2 3 MPMOS L=2U W=50U .MODEL MNMOS NMOS VTO=0.75, KP=25U,LAMBDA=0.01, GAMMA=0.5, PHI=0.5 .MODEL MPMOS PMOS VTO=0.75, KP=10U,LAMBDA=0.01, GAMMA=0.5, PHI=0.5 VDD 3 0 VAB 1 0 IA 2 0 DC 1U .DC VAB 0 5 0.02 VDD 4 5 0.5 .PRINT DC V(1,2) .END
Page V.120
Brooklyn Bridge Effect If Nchannel and Pchannel devices are resistively scaled (i.e., sized to have the same conductance at equivalent terminal conditions) the resistance versus voltage (common mode) will appear as shown below.
280 270
5v
260
250
5v
Id
Page V.121
CPump
M4
M6 +
M7
M8
M2
B
M3 M5
VDBL CHold
B A B

VSS
A B
Operation: 1. A low, B high  C Pump is charged to VDDVSS. 2. A high, B low  CPump transfers negative charge to CHold VDBL 0.5 V DD  V S S 3. Eventually, VDBL approaches the voltage of VDD + VSS. If VDD =  VSS, then VDBL  2VDD.
Page V.122
SUMMARY OF MOS SWITCHES Symmetrical switching characteristics High OFF resistance Moderate ON resistance (OK for most applications) Clock feedthrough is proportional to size of switch (W) and inversely proportional to switching capacitors. Complementary switches help increase dynamic range. As power supply reduces, switches become more difficult to fully turn on. Switches contribute a kT/C noise which folds back into the baseband.
Page V.21
+ v 
When the drain is connected to the gate, the transistor is always saturated. vDS v GS  VT v D  vS v G  vS  VT vDG V T where V T > 0 Large Signal
IV Characteristics i AC DC
Small signal
i G + v S gm v gmbs vbs rds S D
v = vDS = vGS = VT +
2iD
1 1 = g +g g M DS M
Page V.22
VOLTAGE DIVISION USING ACTIVE RESISTORS Objective : Derive a voltage Vout from VSS and VDD
VDD M2 Vout M1 VSS
If VDD = VSS = 5 volts, Vout = 1 volt, and ID1 = ID2 = 50 amps, then use the model parameters of Table 3.12 to find W/L ratios. iD1 = ( vGS  VT ) 2 2 1 = 4.0 A/V2 2 = 11.1 A/V2 K'n = 17 A/V2 K'p = 8 A/V2 1 then ( W/L )1 = 4.25 and ( W/L )2 = 1.34
Page V.23
I = 2(VC  VT)vDS
1 R = 2 (V  V ) C T
Page V.24
+
VGS
M1 S R VSS M2 vDS + D i G
+
VGS
S M2B
M2A
G i
Page V.25
+ i D2 i2 G2 + v i
D1 i1
r ac
VSS
M2 S2
VC 
1mA
I(VSENSE)
0
1mA
2mA
2
1
VDS
NMOS parallel transistor realization M1 2 1 0 5 MNMOS W=15U L=3U M2 2 4 0 5 MNMOS W=15U L=3U .MODEL MNMOS NMOS VTO=0.75, KP=25U, LAMBDA=0.01, GAMMA=0.8 PHI=0.6 VC 1 2 E1 4 0 1 2 1.0 VSENSE 10 2 DC 0 VDS 10 0 VSS 5 0 DC 5 .DC VDS 2.0 2.0 .2 VC 3 7 1 .PRINT DC I(VSENSE) .PROBE .END
Page V.26
M3A
+ V C
M3B
 60uA
 100uA
4
3
2
1
0 1 VAB
PChannel Extended Range Active Resistor M1A 3 4 5 10 MPMOS W=3U L=3U M1B 3 6 5 10 MPMOS W=3U L=3U M2A 10 3 4 4 MNMOS W=3U L=3U M2B 10 5 6 6 MNMOS W=3U L=3U M3A 4 7 0 0 MNMOS W=3U L=3U M3B 6 7 0 0 MNMOS W=3U L=3U VSENSE 1 3 DC 0V VC 7 0 VAB 1 5 VDD 10 0 DC 5V .MODEL MNMOS NMOS VTO=0.75, KP=25U + LAMBDA=0.01, GAMMA=0.8 PHI=0.6 .MODEL MPMOS PMOS VTO=0.75 KP=8U +LAMBDA=0.02 GAMMA=0.4 PHI=0.6 .DC VAB 4.0 4.0 0.2 VC 2 5 1 .PRINT DC I(VSENSE) .PROBE .END
Page V.27
VC Assume the MOSFET's are in the nonsaturation region 1 i1 = (V C  v 2 V T )(v 1  v 2 )  2 (v 1  v 2 ) 2 1 i2 = (V C  v 2 V T )(v 1  v 2 )  (v 1  v 2 ) 2 2 Rewrite as 1 i1 = (V C  v 2 V T )(v 1  v 2 )  (v 1 2  2v 1 v 2 + v 2 2 ) 2 1 i2 = (V C  v 2 V T )(v 1  v 2 )  (v 1 2 + 2v 1 v 2 + v 2 2 ) 2 1 i1  i2 = (V C v 2 V T )(2v 1 )  (v122v1v2+v22v122v1v2v22) 2 i1  i 2 = 2 [ (VC  VT)v1  2v1v2 + 2v1v2 ] 2R = or R= v1 V C  V T 1 W 2K L (VCVT) v1(v1) 2v1 2v1 1 = = = i1i2 2(VCVT)v1 (VCVT) i1i2
Page V.28
r ac/2 v2 v1
i1 v2 VCC v2
VC= 7V
0.6mA 6V 5V 4V 0.2mA
ID(M1)
3V
 0.2mA
 0.6mA
 1.0mA
2
1
V1 Single MOSFET Differential Resistor Realization M1 1 2 3 4 MNMOS1 W=15U L=3U M2 5 2 3 4 MNMOS1 W=15U L=3U VC 2 0 VCC 4 0 DC 5V V1 1 0 E1 5 0 1 0 1 .MODEL MNMOS1 NMOS VTO=0.75 KP=25U +LAMBDA=0.01 GAMMA=0.8 PHI=0.6 .DC V1 2.0 2.0 0.2 VC 3 7 1 .PRINT DC ID(M1) .PROBE .END
Page V.29
The Double MOSFET Differential Resistor VC1 v1 iD2 iD1 i1 v1 v2 i2 R R v + VC2 v iD3 v2 VC1 i2 1 iD1 = (V C1 vV T )(v1 v)  2(v1v)2 1 iD2 = (V C2 vV T )(v1 v)  (v1v)2 2 1 iD3 = (V C1 vV T )(v2 v)  (v2v)2 2 1 iD4 = (V C2 vV T )(v2 v)  (v2v)2 2 1 1 i1=iD1+iD3=(VC1vVT)(v1v) (v1v)2+(VC2vVT)(v2v) (v2v)2 2 2 1 1 i2=iD2+iD4=(VC2vVT)(v1v) (v1v)2+(VC1vVT)(v2V) (v2v)2 2 2 i1  i 2 = [(VC1vVT)(v 1v) + (VC2vVT)(v 2v)  (V C2vVT)(v1 v)  (VC1vVT)(v2v)] = [v1(VC1VC2) + v 2(VC2VC1)] = (VC1VC2)(v1v2) v1v2 v1v2 1 = = i1i2 (VC1VC2)(v1v2) KW (VC1VC2) L 1 v1 ,v 2 min [(V C1VT),(VC2VT)] R i n = KW (VC1VC2) L Rin = iD4 v v + i1
or
Page V.210
DoubleMOSFET, Differential Resistor Realization VC1 iD1 v1 i1 v1 v2 i2 r ac/2 v4 R r ac/2 v3 VC2 iD3 iD4 v2
M4 M3 M1
i1 v3
iD2
VSS
M2
VSS i2 v4
Double MOSFET Differential Resistor Realization M1 1 2 3 4 MNMOS1 W=3U L=3U M2 1 5 8 4 MNMOS1 W=3U L=3U M3 6 5 3 4 MNMOS1 W=3U L=3U M4 6 2 8 4 MNMOS1 W=3U L=3U VSENSE 3 8 DC 0 VC1 2 0 DC 7V VC2 5 0 VSS 4 0 DC 5V V12 1 6 .MODEL MNMOS1 NMOS VTO=0.75 KP=25U +LAMBDA=0.01 GAMMA=0.8 PHI=0.6 .DC V12 3 3 0.2 VC2 2 6 1 .PRINT DC I(VSENSE)) .PROBE .END
3
2
1
V1V2
Page V.211
Restrictions vBULK < Min (vS, v D) v (VC  VT) v1 < VC  VT vBULK < v1 Differential around v1 v1, v2 < min(VC1VT, VC2VT) vBULK < min(v1,v2) Transresistance only
Good
VC or W/L
Page V.31
VDD iD iD VGG +
v
VG = V GG
vMIN
VDD VGG iD +
v
iD
VG = V GG
0 0
vMIN VDD
Page V.32
D G S B
G + vgs S
gm =
2K'WID L gm 2 2 F + V BS 
gmbs =
1 1 r ds g = I ds D
Page V.33
vout

r

Loop equation: vout = [iout  (g m2vgs2 + gmbs2vbs2)]r ds2 + iout r But, v gs2 = vs2 and vbs2 =  vs2. vout = [iout + gm2vs2 + gmbs2vs2]rds2 + iout r Replace vs2 by i outrvout = iout [ rds2 + gm2 rds2r + gmbs2rds2r + r ] Therefore, rout = rds2 + r [1 + gm2 rds2 + gmbs2rds2] MOS Small Signal Simplifications Normally, g m 10g mbs 100g d s Continuing rout rgm2 rds2 r out r x (voltage gain of M2 from source to drain)
Page V.34
Circuit
IREF
SmallSignal Model iOUT + M2 vOUT gmbs2vbs2 gm2vgs2 + vS2 r ds2 vout r ds1 gm1vgs1 iout +
M4
M3 M1
vout = [iout  (g m2vgs2 + g mbs2vbs2)]rds2 + ioutrds1 vout = iout[rds2 + gm2rds2r(1 + 2) + rds1] rout = rds2 + r[1 + g m2rds2(1 + 2)] r ds1gm2rds2(1 + 2)
Note : v MIN = VT + 2VON 0.75 + 1.5 = 2.25 (assuming V ON VT)
NMOS Cascode1mA Slope = 1/R o 0.75mA iO 0.5mA 0.25mA 0mA 0V VMIN 2V 4V vO 6V + vGS2 iO + vO
+ vGS1  8V 10V
Page V.35
iD2 +
vGS2
vGS2
M2
M1
M2
+
vGS1
iD1
S = W/L
M1 
Assume that M1 and M2 are matched but may not have the same W/L ratios. 1). If vGS1 = vGS2, then iD1 = (S1/S2)iD2 a). v GS1 may be physically connected together , or b). v GS1 may be equal to vGS2 by some other means. 2). If i D1 = iD2, then a). vGS1 = VT +
S2/S1(vGS2  VT) , or
b). If S1 = S2 and VS1 V S2 then vGS1 = vGS2 Strictly speaking, absolute matching requires that vDS be equal for two matched devices.
Page V.36
Reduction of VMIN or VOUT (sat) HighSwing Cascode Method 1 for Reducing the Value of vOUT(sat)
IREF 2VT + 2VON IOUT + IOUT
VOUT(sat)
M4
+ VT + VON 
M2 M1
M3
+ VT + VON 
VT + 2VON
vGS = VON + VT =
ID
VT
VT+VON
vGS
Page V.37
Circuit Which Reduces the Value of Vout(sat) of the Cascode Current Sink
iREF
iREF
iout
M6
1/4
M4
+
1/1 1/1
+
VT + 2VON
+
VT + VON 2VT + 3VON
M2
vOUT
M3
+
VT + VON VT + 2VON 1/1 1/1
+
VON
M1
M5
1/1
+
VT + VON
iOUT
iD vOUT(sat) ID
W=1 L 1
W =1 L 4
2V ON
vOUT
vGS VT
VT + VON VT + 2VON
K'W iD = 2 (v  VT ) 2 L GS
K'W 2 2 L (V ON )
Page V.38
iREF
iREF
iO
M5 +
1/4
M4
VT + VON
M1 +
1 VT + VON
M2
1
+
VON
Assume (W/L)1 = (W/L)2 = (W/L)4 = 4(W/L)5 values are identical and ignore bulk effects. Let I = IO REF VGS1 = 2I REF + VT = VON + VT W1 K L 1 2I REF + VT W5 K L 5
and V GS5 =
V GS5 =
+ V T = 2 VON + VT
Page V.39
Since V GS3 = VGS4 = VON +VT VDS1 = V DS2 = V ON which gives a minimum output voltage while keeping all devices in saturation of v M I N = 2 VO N Output Plot:
1000A
750A ID(M4)
500A 250A
0A 0V
1V
2V VOUT
3V
4V
5V
Page V.310
iREF
V T + 2VON
iO
1
VT
+ M3 1 +
V T + VON 1/4
M5 +
M4 M2
VT + V ON
+
VON
M1 +
1 V T + V ON
+
V ON
What is the purpose of M3? The presence of M3 forces the VDS1 = VDS2 which is necessary to guarantee that M1 and M2 act alike (e.g., both will have the same VT).
Page V.311
iD3 vGS3
vOUT
M2 
Iout
M1
vDS3
Principle of operation: As v OUT decreases, M3 will enter the nonsaturation region and iOUT will begin to decrease. However, this causes a decrease in the gatesource voltage of M4 which causes an increase in the gate voltage of M3. The minimum value of vOUT is determined by the gatesource voltage of M4 and Vdsat of M3. Assume that all devices are in saturation. 2IB2 K'(W/L)4 + 2Iout K'(W/L)3 + VT4
vOUT(min) =
Page V.312
CMOS REGULATED CASCODE CURRENT SOURCE  CONT. Small Signal Model r ds3 iout
+ vgs3 +
gm3vgs3 r ds2
RB2
r ds4
gm4vgs4
vgs4

vout

iout = gm3vgs3 + g ds3(vout  v gs4) vgs4 = ioutrds2 vgs3 = vg3  vs3 = gm4(rds4RB2)v gs4  vgs4 = rds2[1 + gm4(r ds4RB2)]iout iout = gm3rds2 [1 + gm4(rds4 RB2)]iout + g ds3 vout  gds3 rds2 iout Solving for vout, vout = rds3[1 + gm3rds2 + gds3rds2 + gm3rds2gm4(r ds4RB2)]iout vout rout = i = rds3[1 + gm3rds2 + gds3rds2 + gm3rds2gm4(r ds4RB2)] out g m 2r3 r out = r ds3 g m3 r ds2 g m4 (r ds4 R B2 ) = 2 Example K' N = 25 A/V2, = 0.01, IB1 = IB2 = 100A, all transistors with minimum geometry (W = 3m, L=3m), and RB2 = rds, we get rds = 1M and gm = 70.7mho rout (1M)(70.7mho)((1M)(70.7mho)(1M1M)= 2.5G!!!
Page V.313
iOUT 80A
60A 40A 20A 0A 0 1 2
.END
Page V.314
Page V.41
Rout iO + vO 
iI + vI Ideally, iO = A I iI Rin 0
MIRROR/ AMPLIFIER
Rout
Graphical Characterization iI II
slope = 1/Rin
iO slope = 1/Rout IO
vMIN
INPUT iO
vI
vMIN
OUTPUT
vO
AI 1
iI
TRANSFER
Page V.42
iO + + vGS M2
iO
+ vDS1 M1 
vDS2 
If vDS1 = vDS2, W 2L 1 iO iI = W1L2 Therefore the sources of error are: 1). v DS1 vDS2 2). M1 and M2 not matched ( and VT)
Page V.43
iI + vDS1 M1
iO
M2
DS1
v SS
Ratio error (%) versus drain voltage difference Used to measure iO 1+ v D S 2 S1 = iI 1+ v D S 1 S2 If S 1 = S 2, v DS2 = 10V, vDS1 = 1V, and i O/iI = 1.501, then iO 1+10 = 1.501 = iI 1+ 0.5 > = 8.5 = 0.059
Ratio Error
+ vGS 
( 1 + v
+ v DS2 
1 + v DS2
Page V.44
iD2 +
vGS2
M1
M2
and
= 2  1
VT = V T2  V T1 and 1 = 
Thus,
VT VT 2 iO 1+ 1+ 1 1 iI 2 2 2(vGSVT) 2(v GSVT) 2VT iO iI 1 +  (v GS  V T ) , V T 5% , (v = 10% GS  V T ) iO iI 1 0.05  ( 0.2) = 1 0.15 = 1 0.25 if and VT are correlated
Page V.45
iO  1)100% iI
RATIO ERROR (
VT(mV)
Page V.46
iI
M1 M2
iO M2
V SS
VSS
Layou
iI
iO
M2 a M2 b M2 c M2 d M2 e
M1
M2 a
M2 b
M2 c
M2 d
M2 e
M1
VSS
VSS
Page V.47
Practical Current Mirrors/Amplifiers Simple mirror Cascode current mirror Wilson current mirror Simple Current Mirror 60uA iI = 60uA iI = 50uA 40uA iI = 40uA iI = 30uA iI = 20uA iI = 10uA
Current mirrors and amplifiers .MODEL MNMOS1 NMOS VTO=0.75 KP=25U +LAMBDA=0.01 GAMMA=0.8 PHI=0.6 M1 1 1 0 0 MNMOS1 W=3U L=3U M2 3 1 0 0 MNMOS1 W=3U L=3U IIN 0 1 VOUT 3 0 .DC VOUT 0 5 0.1 +IIN 0 60U 10U .PRINT DC ID(M2) .PROBE .END
iOUT
20uA
0 0 1 2 3 4 5
vOUT
iI
3u 3u M1 3u 3u M2
iO
+
vO

Page V.48
iI M3
iOUT
60uA
M4
40uA
iOUT
20uA
M1
VSS
M2
0 0 1 2
vOUT
Example of Small Signal Output Resistance Calculation ii io + v3 + rds3 gm3 v3 v1 =v3 =0 + v1 + rds1 gm1 v1 v2 rds2 gm2 v1 v4 rds4 gm4 (v3 +v1 v2 ) io gmbs v2 vo +
vo = v4 + v2 = rds4 [i o  gm4(v 3 + v1  v2) + gmbs4v2] + rds2(io  gm2v1) v 2 = iords2 v o = io [rds4 + (gm4 rds2)rds4 + (rds2gmbs4)rds4 + rds2] vo 4). rout = io = rds4 + rds2 + rds2rds4(gm4 + gmbs4 )
Page V.49
iI
M3
iO
65.5uA
45.0uA
M1 M2
iO
22.5uA
VSS
0 0
Wilson Current Source M1 1 2 0 0 MNMOS W=15U L=3U M2 2 2 0 0 MNMOS W=15U L=3U M3 3 1 2 0 MNMOS W=15U L=3U R 1 0 100MEG .MODEL MNMOS NMOS VTO=0.75, KP=25U, +LAMBDA=0.01, GAMMA=0.8 PHI=0.6 IIN 0 1 VOUT 3 0 .DC VOUT 0 5 0.1 IIN 10U 80U 10U .PRINT DC V(2) V(1) ID(M3) .PROBE .END
vOUT
Principle of Operation: Series negative feedback increase output resistance 1. Assume input current is constant and that there is high resistance to ground from the gate of M3 or drain of M1. 2. A positive increase in output current causes an increase in vGS2 . 3. The increase in vGS2 causes an increase in vGS1 . 4. The increase in vGS1 causes an increase in iD1. 5. If the input current is constant, then the current through the resistance to ground from the gate of M3 or the drain of M1 decreases resulting in a decrease in vGS3. 6. A decrease in v GS3 causes a decrease in the output current opposing the assumed increase in step 2.
Page V.410
iin=0
v3
+ v1 
gm3(v1v2)
+ v2 
gmbs3v2 vout

gm1v2
rds1
rds2
gm2v2
vout = rds3[iout  gm3v1 + gm3v2 + gmbs3v2] + v2 vout = rds3iout  gm3rds3(gm1rds1v2) + gm3rds3v2 + gmbs3rds3v2 + v2 rds2 v2 = iout 1 + g m2 r d s 2 vout = ioutrds3 + [gm3rds3 + gmbs3rds3 + gm1rds1gm3rds3]v2 + v2 rout = rds3 + rds2
1 + g m3 r ds3 + g mbs3 r ds3 + g m1 r ds1 g m3 r ds3 1+gm2rds2
Page V.411
Iin
Iout
M4
M1
M3
M2
Additional diodeconnected transistor equalizes the drainsource voltage drops of transistors M2 and M3
SPICE simulation
77.5uA
45.0uA
Iout
22.5uA
improved Wilson current source .MODEL MNMOS1 NMOS VTO=0.75 KP=25U +LAMBDA=0.01 GAMMA=0.8 PHI=0.6 M1 1 2 3 0 MNMOS1 W=12U L=3U M2 3 3 0 0 MNMOS1 W=12U L=3U M3 5 3 0 0 MNMOS1 W=12U L=3U M4 2 2 5 0 MNMOS1 W=12U L=3U .DC VOUT 0 5 0.2 IIN 10U 80U 10U R 2 0 100MEG IIN 0 2 VOUT 1 0 .PROBE .PRINT DC ID(M1) .END
Vout
Page V.412
iOUT
+
+
M1
vOUT
M2 
vGS4 
VSS
v4
+ g m3 v3 rds3 rds2
gm4vgs4
vout

v3

vout = (iout  gm4vgs4)rds4 + ioutrds2 vgs4 = v 4  v 3 v3 = ioutrds2 v4 = gm3v3rds3 vout = ioutrds4  gm4(gm3ioutrds2rds3  ioutrds2)r ds4 + ioutrds2 rout = rds4 + gm4 g m3 r ds2rds3rds4 + rds2 + gm4 rds2rds4 vOUT(min) = 2IB K'(W/L)4 + 2Iout K'(W/L)3 + VT4
Page V.413
SUMMARY OF CURRENT MIRRORS Output Resistance r ds g m rds2 g m rds2 gm 2rds3 Minimum Voltage VON VT + 2V ON 2VON VT + 2VON
Page V.51
1.) Output voltage/current should be independent of power supply. 2.) Output voltage/current should be independent of temperature. 3.) Output voltage/current should be independent of processing variations.
Current Reference
Vref
Page V.52
Concept of Sensitivity Definition Sensitivity is a measure of dependence of Vref (Iref) upon a parameter or variable x which influences Vref (Iref). Vref Vref x Vref = = x Vref x x
Vref
S
x where
x = VDD or temperature
For example, if the sensitivity is 1, then a 10% change in x will cause a 10% change in V ref.
Vref Ideally,
S
x
Page V.53
Vref
S
V DD
Types of references include, 1. Voltage dividers  passive and active. 2. MOS diode reference. 3. PN junction diode reference. 4. Gatesource threshold referenced circuit. 5. Baseemitter referenced circuit.
Page V.54
RA V1 I RB V2 RC
VSS
Page V.55
VREF

V CC  V B E VCC R If I = R
VCC V REF V t ln RI s
Sensitivity:
VREF
S
V CC
1 VCC ln RI s
VREF
S
V CC
= 0.0362.
VCC
R IR1 R1 R2
I
+
VREF

Page V.56
GateSource Referenced Circuits (MOS equivalent of the pn junction referenced circuit) VDD VREF = VGS = VT + R I
+
1 V REF = VT R
VREF

Sensitivity:
V REF
S
VDD VREF
If V DD = 10V, W/L = 10, R = 100k and using the results of Table 3.12 gives VREF = 1.97V.and
S
VDD
= 0.29.
R IR1
I
+
VREF
R 1 +R 2 V GS R2
R1 R2
V REF

Page V.57
M4 RB M3 M5 iOUT
ID1 = I1 M6
ID2 = I2
M2 M8 M1 R
Principle: If M3 = M4, then I 1 = I2 also, VGS1 = VT1 + therefore, VT1 1 I2 = R + R 2I1 KNS1 (2) 2I1 KNS1 = I2R (1)
I2
Eq. (2)
Page V.58
Bootstrapped Current Sink/Source  Continued An examination of the secondorder effects of this circuitThe relationship between M1 and R can be expressed as, I2R = VT1 + 2I1 1
Instead of assuming that I1 = I2 because of the current mirror, M3M4, let us consider the effects of the channel modulation which gives 1 + PV G S 4 I 2 = I1 1 + P (V D D  V DS1 ) Solving for I1 from the above two expressions gives I1R(1 + PVGS4) = [1 + P(V DDV DS1)] 2I1 1
Differentiating with respect to VDD and assuming the VDS1 and VGS4 are constant gives (IOUT = I1),
20VDD PV T1 +
IOUT
S
VDD
IOUTR(1 + P V GS4 )
1 + P (V D D  V DS1 ) 2 1I1
2I1 1
Page V.59
Bootstrapped Current Sink/Source  Continued Assume that VDD =5V, K N ' = 23.6 A/V2, VTN=0.79V, N=0.53V0.5, P = 0.590V, N=0.02V1, K P ' = 5.8A/V2, VTP=0.52V, P=0.67V0.5, P = 0.6V, N=0.012V1. Therefore, VGS4 = 1.50V, VT2 = 1.085V, VGS2 = 1.545V, and VDS1 = 2.795V which gives
IOUT
S
VDD
IOUT/IOUT = 0.08 = V /V DD DD
V DD
= 3.2A If VDD = 6V  4V = 2V, then IOUT = 0.08 I OUT V DD SPICE Results: 120A 100A 80A IOUT 2.8A for VDD 4V 6V
IOUT
VDD
Page V.510
M4 RB M3 M5 iOUT
ID1 = I1 M6 M1 M8
ID2 = I2
M2
Q1
I2
VBE1 R = I5
V = I2R V BE1
Page V.511
V.52  TEMPERATURE DEPENDENCE Objective Minimize the fractional temperature coefficient which is defined as 1 Vref parts per million per C or ppm/C T CF = V ref T Temperature Variation of References PN Junction: v i I s exp V t
V GO I s = KT 3 exp V t
1 Is Is T
(ln I s ) 3 V GO V GO = T + TV TV T t t
dvBE V BE  V G O = 2mV/C at room temperature dT T (VGO = 1.205 V and is called the bandgap voltage)
GateSource Voltage with constant current (Strong Inversion): dVGS dVT dT = dT + 2L d WCox dT
ID o
Page V.512
+ VREF = VBE = kT ln I = Vt ln I q Is Is 
V DD  v B E V DD I= R R 1
>
VDD V REF = V t ln RI s
TCF =
Vt dR  V REF RdT
Assume VREF = 0.6 volts and that R is a polysilicon resistor dR = +1500 ppm/ C gives a RdT 0.6  1.205 0.026 TC F = (300K)(0.6)  0.6 (0.0015) = 0.003361  0.000065 = 3426 ppm/C
Page V.513
Gate  Source Referenced Circuits MOS Equivalent of the PN Junction Referenced Circuit VDD
I
+
VREF

1 V R E F = V T R +
1 VREF
Page V.514
Example W = 2L, VDD = 5V, R = 100 K , K=110 , VT = 0.7, T = 300 K, = 2.3 mV/C Solving for VREF gives VREF = 1.281 V dR = +1500 ppm/C RdT
5 1.281 1.5 1500 106 6 100K 300 2 2 11010 1 6 2 2 11010 100K (5  1.281)
Page V.515
M4 RB M3 M5 iOUT
I D1 = I1 M6
I D2 = I2
M2 M8 M1 R
2ID1 L + VT VGS1 V ON + V T K'W ID2 = R = = = ID1 = IOUT R R Assuming that VON is constant as a function of temperature because of the bootstrapped current reference, then TCF = 1 dVT 1 dR  1 dR = VT dT R dT VT  R dT
If R is a polysilicon resistor, then 2.3 x 10 3  1.5x10 3 = 3800 ppm/C 1 If R is an implanted resistor, then TC F = TC F = 2.3 x 10 3  0.4x103 = 2700 ppm/C 1
Page V.516
M4 RB M3 M5 iOUT
ID1 = I1 M6 M1 M8
ID2 = I2
M2
Q1
vBE1 I2 R
1 dv BE 1 dR > TCF = v  R dT BE dT
Assuming VBE = 0.6 volts and a polysilicon resistor gives 1 TCF = 0.6 (2x103)  (1.5x103) = 4833 ppm/C
Page V.61
V.6  SUMMARY
The circuits in this chapter represent the first level of building blocks in analog circuit design. The MOS transistor makes a good switch and a variable resistor with reasonable ranges of linearity in certain applications. Primary switch imperfection is clock feedthrough. In order for switches to be used with lower power supplies, VT must be decreased. The primary characteristics defining a current sink or source are VMIN and Rout. V MIN 0 and Rout . Typically the product of VMIN times Rout is a constant in most designs. Current mirrors are characterized by: Gain accuracy Gain linearity VMIN on output Rout Rin Reasonably good power supply independent and temperature independent voltage and current references are possible. These references do not satisfy very stable reference requirements.
Page VI.01
SYSTEMS
CIRCUITS
Chapter 5 CMOS Subcircuits SIMPLE Chapter 6 CMOS Amplifiers
DEVICES
Page VI.11
Page VI.12
VDD VGG2
M2 M2 M2
+
M1 M1
+ vOUT 
+
M1
+ vIN 
vIN 
Page VI.13
5V 1.2
v IN=5V
1.0 0.8
iD (mA)
vIN=4.5V
M2
vIN =4V vIN =3.5V vIN=3V vIN=2.5V vIN=1V v IN=2V vIN =1.5V
W2 15 m = L2 3m
W1 15 m = L1 3m M1
+ vOUT 
+ v IN 5 5 4 3 vOUT 2 1 0 0 1 2 v IN
v OUT
Page VI.14
Active Load CMOS Inverter Output Swing Limits Maximum: vIN =0 iD=0 vSD2=VT2  v OUT (max) V DD V TP  Minimum: Assume v IN = VDD, M1 active, M2 saturated, and VT1 = VT2 = VT. vDS1 2 M1: iD = 1(vGS1 VT)vDS1 2
vIN VDD M2 iD vOUT M1 VSS
2 2 2 2 2 M2: iD = 2 (vGS VT) = 2 (VDDvOUTVT) = 2 (vOUT+VTVDD)2 2 iD = 2 (vOUT VSS+VSS+VTVDD)2 2 2 =2 (vOUTVSS)(VDD VSSVT) Define vOUT' = vOUT V SS and VX = VDD V SS V T (vOUT')2 iD = 1V X vOUT ' (M1) 2 2 2 iD = 2 (M2) v OUT ' V X Equate currents v OUT '2 2 2 2 2 v OUT ' 2V X v OUT ' + V X = 1V X v OUT ' 2 2 2 2 2 or 1v OUT ' 2V X v OUT ' + V X = 2VX vOUT' v OUT ' 2 2 2 1 + vOUT '2 2VX 1 + V X2 = 0 vOUT ' + 1 1 1
2 / 1 2 vOUT' 2VX vOUT' + 1+ / VX2 = 0 2 1
(v OUTVSS)2 = 1 (VDDVSSVT)(vOUTVSS) 2
Page VI.15
1 1 + 2 / 1
Page VI.16
2 1 + 1
+ VSS
VDD = VSS = 5V VT = 1V
vOUT
5
v MAX
1 0 1 v MIN 3 0.1 1 10
1 2
5
Gain ~
1 2
Page VI.17
M2 M1
+ v OUT
+ v out S1=B1
+ vIN 
Small Signal Voltage Gain vout = r  r d s 2 g m1 v in + g m2 v out ds1 gm1 g m1 vout = vin g ds1 + g ds2 + g m 2 gm2 =
W1 2KN L I1 1 W2 2KP L I2 2
1 2
vout vin =
NO W1L2 PO W2L1
If
vout W 1/L1 = 20, then W2/L2 vin = 6.67 using the parameters of Table 3.12
Page VI.18
VGG
M2 I
M2 I
vOUT vIN
M1
vIN
M1
vOUT
V SS
V SS
Pushpull, inverter
M1 vIN = VDD .8V DD
0
C=C' .2V SS B=B'.4V SS .6V SS A=A' V DD
vOUT
.5VSS
.5VDD
Large signal transfer characteristics of inverter with a current source and push pull inverter
Page VI.19
VSS
.8VSS .6VSS
.4VSS
.2VSS
.2VDD
v IN
VSS
Advantages: 1. High gain. 2. Large output signal swing. 3. Large current sink and source capability in push pull inverter.
Page VI.110
M2 I
vIN
M1
vOUT
4
Current in M1 or M2 voltage transfer curve
100 A
v OUT
0
M1 off
vIN + VT2
2
M2 linear
M1 saturated M1 linear
4
vIN  VT2
CMOS inverter DC current and sweep VIN 1 0 VDD 3 0 DC 5.0 VSS 4 0 DC 5.0 M1 2 1 4 4 MNMOS1 W=3U L=3U M2 2 1 3 3 MPMOS1 W=9U L=3U .MODEL MNMOS1 NMOS VTO=0.75 KP=25U +LAMBDA=0.01 GAMMA=0.8 PHI=0.6 .MODEL MPMOS1 PMOS VTO=0.75 KP=8U +LAMBDA=0.02 GAMMA=0.4 PHI=0.6 .DC VIN 5.0 5.0 0.1 .PRINT DC V(2) ID(M1) .PROBE .END
0 A
M2 off
6 5 3 1 0 1 3 5
vIN
Page VI.111
VGG
M2 I
vOUT vIN
M1
v OUT(max.) V D D
VSS
2 VDDVGGVT2 1 V V V SS T1 1 DD
M2 I
vIN
M1
vOUT
v OUT(max.) V D D v OUT(min.) V SS
VSS
Page VI.112
High Gain, CMOS Inverters Small Signal Characteristics Model + vin Small Signal Voltage Gain: vOUT = r  r ds2 g m1 v in + g m2 v in ds1 OR vout g m1 + g m 2 = = vin g + g ds2 ds1
2 I D
W1 KN' L + 1 1 + 2
W2 KP' L 2
K !!! ID
Set g m2 = 0 for the current source inverter W1 W2 Assume that iD = 1 A and L1 = L2 , using the values of Table 3.12 gives vOUT vin = 328 = 194 for the pushpull inverter (L=10 m) for the current source inverter (L=10 m)
Page VI.113
1000
Limit is the subthreshold current where square law characteristic turns into an exponential characteristic. Assume that the level where subthreshold effects begin is approximately 0.1A, the maximum gains of the CMOS inverters become: The CMOS inverters become: PushPull: 1036 Current source load: 615 Current sink load: 422
W = 1, L=10 m L
Page VI.114
Frequency Response of CMOS Inverters General Configuration X = vOUT ; Active Load CMOS Inverter (gm = gm1 ) X = VGG ; CMOS Inverter with a Current Source Load (g m = gm1) X = v IN ;
C GS2 X C GD2 CGD1 M2 C BD2 +
vin
C BD1 M1 CL 
v out

v in
(a) General configuration of an inverter illustrating parasitic capacitances. (b) Small signal model of (a) CGD1 and CGD2 are overlap capacitances CBD1 and C BD2 are the bulkdrain capacitances CL is the load capacitance seen by the inverter Frequency Response vOUT g m R 1(1 s/z) , vIN = s + 1
1 1 = RC
gm and z = C
GD1
1 (gm2 = 0 for push pull and current source inverters) R = g +g +g ds1 ds2 m2 C CGD1+CGS2+CBD1+CBD2+CL (Active load inverter) C CGD1+CGD2+CBD1+CBD2+CL (Current source & pushpull inverter) if g mR >> 1
Page VI.115
Frequency Response of CMOS Inverters Dependence of Frequency Response on Bias Current When g m2 0 (active load inverter):
W 2K' 1 L ID Rg or 3dB = ~ ID C m2 When gm2 = 0 (push pull and current source inverter): ( 1 + 2 ) ID 1 R = ( or = ~ ID 3dB C 1 + 2 ) ID Example: Find the 3dB frequency for the CMOS inverter using a current source load and the CMOS push pull inverter assuming that iD = 1A, CGD1=CGD2=0.2pF and CBD1=CBD2=0.5pF W1 W2 Using the parameters of Table 3.12 and assuming that L1 = L2 =1 Gives, For the active load CMOS inverter, gm2 3dB = C = 3.124x10 6 rads/sec or 512KHz For the push pull or current source CMOS inverter, g gd1 + g ds2 3dB = = 14.3x10 3 rads/sec or 2.27 KHz C gm1 z=C = 29.155 Mrads/sec or 4.64 MHz GD1 The reason for the difference is the higher output resistance of the push pull or current source CMOS inverters
Page VI.116
RL RS v IN +

i2 d RS
2
RL
i2 L
RL v2 n
RS
8 2 id = KTg m (A2/Hz) 3 4KT 2 2 iL = RL (A /Hz) Comments: 1.) 1/f noise has been ignored. 2.) Resistors are noisefree, they are used to show topological aspects. Can repeat the noise analysis for the resistors if desired.
Page VI.117
VDD
e2 n2 M2
2
vOUT vIN
e2 n1 M1
eout
vIN=0 eout
2
= en1
VSS
2 eeq =
2 en1 1
2 gm2 2 en2 + g m1 e2 n1
So
eeq =
2 en1 1
2 2 eeq = en1 1 +
>
Gain =
L2 L1
small
Page VI.118
Noise in An Active Load Inverter  (Cont'd) Suppose the noise is thermal  Sec. 3.2, Eq,(13) 8kT(1+) 3gm 8kT(1+1) 2 eeq = 1 + 3gm1 2 en =
To minimize thermal noise gm1 1. Maximize gain gm2 2. Increase gm1 = 2KNW1 L1 ID
Page VI.119
Noise in Other Types of Inverters Current Source Load Inverter > same as active load inverter PushPull InverterVDD
e2 n2 M2
vIN
M1 e2 n1
vOUT
VSS
1 rout = g ds1 + g ds2 2 2 2 eout = (gm1rout)2 en1 + (gm2rout)2 en2 vout = (gm1 + gm2 )rout vin gm1 gm2 2 2 2 2 2 eeq = g e + en2 n1 m1 + g m 2 g m1 + g m 2 2 gm2 2 en2 1 + g 2 m1 en1 2 en1 2 g 1 + m 2 gm1 ' 2 KPBP L1 1 + ' K BN L 2 N 2 en1 2 ' KP W 2 L 1 1 + K ' W L N 1 2
2 eeq =
Page VI.120
1 gm2
+v2 n2
1 gm2 +g mb2
gm1 v2 n1 g
m2
+v2 n2
gm1 gds1+gds2
1 gds1+gds2
gm1 v2 n1 g
m2
+v2 n2
PushPull inverter
1 gds1+gds2
gds1+gds2
v2 gm2 + g n2 m1 +g m2
Page VI.121
KEY MOSFET RELATIONSHIP USEFUL FOR DESIGN Assume MOSFET is in saturation. KW iD = 2L (vGS VT ) 2 2iD KW/L 2iD KW/L VT
1.)
or
vGS =
2.)
vDS (sat) =
or
3.)
gm =
2IDKW L
or
Page VI.21
v1
v2
v 1 + v 2 2
(100) Differential voltage gain = AVD Common mode voltage gain = AVC (1) AVD Common mode rejection ratio = (1000) AVC VOS(out) Input offset voltage = VOS(in) = (210mV) AVD Common mode input range = VICMR (VSS+2V<VICMR <VDD2V) Power supply rejection ratio Noise (PSRR)
Page VI.22
VI.21  CMOS DIFFERENTIAL AMPLIFIERS NChannel Input Pair Differential Amplifier VDD
M3 M4
iD4 iD2
M2
VSS
Page VI.23
VDD
IDD
vGS1 vG1
M1 M2
vGS2

vG2 vOUT
iD1=iD3
iD2 iD4
iOUT
M3
M4
VSS
Page VI.24
iD1
M1 +
iD2
M2 +
vGS1

vGS2 ISS

(1). vID = vGS1 v GS2 = (2). ISS = iD1 + iD2 Solving for iD1 and iD2 gives,
ISS ISS (3). iD1 = 2 + 2 vID
2iD1
2iD2
2 v ID ISS 4ISS 2
2
And
ISS ISS (4). iD2 = vID 2 2
IS S
iD2
.6 .4
iD1 .2
2  2 2 2
vID ISS
Page VI.25
vOUT
iD1 + v+ 3u/3u 3u/3u 3u/3u iD2 v
50K
3u/3u
v+
Page VI.26
9u/3u
9u/3u
50k
vOUT
v+ 3u/3u 3u/3u v
3u/3u
3u/3u
VSS
5 3 v = 0V v = 1V v = 1V
Output Voltage
1 v = 1V
v = 1V v = 0V
3
5 5 3 1 1 3 5
Page VI.27
v+
9u/3u
9u/3u
vvOUT
3u/3u
3u/3u
50k
VSS
5 v = 1V v = 0V v = 1V 1
Output Voltage
1
3 v = 1V 5 5 3
v = 1V v = 0V
1
Page VI.28
COMMON MODE INPUT RANGE PChannel Input Pair Differential Amplifier VDD
+ M5 vSD5 + + M2 +
vSG1 vG1

vSG2

v M1 SD1

vG2 vOUT
M3
M4
vGS3

VSS
Lowest common mode input voltage at gate of M1(M2) vG1(min) = VSS + vGS3 + vSD1 vSG1 for saturation, the minimum value of vSD1 = vSG1 V T1 Therefore, vG1(min) = VSS + vGS3 V T1 or, vG1(min) = VSS + ISS + VTO3 VT1 2ID1 1 V T1
Page VI.29
COMMON MODE RANGECONT'D Example Assume that VDD varies from 8 to 12 volts and that VSS = 0. Using the values of Table 3.12, find the common mode range for worst case conditions. Assume that ISS = 100A, W1/L1 = W2/L2 = 5, W3/L3 = W4/L4 = 1, and vSD5 = 0.2V. Include the worst case value of K' in the calculations. If V DD varies 10 2V, then we get vG1(max) = VDD v SD5 = 8 0.2 vG1(min) = VSS + =0+ ISS 1 V T1
Therefore, the input common mode range of the pchannel input differential amplifier is from 2.71V to 4.99V
Page VI.210
0V
Page VI.211
CMOS DIFFERENTIAL AMPLIFIER Small Signal Differential Mode Gain NChannel input differential amplifier VDD
M3 M4
vOUT vG1
M1 M2
vG2
VGG
M5
VSS Exact small signal model D1=G3=D3=G4 G1 G2 +v id + + vg1 _ 1 v g2 g m3 _ + v gs4 rds3 _ S3 rds1 g m1 v gs1 S1=S2 + rds5 vs1 =vs2 0 _ v gs1 = v gs2 v
s1
i'out + vout
rds4 
Page VI.212
CMOS DIFFERENTIAL AMPLIFIER Unloaded Differential Transconductance Gain (RL =0) g m1 g m4 (r ds1  rds3 ) iout' = gm4vgs4 g m2vgs2 = v gm2vgs2 1 + g m 3 (r ds1  r ds3 ) gs1 If gm3(r ds1  rds3) >> 1, gm3 = gm4 , and g m1 = gm2 = gmd, then iout' g m1vgs1 gm2vgs2 = gmd(v gs1 vgs2) = gmdvid or i out ' g m d v id = K N'WISS vi d L
Unloaded Differential Voltage Gain (RL = ) gmd 2 v = v out g i d ( N + P ) ds2 + g ds4 K N'W v ISSL i d
Example If all W/L ratios are 3m/3m and ISS = 10A, then gmd(Nchannel) = (17x106)(10x106) = 13 A/V gmd (Pchannel) = (8x106)(10x106) = 8.9 A/V and vout 2(13x106) (Nchannel) = = 86.67 vid (0.01+0.02)10x106 vout 2(8.9x106) (Pchannel) = = 59.33 vid (0.01+0.02)10x106
Page VI.213
INTUITIVE SMALL SIGNAL ANALYSIS OF MOSFET CIRCUITS Principle: Consider only small changes superimposed on the dc conditions. Technique: Identify the transistor(s) that convert input voltage to current (these transistors are called the active devices). Trace the currents to where they flow into the resistance seen from a given node and multiply this resistance times the currents to find the voltage at this node. Example  Differential Amplifier VDD
gm1vin 2 M3 gm1vin 2 M4 Rout gm2vin 2 M1 vin 2 M2 v + in M5 vin + 2
gm1vin 2 +
vOUT
VGG
VSS Current flowing into the output node (drains of M2 and M4) is gm1vin gm2vin iout = 2 + 2 Output resistance, R out, seen at this node is 1 R out = rds2rds4 = g +g ds2 ds4 Therefore, the open circuit voltage gain is v out gm1+gm2 gm1 gm2 vin = 2(gds2+gds4) = gds2+gds4 = gds2+gds4
Page VI.214
CMOS DIFFERENTIAL AMPLIFIER Common Mode Gain The differential amplifier that uses a current mirror load should theoretically have zero common mode gain. For example: VDD
M1M3M4
M3
M4
vOUT vG1
M1
M1M2
M2
vG2
VSS
Therefore, the common mode gain will approach zero and is nonzero because of mismatches in the gain between the two paths.
Page VI.215
vO1 vIC
M1 M2
vO2 vIC
VGG5
M5
vO1 vIC
M1 M2
vO2 vIC
VGG
1 xM5 2
1 xM5 2
VGG
VSS
Page VI.216
rds1
gm1 vgs1
rds1 +
r ds3 gm1 vg1
vo1 
Writing nodal equations 0.5g ds + g ds1 + g mbs1 vs1 gds1 vo1 = gm1 vIC g ds1 + g m1 + g m b s 1 v o1 + g ds1 + g ds3 + g m 3 vo1 = gm1 vIC
vo1 Solving for v gives, IC 0.5gm1gds5 vo1 = vIC gds3+gm30.5g ds + g m1 + g mbs1 + g ds1 + 0.5g ds1 g ds5 or 0.5gm1gds5 gds5 vo1 vIC gm3g m1 + g mbs1 2gm3
Page VI.217
COMMON MODE REJECTION RATIO (CMRR) Differential mode gain Avd CMRR = Common mode gain = Avc For the previous example,
gm1 gm3
CMRR =
gm1gds5 2g m3 g m1 + g mbs1
Therefore, current sinks/sources with a larger output resistance(rds5) will increase the CMRR. Example Let all W/L ratios be unity, ISS = 100A, and use the values of Table 3.12 to find the CMRR of a CMOS differential amplifier. gm1 = 2x17(A/V2)x100A = 58.3S gds5 = 0.01V1 x 100A =1S Therefore, CMRR = 116
Page VI.218
vOUT
M2
vG1
M1
vG2
CT ISS
VSS CT = tail capacitor (common mode only) CM = mirror capacitor = Cdg1 + Cdb1 + Cgs3 + Cgs4 + Cdb3 COUT = output capacitor Cbd4 + Cbd2 + Cgd2 + CL Small Signal Model
+ + g m1vgs1 + v gs3 g m3 1 CM + rds2 rds1 gm4v gs3 g m2v gs2 rds4 C OUT v out 
rds3
C gd4
We will examine the frequency response of the differential amplifier in more detail later.
Page VI.219
SLEW RATE Slew rate is defined as an output voltage rate limit usually caused by the current necessary to charge a capacitance. i.e. i = C
dV dT
VSS ISS Slew rate = C L where CL is the total capacitance seen from the output node to ground. If C L = 5pF and ISS = 10 A, then the SR = 2V/S
Page VI.220
CMOS DIFFERENTIAL AMPLIFIERS NOISE Assumption: Neglect thermal noise(low frequency) and ignore the thermal noise sources of rd and rs . Therefore:
2 KF ind = iD AF (AF = 0.8 and KF = 1028 ) fCoxL2
or vnd =
2
KF = i D(AF1) 2 2 gm 2foCox WL
ind
Page VI.221
VDD
IDD
v2 eq1
M1 M2
v2 eq2
i2 o
+ M3 M4
vOUT
v2 eq3
v2 eq4
VSS
Page VI.222
CMOS DIFFERENTIAL AMPLIFIERS NOISE Total output noise current is found as, iod
2 2
= gm1 2 v1 + g m2 2 v2 + gm32 v3 + g m4 2 v4
Define vneq as the equivalent input noise voltage of the differential amplifier. Therefore, iod = gm12 vneq or
gm3 2 2 2 2 2 2 vneq = veq1 + veq2 + veq3 + veq4 gm1 Where gm1 = gm2 and gm3 = gm4
VDD I DD
v2 neq
M1 M2
i2 o
+ M4 
M3
vOUT VSS
It is desirable to increase the transconductance of M1 and M2 and decrease the transconductance of M3 and M4. (Empirical studies suggest pchannel devices have less noise)
Page VI.223
and
en3 = en4
K N 'B N L12 2BP 2 eeq (1/f) = fW L 1 + K 'B L 1 1 P P 3 1) Since BN 5BP use PMOS for M1 and M2 with large area. K P'BP L1 1 2 12.5 so that eeq (1/f) 2) Make L < K 'B 3 N N 2BP fW1L1
Thermal Noise
2
eeq (th) = 3
16KT(1+1)
W1 2K P'I 1 L 1
3 K N ' W 1 + L3 K P'W1 L1
Page VI.31
VDD
Miller effect: Inverter Cin Gain x Cgd1 Cascode Cin 3Cgd1 v1 2 vin
VGG2
M3 vout
VGG1 Cgd1
M2 +
vin
M1 v 1 VSS
Large Signal Characteristics When V GG1 designed properly, vout(min) = V on1 + V on2
Page VI.32
+
vin
+
gm1 vin v1
C1
rds2
+
vin gm1vin C2 rds1
+
v1
+
C3 rds3 vout
Nodal Equations: (gm1 sC1)vin + (g m2 + g mbs2 + g ds1 + g ds2 + sC1 + sC2)v1 (gds2)vout = 0 (gds2 + gm2 + gmbs2)v1 + (gds2 + gds3 + sC3)vout = 0 Solving for v out/vin gives (sC1gm1)gm2(1+) 2 s (C3C1+C3C2)+s (C 1+C2)(g ds2+g ds3) +C3gm2 (1+) +gds3gm2(1+)
Page VI.33
Small Signal Characteristics Lowfrequency Gains: vout g m1 (g ds2 + g m2 + g mbs2 ) = vin g ds1 g ds2 + g ds3 (g m2 + g mbs2 + g ds1 + g ds2 ) gm 1 gds3 = 2K'(W1/L 1)ID1 3ID3
M3
Page VI.34
Voltage Gain of M1: v1 gm1 = vin gm2 ? What is the small signal resistance looking into the source of M2? Consider the model below:
i1 + v1 = vs2 gm2 vgs2 r ds2 r ds3
vs2 = (i1 + gm2vgs2)r ds2 + i1rds3 = rds2i1 + gm2(vs2)r ds2 + i1rds3 or vs2(1 + g m2 rds2) = i1(rds2 + rds3) Therefore, r ds2 + r ds3 r ds2 + r d s 3 r d s 3 vs2 1 g r = g 1 + r R= i =1 + g r 1 m2 d s 2 m2 ds2 m2 ds2 Some limiting cases: 1 rds3 = 0 R = g m2 2 rds3 = rds2 R = g m2 and rds3 rds3 >> rds2 R = gm2rds2 Therefore, the gain vin to v1 is g m1 (g ds2 + g ds3 ) 2gm1 2gm1 v1 vin (g m2 + g mbs2 )g ds3 g m2 + g mbs2 gm2
Page VI.35
vout
iin + M1 v1 C
M3
iin
R1
C1
Page VI.36
Note: s s 1 s2 1 d(s) = 1 + as + bs2 = 1 p 1 p = 1 sp + p + p p 1 2 1 2 1 2 If p2 >> p 1 , then s s2 d(s) 1 p + p p 1 1 2 Using this technique we get, p1 1 1 R1(C1+C3)+R3(C2+C3)+gm1R1R3C2 gm1R1R3C2 1 p1 = a a p2 = b
or
and
Page VI.37
CASCODE AMPLIFIER  CONTINUED How does the Cascode Amplifier solve this problem?
VDD M5 VGG5 M2 VGG2 M4 1 ro =g +g ds3 ds4 iin M1 M3 VSS Cgd1 + v1 rds2 + v2 r2  gm2(1+)v2 + C3 r3 vout Cgd1 vout
iin
r1
C2 gmv1
1 g m2
Page VI.38
io
gmbs2 v1
r ds2
g m3 v4
gmbs3 v4
r ds3
vout
D1=S2
+
vin
+
gm1 v in v1 r ds1 r ds4
+ v4 
' =rds3
Page VI.41
Page VI.42
CLASS A AMPLIFIER
VDD
VGG2 IQ
M2
Iout Vout
Vin
M1
VSS
CL
RL
KnW1 2 Iout 2L1 (VDD VSS VT1) IQ KpW2 Iout = 2L (VDD V GG2 VT2) 2 < Iout+ 2
+=
Iout determined by: 1. Iout = C L dvout dt = CL (slew rate) vout(peak) 2. I out = RL PRL 25%
(typically large)
Page VI.43
Push Pull
VDD
M1
vOUT vIN
M1
vOUT
VGG
M2
VSS
M2
VSS
Large Signal Characteristics vOUT = vIN vGS1 Maximum Output Swing Limits vOUT (MAX) = VDD VT1 (VT1 greater than V T0 because of v BS) Single Channel Follower: vOUT(MIN) = V SS Push Pull Follower: vOUT(MIN) = VSS + VT2 (VT2 greater than VT0 because of v BS)
Page VI.44
SOURCE FOLLOWERS Small Signal Characteristics Single Channel Follower (Current source and active load):
C1
+
vin
gm1 vin gm1 vout rds1 gmbs1 vout gm2 vgs2 rds2 C2
+
vout
Small Signal Voltage Transfer Function: gm1 vout = vin gds1+gds2+gm1+gmbs1+gm2 where g m2 = 0 if v GS2 = V G G Example:
then; vout 41.23 = vin 1+1+41.23(1+0.2723)+41.23 = 0.4309 when vGS2 = vOUT vout 41.23 = vin 1+1+41.23(1+0.2723) = 0.751 when vGS2 = VGG vout 0.786 (gds1= gds2 0) Approximation gives v in Output Resistance: 1 r out = gds1+gds2+gm1+gmbs1+gm2 where g m2 = 0 if v GS2 = V G G rout = 10.5 K (vGS2 = vOUT) and rout = 18.4 K (vGS2 = VGG)
Page VI.45
+
vin
gm1vin
M1
M2
+
C2 v out
gm1vout
Small Signal Voltage Transfer Function: g m1 + g m 2 vout vin = g ds1 + g ds2 + g m1 + g mbs1 + g m2 + g m b s 2 Example: W 10 m If VDD = VSS = 5V, vOUT = 0V, iD = 100A, and L = 10m then, vout 41.23 + 28.28 = vin 1 + 0.5 + 41.23(1 + 0.2723) + 28.28(1 + 0.1268) = 0.81 Output Resistance: 1 r out = g ds1 + g ds2 + g m 1 + g mbs1 + g m 2 + g m b s 2 = 11.7K
Page VI.46
+ + 
M2
Iout Vout
M1
VSS
CL
RL
ImplementationVDD
M5
M6
M1
vIN
M3
VGG3
Iout
Vout
M2
M4
VGG4
CL
RL
M7
VSS
M8
Page VI.47
M2
Iout Vout
VTR vIN
M1
CL VSS
RL
VDD VGG6
M6 M2 M5 M4 M1
Iout Vout RL
CL
vIN
M3
VSS
Page VI.48
VDD
error amplifier
vIN + +
M2
Iout
Vout
M1
CL
RL
VSS
M2
R1 vIN
R2
Iout
Vout
M1
CL
RL
VSS
Page VI.51
VI.5  SUMMARY
Analog Amplifier Building Blocks Inverters  Class A PushPull  Class AB or B Cascode  Increased bandwidth Differential  Common mode rejection, good input stage Output  Low output resistance with minimum distortion
Page VII.01
SECTION 7  COMPARATORS
Page VII.01
VII. COMPARATORS
Contents VI.1 VI.2 VI.3 VI.4 VI.5 Comparators Models and Performance Development of a CMOS Comparator Design of a TwoStage CMOS Comparator Other Types of Comparators Improvement in Comparator Performance A. Hysteresis B. Autozeroing VI.6 High Speed Comparators Organization
Chapter 10 D/A and A/D Converters
SYSTEMS
CIRCUITS
Chapter 5 CMOS Subcircuits SIMPLE Chapter 6 CMOS Amplifiers
DEVICES
Page VII.11
Page VII.12
VOLTAGE COMPARATORS
Definition of a Comparator VA VB
VOUT

VOUT =
VA  VB
when V A < V B
VOL
Inverting VOUT V OL V OH
when VA VB
VOH
VOUT =
when V A V B
VA  VB VOL
Page VII.13
COMPARATOR PERFORMANCE
1. Speed or propagation time delay. The amount of time between the time when VA  V B = 0 and the output is 50% between initial and final value. 2. Resolving capability. The input change necessary to cause the output to make a transition between its two stable states. 3. Input common mode range. The input voltage range over which the comparator can detect V A = VB . 4. Output voltage swing (typically binary). 5. Input offset voltage. The value of V OUT reflected back to the input when VA is physically connected to V B.
Page VII.14
APPROACHES TO THE DESIGN OF VOLTAGE COMPARATORS Open Loop Use of a highgain differential amplifier. V OH  V O L Gain = resolution of the comparator Regenerative Use of positive feedback to detect small differences between two voltages, VA and VB. I.e., sense amplifiers in digital memories. Open Loop  Regenerative Use of low gain, high speed comparator cascaded with a latch. Results in comparators with very low propagation time delay. Charge Balancing Differential charging of a capacitor. Compatible with switched capacitor circuit techniques. Offset Voltage (Power supply) 110 mV 0.1 mV 0.1 mV
Page VII.15
VOUT VOH
VP  VN
VOL
Model VP + + fo VP  VN VN V OH  VN ) = V OL
for ( V P  V N ) 0
+ VO 
fo( V P
for ( V P  V N ) 0
Page VII.16
Model VP + + f1 VP  VN VN 
+ VO
Page VII.17
COMPARATOR MODELS  CONT'D First Order Model with Offset Transfer Curve VOUT VOS VIL VIH VOL First Order Model with Offset +  VOS VP + + V'P + f1 V'P  V'N VN V'N + VO VOH
VP  VN
Time Response of Noninverting, first order model VOH VOUT VOL VIH VP  VN VIL Time tP v = VIH + VIL 2 v = VOH + VOL 2
Page VII.21
vO
VBIAS
VDD
vO
vN
VTRP
Page VII.22
CALCULATION OF THE TRIP POINT, VTRP vO VDD VIN M2 vO VBIAS M1 VSS Operating RegionsvDS1 v GS1  VT VBIAS  VT1 VSS VSS M1 sat. M1 act. VIN vN VTRP VDD VDD
M c 2a M t. t.
vO = V IN + VT2
a 2s
Trip PointAssume both M1 and M2 are saturated, solve and equate drain currents for VTRP. Assume 0. K N W1 2 iD1 = 2 L V BIAS  V SS  V T 1 1 K P W2 2 iD2 = 2 L V D D  v I N  VT2 2 vIN = VTRP = VDD VT2 KN( W1/L1) KP( W2/L2) ( V BIAS  V SS  V T 1)
iD1=iD2
Page VII.23
M3
M4 vO
vP
M1
M2
vN
VBIAS
M5
vP  vN Av
Page VII.24
DERIVATION OF OUTPUT SWING LIMITS VDD M3 I1 vP M4 I2 M2 vO vN 1. Current in M1 increases and current in M2 decreases. 2. Mirroring of M3M4 will cause vO to approach VDD . 3. VOH' = VDD  VDS4(sat) VOH ' = VDD VOH ' = VDD V O H ' = VD D I4 4 I5 Kp'( W4/L4) I5 Kp'( W3/L3) vP > vN
M1
ISS
VBIAS
M5 VSS
vP < vN Assume vN is a fixed DC voltage 1. vO starts to decrease, M3M4 mirror is valid so that I1 = I2 = ISS/2 . 2. VOL ' = vN  VGS2 + VDS2 when M2 becomes nonsat. we have VDS2(sat) = VGS2  VT so that V OL ' = v N  V T 2 3. For further decrease in vO, M2 is nonsat and therefore the VGS2 can increase allowing the sources of M1 and M2 to fall(as v P falls). 4. Eventually M5 becomes nonsat and I5 starts to decrease to zero. M2 becomes a switch and v O tracks V S2(VDS5) all the way to VSS. V OL = V SS .
4. Finally, vO V DD causing the mirror M3M4 to no longer be valid and V OH V DD. (I2 = I4 = 0 , I3 = I1 = I5)
Page VII.25
TWOSTAGE COMPARATOR Combine the differential amplifier stage with the inverter stage. Sufficient gain. Good signal swing.
VDD M3 M4 M6 vN I8 M1 M2 vP vO
M8
M5
M7
VSS
Page VI.31
Page VI.32
VDD =10V +
20 10
I8
vN M1
vP M2
i6 i7
vO =5V
20A
10 10 3V
M5
VSS =0V
M7
10 10
(1) Find the mismatch between i6 and i 7 i7 1 + N v D S 7 W7/L7 1 + (0.015)(5) = i5 = 1 + N v D S 5 1 + (0.015)(3) (1) = 1.029 W5/L5 i6 1 + P v D S 6 W6/L6 1 + (0.02)(5) = i4 = 1 + P v D S 4 1 + (0.02)(2) (2) = 2.115 W4/L4 i5 = 2i4 i7 = (1.029)(2)i4 = 2.057i4 and i6 = 2.115i4 (2) Find how much vGS6 must be reduced to make i6 = i 7 vGS6 = vGS6(2.115i4)  vGS6(2.057i4) vGS6 = 2L6 KPW6 i 4 2.115  2.057 = 14.11 mV
(3) Reflecting vGS6 into the input KN( W2/L2) 2 = 89.9 I5 2 + 4 vGS6 14.1 mV = 0.157 mV VOS = A (diff) = 89.9 v A v(diff) =
Page VI.33
DESIGNING FOR COMMON MODE INPUT RANGE VDD + VSG3 M3 VDG1 + I5/2 + VDS1 I5 M5 + VDS5 VSS Example Design M1 through M4 for a CM input range 1.5 to 9 Volts when VDD = 10 V, ISS = 40A, and VSS = 0V. Table 3.12 parameters with VTN,P = 0.4 to 1.0 Volts, I5 vG1(min) = VSS + VDS5 + 1 + VT1(max) 40A + 1 (assumed VDS5 0.1V it probably more 1.5 = 0 + 0.1 + 1 reasonable to assume 1 is already defined and find 5) 1 = KNW 1 2 L1 = 250 A/V W1 W 2 L1 = L2 = 14.70 
vG1 (min) = VSS + VDS5 + VGS1 v G1 (min) = V SS + V DS5 + V T1 (max) + vG1 (max) = VDD  VSG3  VDG1(sat) v G1 (max) = V D D I5 23  VT3(max) + V T1 (min) I5 21
VG1
+ M1 VGS1 VBIAS
vG1(max) = VDD 3 =
K PW 3 2 L3 = 250 A/V
Page VI.34
GAIN OF THE TWOSTAGE COMPARATOR + gm1vid r ds2 r ds4 v1 gm6v1 r ds6 r ds7 + vout 
2 Av =
W1 W6 KNKP L L 1 6
( 2 + 4) ( 6 + 7)
I1I6
W6 W1 Using L = 5, L = 5, N = 0.015V1 , P = 0.02V1 1 6 and Table 3.12 values; 2 (17)(8)(5)(5) . 6 95199.106 Av = 10 = (0.015+0.02)2 I1I6 I1I6 Assume I1 = 10 A and I6 = 100 A Av = 3010 V OH  VOL = Resolution = 5 mV (assume) Av 5 . then VOH  V OL = 1000 3000 = 15 Volts
Page VI.35
VGS6 + 
vN
M1
M2
vP CL1
VBIAS
v CI
dv iC = C dt , t = t2+ = C L2
t+ 2
K P W6 V 2 L6 ( D D
V TRP3  V S S  v P  V D G 2  V T6  ) 2 
I7
Slew rate =
Page VI.36
CALCULATION OF COMPARATOR PROPAGATION DELAY Find the total propagation delay of the comparator shown when the input vP goes from 1 to +1 in 2ns. Assume the trip point of the output(next stage) is zero. Total delay = 1st stage + 2nd stage delay delay t = t 1 + t2 ( v DO (t 0 )  V TRP2) t1 = CL1 , I5 vDO(t0) = 5 because vP = 1V VTRP2 = VDD  VGS6, VGS6 = VT6  + VGS6 = 1 +
+5V M3
10 10
M4 vDO
40 10 C L1=0.3pF
vN
M1
20 10
M2
M6 I6 CL2= 10pF
vP
I7 =40A 5V
vO
I5=20A
2.40 = 2.58 V VTRP2 = 5  2.58 = 2.42 V 8.4 0.3pF = 38.7ns t1 = (5  2.42) 20A CL2 CL2 t2 = v O (t 0 )  0 =5 I 6  I 7 I 6  I 7 KP6' W6 I6 = 2 L V D D  V D O (min)  VT6 2 6 [VDO(min) is an optimistic assumption based on vDS2 0] VDO(min) vDS2(0)  vGS1 + vN = VT1 I6 = 8.106 2 2 (4)(5  (1.77) 1) = 533 A 10 pF t2 = 5 (533  40) A = 101 ns I5 = 1.77 KN.2
Page VI.37
M4
(6)
M6
vN
3v 2.42v
M1
20 10 10 10
M2
CL1 vP
40 10 (9)
vO
CL2
M7 5V
20 10
M8
V(9)
1v
vP
tprop=167 ns
V(6)
COMPARATOR PROPAGATION DELAY VDD 10 0 DC 5V VSS 11 0 DC 5V VN 1 0 DC 0V VP 2 0 PULSE(1 1 0N 1N 1N 500N 1U) M1 3 1 5 5 MNMOS W=20U L=10U M2 6 2 5 5 MNMOS W=20U L=10U M3 3 3 10 10 MPMOS W=10U L=10U M4 6 3 10 10 MPMOS W=10U L=10U M5 5 8 11 11 MNMOS W=10U L=10U M6 9 6 10 10 MPMOS W=40U L=10U M7 9 8 11 11 MNMOS W=20U L=10U M8 8 8 11 11 MNMOS W=10U L=10U CL1 6 0 0.3PF CL2 9 0 10PF IS 0 8 DC 20UA .MODEL MNMOS NMOS VTO=1 KP=17U +LAMBDA=0.015 GAMMA=0.8 PHI=0.6 .MODEL MPMOS PMOS VTO=1 KP=8U +LAMBDA=0.02 GAMMA=0.4 PHI=0.6 .TRAN 2N 300N .PRINT TRAN V(6) V(9) V(2) .PROBE .END
3 v
5 v 0ns
50ns
100ns
150ns
200ns
250ns
300ns
Time
Page VI.38
vin

+ gm1 
gm2 R1 C1 R2 C2
vout

Example  (Fig 7.34) I5 = 20A R1 = g 1 1 = 10A = 3.33M ds2 + g ds4 1 p1 = (0.3pF)(3.33M) = 1Mrps 1 1 = 40A(.03) = 833K ds6 + g ds7 1 p2 = (10pF)(833K) = 120Krps
I7 = 40A R2 = g
Page VI.39
M8
M5
M7
VSS Key Relationships for Design: i D = (v G S  V T ) 2 2 or v DS (sat) = Also, gm = where KW = L 2 ID 2iD(sat) iD (sat) = 2 [vDS(sat)]2
Page VI.310
COMPARATOR DESIGN PROCEDURE 1. Set the output current to meet the slew rate requirements. dV i = C dt 2. Determine the minimum sizes for M6 and M7 for the proper ouput voltage swing. vDS (sat) = 2ID
3. Knowing the second stage current and minimum device size for M6, calculate the second stage gain. A2 = g m6 g ds6 + g ds7
4. Calculate the required first stage gain from A2 and gain specifications. 5. Determine the current in the first stage based upon proper mirroring and minimum values for M6 and M7. Verify that Pdiss is met. 6. Calculate the device size of M1 from A1 and I DS1. A1 = g g m1 ds1 + g ds3 and gm1 = 2K'W/L IDS1
7. Design minimum device size for M5 based on negative CMR requirement using the following (IDS1 = 0.5IDS5): vG1(min) = VSS + VDS5 + where VDS5 = IDS5 1 + VT1(max)
2IDS5 5 = VDS5(sat)
8. Increase either M5 or M7 for proper mirroring. 9. Design M4 for proper positive CMR using: vG1(max) = VDD IDS5 3  VTO3 (max) + VT1
Page VI.311
DESIGN OF A TWOSTAGE COMPARATOR Specifications: Avo > 66 dB Pdiss < 10 mW CL = 2 pF tprop < 1 s CMR = 46 V Output swing is VDD  2V and VSS + 2V 1). For t prop << 1 s choose slew rate at 100 V/s I7 = CL dvOUT . 12 . 6 dt = ( 2 10 ) ( 100 10 ) = 200 A Lambda = 0.05V1 (L = 5 m) VDD = 10 V VSS = 0 V K'W Recall that = L
2). Size M6 and M7 to get proper output swing, M7: 2V > vDS7(sat) = M6: 2V > vDS6(sat) = 2( IOUT+I7) = 6 W6 2(400A) L6 > 12.5 8.0 A/V 2( W6/L6) 2I7 7 = W7 2(200A) L7 > 5.88 17.0A/V 2( W7/L7)
Page VI.312
COMPARATOR DESIGN  CONT'D S4 5). Assuming vGS4 = v GS6, then I4 = S6 I6 1 choose S 4 = 1 which gives I4 = 12.5 (200A) = 16.0 A S5 200 A Assume S5 = 1 which gives I 5 = I = 7 S7 5.88 = 34 A 1 and I4 = I5 = 17 A 2 W to keep L ratios greater than 1. Choose I 4 = 17 A W4 W 6 17 I5 = 34 A = 1.06 1.0 L4 = L6 200 Pdiss = 10( I 7 + I 5 ) = 2.34 mW < 10 mW 1 6). A1 = + 1 4 W1 L = 200 1 2KN'W1 W1 I 2 4 = 200 = ( + )A [ 1 4 1 ] I4L 1 L1 2KN' (Good for noise)
I5 1  VT1(max)
8). S5 =
Page VI.313
34 A = 2.76.10 6 ( 1 0  6  1 + 0 . 5) 2 W3 (2.76)(2) W3 W 4 L = = 0.69 8 L3 = L4 > 0.69 3 W4 (Previously showed L > 1.06 so no modification is necessary) 4 10). Summary
W Wdrawn = (L  1.6) L Design Ratios Actual Values with 5m minimum geometry Proper Mirroring and LD = 0.8m
W1 L1 W3 L3 W5 L5 W6 L6 W7 L7
W1 L1 W3 L3 W5 L5 W6 L6 W7 L7
Page VII.41
MP3 MP8
MP4
vOUT
MN11
MN25
MN10
v2
v1
MN24
MN7
MN9
MN5
V SS
where R out (rds5gm11rds11)((rds4rds2)gm13rds13) = =g 1 ds5gds11 (gds2+gds4)gds13 gm11 + gm13 gm1 +gm2 vin ds5gds11 (gds2+gds4)gds13 gm11 + gm13
The small signal voltage gain is vout = r out (i2i1) = (gm2 +gm1 )Rout vin = g
Page VII.42
FOLDED CASCODE CMOS COMPARATOR  CONTINUED Frequency Response Small signal modelC1 i1 gm12 gm2 v1 C2 gm13 1 i2 i2 i1 + C3 rout vout 
gm1 v2
where C1 = C GS12 + C BS12 + C DG3 + C BD3 C2 = C GS13 + C BS13 + C DG4 + C BD4 and C3 = CDG11 + CBD11 + CDG13 + CBD13 + CLoad AVD03 AVD(s) s + 3 where 1 3 = routC3 Typical performanceW 1 W 2 W 11 W 13 ID1 = ID2 = 50A and ID3= I D4 = 100A, L1 = L2 = L11 = L13 =1, assume C 3 0.5pF, and using the values of Table 3.12 gives: gm1 = gm2 = gm11 =41.2 S gds5 = gds11 = 0.5S gm13 = 28.3S
Therefore, rout = 121M, 3 = 16.553krps, and AVD0 = 4,978 resulting in a gainbandwidth of 13.11MHz. C 3V 0.5pFx10V Delay = T = I = 100A = 50nS max
Page VII.43
BIAS
M1
M6 M8 M10 vO
M2
M3
+ M9 M7 M11
M4
M5
Performance (ISET = 50 A) Rise time = 100 ns into 50 pF Fall time Propagation delay = 1 s Slew rate = 2.7 Volts/s Loop Gain = 32,000
Comments The inverter pair of M8M9 and M10M11 are for the purpose of providing an output drive capability and minimizing the propagation delay.
Page VII.44
V DD
V DD
M8
M6
BIAS M2 M9 M4
M1
VPB
vO + M3 M5
VNB
M7
V SS
M6 and M7 provide a current, pushpull output drive capability similiar to the current , pushpull CMOS OP amp.
Page VII.61
Comparator threshold
Time
Comparator output
Comparator with Hysteresis vin vout VTRP+ VTRPTime vin VTRPVTRP+ comparator output
Page VII.62
vB vA
+ R2 + V  REF
vB
R1
VOL
VOLR1 R1 +R2
vOUT
R1 V R2 OL
vIN
Page VII.63
M1
M2 vO
BIAS M9
M5 M7 VSS
(1). Positive feedback gives hysteresis. (2). Also speeds up the propagation delay time.
6.0V
5.0V
4.0V
3.0V
2.0V
Page VII.64
200m
0m
200m
400m
600m
Page VII.65
+
VOS +
IDEAL
+
+ VOS
IDEAL CAZ + V  OS
VIN
VOS + VOS +
+ 
IDEAL
+ 0V 
Page VII.66
vIN+ vIN
+ 1 + CAZ
VOS IDEAL + VOS
vOUT
Good for inverting or noninverting when the other terminal is not on ground.
Page VII.67
Page VII.61
+ vIN 
C1
C2
C3
Cn
Latch
Q Q
n firstorder, openloop comparators with identical gains, A Concept: voltage High Output Level
A5 A4 A3 A2 A t3 tL
Propagation delay time = t3 + tL for n=3 Answer: tp(min) occurs when n=6 and A=2.72=e Implementation: n=3 and A6 gave nearly the same result with less area.
[Ref: Doernberg et al., A 10bit 5 MSPS CMOS TwoStep FLASH ADCJSSC April 1989 pp 241249]
Page VII.62
+ vIN 
+ 
+ 
+ 
Latch
Q Q
VDD
Q FB Reset Q FB
VB1
LATCH
VB2 VSS
vIN
_ +
+ VOS 
Page VII.71
Positive feedback is used for regenerative comparators. Use autozeroing to remove offset voltages (charge injection is limit). Fastest comparators using lowgain, fast open loop amplifiers cascaded with a latch.
Page VII.01
VIII. SIMPLE CMOS OPERATIONAL AMPLIFIERS (OP AMPS) AND OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS (OTA'S)
Contents VIII.1 VIII.2 VIII.3 Organization
Chapter 10 D/A and A/D Converters
SYSTEMS
CIRCUITS
Chapter 5 CMOS Subcircuits SIMPLE Chapter 6 CMOS Amplifiers
DEVICES
Op Amp Characteristics
Nonideal model for an op amp
V 1
icm
CMRR V 2 V os V 1 I n
2
I b2
2
n C
R id + Ideal
out
id
icm
I b1
Boundary Conditions Process Specification Supply Voltage Supply Current Temperature Range Typical Specifications Gain Gainbandwidth Settling Time Slew Rate Input CMR CMRR PSRR Output Swing Output Resistance Offset Noise Layout Area
Requirement See Tables 3.11 and 3.12 +5 V 10% 100 A 0 to 70C 80 dB 10 MHz 0.1 sec 2 V/sec 2 V 60 dB 60 dB 2 VPP Capacitive load only 5 mV 50nV/ Hz at 1KHz 10,000 square m
Gain, dB
6dB/oct GB 2
0 dB
Frequency
180
90
Power supply rejection ratio (PSRR): vout vin (v ps =0) A vd(s) VDD PSRR = Avd(s) = Aps(s) = vout vOUT vps (v in=0) Commonmode input range (ICMR). Maximum common mode signal range over which the differential voltage gain of the op amp remains constant. Maximum and minimum output voltage swing. Slew rate:
vOUT Slew rate = max t
10V
5V Output Voltage 0V
5V
10V 0s
Settling Time
1.4 1.2
Upper tolerance
1 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14
Vout(t)
Lower tolerance
Settling time
Time (sec)
Design Approach
Design
Specifications
Iterate
Analysis Simulation
Modify
Specifications: Gain Output voltage swing Settling time Power dissipation Supply voltage Silicon area Bandwidth PSRR CMRR Noise Commonmode input range
Design Strategy
The design process involves two distinct activities: Architecture Design Find an architecture already available and adapt it to present requirements Create a new architecture that can meet requirements Component Design Design transistor sizes Design compensation network If available architectures do not meet requirements, then an existing architecture must be modified, or a new one designed. Once a satisfactory architecture has been obtained, then devices and the compensation network must be designed.
Op Amp Architecture
VDD
M3 M1
M4 M6 M2
IBias M5
Compensation
vOUT
M7
Compensation
In virtually all op amp applications, feedback will be applied around the amplifier. Therefore, stable performance requires that the amplifier be compensated. Essentially we desire that the loop gain be less than unity when the phase shift around the loop is greater than 135
A
OUT
+
IN
OUT A = IN 1 + A
Goal: 1 + A > 0 Rule of thumb: arg[A] < 135 at mag[A ] = 1
A (dB)
GB 0 dB 1 2
Frequency
12dB/oct
0o Frequency
3 2 1
1.0V
1 = 1000 rps
0.5V
Case 1: 2 = 1 x 106 rps Case 2: 2 = 0.5 x 106 rps Case 3: 2 = 0.25 x 106 rps
Types of Compensation 1. Miller  Use of a capacitor feeding back around a highgain, inverting stage. Miller capacitor only Miller capacitor with an unitygain buffer to block the forward path through the compensation capacitor. Can eliminate the RHP zero. Miller with a nulling resistor. Similar to Miller but with an added series resistance to gain control over the RHP zero. 2. Self compensating  Load capacitor compensates the op amp (later). 3. Feedforward  Bypassing a positive gain amplifier resulting in phase lead. Gain can be less than unity.
Miller Compensation
VDD
M3 M1 CM
M4 M2 Cc M6 v OUT C1
IBias M5
+
CL
M7
Smallsignal model
1 gds2+g ds4 v gm1 in 2 CM r ds1 Cc 1 gds6 +gds7
+
v1
gm4v 1 1 gm3 v g m2 in 2
+
v2 C1
+
gm6 v2 CL vout
+
vin gm1vin
+
v2 C1
+
gm6v2 CL vout
Analysis
(gmI)(gmII)(RI)(RII)(1  sCc/gmII) Vo(s) = Vin(s) 1 + s[RI(C1 + Cc) + RII(CL + Cc) + gmIIRIRIICc] + s2RIRII[C1CL + Cc(C1+ CL)] p1 g 1 mII RI RII Cc
z1 =
where
gmI = gm1 = gm2 gmII = gm6
RI = g
1 ds2+gds4
RII = g
1 ds6+gds7
Miller Compensation
After compensation 1 2
GB
Frequency
12dB/oct
180o Before compensation Arg[A] 90o After compensation Phase margin Frequency
0o
Conditions for Stability Unitygainbandwith is given as: GB = Av(0)p1 = ( gmIgmIIRIRII) 1 gmI = C c gmIIRIRIICc
If 60 phase margin is required, then the following relationships apply: gmII 10gmI Cc > Cc Furthermore, gmII 2.2gm I C2 > Cc which after substitution gives: C c > 0.22C 2 Note:
gmI = gm1 = gm2 and gmII = gm6
g m II > 10g m I
M6
M1
M2 RZ
Cc
V OUT
CII
Vbias
M7 M5
RZ +
vin gmI vin
Cc
+
v2
+ RI
CI gmII v2
RII
CII vout
VI sCc gmIVin + R + sCIVI + (VI Vo) = 0 I 1 + sCcRz Vo sCc gmIIVI + R + sCIIVo + (Vo VI) = 0 II 1 + sCcRz These equations can be solved to give Vo(s) a{1 s[(Cc/gmII) RzCc]} Vin(s) = 1 + bs + cs2 + ds3 where a = gmIgmIIRIRII b = (CII + Cc)RII + (CI + Cc)RI + gmIIRIRIICc + RzCc
Allen and Holberg  CMOS Analog Circuit Design c = [RIRII(CICII + CcCI + CcCII) + RzCc(RICI + RIICII)] d = RIRIIRzCICIICc If Rz is assumed to be less than RI or RII and the poles widely spaced, then the roots are p1 1 1 g R RC (1 + gmIIRII)RICc mII II I c gmII C CICII + CcCI + CcCII II gmIICc
p2
1 p3 = R C z I and z1 = By setting Rz = 1/gmII The RHP zero moves to infinity 1 Cc(1/gmII Rz)
M6
M1
M2
MZ
Cc
V OUT
CII
Vbias
M7 M5
VDD M6 M3 M4
Cc
vout
vin +
M1
M2
CL
VSS Figure 6.31 Schematic of an unbuffered, twostage CMOS op amp Important with relationships: an nchannel input pair. gm1 = gm2 = gmI, gm6 = gmII, gds2 + gds4 = GI, and gds6 + gds7 = GII.
Slew rate SR = I5 Cc gm1 gds2 + gds4 gm6 gds6 + gds7 = 2gm1 I5( 2 + 4) = gm6 I6( 6 + 7) (1)
+ VBias 
M5
M7
(2)
(3)
gm1 Cc
(4)
(5)
(6)
(7)
1
2IDS
+ VT1(max) + VDS5(sat)
(8)
Saturation voltageVDS(sat) =
(9)
All transistors are in saturation for the above relationships. The following design procedure assumes that specifications for the following parameters are given. 1. 2. 3. 4. 5. 6. 7. Gain at dc, Av(0) Gainbandwidth, GB Input commonmode range, ICMR Load Capacitance, CL Slewrate, SR Output voltage swing Power dissipation, Pdiss
Choose a device length to establish of the channellength modulation parameter . Design the compensation capacitor Cc. It was shown that placing the loading pole p2 2.2 times higher than the GB permitted a 60 phase margin (assuming that the RHP zero z1 is placed at or beyond ten times GB). This results in the following requirement for the minimum value for Cc. Cc > (2.2/10) CL Next, determine the minimum value for the tail current I5, based upon slewrate requirements. Using Eq. (1), the value for I5 is determined to be I5 = SR (Cc) If the slewrate specification is not given, then one can choose a value based upon settlingtime requirements. Determine a value that is roughly ten times faster than the settlingtime specification, assuming that the output slews approximately onehalf of the supply rail. The value of I5 resulting from this calculation can be changed later if need be. The aspect ratio of M3 can now be determined by using the requirement for positive input commonmode range. The following design equation for (W/L)3 was derived from Eq. (7). S 3 = ( W /L )3 = I5 (K'3) [VDD Vin(max) VT03(max) + VT1(min)]2
If the value determined for (W/L)3 is less than one, then it should be increased to a value that minimizes the product of W and L. This minimizes the area of the gate region, which
Allen and Holberg  CMOS Analog Circuit Design in turn reduces the gate capacitance. This gate capacitance will affect a polezero pair which causes a small degradation in phase margin. Requirements for the transconductance of the input transistors can be determined from knowledge of Cc and GB. The transconductance gm2 can be calculated using the following equation gm1 = GB (Cc) The aspect ratio (W/L)1 is directly obtainable from gm1 as shown below g2 m1 S1 = (W/L)1 = (K' )(I ) 2 5 Enough information is now available to calculate the saturation voltage of transistor M5. Using the negative ICMR equation, calculate VDS5 using the following relationship derived from Eq. (8). I5 VDS5 = Vin(min) VSS 1
1/2
VT1(max)
If the value for VDS5 is less than about 100 mV then the possibility of a rather large (W/L)5 may result. This may not be acceptable. If the value for VDS5 is less than zero, then the ICMR specification may be too stringent. To solve this problem, I5 can be reduced or (W/L)1 increased. The effects of these changes must be accounted for in previous design steps. One must iterate until the desired result is achieved. With VDS5 determined, (W/L)5 can be extracted using Eq. (9) in the following way S 5 = ( W /L )5 = 2(I5) K'5(VDS5)2
For a phase margin of 60, the location of the loading pole was assumed to be placed at 2.2 times GB. Based upon this assumption and the relationship for p2 in Eq. (5), the transconductance gm6 can be determined using the following relationship gm6 = 2.2(gm2)(CL/Cc) Since S3 is known as well as gm6 and gm3, assuming balanced conditions, gm6 S6 = S3 g m3 I6 can be calculated from the consideration of the proper mirroring of firststage the current mirror load of Fig. 6.31. For accurate current mirroring, we want VSD3 to be equal to VSD4. This will occur if VSG4 is equal to VSG6. VSG4 will be equal to VSG6 if
Allen and Holberg  CMOS Analog Circuit Design (W/L)6 S 6 I6 = (W/L) I1 = S I1 4 4 Choose the larger of these two values for I6 (Eq. 19 or Eq. 20). If the larger value is found in Eq (19), then (W/L)6 must be increased to satisfy Eq. (20). If the larger value is found in Eq. (20), then no other adjustments must be made. One also should check the power dissipation requirements since I6 will most likely determine the majority of the power dissipation. The device size of M7 can be determined from the balance equation given below I6 I6 S7 = (W/L)7 = (W/L)5 = S5 I5 I5 The firstcut design of all W/L ratios are now complete. Fig. 6.32 illustrates the above design procedure showing the various design relationships and where they apply in the twostage CMOS op amp.
VDD
VSG6 +
Vout(max)
M6
I6
M3
M4
Cc
vin +
g GB = m1 Cc
M1
I5
M2
I5 = SRCc
Vout(min)
M5 VSS
M7
Figure 6.32 Illustration of the design relationships and the circuit for a twostage CMOS op amp.
At this point in the design procedure, the total amplifier gain must be checked against the specifications. Av = (2)(gm2)(gm6) I5( 2 + 3)I6( 6 + 7)
If the gain is too low, a number of things can be adjusted. The best way to do this is to use the table below, which shows the effects of various device sizes and currents on the
Allen and Holberg  CMOS Analog Circuit Design different parameters generally specified. Each adjustment may require another pass through this design procedure in order to insure that all specifications have been met. Table 6.32 summarizes the above design procedure.
Increase DC Gain Increase GB Increase RHP Zero Increase Slew Rate Increase CL
Design Procedure:
This design procedure assumes that the gain at dc (Av), unity gain bandwidth (GB), input common mode range (Vin(min) and Vin(max)), load capacitance (CL), slew rate (SR ), settling time (Ts), output voltage swing (Vout(max) and Vout(min)), and power dissipation (Pdiss) are given. 1. 2. Choose the smallest device length which will keep the channel modulation parameter constant and give good matching for current mirrors. From the desired phase margin, choose the minimum value for Cc, i.e. for a 60 phase margin we use the following relationship. This assumes that z 10GB. Cc > 0.22 CL 3. Determine the minimum value for the tail current (I5) from the largest of the two values. I5 = SR .Cc VDD + VSS I5 10 . 2 Ts 4. Design for S3 from the maximum input voltage specification. S3 = 5. I5 K'3[VDD Vin(max) VT03(max) + VT1(min)]2 1
Verify that the pole of M3 due to Cgs3 and Cgs4 (=0.67W3L3Cox) will not be dominant by assuming it to be greater than 10 GB gm3 2Cgs3 > 10GB .
6.
Design for S1 (S2) to achieve the desired GB. gm1 = GB . Cc S2 = gm2 K'2I5
2
7.
Design for S5 from the minimum input voltage. First calculate VDS5(sat) then find S5. VDS5(sat) = Vin(min) VSS S5 = 2I5 K'5[VDS5(sat)]2 I5
VT1(max) 100 mV
Allen and Holberg  CMOS Analog Circuit Design 8. Find gm6 and S6 by the relationship relating to phase margin, load, and compensation capacitors, and the balance condition. gm6 = 2.2gm2(CL/Cc) gm6 S6 = S3 g m3 9. Calculate I6 : I6 = (S6/S4)I4 = (S6/S4)(I5/2) 10. Design S7 to achieve the desired current ratios between I5 and I6. S7 = (I6/I5)S5 11. Check gain and power dissipation specifications. Av = 2gm2gm6 I5( 2 + 3)I6( 6 + 7)
Pdiss = (I5 + I6)(VDD + VSS) 12. If the gain specification is not met, then the currents, I5 and I6, can be decreased or the W/L ratios of M2 and/or M6 increased. The previous calculations must be rechecked to insure that they have been satisfied. If the power dissipation is too high, then one can only reduce the currents I5 and I6. Reduction of currents will probably necessitate increase of some of the W/L ratios in order to satisfy input and output swings. 13. Simulate the circuit to check to see that all specifications are met.
Therefore
Allen and Holberg  CMOS Analog Circuit Design 30 106  .85 = 0.35V 110 1063
Using VDS5 calculate (W/L)5 from Eq. (16) (W/L)5 = 2(30 106) = 4.49 4.5 (50 106)(0.35)2
From Eq. (20) of Sec. 6.2, we know that gm6 10gm1 942.5S Assuming that gm6 = 942.5S (W/L)6 = 15 942.5 106 = 94.25 150 106
Using the equations for proper mirroring, I6 is determined to be I6 = (15 106)(94.25/15) = 94.25 A Finally, calculate (W/L)7 94.25 106 (W/L)7 = 4.5 14.14 30 106 Check the Vout(min) specification although the W/L of M7 is so large that this is probably not necessary. The value of Vout(min) is Vmin(out) = VDS7(sat) = 2 94.25 = 0.348V 110 14.14
which is much less than required. At this point, the firstcut design is complete. Examining the results shows that the large value of M7 is due to the large value of M5 which in turn is due to a tight specification on the negative input common mode range. To reduce these values the specification should be loosened or a different architecture (i.e. pchannel input pair) examined. Now check to see that the gain specification has been met Av = (2)(94.25 106)(942.5 106) = 19,240 30 106(.04 + .05)38 106(.04 + .05)
Organization
Chapter 10 D/A and A/D Converters
SYSTEMS
CIRCUITS
Chapter 5 CMOS Subcircuits SIMPLE Chapter 6 CMOS Amplifiers
DEVICES
IX.1 IMPROVING THE TWOSTAGE ARCHITECTURE Amplifiers Using an MOS Output Stage PUSHPULL CMOS OTA This amplifier is a simple extension of the seventransistor OTA studied in Section 8.
VDD
VDD
M9
M7
VDD vOUT
M1 M8
VDD
M2 + Cc CL M6
M3
M4
Network equations: [g1 + s(C1 + CL)]v1  sCcv2 = gm1vi gm1AIvi 2 i7 AI is the current gain from M1 to M7: AI = i 1 g m6 z= AI Cc 1 2 g1g2 p1 gm6Cc g m6 p2 C L gm1gm6 AV g g 1 2 [g5 + sCc]v1 + [g2 + s(Cc + CL)]v2 = To guarantee that the zero stays in the lefthalf plane, AI > 2
Example:
VDD VDD
VDD
M9
M7
VDD
VDD
M9
M7
VDD
M8
M1
VDD
M2
+
Cc CL
M6
M1
M2
+
Cc CL
M6
M3
M4
M3
M4
PushPull (AI 3)
Standard (AI = 0)
Standard phase
10
10
10
10
10
10
10
10
Frequency
IX.2 TwoStage Cascode Architecture Why Cascode Op Amps? Control the frequency behavior Increase PSRR Simplifies design
Where is the Cascode Technique Applied? First stage Good noise performance Requires level translation to second stage Requires Miller compensation Second stage Self compensating Reduces the efficiency of the Miller compensation Increases PSRR
Definition:
+ vdd + vin vss + + vout + VSS VDD
Calculation of PSRR:
+ vdd + vout + K VSS Addvdd v1 vout Av (v1 v2 )
VDD
=>
v2
vout = Addvdd + A v(v1v2) = A ddvdd  Avvout vout(1 + Av) = A ddvdd vout Add A dd 1 = = vdd 1 + Av Av PSRR+
Extends bandwidth beyond GB
+ vdd 
+ 
VDD
1.) The M7 current sink causes VGS6 to act like a battery. 2.) Therefore, vdd
M6
M3
M4
M1
M2
Cc
+
M7
M5
+
VBias
VSS + 
model
Must reduce C c !
60 to 80dB
VDD
M3
M4 M6
M1
M2
Cc
M5
+
M7
vout
+
VBias
?
+ vss VSS + 
+
VBias
+
+ vss VSS + VBias
vss VSS + + 
Transconductance injection
Capacitance injection
Intuitive Interpretation of the Negative PSRR for the TwoStage OTA Continued Transconductance injection: Path through the input stage: Not important as long as CMRR is high. Path through the output stage: vout issRout = gm7 vssRout
0dB Vout Vss 20 to 40 dB
vout vss = g m7Rout Frequency dependence 1 Rout Rout sCout Capacitance injection:
+ vss Vout Vss 0dB 1 Rout C gd7
1 Rout Cout
60 to 80dB
Reduce Cgd7!
Problems with the twostage OTA: Insufficient gain Poor stability for large load capacitance Poor PSRR These problems can be addressed using various cascode structures.
We will consider several approaches: Cascoding the first stage Cascoding the second stage Folded cascode
VDD
M3
M4
VDD
MC2
VDD
VO1
MC1
+ M1 M2
VBIAS VSS
gmcrdsc 2
Requires voltage translation to drive next stage Requires additional biasing for cascode devices Commonmode problem at drains of M1 and M2
VDD
M3
M4 ICM
VDD
VBP
MC2
VDD
VO1
MC3
MC1
+ M1
M9 M2
VBIAS VSS
Commonmode circuitry (M9) maintains Vds of M1 and M2 A V = gm1ro1 ro1 (gmc2rdsc2)rds4  (gmc1rdsc1)rds2 1 p1 C r L o1 GB A Vp1 gm1 CL
Output range of this amplifier is poor when used by itself. It needs an output stage to be practical.
M3
M4
ICM VBP
ICM
vin 2 VSS
vin vin 2 2 M1
VSS
VSS
I5 +ICM
VSS
M2 VBIAS M5 VSS M7
M3 VB1 M8
M4
M6 Cc
M9 M1 M2
vOUT
M5 VB2 M7 VSS
+PSRR is reduced by M9
M9 M1 VBIAS M5 VSS M2
M7
VDD M3 M4 M6
VBP
MC6
Comp
Vo
M1
M2
VBN
MC5
VBIAS M5 VSS
M7
VDD M9 VDD MC3 VBP VDD M1 M5 VBIAS M8 M7 I5 M2 VBN + MC1 VSS CL VDD M3 M4 VDD M6 MC2 VBP VDD
VDD
VSS
Design Example Pertinent design equations: iOUT SR = C L AV = GB = gm2 2(gm4) (gm6 + gm7 ) ro g m2 (g m6 + g m7 ) 2(gm4)CL I5 3  VT3(max) + V T1(min) I5 1 + VT1(max)
Vin(max) = VDD 
Vin(min) = VSS + VDS5 + Specifications: VDD = VSS = 5V SR = 5V/s into CL = 50pf GB = 5 MHz AV > 5000 CMR = 3V Output swing = 3V
Design Procedure 1.) Design for maximum source/sink current Isource/sink = C L(SR) = 50pf(5V/s) = 250 A 2.) Note that S6 Max. IOUT (source) = S I5 4 Max. IOUT (Sink) = Max. IOUT (source) if S3 = S 4, S9 = S6 and S7 = S 8
3.) Choose I 5 = 100 A S 9 = S 6 = 2.5 S 4 = 2.5 S 3 4.) Design for 3V output capability a.) Negative peak Let VDSC1(sat.) = V DS7(sat.) = 1V under negative peak conditions, IC1 = I 7 = 250 A Divide 2V equally, 2V = 2I7 + KN'S7 2IC1 =2 KN'SC1 2I7 KN'S7 = 2 500 A 17 A/V 2 S 7
S 7 = S C1 = 29.4
> S 8 = S 7 = 29.4
b.) Positive peak, divide voltage equally, VSD6 = VSDC2 = 1V , > 2V = S 6 = S C2 = 62.5 5.) Design of VBP and V BN a.) VBN (Assume max. I OUT (sink) conditions)
IOUT(sink) = 250 A MC1 VBN 3 5V 4 M7 5
2I6 + KP'S6
2IC2 =2 KP'SC2
2I6 KP'S6
> S 3 = S 4 = 25
VDSC1 = VGSC1  V TC1 (ignoring bulk effects) 1 = VGSC1 1 > VGSC1 = 2V V BN = 2V
+4 VBP MC2
6.) Check max. Vin influence on S3 (S4) Vin (max) = VDD +3 = +5 S3 = I5 3  VT03max + VT1(min) 100 A  1.2 + 0.8 KP'S3
With S 3 = 25, V in (max) = 3.89V which exceeds the specification. 7.) Find gm1 (gm2) a.) AV specification gm1 g m6 + g m 7 R II AV = gm4 2 gm4 = gm6 = gm7 = 2I4Kp'S4 = 141.1 s 2I6KP'S6 = 353.5 s 2I7KN'S7 = 353.5 s
gmc1 = gm7 gmc2 = gm6 1 rds6 = rdsc2 = I = 0.4 M 6 P 1 rds7 = rdsc1 = I7 = 0.8 M RII (gmc1rdsc1rds7)  (gmc2rdsc2rds6) = 45.25 M
gm1 707 s ( 226.24 M  56.56 M ) > 5000 V/V 141.1 2
gm1 > 44 s
b.) GB specification GB = gm1 = g m1 (g m6 + g m7 ) (50pF) = 10.10 6 rps 2gm4 (10 .106)(141.1.106)(50.1012) = 627 S 707.106/2
gm 2 = 231 S 1 = S2 = I5K N ' gm1gm6+gm7 627 707S R II = (45.25M ) = 71,080 gm4 2 141.1 2 8.) Find S5 from Vin (min) AV = Vin (min) = VSS + VDS5 + 3 = 5 + VDS5 + I5 1 + VT1(max) 100 A + 1.2 A 17 2 S 1 V
V DS5 = 0.8 
S5 = 9.) VBIAS 
10.) Summary of design S1 = S2 = 231 S3 = S4 = 25 S5 = 28.6 S6 = S9 = SC2 = SC3 = 62.5 11.) Check on power dissipation Pdiss = 10(I8 + I5 + I7) = 10(125A + 100A + 125A) = 3.5mW 12.) Design W's for lateral diffusion and simulate S7 = S8 = SC1 = 29.4 VBP = 2V VBN = 2V VBIAS = 3.359V
1.5 I
1.5 I
VBP
M3 I vIN M5
v+ IN
M1 M2
I M7 M8
VSS
Currents in upper current sinks must be greater than I to avoid zero current in the cascode mirror (M5M8). Advantages Good input CMR. Good frequency response. Self compensating.
M1 M2
+ M9
VB3 Cc M16
M14 V OUT
M8
VB1
M12 VSS
M13
+ + + R R 
VDD
+ Vin CL
VDD 
VDD + CL
Common mode feedback
VBIAS
Vout
VSS
MP2A VDD MP2 vOUT + CL VSS MN2 MN1 VSS VSS VSS MN1A VBIAS4 VSS MN2A VBIAS3 VDD VBIAS2
CL + vIN 
v+ IN
vOUT vIN v+ IN
vIN
vOUT
VB1 VSS
VSS
combine
M17
M12
M11
VB2
M14
v+ IN v+ IN
M1
M2
vIN
M3
M4
vIN
M18
VB1
M10
M9
M13
M17
M12
M11
M14
M5 v+ OUT v+ IN M7 M1 M2
M6 vIN M8 vOUT
M3 I
M4 I
M18
M10
M9
M13
DC problem solved, but amplifier has low gain and requires CM feedback
M12
M11 VB3 M6
M1
M2 M8
vIN VB4
M3
M4
I M10 M9 M13
IX.5 LOW POWER AMPLIFIERS General Objective is to minimize the dc power dissipation. Typical applications are: 1. Battery powered circuits. 2. Biomedical instrumentation. 3. Low power analog "VLSI." Weak Inversion or Subthreshold Operation Drain current qvGS W iD = I D exp nkT ( 1 + lv D S) L
rds ( iD )1
iD
square law
exponential
VT
vGS
Consider the twostage op amp with reduced currents and power supplieds, AV = where, gm1 ID1 GB = C = (n kT/q)C 1 and 2ID1 n1kT SR = C = 2GB q gm2 gm6 1 = n2n6( kT/q) 2( l2+l4) ( l6+l7) ( gds2+gds4) ( gds6+gds7)
VDD
M3
M4 M6 C
M1
M2
M5
M7
VSS
Design Example
Calculate the gain, unitygain bandwidth, and slew rate of the previous twostage op amp used in weak inversion if: ID5 = 200nA L = 10 m C = 5pF nP = 1.5 P = 0.02V1 N = 0.01V1
nN = 2.5
T = 27C
SR = 2(153.85.103)(2.5)(0.026) = 0.04V/s If V DD = V SS = 2.5, the power dissipation is 0.2W assuming ID7 = I D5.
CC
VB
M9
M5 M7
CC
M5 M13 M7
VB
M9
VSS
VDD
M3 M8
M4 M6
M1
M2
VB1
M10
VDD CC
VB2 VB
M9 M5 M11 M7
VSS
VSS
Micropower Op Amp
VDD
M9 M5 M7 M8 M6 M10 M16
va v1
M3 M4
vb
M15
M18 100nA
v+ 2
M17
vo
M19
VBIAS
M11
M2
120nA
VSS Pdiss = VDD VSS(260nA) vo = vagm9ro  vbgm10ro g m9ro(va  vb) where ro (rds10gm18rds18)(rds12gm19rds19) and nP 1 + k (va  vb) = va  vb = n 1  k ( v 2  v 1 ) N ; gm9 = gm10
SmallSignal Analysis va
gm3 v1 1 gm5 gm8 vb gm7 va 1 gm6
vb
gm4 v2
gm3 g m8 va = v1 g  vb g m5 m5 gm4 g m7 vb = v2 v a gm6 gm6 gm3 v1g m5 v2gm4 gm6
m5
1 gm7 g
m4
gm8 g
m5
1
va v
b
va =
gm3 v1g
m5
gm8 g 1 gm8 g
m5
gm4 v2g
m6
1 gm7 g
m4
gm 3 g m4 g m 8 v 1 g + v 2 g g m5 m5 m6 = g m7 g m 8 1gm5 gm6
1
vb =
1 gm7 g
m6
gm3 v1g
m5
gm4 v2g
m6
1 gm7 g
m4
gm8 g
m5
gm 4 g m3 g m 7 v 2 g + v 1 g g m6 m5 m6 = g m7 g m 8 1gm5 gm6
1
v a  vb =
gm3 g m4 g m 8 gm4 g m3 g m 7 v1 + v  v2 + v 2 1 gm5 gm5 gm6 gm6 gm5 gm6 g m7 g m 8 1 g g m5 m4
gm3 = gm4 = gmI ; gm5 = gm6 = gmII ; gm7 = gm8 = gmIII Then gmI g mI g mIII gmI g mI g mIII v1 + v v + v 2 2 1 gmII gmII2 gmII gmII2 v a  vb = g mIII 2 1gmII2 gmIII gmII = k
gmI gmII
Define:
1  k
I8 S 8 in W.I. gm is proportional to I I6 = S6 I 8 S8 I 7 S7 = = k; I6 S6 I5 = S5 = k Since under balanced conditions I 3 = I4 ; I4 = I5 I4 = I6 (1 + k) I3 = I5 (1 + k) Again, since gm I in weak inversion, then gm4 I 6(1 + k) or gm4 = I6 kT (1 + k) nN q
then
nP gmI = (1 + k) gmII nN
Need large sinking and source currents without having to have large quiescent currents. One possible solution uses "tail current boosting" Assume that S 3 = S4 = S11 = S13, S18 = AS17, S15 = S16 = S17 = ..
M11
M3 I1 I1 I2 M1 I2
M4
M13
I2 M2 +
I2 I1
A I2 I1
M18
M9
M10 M19
vIN
Positive feedback I10 iOUT (max/min) 1  Loop gain = I10 g m 1 8 gm 1 3 1 g m17 gm14 = I10 gm 1 3 1 g A m9
M8
M13
M14
M5A
M5B
vOUT
VBN
M6B
I10
M7 M15
M16 M17
M18 M9
M10 M19
M20 M21
M22
M6A VSS
A=2
1 vIN/ nVt
t/T
t/T
Switched resistor
Implementation of the Continuous Time Switched Resistor Realization using Dynamic Techniques
RFET
Switched resistor
1 + vIN 2
COS M1
VSS
During phase 2 the offset and bias of the inverter is sampled and applied to C OS and C B. During phase 1 COS is connected in series with the input and provides offset cancelling plus bias for M1. CB provides the bias for M2.
VDD + VB2 
2 M4
M8
VDD
M7
M3
VDD
IB
2 vIN
C2
1 v+ IN vOUT
C1 VSS M6 M2 VSS
1 M5 + VB1 
2 M1
VSS
M8
VDD
IB
VSS
M5
VSS
M4
VDD
vOUT
VSS
M1
VSS
2 M8 1 2
1 M4
VDD
M7 C2 RB vIN C4
M3
VDD
1 1
2 v+ IN vOUT
2 C1
C3 M2 VSS
VSS
M6
2 M5 1 2
1 M1
VSS
1.6 mW dissipation
Used with a 28.6 MHz clock to realize a 5th order switched capacitor filter with a cutoff frequency of 3.5 MHz.
Page X.01
SYSTEMS
CIRCUITS
Chapter 5 CMOS Subcircuits SIMPLE Chapter 6 CMOS Amplifiers
DEVICES
Page X.02
Page X.03
Multiplexer
Digital System
Reference
Transmission links Magnetic tape recorders Computer memories Paper tape recorders Realtime processor Comparators System and process controls Numerical machine controls Minicomputers Miroprocessors Etc.
Digital System
Filter
Amplifier
Audio systems Controllers Actuators CRT displays Analog recorders Analog computers Hybrid computers Analog meters Transducers Servomotors XY plotters Modems Etc.
Reference
Page X.11
X.1  CHARACTERIZATION AND DEFINITION OF CONVERTERS General Concept of DigitaltoAnalog (D/A) Converters
Reference
b0 b1 b2 b3
DigitaltoAnalog Converter
vOUT or iOUT
bN1
or iOUT = KIrefD
K = gain constant (independent of digital input) b1 b2 b N1 b0 D = N + N1 + N2 + + 1 = scaling factor 2 2 2 2 Vref (I ref ) = voltage (current) reference bN1 = most significant bit (MSB) b0 = least significant bit (LSB) For example, b1 b2 bN  1 b0 vOUT = KV ref N + N1 + N2 + + 2 2 2 21 N1 1 b j2 j = KVref N 2 j=0
Page X.12
Voltage References
Vref
Scaling Network
DVref
Output Amplifier
vOUT = KDVref
Binary Switches
b0 b1 b2
bN1
b0 b1 b2 Latch
V* out
bN1
Clock
Page X.13
Serial
Parallel
Charge
Voltage
Charge
Current
Page X.14
Static Characterization of D/A Converters Ideal inputoutput D/A converter Static Characteristic 1.000 0.875 0.750 Analog Ouput Value 1 LSB 0.625 0.500 0.375 0.250 0.125 0.000 000 Ideal analog output
001
010
110
111
Vref 2N
Page X.15
Definitions Resolution is the smallest analog change resulting from a 1 LSB digital change (quantified in terms of N bits). Quantization Noise is the inherent uncertainty in digitizing an anlog value with a finite resolution converter.
Infinite resolution analog output  finite resolution analog output 0.5LSB 0.5 VREF 2N = VREF 2 N+1
Digital Input Code 0.5LSB 000 0.5 001 010 011 VREF 2N = VREF 2 N+1
Dynamic range (DR) is the ratio of FS to the smallest resolvable difference. 2N 1 V REF FS 2N DR = LSB change = = 2N 1 1 VREF N 2 N DR(dB) = 20 log 10( 2 1) 6N dB Signal to noise ratio (SNR) for a sawtooth waveform Approximating FS = LSB(2N 1) LSB(2 N), 2N Full scale RMS value 12 N 2 2 SNR = RMS value of quantization noise = = 2 1 2 2 12 SNR (dB) = 20 log 10
6 6 2 N = 20 log 10 + 20 log10 (2 N) 2 2
Page X.16
Definitions  Continued Full scale (FS) is the the maximum DAC analog output value. It is one LSB less than V REF . FS = VREF 2N 1 2N
A monotonic D/A (A/D) converter is one in which an increasing digital input code (analog input) produces a continuously increasing analog output value (digital output code). Offset error is a constant shift of the actual finite resolution characteristic from the ideal infinite resolution characteristic. Gain error is a deviation between the actual finite resolution characteristic and the ideal infinite resolution characteristic which changes with the input . Integral nonlinearity (INL) is the maximum difference between the actual finite resolution characteristic and the infinite resolution characteristic. Differential nonlinearity (DNL) is the maximum deviation of any analog FS output changes caused by an input LSB change from its ideal change of N 2 .
Page X.17
VREF 7 8
001 1 8
010 2 8
011 3 8
100 4 8
101 5 8
110 6 8
111 7 8 8 8
Page X.18
7 8 5 8 3
Offset 8 Error
7 8
Gain Error
5 8 3 8 1 8 0
1 8 0
Offset Error
Gain Error
7 8 5 8 3 8 1 8 0
Nonlinearity
7 8 5 8 3 8 1 8 0
Nonmonotonicity
Linearity Error
Page X.19
Integral and Differential Linearity for a D/A Converter D/A Converter with 1.5 LSB integral nonlinearity and 0.5 LSB differential nonlinearity
10 9
0.5 LSB
8 7 6 5 4 3 2 1 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1011
1.5 LSB
Ideal
D/A converter with 1 LSB integral nonlinearity and 1 LSB differential nonlinearity
Ideal 0 LSB
10 9
8 7 6 5 4 3 2 1 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1011
1 LSB
2 LSB
Page X.21
X.2 VOLTAGE SCALING CONVERTERS 3BIT VOLTAGE SCALING D/A CONVERTER Assume that b0 = 1, b1 = 0, and b2 = 1 MSB: b2 LSB: b0
+VREF
R/2 8 R 7 R 6 R 5 R 4 R 3 R 2 R 1 R/2
b0
b0
b1
b1
b2
b2
vOUT
vOUT =
Page X.22
OUT
000
001
010
011
100
101
110
111
Input
Advantages: Inherent monotonicity Compatible with CMOS technology Small area if n < 8 bits Disadvantages: Large area if n > 8 bits Requires a high input impedance buffer at output Integral linearity depends on the resistor ratios
Page X.23
3BIT VOLTAGE SCALING D/A CONVERTER WHICH MINIMIZES THE SWITCHES Require time for the logic to perform
b0 +VREF
R/2 8 R 7 R 6 R 5 R 4 R 3 R 2 R 1 R/2
b1
b2
3to8 Decoder
vOUT
Page X.24
Accuracy Requirements of a Voltage Scaling D/A Find the accuracy requirements for the voltage scaling D/A converter as a function of the number of bits N if the resistor string is a 5 micron wide polysilicon strip. If the relative accuracy is 2%, what is the largest number of bits that can be resolved to within 0.5 LSB? Assume that the ideal voltage to ground across k resistors is kR V k = N VREF 2 R The worst case variation in Vk is found by assuming all resistors above this point in the string are maximum and below this are minimum. Therefore, V k' = kRminVREF
( 2Nk) R max + kR min
The difference between the ideal and worst case voltages is, Vk Vk' kRmin kR = VREF VREF 2NR ( 2Nk) R max + kR min Assuming that this difference should be less than 0.5 LSB gives, kRmin kR 0.5 < 2NR ( 2Nk) R max + kR min 2N Expressing Rmax as R+0.5R and Rmin as R0.5R and assuming the worst case occurs midway in the resistor string where k=0.5( 2N) and assuming that 5 micron polysilicon has a 2% relative accuracy gives, 0.5(R 0.5 R) 1 R 1 0 . 5  0.5(R + 0.5 R) + 0.5(R 0.5 R) = 4 R < 2 2N R 1 < N1 R 2 or 0.25(0.02) < 0.5( 2N) N = 6
Page X.25
2R
2R
b0
b1
b2
b N1
bN + VREF
Equivalent circuit at A:
R b0 VREF + 2 A
Equivalent circuit at B:
R R B 2R + b1 VREF +
0
B
1
+ b0 VREF 2
=

( b4 + b2 )V
REF
+ 
b0 2N
sign bit
bN
+ VREF
Page X.31
v OUT +
Terminating capacitor
VREF
Operation: 1.) During 1, all capacitors are discharged. 2.) During 2 , capacitors with bi = 1 are connected to VREF and capacitors with bi = 0 are grounded. 3.) The resulting output voltage is,
bN1C b N2 C/2 b N3 C/4 b 0 C / ( 2N1) vOUT = VREF 2C + 2C + 2C + ... + 2C
+ VREF 
Page X.32
Other Versions of the Charge Scaling D/A Converter Bipolar Operation: Charge all capacitors to V REF. If bi = 1, connect the capacitor to ground, if bi = 0, connect the capacitor to VREF. Will require an extra bit to decide whether to connect the capacitors initially to ground or to VREF.
FourQuadrant Operation: If VREF can have values, then a full, four quadrant DAC can be obtained.
Multiplying DAC: If VREF is an analog signal (sampled and held), then the output is the product of a digital word and an analog signal and is called a multiplying DAC (MDAC).
Page X.33
Influence of Capacitor Ratio Accurcy on No. of Bits Use the data of Fig.2.42 to estimate the number of bits possible for a charge scaling D/A converter assuming a worst case approach and the worst conditions occur at the midscale (1 = MSB). The ideal output of the charge scaling DA converter is, vOUT Ceq. VREF = 2C The worst case output of the charge scaling DA converter is, Ceq.(min) v'OUT VREF = 2C  C eq. (max) + C eq. (min) The difference between the ideal output and the worst case output is, vOUT v 'O U T Ceq.(min) 1 = VREF VREF 2 ( 2C  C eq.) (max) C eq.(min) Assuming the worst case condition occurs at midscale, then Ceq. = C vOUT v 'O U T VREF  VREF C(min) 1 = 2  C (max)  C (min)
If C(max) = C + 0.5C and C(min) = C  0.5C, then setting the difference between the ideal and worst case to 0.5LSB gives, 0.5( C (max) C (min))  C (min) 0.5( 1/2N) C (max) + C (min) or 1 C(max)  C (min) N ( C (max) + C (min)) 2 or C 1 2C 2N C 2C 2N C 1 C 2N1
A 50m x 50m unit capacitor gives a relative accuracy of 0.1% and N = 11 bits. It is more appropriate that the relative accuracy is a function of N. For example, if C/C 0.001 + 0.0001N, then N=9 bits.
Page X.34
Increasing the Number of Bits for a Charge Scaling D/A Converter Use a capacitive divider. For example, a 13bit DACLSB Array MSB Array
1.016pF (Attenuating capacitor) 1pF 2pF 4pF 8pF 16pF 32pF 1pF 2pF 4pF 8pF 16pF 32pF
+
64pF
v OUT
1pF b0 b0 b1 b1 b2 b2 b3 b3 b4 b4 b5 b5 b6 b6 b7 b7 b8 b8 b9 b9 b 10 b 10 b 11 b 11 b12 b 12
+VREF VREF
VL =
i=0
b iCi VREF 64
VR =
i=6
12
bi Ci VREF 127
vOUT
VL

VR

VR =
12 i=6
biVREFCi 127
and VL=
5 i=0
biVREFCi 64
or
biCi + 64
5 i=0
Page X.35
Removal of the Amplifier Input Capacitance Effects Use the binary weighted capacitors as the input to a charge amplifier. Example of A TwoStage Configuration:
VREF b b 1 0 0 b b b b b b b b b b 1 1 1 1 2 2 1 3 3 1 1 5 5 4 4 C 8 C 4 C 2 C 8 C 8 b b 1 6 6 C 4 b b 1 7 7 C 2
2C
v OUT
Page X.41
v OUT
C k2 2
k2
C1 2C
C0 C
C
2k1 C
C k=8 A
S0A S0B
Advantages: Resistor string is inherently monotonic so the first M bits are monotonic. Can remove voltage threshold offsets. Switching both busses A and B removes switch imperfections. Can make tradeoffs in performance between the resistors and capacitors. Example with 4 MSB's voltage scaling and 8 LSB's charge scaling:
Page X.42
Voltage Scaling, Charge Scaling DAC  Cont'd Operation: 1.) SF, SB, and S1B through Sk,B are closed discharging all capacitors. If the output of the DAC is applied to any circuit having a nonzero threshold, switch SB could be connected to this circuit to cancel this threshold effect. 2.) Switch SF is opened and buses A and B are connected across the resistor whose lower and upper voltage is V'REF and V'REF + 2MVREF respectively, where b1 b2 bM  1 b0 V'REF = V ref M + M1 + M2 + + 2 2 2 21
+ 2k1 C + 2MV
REF
2k2 C
2C
C
SA SB
A
S k,A S k1,A S k1,B
vOUT
S 2A S 2B
S k,B
+ V 'REF 
3.) Final step is to determine whether to connect the bottom plates of the capacitors to bus A (bi=1) or bus B (bi=0).
Ceq. 2MVREF + + V 'REF 2KC  Ceq. + vOUT vOUT = M+K1 i=0
bi2(M+Ki) VREF
Page X.43
Charge Scaling, Voltage Scaling DAC Use capacitors for MSB's and resistors for LSB's
vOUT 2N1C 2 N2C 2 N3C 4C 2C C
VREF
VREF
Switch network
MSBs
R LSBs
Page X.51
C1
C2
13/16
13/16
Close S4: VC2 = 0 Start with LSB firstClose S2 (b0=1): VC1 = VREF VREF Close S1: VC1 = 2 = VC2 Close S3 (b1=0): VC1 = 0 VREF Close S1: VC1 = VC2 = 4 Close S2 (b2=1): VC1 = VREF 5 Close S1: VC1 = VC2 = 8 VREF Close S2 (b3=1): VC1 = VREF 13 Close S1: VC1 = VC2 = 16 VREF
Comments: LSB must go first. n cycles to make an nbit DA conversion. Top plate parasitics add error. Switch parasitics add error.
Page X.52
1/2 b1 z
1
1/2 bN1 z
1
1/2
vOUT
MSB
VREF
Approaches: 1.) Pipeline with N cascaded stages. 2.) Algorithmic. vOUT(z) = bi z1VREF 1  0.5z  1
Page X.53
1 2
Assume that the digital word is 11001 in the order of MSB to LSB. The steps in the conversion are: 1.) VOUT(0) is zeroed. 2.) LSB = 1, switch A closed, VOUT (1) = VREF . 3.) Next LSB = 0, switch B closed, VOUT(2) = 0 + 0.5VREF VOUT (2) = 0.5V REF . 4.) Next LSB = 0, switch B closed, VOUT (3) = 0 + 0.25VREF VOUT (3) = 0.25VREF. 5.) Next LSB = 1, switch A closed, VOUT(4) = VREF + (1/8)VREF VOUT(4) = (9/8)VREF . 6.) Finally, the MSB is 1, switch A is closed, and VOUT(5) = VREF + (9/16)VREF VOUT(5) = (25/16)VREF 7.) Finally, the MSB+1 is 0 (always last cycle), switch A is closed, and VOUT(6) = (25/32)VREF
Page X.61
X.6  CHARACTERIZATION OF ANALOG TO DIGITAL CONVERTERS General A/D Converter Block Diagram
y(kTN)
A/D Converter Types 1.) Serial. 2.) Medium speed. 3.) High speed and high performance. 4.) New converters and techniques.
Page X.62
111
101
100
Ideal transition
011
000
1 FS 8
Allen and Holberg  CMOS Analog Circuit Design Nonideal Characteristics of A/D Converters
Page X.63
Offset error
111 110 111
Ideal
Gain error
Ideal
1 FS 4
1 FS 2
3 FS 4
FS
Offset Error
111 110
111
Ideal
110
Ideal
Nonlinearity
Integral Nonlinearity
Differential Nonlinearity
Page X.64
Hold ts
Output valid for A/D conversion
S(t) S* S(t) t
Tsample = ts + ta ta = acquisition time ts = settling time tADC = time for ADC to convert analog input to digital word. Conversion time = ts + ta + tADC. kT Noise = C V 2 (rms)
Page X.65
vI CH
+
A1
vO
Improved
A1 CH
A2
+
vO
vI
Waveforms
Page X.71
vIN*
NT NT
+ Ramp generator vr vr vIN* Reset 0 Interval counter f= 1 T clock NT t Output Output counter
VREF
Simplicity of operation Subject to error in the ramp generator Long conversion times
Page X.72
Dual Slope, A/D Converter Block Diagram: 1 Vin* 2 VREF Positive integrator vint Vth + 
Digital control
Counter Operation:
Binary output
1.) Initially vint = 0 and vin is sampled and held (Vin* > 0). 2.) Reset by integrating until vint(0) = Vth. 3.) Integrate Vin* for Nref clock cycles to get, NrefT * * vint(t1) = vint (NrefT) = k Vin dt + vint(0) = kNrefTVin + Vth 0 * 4.) The Carry Output on the counter is used to switch the integrator from Vin to V REF. Integrate until vint is equal to Vth resulting in NoutT + t1 vint(t1 + t2) = vint(t1) + k VREFdt = V th t1 Nout * * = V in kNref TVin + Vth  kVREFNoutT= Vth VREF N ref
Page X.73
Vth
0 0
Reset
t
t1 = NrefT t0 (start) t'2 t'' 2 t''' 2 t2 = Nout T
Very accurate method of A/D conversion. Requires a long time 2( 2N) T
Allen and Holberg  CMOS Analog Circuit Design Switched Capacitor Integrators Noninverting: C1 + v1 (t) 1 2 1 2 + v2 (t) C2 +
Page X.74
Operation: Assume nonoverlapping clocks 1 and 2. During 1, C1 is charged to v1[ ( n1) T] giving a charge of q1[ ( n1) T] on C1. During 2, the charge across C1 is added to the charge already on C2 which is q2[ ( n1) T] resulting in a new charge across C2 designated as q2( nT) . The charge equation can be written as, q2( nT) = q2[ ( n1) T] + q1[ ( n1) T] or C2v2( nT) = C2 v2 [ ( n1) T] + C1 v1 [ ( n1) T] Using zdomain notation gives C2v2(z) = C2z1v2(z) + C1z1v1(z) or v2(z) C1 z1 H(z) = v (z) = C2 1 1  z1
Allen and Holberg  CMOS Analog Circuit Design Replacing z by ejT gives, jT e j T C1 C1 e 2 = H(ejT) = T T C2 j C2 1  ejT e 2  ej2 o ( /2) j sin( /2) Mag. error o j
Page X.75
1 if f << fc = T
ejx  ejx 2j
Page X.76
Magnitude Plots of the Switched Capacitor Integrator o = c 2 T 2f f = 2f = f = 2 c c c Log Plot10 T o 2 sin T 2 H(ej t ) dB 0 o =0.5 c o 10 0.1 Linear Plot10 8 6 H(ej t ) 4 2 0 T o 2 sin T 2 1 2 3
4 5
0.5
1.5
c
2.5
3.5
Page X.77
v1 (t) 
)
o j
, if f << fc = 1/T
Settling Time and Slew Rate of the Op Amp Important when the op amp plus feedback circuit has two or more poles or the op amp has a second pole. 1
t 2 t
Slew Rate
vout
Settling Time
Page X.81
Input Comparator
Conditional gate
Output register
Shift register
Clock
0.5VREF
t T
Page X.82
R 2 M1 R2 M
SA SB
V* in
Resistor switches
start
Operation: 1.) With SF closed, the bottom plates of all capacitors are connected through switch SB to Vin*. (Automatically accounts for voltage offsets). 2.) After SF is opened, a successive approximation search among the resistor string taps to find the resistor segment in which the stored sample lies. 3.) Buses A and B are then connected across this segment and the capacitor bottom plates are switched in a successive approximation sequence until the comparator input voltage converges back to the threshold voltage. Capable of 12bit monotonic conversion with a DL of 0.5LSB within 50s.
Page X.83
V* in
+ 
S2 precharge Vref Serial D/A converter (Fig. 10.31) S3 discharge S1 charge share S4 reset D/A control register
Start Clock
Conversion Sequence: 1.) Assume first K MSB's have been decided so that, 1 1 1 Digital word = aM N + aN1 + ... + a +. +1 NK 2 2N1 2NK+1 2.) Assume (K + 1)th MSB is 1 and compare this analog output with Vin* to determine aNK. 3.) Store aNK in the DATA storage register and contiune.
Page X.84
C1
C2
13/16
13/16
Comments: LSB must go first. n cycles to make an nbit DA conversion. Top plate parasitics add error. Switch parasitics add error.
Close S4: VC2 = 0 Store with LSB firstClose S2 (b0=1): VC1 = VREF VREF Close S1: VC1 = 2 = VC2 Close S3 (b1=0): VC1 = 0 VREF Close S1: VC1 = VC2 = 4 Close S2 (b2=1): VC1 = VREF 5 Close S1: VC1 = V C2 = 8 VREF Close S2 (b3=1): VC1 = VREF 13 Close S1: VC1 = V C2 = 16 VREF
Page X.85
0 1 2 0 1 1 bit
2 3 4 0 1 2 bits
2 3 4 5 6 0 1 3 bits
2 3 4 5 6 7 8 4 bits
0 1 2 0 1
2 3 4 0 1
2 3 4 5 6 0 1
2 3 4 5 6 7 8
Allen and Holberg  CMOS Analog Circuit Design A 1BIT/PIPE PIPELINE A/D CONVERTER Single Bit/Stage, NStage Pipeline Converter Converter in 1 clock cycle using storage registers Requires N comparators Dependent upon passive component linearity Can use error correcting algorithms and selfcalibration techniques Block Diagram of the 1Bit/Pipe A/D Architecture MSB bi
Page X.86
LSB
+ 
+ 
+ 
V* in
1 Vref
vi1
z1
1 ith stage
vi
z1
Vi = 2Vi1  biVref
Output of the nth stage can be written as: N1 N A V VN = i in Aj bi + bN Vref i=1 i=1 j=i+1 N where Ai and bi are the gain and bit value of the ith stage
Allen and Holberg  CMOS Analog Circuit Design Graphical Examples illustrating operation
Example 1 x2 1 3/4 1/2 1/4 0 1/4 1/2 3/4 1 B=1 1 3/4 1/2 1/4 0 1/4 1/2 3/4 1 B=1 VREF 1 3/4 1/2 1/4 0 1/4 1/2 3/4 1 B=0 1 3/4 1/2 1/4 0 1/4 1/2 3/4 1
Page X.87
x2
VREF
x2
+VREF
B=1
Example 2 1 3/4 1/2 1/4 0 1/4 1/2 3/4 1 B=0 1 3/4 1/2 1/4 0 1/4 1/2 3/4 1 B=1 x2 VREF 1 3/4 1/2 1/4 0 1/4 1/2 3/4 1 B=0 1 3/4 1/2 1/4 0 1/4 1/2 3/4 1 B=1 x2 +VREF
x2 VREF
Page X.88
IDEAL STAGE PERFORMANCE Vi Vi1 ith Stage Plot of: V = 2 V bi ref ref Vi Vref 1
1 bi+1 =1
.5
.5
1.) bi+1 must change at 0, and 0.5Vref. (when Vi1=0 and 0.5Vre f) 2.) bi must change at Vi=0. 3.) Vi cannot exceed Vref. 4.) Vi should not be less than Vref when Vi1=Vref.
Page X.89
IDEAL PERFORMANCE Example Assume V in* = 0.4V and Vref = 1V Stage i 1 2 3 4 Input to the ith stage, Vi1 0.4 2(0.4000)1 = 0.200 2(0.200)+1 = +0.600 2(+0.600)1 = +0.200 Vi1 > 0? Yes No Yes Yes Bit i 1 0 1 1
1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0.6 0.2 0.2 0.6 1 0.6 0.2 0.2 0.6 1 0.6 0.2 0.2 0.6 1 0.6 0.2 0.2 0.6 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0.2 0.6 0.6 0.2 1 0.2 0.6 0.6 0.2 1 0.2 0.6 0.6 0.2 1 0.2 0.6 0.6 0.2 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0.6 0.2 0.2 0.6 1 0.6 0.2 0.2 0.6 1 0.6 0.2 0.2 0.6 1 0.6 0.2 0.2 0.6 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0.2 0.6 0.6 0.2 1 0.2 0.6 0.6 0.2 1 0.2 0.6 0.6 0.2 1 0.2 0.6 0.6 0.2 1
Allen and Holberg  CMOS Analog Circuit Design Output Voltage for a 4stage Converter
Page X.810
1 0.8 0.6 Inputs (Volts) 0.4 0.2 0 0.2 0.4 0.6 0.8 1 1 0.8 0.6 0.4 0.2 0 0.2 VIN (Volts) 0.4 0.6 0.8 1
Page X.811
RESOLUTION LIMITS OF THE 1BIT/STAGE PIPELINE ADC 1stOrder Errors of The 1Bit/Stage Pipeline ADC Gain magnitude and gain matching (k1) Offset of the X2 amplifier and the sample/hold (k2) Comparator offset (k3) Summer magnitude and gain matching (k4) Summer offset (k 5) Illustration:
+ 
k3 Vi1 2
k2 + + +
bi Vref
+ + k4
k5 +
Vi
k1
Ai = all gain related errors of the ith stage VOSi = system offset errors of the ith stage VOCi = the comparator offset of the ith stage Asi = the gain of the summing junction of the ith stage
Page X.812
Generalization of the FirstOrder Errors Extending the ith stage firstorder errors to N stages gives: VN = N1 N Aj VOSi + VOSN A V + i in i=1 i=1 j=i+1 N N1 N  Vref Aj Asibi + A sNbN i=1 j=i+1 Assuming identical errors in each stage gives:
VN = A NVin +
( ANi) VOS
i=1
( 2Ni) bi
i=2
Page X.813
Identification of Errors 1. Gain Errors 2N( A/A) < 1 N=10 A 1 < A 1000
2A A 2A 1A 1+
1 bi+1 =1
1 bi =1 bi =+1
Page X.814
Identification of Errors  Cont'd 2. System Offset Errors VOS < For N=10 and V ref = 1V, VOS < 1mV Vref 2N
Illustration of system offset error Vi Vref 1 1+VOS 1+VOS bi+1 =+1 Vi1 Vref
1 bi+1 =1
1 bi =1 bi =+1
Page X.815
Identification of Errors  Cont'd 3. Summing Gain Error As 1 < A s 2N A 1 For N=10, A < 1024 Vi Vref 1+As /As 1As /As
1
0.5
0.5
Vi1 Vref
Page X.816
Identification of Errors  Cont'd 4. Comparator Offset Error The comparator offset error is any nonzero value of the input to a stage where the stage bit is caused to change. It can be expressed as: Vi = 2Vi1  biVref where
+1 if Vi1 > VOCi bi = 1 if V < V i1 OCi
0.5
0.5
bi =1 VOC = ?
bi =+1
Page X.817
SUMMARY
1.) The 1bit/pipe, pipeline converter which uses standard components including a sample and hold, an amplifier, and a comparator would be capable of realizing at most an 8 or 9 bit converter. 2.) The accuracy of the gains and offset of the first stage of an NBit converter must be within 0.5LSB. 3.) The accuracy of the gains and offset of a stage diminishes with the remaining number of stages to the output of the converter. 4.) Error correction and selfcalibrating techniques are necessary in order to realize the potential resolution capability of the 1bit/'stage pipeline ADC.
Page X.818
Cyclic Algorithmic A/D Converter The output of the ith stage of a pipeline A/D converter is Voi = (2Vo,i1  biVREF )z1 If Voi is stored and feedback to the input, the same stage can be used for the conversion. The configuration is as follows: Comparator X2 Voi
+1
+1
+Vref Vref
1
Page X.819
Algorithmic ADC  Example Assume that Vin* = 0.8VREF. The conversion proceeds as; 1.) 0.8VREF is sampled and applied to the X2 amplifier by S1. 2.) Va(0) is 1.6VREF (b1=1) which causes VREF to be subtracted from Va(0) giving Vb(0) = 0.6V REF 3.) In the next cycle, Va(1) is 1.2VREF (b2=1) and Vb(1) is 0.2VREF. 4.) The next cycle gives Va(2) = 0.4VREF (b3=0) and Vb(2) is 0.4VREF. 5.) The next cycle gives Va(3) = 0.8VREF (b4=0) and Vb(3) is 0.8VREF. 6.) Finally, V a(4) = 1.6V REF (b5=1) and V b(4) = 0.6V REF. The digital word is 11001. Vanalog = 0.78125VREF.
Va/VREF
2.0 1.6 1.2 0.8 0.4 0
Vb /VREF
2.0 1.6 1.2 0.8 0.6 0.4 0.2
t T
t T
Page X.820
Algorithmic A/D ConvertersPractical Results Only one accurate gainoftwo amplifier required. Small area requirements Slow conversion time  nT. Errors: Finite op amp gain, input offset voltage, charge injection, capacitance voltage dependence.
Practical Converter 12 Bits Differential linearity of 0.019% (0.8LSB) Integral linearity of 0.034% (1.5LSB) Sample rate of 4KHz.
Page X.821
SELFCALIBRATING ADC's
S1 MAINDAC COMP
CN CN1 C1B C1A CCAL
CONTROL LOGIC
VN
VN1
DATA OUTPUT
Main ADC is an Nbit charge scaling array. Sub DAC is an Mbit voltage scaling array. Calibration DAC is an M+2 bit voltage scaling array. This is an voltagescaling, chargescaling A/D converter with (N+M) bits resolution.
Page X.822
SelfCalibration Procedure During calibration cycles, the nonlinearity factors caused by capacitor mismatching are calibrated and stored in the data register for use in the following normal conversion cycles. The calibration procedure begins from MSB by connecting CN to VREF and the remaining capacitors CNX to GND, then exchange the voltage connection as follows:
VX
VX
CN
CNX
CN
CNX
VREF
VREF
where C NX = C1B + C1A + ... + C N1 The final voltage VX after exchanging the voltage connections is VX = VREF CNX  CN CNX + C N
If the capacitor ratio is accurate and CNX = CN VX = 0, otherwise VX 0. This residual voltage VX is digitized by the calibration DAC. Other less significant bits are calibrated in the same manner. After all bits are calibrated, the normal successiveapproximation conversion cycles occurs. The calibrated data stored in the data register is converted to an analog signal by calibration DAC and is fed to the main DAC by CCAL to compensate the capacitor mismatching error.
Page X.823
SelfCalibrating ADC Performance Supply voltage 5V Resolution of 16 bits Linearity of 16 bits Offset less than 0.25 LSB Conversion time for 0.5 LSB linearity: 12 s for 12 Bits 80 s for 16 Bits. RMS noise of 40 V. Power dissipation of 20 mW (excludes logic) Area of 7.5 mm (excludes logic).
Page X.91
X.9  HIGH SPEED ADC's Conversion Time T (T = clock period) Flash or parallel Time interleaving Pipeline  Multiple Bits Pipeline  Single Bit
Page X.92
+ + + + + + + 
1 1
0 0
Fast conversion time, one clock cycle Requires 2N1 comparators Maximum practical bits is 6 or less 6 bits at 10 MHz is practical
Page X.93
TimeInterleaved A/D Converter Array Use medium speed, high bit converters in parallel. T1 S/H Nbit A/D
Page X.94
320
160 FLASH
80
40 3 20 m
10
# of bits
Page X.95
2MBIT, PARALLELCASCADE ADC Compromise between speed and area 8bit, 1M Hz. Gain = 2M V* in Vref + + + Digital decoding network + Vref + + + Digital decoding network V* in
+ D/A Converter
+ 
M MSB's
M LSB's
Page X.96
Conversion of Digital back to Analog for Pipeline Architectures Use XOR gates to connect to the appropriate point in the resistor divider resulting in the analog output corresponding to the digital output. Vref Analog Out
V* in 1 0 + 1 + 0 + 0 0 0 1
+ 
Page X.101
y(kTN)
Modulator Quantization
y(kTN)
The antialiasing filter at the input stage limits the bandwidth of the input signal and prevents the possible aliasing of the following sampling step. The modulator pushes the quantization noise to the higher frequency and leaves only a small fraction of noise energy in the signal band. A digital low pass filter cuts off the high frequency quantization noise. Therefore, the signal to noise ratio is increased.
Page X.102
ANTIALIASING FILTER The antialiasing filter of an oversampling ADC requires less effort than that of a conventional ADC. The frequency response of the antialiasing filter for the conventional ADC is sharper than the oversampling ADC. Conventional ADC's AntiAliasing Filter
fB
f fN/2 fS=fN
fB
f fN/2 fN fS/2 fS fB : Signal Bandwidth fN : Nyquist Frequency, fN = 2fB fS : Sampling Frequency and usually fS >> fN fS M : Oversampling ratio, M = f N So the analog antialiasing filter of an oversampling ADC is less expensive than the conventional ADC. If M is sufficiently large, the analog antialiasing filter is simply an RC filter.
Allen and Holberg  CMOS Analog Circuit Design QUANTIZATION Conventional ADC's Quantization
Page X.103
The resolution of conventional ADCs is determined by the relative accuracy of their analog components. For a higher resolution, selfcalibration technique can be adopted to enhance the matching accuracy. Multilevel Quantizer: output (y)
5 3
ideal curve
6 4 2 1 1 3 5 2 4 6
input (x)
y=Gx+e
e
1
x
1
The quantized signal y can be represented by y = Gx + e where, G = gain of ADC, normally = 1 e = quantization error
Allen and Holberg  CMOS Analog Circuit Design Conventional ADC's Quantization  Cont'd The mean square value of quantization error, e, is /2 2 1 e(x)2 dx = e2rms = 12 /2 where
Page X.104
VREF ) 2N When a quantized signal is sampled at fS (= 1/), all of its noise power folds into the frequency band from 0 to fS/2. If the noise power is white, then the spectral density of the = the quantization level of an ADC (typically sampled noise is 2 E(f) = erms f S where = 1/fS and fS = sampling frequency The inband noise energy no is fB 2 e 2f 2 B 2 2 rms 2 no = E (f)df = e rms (2fB) = erms f = M S 0 erms no = M fS The oversampling ratio M = 2f B Therefore, each doubling of the sampling frequency decreases the inband noise energy by 3 dB, and increases the resolution by 0.5 bit. This is not a very efficient method of reducing the inband noise. 1/2 = erms 2
Page X.105
analog fB input
MODULATOR
Oversampling ADCs consist of a modulator, a decimator (downsampler), and a digital low pass filter. modulator Also called the noise shaper because it can shape the quantization noise and push majority of the noise to high frequency band. It modulates the analog input signal to a simple digital code, normally is one bit, using a sampling rate much higher the Nyquist rate. Decimator Also called the downsampler because it down samples the high frequency modulator output into a low frequency output. Lowpass filter Use digital low pass filter to cut off the high frequency quantization noise and preserve the input signal.
Page X.106
SigmaDelta () Modulator First Order Modulator The open loop quantizer in a conventional ADC can be modified by adding a closed loop to become a modulator. fS
x(t)
+

Integrator
A/D
yi
Page X.107
gn 
wn+1
Delay
wn en
yn
Accumulator yn = wn + en (1)
Quantizer
wn+1 = gn + wn = xn  yn + wn = xn (wn + en) + wn = xn  en (2) Therefore, wn = xn1  en1, which when substituted into (1) gives yn = xn1 + ( en  en1) The output of modulator yn is the input signal delayed by one clock cycle xn1, plus the quantization noise difference en  en1. The modulation noise spectrum density of en  en1 is N(f) = E(f) 1  z1 = E(f) 1  ej = 2E(f) sin 2 = 2e rms 2 sin 2 Plot of Noise Spectrum 2 signal baseband N(f)
1.5 N(f)/E(f)
E(f)
0.5
0 0 fB Frequency fS 2
Allen and Holberg  CMOS Analog Circuit Design First Order ModulatorContd The noise power in the signal band is 2 2 2 df 2e no = N(f) 2 sin df = rms 2 0 0 fB 2 2 no = 2erms 2 (f) df 0 2f f where sin 2 = sin = sin f 2fS f S if fS >> f Therefore, 2 erms2(2fB)3 2 2 f 2 df = no (2)32 erms 3 0 where , fS >> fB Thus, no = erms 3/2 = erms M3/2 2fB 3 3 fB fB fB
Page X.108
Each doubling of the oversampling ratio reduces the modulation noise by 9 dB and increase the resolution by 1.5 bits.
Page X.109
Oversampling Ratio Required for a FirstOrder Modulator A block diagram for a firstorder, sigmadelta modulator is shown in the zdomain. Find the magnitude of the output spectral noise with VIN(z) = 0 and determine the bandwidth of a 10bit analogtodigital = rms value of converter if the sampling frequency, fS, 12 quantization is 10 MHz. noise + Vin (z) + Vout (z) Solution + 1 1 z1 Vout(z) = e rms + z1 [Vin(z) Vout(z)] or z1 Vout(z) = z erms if Vin(z) = 0 Vout(z) = (1z1)erms 2 =2 N(f) = E(f) e sin 1  ej = 2E(f) sin fS rms 2 2 The noise power is found as fB fB 2 f 2 2 2 N(f)2 df = 2 no(f) = erms sin2 2 df fS 0 0 2 f Let sin 2 f if fS >> fB. Therefore, fB 2 2 2 82 2 fB 3 f2 df = no(f) = 4 f erms ()2 3 erms S fS 0 or 3/2 VREF fB 8 10 no(f) = erms f 3 2 S Solving for fB/fS gives (using in erms term is equal to VREF) fB 12 3 1 2/3 = [0.659x103]2/3 = 0.007576 = fS 8 210 fB = 0.00757610MHz = 75.76kHz.
Page X.1010
The onebit output from the modulator is at very high frequency, so we need a decimator (or down sampler) to reduce the frequency before going to the digital filter. fS fD
analog fB input
MODULATOR
LOWPASS DECIMATOR FILTER Removes the modulation noise Removes the outofband components of the signal to lowpass filter yn REGISTER
from modulator xn
fS fS 1 N yn = N xn , where N = = downsampling ratio fD N=0 The transfer function of decimator is N1 1 1  zN Y(z) 1 H(z) = X(z) = N zi = N 1  z1 i=0 sinc(fN) H(ej) = sinc(f)
Allen and Holberg  CMOS Analog Circuit Design Frequency Spectrum of the Decimator sinc(fN) H(ej) = sinc(f) 10 0 Signal Bandwidth 10 Magnitude (dB) Quantization Noise
Page X.1011
fD
Frequency
fS 2
fD = intermediate decimation frequency When the modulation noise is sampled at fD, its components in the vicinity of fD and the harmonics of fD fold into the signal band. Therefore, the zeros of the decimation filter must be placed at these frequencies.
Allen and Holberg  CMOS Analog Circuit Design Digital Lowpass Filter fS fD
Page X.1012
analog fB input
MODULATOR
50
80
110
4000
Frequency (Hz)
Allen and Holberg  CMOS Analog Circuit Design After Digital Low Pass Filtering 0
Page X.1013
0 Bit resolution
Frequency (Hz)
1000
From the frequency response of above diagram, the signaltonoise ratio (SNR) signal SNR = 10log 10 f (dB) B
noise(f)
Allen and Holberg  CMOS Analog Circuit Design System block in time domain and frequency domain
Page X.1014
digital PCM
2fB
LOWPASS
fD
DECIMATOR
FILTER
analog fB input
MODULATOR
Time
Frequency
Frequency
Time
fS
Frequency
Page X.1015
Second order modulator can be implemented by cascading two first order modulators. INTEGRATOR 2 INTEGRATOR 1 xn DELAY A/D + + + + + + DELAY D/A QUANTIZER yn = xn1 + (en  2en1 + en2) The output of a second order modualtor yn is the input signal delayed by one clock cycle xn1, plus the quantization noise difference en  2en1 + en2. The modulation noise spectrum density of en  2en1 + en2 is 2 2 N(f) = E(f) 1  z1 = E(f) 1  ej = 4E(f) sin2 2 Noise Spectrum 4
yn
3 N(f)/E(f)
signal baseband
E(f) 1
fB
Frequency
fS 2
Allen and Holberg  CMOS Analog Circuit Design SecondOrder Modulator Condd
Page X.1016
The noise power in the signal band is 2 2 5/2 2 5/2 no = e rms M = M = ( M) 5/2 , fs >> fo 12 5 5 2 15 Each doubling of the oversampling ratio reduces the modulation noise by 15 dB and increase the resolution by 2.5 bits. HigherOrder Modulators Let L = the number of loops. The spectral density of the modulation can be written as L 2sin 2  NL(f) = e rms 2 The rms noise in the signal band is given approximately by L no erms (2fB) L+0.5 2L+1 This noise falls 3(2L+1) dB for every doubling of the sampling rate providing L+0.5 extra bits. Decimation Filter sinc(fN) L+1 is close to being optimum for decimating the A filter function of sinc(f) signal from an Lthorder modulator. Stability For orders greater than 2, the loop can become unstable. Loop configuration must be used that provide stability for order greater than two.
Page X.1017
where is the signal level out of the 1bit quantizer and fs = (1/) = the sampling frequency and is 10MHz. Find the signal bandwidth, fB, in Hz if the modulator is to be used in an 18 bit oversampled ADC. Be sure to state any assumption you use in working this problem.
Allen and Holberg  CMOS Analog Circuit Design Circuit Implementation of A Second Order Modulator
Page X.1018
S1 IN
S2 C1
S3
Fully differential, switchedcapacitor integrators can reduce charge injection effect. Circuit Tolerance of a Second Order Modulator 1. 20% variation of C1/C2 has only a minor impact on performance. 2. The Op Amp gain should be comparable to the oversampling ratio. 3. The unitygain bandwidth of Op Amp should be at least an order of magnitude greater than the sampling rate.
Allen and Holberg  CMOS Analog Circuit Design SOURCES OF ERRORS IN A/D CONVERTERS 1. Quantization in time and amplitude Jitter and hysteresis 2. Linear Errors Gain and delay 3. Nonlinear Errors Harmonic distortion Thermal noise
Page X.1019
Page X.1020
Comparison of the Various Examples Discussed Type of Converter ResoluNo. of No. of Dependent tion Cycles/ Compar on Passive Components Conver ators sion 1 2 1 after initial delay 64 2N1 31 3 3 Yes Yes Yes Yes Low 10 bits 13 bits 16 bits Speed INL/DNL (LSB's) Area Power (mW)
High 5Ms/s
N/A 3/0.6
Page X.111
X.11 FUNDAMENTAL LIMITS OF SAMPLING A/D CONVERTERS kT/C Noise Assume that the ON resistance of a switch is R and the sampling capacitor is C and that the time to charge the capacitor fully is 1 T = f 10RC c Set the value of the LSB = Vref = 2N kT C
= 10kTRfc
2N f c =
Vref 10kRT
(3)
Taking the log of both sides of (3) gives N = 1.67 log(fc) + 3.3 log(Vref)  1.67 log(10kRT) or N = 32.2 + 3.33 log(V ref )  1.67 log(Rf c ) (At room temperature) kT/C Noise Comparison of highperformance, monolithic A/D converters in terms of resolution versus sampling frequency with fundamental limits due to kT/C noise superimposed.
Page X.112
Fundamental Limits of Sampling A/D Converters  Continued Maximum Sample Rate Assume that the maximum sample rate is determined by the time required for the amplifiers and/or samplehold circuits to settle with the desired accuracy for high resolution. Further assume that the dynamics of these circuits can be modeled by a secondorder system with a transfer function of n2 A(s) = A(0) s 2 + 2 n s + n 2 If n GB of the circuit and if the system is underdamped, then the step response is given as
eGBt vo(t) = 1 sin 1 2 GBt + A(0) 2 1
Settling Time 4 8 n t 12 16 20
If we define the error () in vo settling to A(0) as the multiplier of the sinusoid, then an expression for the settling time can be derived as
eGBt 1 1 2GB fsample = = ts = 2GB ln ts 1 1  2 ln 12
Page X.113
Analog In
Analogtodigital converter
Digital Out
V Slope = dvin dt t
dvin V = slope x T = dt T Vref/2N V T = Aperature uncertainty = dV = dv /dt in in dt Assume that vin(t) = Vp sin t
dvin dt = V p max
T = Therefore, T =
Page X.121
A/D Architecture Serial 1 = 2N T fc Successive Approximation 1 fc NT High Speed 1 T < f < NT c Oversampling 1 << T fc
Typical Performance Characteristics 1100 conversions/sec., 1214 bit accuracy, requires no elementmatching, a stable voltage reference is necessary 10,000100,000 conversions/sec., 810 bits of untrimmed or uncalibrated accuracy, 1214 bits of trimmed or calibrated accuracy 1 to 40 megaconversions/sec., 79 bits of accuracy, 1012 bits of accuracy with error correction and other techniques 8,000600,000 conversions/sec., 1216 bits accuracy, requires linear integrators but no precision passive components, minimizes noise and offsets
Conclusions The best A/D converter depends upon the application Both resolution and speed are ultimately limited by the accuracy of the process High resolution A/D's will be more oriented toward "signal averaging" type converters, particularly with shorter channel lengths