Chaptor 06

ECE2072/TRC2300/TEC2172 Sequential logic
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Sequential circuits

simple circuits with feedback latches edge-triggered flip-flops cascading flip-flops for proper operation clock skew metastability and synchronization shift registers simple counters
Timing methodologies

Asynchronous inputs
Basic registers

Hardware description languages and sequential logic

Copyright 2004, Gaetano Borriello and Randy H. Katz 1
VI - Sequential Logic
Sequential circuits
Circuits with feedback

outputs = f(inputs, past inputs, past outputs) basis for building "memory" into logic circuits door combination lock is an example of a sequential circuit

state is memory state is an "output" and an "input" to combinational logic combination storage elements are also memory
new value C1 C2 multiplexer comparator equal open/closed
equal
reset
C3
mux control
comb. logic state clock
Circuits with feedback

How to control feedback?

what stops values from cycling around endlessly
X1 X2 Xn
switching network
Z1 Z2 Zn
Copyright 2004, Gaetano Borriello and Randy H. Katz
Simplest circuits with feedback

Two inverters form a static memory cell

will hold value as long as it has power applied

"1" "stored value" "0"
How to get a new value into the memory cell?

selectively break feedback path load new value into cell

"data" "load"
"remember" "stored value"
Memory with cross-coupled gates

Cross-coupled NOR gates

similar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1)

R R S Q S Q
Q'
Cross-coupled NAND gates

similar to inverter pair, with capability to force output to 0 (reset=0) or 1 (set=0)

Q S' Q
S' R'
R'
Q'
Timing behavior
R Q
Q'
Reset R S Q \Q
Hold
Set
Reset
Set
100
Race
State behavior or R-S latch

R S
Q Q'
Truth table of R-S latch behavior

Q Q' 0 1 S 0 0 1 1 R 0 1 0 1 Q hold 0 1 unstable Q Q' 1 0
Q Q' 0 0
Q Q' 1 1
Theoretical R-S latch behavior

SR=10 SR=00 SR=01 Q Q' 0 1 SR=01 SR=11
R S
Q Q'
SR=01 SR=10
Q Q' 1 0
SR=00 SR=10
State diagram

states: possible values transitions: changes based on inputs

SR=01 possible oscillation between states 00 and 11
SR=11 SR=00
Q Q' 0 0
SR=11 SR=00 SR=11 SR=10
Q Q' 1 1
8
Observed R-S latch behavior

R S
Q Q'
Very difficult to observe R-S latch in the 1-1 state

one of R or S usually changes first a so-called "race condition" or non-deterministic transition

SR=00 SR=01 Q Q' 0 1 SR=01 SR=11 Q Q' 0 0
Ambiguously returns to state 0-1 or 1-0

SR=10 SR=01 SR=10 Q Q' 1 0 SR=00 SR=10
SR=11 SR=00
SR=11 SR=00
9
R-S latch analysis

Break feedback path

R Q
Q(t)
S R Q(t+)
S S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q(t) 0 1 0 1 0 1 0 1
Q' Q(t+) 0 hold 1 0 reset 0 1 set 1 X not allowed X
S
0 0 0 X X 1 1
Q(t)
R characteristic equation Q(t+) = S + R Q(t)
10
Activity: R-S latch using NAND gates

R
Q'
Q(t)
R S
S 0 0 0 0 1 1 1 1
R 0 0 1 1 0 0 1 1
S 1 1 1 1 0 0 0 0
R 1 1 0 0 1 1 0 0
Q(t) 0 1 0 1 0 1 0 1
Q(t+) 0 1 0 0 1 1 X X
hold
0 0 0 X X
S
1 1
reset set not allowed
Q(t)
R characteristic equation Q(t+) = S + R Q(t)

11
Gated R-S latch

R'
Note inputs are inverted enable' - so asserted low!
Control when R and S inputs matter

S'
Qbar S
otherwise, the slightest glitch on R or S while enable is low could cause change in value stored
Bubble match inputs clarifies logic intention

R Q enable Qbar S
Set
100
Reset
S' R' enable' Q Qbar

VI - Sequential Logic Copyright 2004, Gaetano Borriello and Randy H. Katz 12
Clocks
Used to keep time

wait long enough for inputs (R' and S') to settle then allow to have effect on value stored period (time between ticks) duty-cycle (time clock is high between ticks - expressed as % of period)
duty cycle (in this case, 50%)
Clocks are regular periodic signals

period
13
Clocks (contd)
Controlling an R-S latch with a clock

can't let R and S change while clock is active (allowing R and S to pass) only have half of clock period for signal changes to propagate signals must be stable for the other half of clock period
R clock S Q S
stable changing stable changing stable R and S clock
14
Cascading latches

Connect output of one latch to input of another How to stop changes from racing through chain?

need to be able to control flow of data from one latch to the next move one latch per clock period have to worry about logic between latches (arrows) that is too fast
R S clock
R S
Q Q
R S
Q Q
15
Master-slave structure
Break flow by alternating clocks (like an air-lock)

use positive clock to latch inputs into one R-S latch use negative clock to change outputs with another R-S latch master-slave flip-flop twice as much logic output changes a few gate delays after the falling edge of clock but does not affect any cascaded flip-flops
master stage slave stage R S CLK R S Q Q P R S Q Q
View pair as one basic unit

16
The 1s catching problem

In first R-S stage of master-slave FF

0-1-0 glitch on R or S while clock is high is "caught" by master stage leads to constraints on logic to be hazard-free
master stage R 1s catch S CLK R S Q Q P P slave stage R S Q Q
Set S R CLK P P Q Q
Reset
Master Outputs Slave Outputs

D flip-flop
Make S and R complements of each other

eliminates 1s catching problem can't just hold previous value (must have new value ready every clock period) value of D just before clock goes low is what is stored in flip-flop can make R-S flip-flop by adding logic to make D = S + R Q
master stage R Q Q P slave stage R S Q Q Q Q
D CLK
10 gates
Edge-triggered flip-flops
More efficient solution: only 6 gates

sensitive to inputs only near edge of clock signal (not while high)
D D holds D when clock goes low (1+D)=1=0 Q negative edge-triggered D flip-flop (D-FF) 4-5 gate delays must respect setup and hold time constraints to successfully capture input
D Clk Q
R Clk=1 S
Q (1+R+D)=1=0 holds D when clock goes low
characteristic equation Q(t+1) = D
19
Edge-triggered flip-flops (contd)

Step-by-step analysis
D D D R Q Clk=0 S D S D R 0 D D Q
Clk=0
D when clock goes high-to-low data is latched
new D=D2 where D2 old D
(D2+D)=1=0 when clock is low data is held

20
Edge-triggered flip-flops (contd)

Positive edge-triggered
inputs sampled on rising edge; outputs change after rising edge inputs sampled on falling edge; outputs change after falling edge
100
Negative edge-triggered flip-flops

D CLK Qpos Qpos Qneg Qneg
positive edge-triggered FF negative edge-triggered FF
21
Comparison of latches and flip-flops
D Q CLK positive edge-triggered flip-flop D CLK Qedge D Q G CLK transparent (level-sensitive) latch
Qlatch
behavior is the same unless input changes while the clock is high
Comparison of latches and flip-flops (contd)

Type unclocked latch level-sensitive latch master-slave flip-flop negative edge-triggered flip-flop When inputs are sampled When output is valid always clock high (Tsu/Th around falling edge of clock) clock high (Tsu/Th around falling edge of clock) clock hi-to-lo transition (Tsu/Th around falling edge of clock) propagation delay from input change propagation delay from input change or clock edge (whichever is later) propagation delay from falling edge of clock propagation delay from falling edge of clock
23
Rules for interconnecting components and clocks

guarantee proper operation of system when strictly followed
Approach depends on building blocks used for memory elements

we'll focus on systems with edge-triggered flip-flops

found in programmable logic devices
many custom integrated circuits focus on level-sensitive latches (1) correct inputs, with respect to time, are provided to the flipflops (2) no flip-flop changes state more than once per clocking event
Basic rules for correct timing:

24
Timing methodologies (contd)

Definition of terms
clock:
periodic event, causes state of memory element to change can be rising edge or falling edge or high level or low level setup time: minimum time before the clocking event by which the input must be stable (Tsu) hold time: minimum time after the clocking event until which the input must remain stable (Th)
Tsu Th data D Q D Q
input clock there is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized
clock stable changing data clock
25
Typical timing specifications

Positive edge-triggered D flip-flop

setup and hold times minimum clock width propagation delays (low to high, high to low, max and typical)
Tsu Tsu D 1.8 ns Th 0.5 ns Tw 3.3 ns 1.8 ns Th 0.5 ns Tw 3.3 ns Tpd 3.6 ns 1.1 ns
Clk
Tpd 3.6 ns 1.1 ns
all measurements are made from the clocking event (the rising edge of the clock)
Cascading edge-triggered flip-flops

Shift register

new value goes into first stage while previous value of first stage goes into second stage consider setup/hold/propagation delays (prop must be > hold)
D Q Q0 D Q Q1 OUT
IN
CLK IN Q0 Q1 CLK
100
27
Cascading edge-triggered flip-flops (contd)

Why this works

propagation delay exceed hold time: Tp > Th clock width constraint exceeds setup time: Tperiod > Tp + Tsu this guarantees following stage will latch current value before it changes to new value
In Q0 Q1 Tsu 1.8ns Tp 1.1-3.6ns Tsu 1.8ns Tp 1.1-3.6ns timing constraints guarantee proper operation of cascaded components
CLK Th 0.5ns
assumes infinitely fast distribution of the clock Th 0.5ns

Clock skew
The problem
correct behavior assumes next state of all storage elements determined by all storage elements at the same time this is difficult in high-performance systems because time for clock to arrive at flip-flop is comparable to delays through logic effect of skew on cascaded flip-flops:
100 In Q0 Q1 CLK0 CLK1 CLK1 is a delayed version of CLK0
original state: IN = 0, Q0 = 1, Q1 = 1 due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1

How to avoid clock skew

Design wire/track layout for identical delay of related signals
30
Summary of latches and flip-flops

Development of D-FF
level-sensitive used in custom integrated circuits

can be made with 4 switches

edge-triggered used in programmable logic devices good choice for data storage register similar to S-R but with 1-1 being used to toggle output (complement state) good in days of TTL/SSI (more complex excitation function: Q+ = J Q + K Q) not a good choice for PALs/PLAs as it requires 2 inputs can always be implemented using D-FF used at start-up or to reset system to a known state
Historically J-K FF was popular but now less common

Preset and clear inputs are highly desirable on flip-flops

31
Asynchronous inputs (Katz2e Sec 6.2.3)

Clocked synchronous circuits

Inputs, state, and outputs sampled or changed in relation to a common reference signal (called the clock) e.g., master/slave JK, edge-triggered D flip-flop Any number of devices from the same family can be cascaded together and will perform correctly (at the appropriate clock frequency) since setup and hold times will be satisfied. Inputs, state, and outputs sampled or changed independently of a common reference signal e.g., R-S latch, asynchronous Set/Reset inputs to D flip-flop No setup/hold constraints Glitches/hazards a major concern since they are more likely to cause state changes than in synchronous circuits.
Asynchronous circuits

Asynchronous inputs
Asynchronous inputs to synchronous circuits

inputs can change at any time, will not meet setup/hold times dangerous, synchronous inputs are greatly preferred
D Q
Asychronous inputs cannot be avoided for any circuit that interfaces with the outside world!
Handling asynchronous inputs

Never allow asynchronous inputs to fan-out to more than one flip-flop

If input changes near clock edge, each flip-flop may enter different state
Synchronize early and then treat as synchronous signal

Clocked Synchronous System Async Input D Q Q0 Async Input D Q Synchronizer D Q Q0
Clock D Q Q1 D Q
Clock Q1
Clock
Clock
34
Handling asynchronous inputs (contd)

What can go wrong?

input changes too close to clock edge (violating setup time constraint)
In Q0 Q1 CLK
In is asynchronous and fans out to D0 and D1 one FF catches the signal, one does not inconsistent state may be reached!
35
Synchronizer failure: Metastability

When an asynchronous input changes near a clock edge, the synchronizer may enter a metastable state - neither 0 or 1 Hill analogy for metastability:

Valleys represent possible stable states -- 1 or 0 Current state represented by position of the ball To move from one stable state to another, the ball must be injected with sufficient energy to climb over the hill If just the right amount of energy is injected, the ball may remain tottering at the top of the hill
metastable state
hungry dog analogy
stable state logic 0

stable state logic 1

Synchronization failure: Metastability

Synchronizer may stay in metastable state indefinitely! In practise, thermal disturbances and timing asymmetries cause the output to return to 0 or 1 after some time. System failure can occur if the flip-flop has not left the metastable state by the ed of the clock period.
oscilloscope traces demonstrating synchronizer failure and eventual decay to steady state
37
Dealing with synchronization failure

Probability of failure can never be reduced to 0, but it can be reduced

(1) slow down the system clock this gives the synchronizer more time to decay into a steady state; synchronizer failure becomes a big problem for very high speed systems (2) use fastest possible logic technology in the synchronizer this makes for a very sharp "peak" upon which to balance (3) cascade two synchronizers this effectively synchronizes twice (both would have to fail)
asynchronous input
Q Clk
synchronized input
synchronous system
Speed-Independent Circuits (Katz2e Sec 6.2.5)

As circuits get larger and faster, clock skew increases and different components effectively become asynchronous. When clock skew is sufficiently problematic, a global clock must be discarded in favour of delay-insensitive signaling:
Sender (server) and receiver (client) circuits communicate without the need for a global clock Synchronization is achieved through a handshaking protocol using additional signals: request and acknowledge
Request Client (independently clocked subsystem) Data flow Acknowledge Server (independently clocked subsystem)
39
Four-Cycle Handshaking
Handshaking steps:

Client asserts request line Server places data on data lines and asserts acknowledge line Client receives data and unasserts request line Server removes data from data lines and unasserts acknowledge

Undetermined delay between each step does not lead to failure Request is asynchronous with respect the to server and acknowledge is asynchronous with respect to the client, so the potential for synchronizer failure is unavoidable!
Req Data Ack
40
Two-Cycle Handshaking

Also called non-return-to-zero signalling Handshaking steps:

Client complements request line Server drives data lines and complements acknowledge line
Client and server require extra logic to store current state of acknowledge and request lines
first request Req Data Ack data 1 data 2 second request
41
Self-Timed Circuits

The client/server circuits considered above were speed insensitive but still used internal independent clocks We can also use same handshaking approach to build logic circuits without any internal clocks!
Delay line slows acknowledge signal to ensure combinational logic has sufficient time to compute a stable output Delay line should have same number of gate levels as longest delay through combinational logic
Self-timed circuits are increasingly important as clock distribution becomes a more difficult problem
Input Combinational Logic Delay
Output Ack
Req
Flip-flop features
Reset (set state to 0) R

synchronous: Dnew = R' Dold (when next clock edge arrives) asynchronous: doesn't wait for clock, quick but dangerous
Preset or set (set state to 1) S (or sometimes P)

synchronous: Dnew = Dold + S (when next clock edge arrives) asynchronous: doesn't wait for clock, quick but dangerous
Both reset and preset

Dnew = R' Dold + S Dnew = R' Dold + R'S
(set-dominant) (reset-dominant)
Selective input capability (input enable or load) LD or EN

multiplexor at input: Dnew = LD' Q + LD Dold load may or may not override reset/set (usually R/S have priority)
Complementary outputs Q and Q'
43
Registers
Collections of flip-flops with similar controls and logic

stored values somehow related (for example, form binary value) share clock, reset, and set lines similar logic at each stage shift registers counters
"0" R S D Q CLK IN1 IN2 IN3 IN4
44
Examples

OUT1
OUT2
OUT3
OUT4
R S D Q
R S D Q
R S D Q
Register Files
A register file groups multiple registers in a single element:

RE/WE indicate when a read or write operation is performed Address lines A1-A5 indicate which register is to be read/written Word to be written is sent to data inputs D1-D8 Word to be read is asserted on outputs Q1-Q8
If no external clock, WE is used to generate internal clock

WE RE A1 A2 A3 A4 A5 D1 D2 D8 Q1 Q2 Q8
45
Random Access Memories (RAM)

A register file typically holds 4-32 data words, but many digital systems require thousands or millions of data words Random access memory (RAM) generalizes the concept of a register file by using a transistor-efficient storage element A large RAM can hold 128 million binary values (16 MBs)
1024x4 SRAM
CS WE A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 I/O3 I/O2 I/O1 I/O0 Writej Dj Dj Writej Dj
capacitor
Static RAM (SRAM) storage element

Dynamic RAM (DRAM) storage element

46
Shift register
Holds samples of input

store last 4 input values in sequence 4-bit shift register:

OUT1 IN CLK D Q D Q OUT2 D Q OUT3 D Q OUT4
47
Shift register application

Parallel-to-serial conversion for serial transmission

parallel outputs
parallel inputs
serial transmission
48
Pattern recognizer
Combinational function of input samples

in this case, recognizing the pattern 1001 on the single input signal
OUT
OUT1 IN CLK D Q D Q
OUT2 D Q
OUT3 D Q
OUT4
49
Universal shift register

Holds 4 values

serial or parallel inputs serial or parallel outputs permits shift left or right shift in new values from left or right
output clear sets the register contents and output to 0 s1 and s0 determine the shift function s0 0 0 1 1 s1 0 1 0 1 function hold state shift right shift left load new input
left_in left_out clear s0 s1 input

right_out right_in clock
50
Design of universal shift register

Consider one of the four flip-flops

new value at next clock cycle:
clear 1 0 0 0 0
s0 0 0 1 1
s1 0 1 0 1
new value 0 output output value of FF to left (shift right) output value of FF to right (shift left) input
Nth cell to N-1th cell Q D to N+1th cell CLK
CLEAR 0 1 2 3 s0 and s1 control mux Q[N-1] (left) Q[N+1] (right)
Input[N]
51
Counters
Sequences through a fixed set of patterns

in this case, 1000, 0100, 0010, 0001 called a ring counter Is this self-starting? Only counts in above pattern if one of the patterns is its initial state (by loading or set/reset)
52
Activity
How does this counter work?

Counts through the sequence: 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000 Known as Mobius (or Johnson) counter Above circuit not self-starting!
53
Binary counter
Logic between registers (not just multiplexer)

XOR decides when bit should be toggled always for low-order bit, only when first bit is true for second bit, and so on
OUT1 D Q CLK D Q OUT2 D Q OUT3 D Q OUT4
"1"
54
Counter Design Example

Step 1: Draw state transition diagram Step 2: Derive state transition table Step 3: Express each next state bit as function of present state Example: 3-bit binary counter
C B A
111 000 001 110 010
C+ B+ A+ 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0
101 100 011
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
A+ = A B+ = B A + B A C+ = C A + B C + C B A Next state logic
State transition diagram

State transition table

Four-bit binary synchronous up-counter

Standard component with many applications

positive edge-triggered FFs w/ synchronous load and clear inputs parallel load data from D, C, B, A enable inputs: must be asserted to enable counting EN RCO: ripple-carry out used for cascading counters

high when counter is in its highest state 1111 implemented using an AND gate
(2) RCO goes high
D C RCO B QD A QC LOAD QB QA CLK CLR
(3) High order 4-bits are incremented
(1) Low order 4-bits = 1111
56
Offset counters
Starting offset counters use of synchronous load

"1" "0" "1" "1" "0"
EN RCO QD D QC C QB B QA A LOAD CLK CLR
e.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1111, 0110, . . .
"0"
Ending offset counter comparator for ending value

e.g., 0000, 0001, 0010, ..., 1100, 1101, 0000

"1" "0" "0" "0" "0" EN D C B A LOAD CLK CLR RCO QD QC QB QA
Combinations of the above (start and stop value)

57
Hardware Description Languages (Verilog) and Sequential Logic

Behavioral Verilog module for edge-triggered D flip-flip:

module dff input output reg (clk, d, q); clk, d; q; q; Indicates that q should be considered for a register it is necessary for variables updated in an always block to be declared reg, even if they are not allocated a register! Indicates that statement should only be executed on positive edge of signal in sensitivity list. For negative edge-triggered flipflop use negedge
58
always @(posedge clk) q = d; endmodule
Edge-triggered D flip-flop with Asynchronous Set and Reset (replace text p296 version)
module dff_async_rs (clk, r, s, d, q); input clk, r, s, d; Indicates a 1-bit binary output q; number with the value 0. reg q; Format specifier: always @(posedge clk width radix value where radix = or posedge r or posedge s) b (binary), d (decimal) begin h (hex), o (octal) if (s) q = 1'b1; else if (r) q = 1'b0; Four valid binary values: else q =d; 0, 1, end x (unknown), endmodule z (high impedance)
Shift Register Implementation

OUT1
OUT2 DQ
OUT3 DQ
OUT4
Shift register:
IN CLK
DQ
DQ
module shift4bit (clk, in, out1, out2, out3, out4); input clk, in; output out1, out2, out3, out4; reg out1, out2, out3, out4; always @(posedge clk) begin out4 = out3; out3 = out2; out2 = out1; out1 = in; end endmodule
Order within block is important! The following wont work: out1 out2 out3 out4 = = = = in; out1; out2; out3;
Delayed Assignment
Delayed (or non-blocking) assignments are indicated by <= instead of =, and take place simultaneous at end of block rather than in the order written. The following shift register implementation is correct:
always @(posedge clk) begin out1 <= in; out2 <= out1; out3 <= out2; out4 <= out3; end
Shorthand notation for multiple assignments:
always @(posedge clk) begin {out1, out2, out3, out4} <= {in, out1, out2, out3}; end
Example: 3-bit Binary Counter

module counter (clk, q0, q1, q2); input clk; output q0, q1, q2; 3-bit state reg [2:0] count; initial count = 0; always @(posedge clk) count = count + 1; assign q2 = cnt[2]; assign q1 = cnt[1]; assign q0 = cnt[0]; endmodule
initial block executed only once at start of simulation. Note: the initial block can appear anywhere in the module; it is still executed once at start
Example: Register File

module register_file_32_by_8 (we, re, abus, dbus, obus); parameter mem_size = 32; parameter dbus_width = 8; parameter abus_width = 6; input we, re; input [abus_width-1:0] abus; input [dbus_width-1:0] dbus; output [dbus_width-1:0] obus; reg [dbus_width-1:0] out; reg [dbus_width-1:0] regfile [mem_size-1:0]; always @(posedge we) regfile[abus] = dbus; always @(posedge re) out = regfile[abus]; assign obus = (re) ? out : 8bzzzzzzzz; endmodule
HDL for Sequential Logic Summary

reg keyword may create a memory variable to store the state of a sequential circuit needed when always blocks used even for combinational circuits. Event control keywords posedge and negedge allow us to implement edge-triggered behavior in latches. Delayed (non-blocking) assignment removes dependency on order of statements in sequential block (between begin and end keywords)
Affected registers are updated simultaneously at end of block
64
Sequential logic summary

Fundamental building block of circuits with state

latch and flip-flop R-S latch, R-S master/slave, D master/slave, edge-triggered D flip-flop use of clocks cascaded FFs work because propagation delays exceed hold times beware of clock skew synchronizer failure: what it is and how to minimize its impact shift registers counters

Asynchronous inputs and their dangers

Basic registers

Hardware description languages and sequential logic


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ECE2072/TRC2300/TEC2172 Sequential logic

Hardware description languages and sequential logic

Circuits with feedback

comb. logic state clock

Circuits with feedback

How to control feedback?

what stops values from cycling around endlessly

Copyright 2004, Gaetano Borriello and Randy H. Katz

Simplest circuits with feedback

Two inverters form a static memory cell

will hold value as long as it has power applied

How to get a new value into the memory cell?

selectively break feedback path load new value into cell

"remember" "stored value"

Copyright 2004, Gaetano Borriello and Randy H. Katz

Memory with cross-coupled gates

Cross-coupled NOR gates

similar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1)

Cross-coupled NAND gates

similar to inverter pair, with capability to force output to 0 (reset=0) or 1 (set=0)

Copyright 2004, Gaetano Borriello and Randy H. Katz

State behavior or R-S latch

Truth table of R-S latch behavior

Copyright 2004, Gaetano Borriello and Randy H. Katz

Theoretical R-S latch behavior

states: possible values transitions: changes based on inputs

SR=11 SR=00 SR=11 SR=10

Copyright 2004, Gaetano Borriello and Randy H. Katz

Observed R-S latch behavior

Very difficult to observe R-S latch in the 1-1 state

one of R or S usually changes first a so-called "race condition" or non-deterministic transition

Ambiguously returns to state 0-1 or 1-0

SR=10 SR=01 SR=10 Q Q' 1 0 SR=00 SR=10

Copyright 2004, Gaetano Borriello and Randy H. Katz

R-S latch analysis

Break feedback path

Q' Q(t+) 0 hold 1 0 reset 0 1 set 1 X not allowed X

R characteristic equation Q(t+) = S + R Q(t)

Copyright 2004, Gaetano Borriello and Randy H. Katz

Activity: R-S latch using NAND gates

reset set not allowed

R characteristic equation Q(t+) = S + R Q(t)

Copyright 2004, Gaetano Borriello and Randy H. Katz

Gated R-S latch

Note inputs are inverted enable' - so asserted low!

Control when R and S inputs matter

Bubble match inputs clarifies logic intention

S' R' enable' Q Qbar

Used to keep time

Clocks are regular periodic signals

Copyright 2004, Gaetano Borriello and Randy H. Katz

Controlling an R-S latch with a clock

Copyright 2004, Gaetano Borriello and Randy H. Katz

Copyright 2004, Gaetano Borriello and Randy H. Katz

Break flow by alternating clocks (like an air-lock)

View pair as one basic unit

Copyright 2004, Gaetano Borriello and Randy H. Katz

The 1s catching problem

In first R-S stage of master-slave FF

Master Outputs Slave Outputs

Make S and R complements of each other

More efficient solution: only 6 gates

Q (1+R+D)=1=0 holds D when clock goes low

characteristic equation Q(t+1) = D